[Feature][Modem]Update MTK MODEM V1.6 baseline version: MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6
MTK modem version: MT2735_IVT_MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6.tar.gz
RF modem version: NA
Change-Id: I45a4c2752fa9d1a618beacd5d40737fb39ab64fb
diff --git a/mcu/tools/DebuggingSuite/Misc/codescape_simulator_load_elf_template.py b/mcu/tools/DebuggingSuite/Misc/codescape_simulator_load_elf_template.py
new file mode 100755
index 0000000..cdad7bc
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Misc/codescape_simulator_load_elf_template.py
@@ -0,0 +1,35 @@
+import sys
+from imgtec import codescape
+
+elf_path = "[CMMAUTOGEN_ELFPath]"
+
+import wx
+
+if __name__ == "__main__":
+ da = codescape.GetFirstProbe()
+ thread = da.cores[0].hwthreads[0]
+
+ core_num = 4
+ print "=== Get Core Number ===: %d" %(core_num)
+ print "=== Start Loading .elf ==="
+ print "Image path: " + elf_path
+ for core_idx in range(core_num):
+ if(core_idx == 0):
+ # load binary only on VPE0 of 0 core
+ thread = da.cores[core_idx].hwthreads[0]
+ thread.Stop()
+ thread.LoadProgramFile(elf_path, False, 0x83, True, "")
+ print "[Core%d,VPE0] Load ELF successfully" %(core_idx)
+ thread = da.cores[core_idx].hwthreads[1]
+ thread.Stop()
+ thread.LoadProgramFile(elf_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE1] Load ELF successfully" %(core_idx)
+ else:
+ thread = da.cores[core_idx].hwthreads[0]
+ thread.Stop()
+ thread.LoadProgramFile(elf_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE0] Load ELF successfully" %(core_idx)
+ thread = da.cores[core_idx].hwthreads[1]
+ thread.Stop()
+ thread.LoadProgramFile(elf_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE1] Load ELF successfully" %(core_idx)
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Misc/coretracer/OSA/osa_mips.exe b/mcu/tools/DebuggingSuite/Misc/coretracer/OSA/osa_mips.exe
new file mode 100755
index 0000000..e978a53
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Misc/coretracer/OSA/osa_mips.exe
Binary files differ
diff --git a/mcu/tools/DebuggingSuite/Misc/coretracer/OSA/osa_tasklistondemand.py b/mcu/tools/DebuggingSuite/Misc/coretracer/OSA/osa_tasklistondemand.py
new file mode 100755
index 0000000..70d5c1d
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Misc/coretracer/OSA/osa_tasklistondemand.py
@@ -0,0 +1,113 @@
+#!/usr/bin/python
+import sys
+import gdb
+import time
+import math
+if 64 - 64: i11iIiiIii
+if 65 - 65: O0 / iIii1I11I1II1 % OoooooooOO - i1IIi
+def o0OO00 ( addr , size ) :
+ oo = [ ]
+ if 27 - 27: oO0OooOoO * o0Oo
+ i1IiI1I11 = gdb . inferiors ( ) [ 0 ]
+ IIiIiII11i = i1IiI1I11 . read_memory ( addr , size )
+ for o0oOOo0O0Ooo in IIiIiII11i :
+ oo . append ( o0oOOo0O0Ooo . encode ( "hex" ) )
+ return "" . join ( oo )
+ if 2 - 2: o0 * i1 * ii1IiI1i % OOooOOo / I11i / Ii1I
+def IiiIII111iI ( addr , size ) :
+ oo = [ ]
+ if 34 - 34: iii1I1I / O00oOoOoO0o0O . O0oo0OO0 + Oo0ooO0oo0oO . I1i1iI1i - II
+ Oo = size
+ size = int ( math . ceil ( float ( int ( size ) ) / 4 ) * 4 )
+ i1IiI1I11 = gdb . inferiors ( ) [ 0 ]
+ IIiIiII11i = i1IiI1I11 . read_memory ( addr , size )
+ I1Ii11I1Ii1i = 0
+ for o0oOOo0O0Ooo in IIiIiII11i :
+ I1Ii11I1Ii1i = I1Ii11I1Ii1i + 1
+ if I1Ii11I1Ii1i % 4 == 1 :
+ Ooo = o0oOOo0O0Ooo
+ elif I1Ii11I1Ii1i % 4 == 2 :
+ o0oOoO00o = o0oOOo0O0Ooo
+ elif I1Ii11I1Ii1i % 4 == 3 :
+ i1oOOoo00O0O = o0oOOo0O0Ooo
+ elif I1Ii11I1Ii1i % 4 == 0 :
+ oo . append ( o0oOOo0O0Ooo . encode ( "hex" ) )
+ oo . append ( i1oOOoo00O0O . encode ( "hex" ) )
+ oo . append ( o0oOoO00o . encode ( "hex" ) )
+ oo . append ( Ooo . encode ( "hex" ) )
+ if 15 - 15: I11iii11IIi
+ O00o0o0000o0o = Oo % 4
+ if O00o0o0000o0o != 0 :
+ O00o0o0000o0o = 4 - O00o0o0000o0o
+ for O0Oo in range ( O00o0o0000o0o ) :
+ oo . pop ( )
+ if 80 - 80: OoooooooOO . o0Oo
+ return "" . join ( oo )
+ if 87 - 87: Ii1I / I11iii11IIi + II - I11iii11IIi . I11iii11IIi / oO0OooOoO
+ if 11 - 11: o0Oo % OOooOOo - o0
+def oo0O000OoO ( init_node , block_size , offset_next , head_node , request_limit ) :
+ if 34 - 34: O00oOoOoO0o0O * o0Oo
+ init_node = int ( init_node )
+ iiiI11 = ( ( init_node & 0xff ) << 24 ) | ( ( init_node & 0xff00 ) << 8 ) | ( ( init_node & 0xff0000 ) >> 8 ) | ( ( init_node & 0xff000000 ) >> 24 )
+ if 91 - 91: OOooOOo / oO0OooOoO . I11i + iii1I1I
+ if 47 - 47: ii1IiI1i / O0oo0OO0 * OoooooooOO
+ II111iiii = ""
+ IIoOoOo00oOo = 0
+ Ooo00O00O0O0O = init_node
+ while ( Ooo00O00O0O0O != head_node or IIoOoOo00oOo == 0 ) and IIoOoOo00oOo < request_limit :
+ if 90 - 90: oO0OooOoO + Ii1I / OOooOOo % oO0OooOoO - O0
+ if 29 - 29: OOooOOo / iIii1I11I1II1
+ if 24 - 24: O0 % OOooOOo + i1IIi + II + I11i
+ if 70 - 70: o0 % o0 . I1i1iI1i % i1 * OOooOOo % Ii1I
+ if 23 - 23: i11iIiiIii + o0Oo
+ II111iiii = II111iiii + str ( hex ( iiiI11 ) ) [ 2 : 10 ] . zfill ( 8 ) + o0OO00 ( Ooo00O00O0O0O , block_size )
+ if 68 - 68: ii1IiI1i . Ii1I . i11iIiiIii
+ IIiI = o0OO00 ( Ooo00O00O0O0O + offset_next , 4 )
+ iiiI11 = int ( IIiI , 16 )
+ Ooo00O00O0O0O = ( ( iiiI11 & 0xff ) << 24 ) | ( ( iiiI11 & 0xff00 ) << 8 ) | ( ( iiiI11 & 0xff0000 ) >> 8 ) | ( ( iiiI11 & 0xff000000 ) >> 24 )
+ if 22 - 22: o0 % O0oo0OO0
+ if 84 - 84: i11iIiiIii . OOooOOo
+ IIoOoOo00oOo = IIoOoOo00oOo + 1
+ if 100 - 100: O0oo0OO0 - O0oo0OO0 - II
+ if 20 - 20: OoooooooOO
+ print II111iiii
+ if 13 - 13: i1IIi - O0oo0OO0 % Ii1I / iIii1I11I1II1 % Oo0ooO0oo0oO
+ if 97 - 97: i11iIiiIii
+ if 32 - 32: o0 * O0 % Ii1I % O0oo0OO0 . I1i1iI1i
+ if 61 - 61: I11iii11IIi
+ if 79 - 79: o0 + o0Oo - Oo0ooO0oo0oO
+ if 83 - 83: I11iii11IIi
+ if 64 - 64: i1 % I11iii11IIi % Oo0ooO0oo0oO / ii1IiI1i - i1
+ if 74 - 74: Oo0ooO0oo0oO * O0
+ if 89 - 89: Ii1I + o0
+ if 3 - 3: i1IIi / o0Oo % O00oOoOoO0o0O * i11iIiiIii / O0 * O00oOoOoO0o0O
+ if 49 - 49: Ii1I % O0oo0OO0 + i1IIi . o0Oo % I11i
+ if 48 - 48: O00oOoOoO0o0O + O00oOoOoO0o0O / oO0OooOoO / iIii1I11I1II1
+ if 20 - 20: OOooOOo
+ if 77 - 77: ii1IiI1i / O00oOoOoO0o0O
+ if 98 - 98: iIii1I11I1II1 / i1IIi / i11iIiiIii / OOooOOo
+ if 28 - 28: iii1I1I - I1i1iI1i . I1i1iI1i + ii1IiI1i - OoooooooOO + O0
+ if 95 - 95: i1 % Ii1I . O0
+ if 15 - 15: I11iii11IIi / O0oo0OO0 . O0oo0OO0 - i1IIi
+ if 53 - 53: I1i1iI1i + o0Oo * Ii1I
+OooOooooOOoo0 = gdb . parse_and_eval ( "$osa_tasklistinput0" )
+o00OO0OOO0 = gdb . parse_and_eval ( "$osa_tasklistinput1" )
+oo0 = gdb . parse_and_eval ( "$osa_tasklistinput2" )
+o00 = gdb . parse_and_eval ( "$osa_tasklistinput3" )
+OooOooo = gdb . parse_and_eval ( "$osa_tasklistinput4" )
+OooOooo = OooOooo . cast ( gdb . lookup_type ( 'int' ) )
+O000oo0O = gdb . parse_and_eval ( "$osa_tasklistinput5" )
+O000oo0O = O000oo0O . cast ( gdb . lookup_type ( 'int' ) )
+if 66 - 66: I11i / ii1IiI1i - o0Oo . iii1I1I / o0Oo * iii1I1I
+if 29 - 29: I11i % o0Oo + I11iii11IIi / OOooOOo + iii1I1I * OOooOOo
+if 42 - 42: O0oo0OO0 + Ii1I
+if O000oo0O == 0 :
+ oo0O000OoO ( OooOooooOOoo0 , o00OO0OOO0 , oo0 , o00 , OooOooo )
+elif O000oo0O == 1 :
+ print o0OO00 ( OooOooooOOoo0 , o00OO0OOO0 )
+else :
+ oo0O000OoO ( OooOooooOOoo0 , o00OO0OOO0 , oo0 , o00 , OooOooo )
+ if 76 - 76: II - i1
+ if 70 - 70: I11iii11IIi
+ if 61 - 61: I11i . I11i
+# dd678faae9ac167bc83abf78e5cb2f3f0688d3a3
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/ELBRUS/OnTargetMemoryDump.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/ELBRUS/OnTargetMemoryDump.cmm
new file mode 100644
index 0000000..e852ff6
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/ELBRUS/OnTargetMemoryDump.cmm
@@ -0,0 +1,344 @@
+; Copyright Statement:
+; --------------------
+; This software is protected by Copyright and the information contained
+; herein is confidential. The software may not be copied and the information
+; contained herein may not be used or disclosed except with the written
+; permission of MediaTek Inc. (C) 2005
+;
+; BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+; THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+; RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+; AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+; EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+; NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+; SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+; SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+; THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+; NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+; SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+;
+; BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+; LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+; AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+; OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+; MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+;
+; THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+; WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+; LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+; RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+; THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+
+; This cmm is for dumping memory on Target directly.
+
+system.down
+;system.cpu MIPSinterAptiv
+;SYStem.OPTION Endianess little
+
+;SYSTEM.OPTION.EnReset OFF
+;SYSTEM.OPTION.WaitReset OFF
+;System.Option ResBreak OFF
+;system.JtagClock 20MHz
+;system.multicore SWDP OFF
+;system.multicore COREBASE 0xF00A1000
+
+
+
+;system.up
+system.mode attach
+
+
+LOCAL &SWLA_DUMP
+GLOBAL &store_folder
+
+;dialog
+;(
+; header "folder select"
+; pos 1. 1. 27. 1.
+; text "select memory dump folder:"
+
+; pos 1. 2. 20. 1.
+;tmp: edit "" ""
+
+; pos 22. 2. 5. 1.
+; button "..."
+; (
+; dialog.setdir tmp "lib*"
+; )
+; pos 1. 3. 20. 1.
+;check: checkbox "Dump SWLA?" ""
+
+; pos 11. 4. 5. 1.
+; defbutton "OK" "continue"
+;)
+;stop
+; &store_folder=dialog.string(tmp)
+;IF DIALOG.BOOLEAN(check)
+;(
+; &SWLA_DUMP=1
+;)
+;ELSE
+;(
+; &SWLA_DUMP=0
+;)
+;dialog.end
+
+&store_folder="User define, but no space in the path"
+;AREA.RESet
+;mkdir "&store_folder"
+;cd "&store_folder"
+;=========================== +Dump MCU REGIONS+ ========================
+PRINT "Preparing to dump MCU regions..."
+[CMMAUTOGEN_DUMP_UC_COMMON_REGIONS]
+[CMMAUTOGEN_DUMP_UC_CORE_REGIONS]
+[CMMAUTOGEN_DUMP_C_COMMON_REGIONS]
+
+LOCAL &THREAD_NUM
+LOCAL &temp_addr
+LOCAL &THREAD_IDX
+LOCAL &ORG_CORE
+&temp_addr=0x0
+thread.num &temp_addr
+&THREAD_NUM=data.long(&temp_addr)
+&THREAD_NUM=&THREAD_NUM+1
+&THREAD_IDX=1
+&BYPASS=0
+&ORG_CORE=0xFF
+
+LOCAL &CORE_IDX
+LOCAL &VPE_IDX
+LOCAL &TC_IDX
+WHILE (&THREAD_IDX<&THREAD_NUM)
+(
+
+
+ ;switch thread[]
+ thread.select &THREAD_IDX
+
+ ;get core_idx, vpe_idx, tc_idx
+ thread.findcore &temp_addr
+ &CORE_IDX=data.long(&temp_addr)
+ thread.findvpe &temp_addr
+ &VPE_IDX=data.long(&temp_addr)
+ thread.findtc &temp_addr
+ &TC_IDX=data.long(&temp_addr)
+
+ ;dump core specific region
+ IF (&ORG_CORE!=&CORE_IDX)
+ (
+ GOSUB SUB_DUMP_BY_CORE &CORE_IDX
+ &ORG_CORE=&CORE_IDX
+ )
+
+ ;dump cpu registers
+ GOSUB SUB_DUMP_REG &CORE_IDX &VPE_IDX &TC_IDX
+
+ &THREAD_IDX=&THREAD_IDX+1
+)
+
+PRINT "MCU dump regions - done!"
+stop
+
+;=========================== -Dump MCU REGIONS- ========================
+
+
+
+;=========================== +Dump BBREG+ ========================
+
+
+;=========================== -Dump BBREG- ========================
+
+;=========================== +Dump SWLA+ ========================
+IF (&SWLA_DUMP==1)
+(
+ PRINT "Preparing to dump SWLA..."
+ ;GOSUB SUB_DUMP_SWLA
+)
+;=========================== -Dump SWLA- ========================
+
+
+
+
+PRINT "Dumping Finished!!! "
+
+ENDDO
+;STOP
+;END
+
+;========================================================================
+; function
+;========================================================================
+
+SUB_DUMP_CORE0_C_REGION:
+[CMMAUTOGEN_DUMP_CORE0_C_REGIONS]
+RETURN
+
+SUB_DUMP_CORE1_C_REGION:
+[CMMAUTOGEN_DUMP_CORE1_C_REGIONS]
+RETURN
+
+SUB_DUMP_CORE2_C_REGION:
+[CMMAUTOGEN_DUMP_CORE2_C_REGIONS]
+RETURN
+
+SUB_DUMP_CORE3_C_REGION:
+[CMMAUTOGEN_DUMP_CORE3_C_REGIONS]
+RETURN
+
+SUB_DUMP_BY_CORE:
+ ENTRY &CORE_NUM
+ IF (&CORE_NUM==0)
+ (
+ GOSUB SUB_DUMP_CORE0_C_REGION
+ )
+ IF (&CORE_NUM==1)
+ (
+ GOSUB SUB_DUMP_CORE1_C_REGION
+ )
+ IF (&CORE_NUM==2)
+ (
+ GOSUB SUB_DUMP_CORE2_C_REGION
+ )
+ IF (&CORE_NUM==3)
+ (
+ GOSUB SUB_DUMP_CORE3_C_REGION
+ )
+RETURN
+
+SUB_DUMP_REG:
+ ENTRY &core_id &vpe_id &tc_id
+
+ LOCAL &BIN_FILE_NAME
+ &BIN_FILE_NAME="&store_folder\mips_regs_&core_id&vpe_id&tc_id.bin"
+ ®_STORE_BASE_ADDR=0x0
+
+ GOSUB SUB_DUMP_CPU_REG ®_STORE_BASE_ADDR
+ ENTRY ®_END_ADDR
+ print "Dumping mips_regs_&core_id&vpe_id&tc_id.bin..."
+ stop
+ D.SAVE.BINARY &BIN_FILE_NAME ®_STORE_BASE_ADDR--®_END_ADDR
+
+RETURN
+
+SUB_DUMP_CPU_REG:
+ ENTRY ®_STORE_BASE_ADDR
+ ;general register
+ D.S (®_STORE_BASE_ADDR+0x0000) %LONG r(R0)
+ D.S (®_STORE_BASE_ADDR+0x0004) %LONG r(R1)
+ D.S (®_STORE_BASE_ADDR+0x0008) %LONG r(R2)
+ D.S (®_STORE_BASE_ADDR+0x000C) %LONG r(R3)
+ D.S (®_STORE_BASE_ADDR+0x0010) %LONG r(R4)
+ D.S (®_STORE_BASE_ADDR+0x0014) %LONG r(R5)
+ D.S (®_STORE_BASE_ADDR+0x0018) %LONG r(R6)
+ D.S (®_STORE_BASE_ADDR+0x001C) %LONG r(R7)
+ D.S (®_STORE_BASE_ADDR+0x0020) %LONG r(R8)
+ D.S (®_STORE_BASE_ADDR+0x0024) %LONG r(R9)
+ D.S (®_STORE_BASE_ADDR+0x0028) %LONG r(R10)
+ D.S (®_STORE_BASE_ADDR+0x002C) %LONG r(R11)
+ D.S (®_STORE_BASE_ADDR+0x0030) %LONG r(R12)
+ D.S (®_STORE_BASE_ADDR+0x0034) %LONG r(R13)
+ D.S (®_STORE_BASE_ADDR+0x0038) %LONG r(R14)
+ D.S (®_STORE_BASE_ADDR+0x003C) %LONG r(R15)
+ D.S (®_STORE_BASE_ADDR+0x0040) %LONG r(R16)
+ D.S (®_STORE_BASE_ADDR+0x0044) %LONG r(R17)
+ D.S (®_STORE_BASE_ADDR+0x0048) %LONG r(R18)
+ D.S (®_STORE_BASE_ADDR+0x004C) %LONG r(R19)
+ D.S (®_STORE_BASE_ADDR+0x0050) %LONG r(R20)
+ D.S (®_STORE_BASE_ADDR+0x0054) %LONG r(R21)
+ D.S (®_STORE_BASE_ADDR+0x0058) %LONG r(R22)
+ D.S (®_STORE_BASE_ADDR+0x005C) %LONG r(R23)
+ D.S (®_STORE_BASE_ADDR+0x0060) %LONG r(R24)
+ D.S (®_STORE_BASE_ADDR+0x0064) %LONG r(R25)
+ D.S (®_STORE_BASE_ADDR+0x0068) %LONG r(R26)
+ D.S (®_STORE_BASE_ADDR+0x006C) %LONG r(R27)
+ D.S (®_STORE_BASE_ADDR+0x0070) %LONG r(R28)
+ D.S (®_STORE_BASE_ADDR+0x0074) %LONG r(R29)
+ D.S (®_STORE_BASE_ADDR+0x0078) %LONG r(R30)
+ D.S (®_STORE_BASE_ADDR+0x007C) %LONG r(R31)
+ D.S (®_STORE_BASE_ADDR+0x0080) %LONG r(HI)
+; D.S (®_STORE_BASE_ADDR+0x0084) %LONG r(HI1)
+; D.S (®_STORE_BASE_ADDR+0x008C) %LONG r(HI2)
+; D.S (®_STORE_BASE_ADDR+0x0090) %LONG r(HI3)
+ D.S (®_STORE_BASE_ADDR+0x0094) %LONG r(LO)
+; D.S (®_STORE_BASE_ADDR+0x0098) %LONG r(LO1)
+; D.S (®_STORE_BASE_ADDR+0x00A0) %LONG r(LO2)
+; D.S (®_STORE_BASE_ADDR+0x00A4) %LONG r(LO3)
+; D.S (®_STORE_BASE_ADDR+0x00A8) %LONG r(EPC)
+; D.S (®_STORE_BASE_ADDR+0x00AC) %LONG r(EEPC)
+ D.S (®_STORE_BASE_ADDR+0x00B0) %LONG r(CAUSE)
+; D.S (®_STORE_BASE_ADDR+0x00B4) %LONG r(CNT)
+; D.S (®_STORE_BASE_ADDR+0x00B8) %LONG r(CMP)
+ D.S (®_STORE_BASE_ADDR+0x00BC) %LONG r(PC)
+; D.S (®_STORE_BASE_ADDR+0x00C0) %LONG r(SR)
+ D.S (®_STORE_BASE_ADDR+0x00C0) %LONG r(status)
+; D.S (®_STORE_BASE_ADDR+0x00C4) %LONG r(PRID)
+; D.S (®_STORE_BASE_ADDR+0x00C8) %LONG r(CNF)
+; D.S (®_STORE_BASE_ADDR+0x00CC) %LONG r(DSPC)
+local ®_END_ADDR
+®_END_ADDR=0
+®_END_ADDR = ®_STORE_BASE_ADDR+0x00CC
+RETURN ®_END_ADDR
+
+
+
+SUB_DUMP_SWLA:
+; LOCAL &BINNAME
+; &BINNAME="_sla_mem_no_header.bin"
+; IF Y.EXIST(SA_LoggingIndex)
+; (
+; &start_addr=V.VALUE(SA_LoggingStart)
+; &stop_addr=V.VALUE(SA_LoggingStop)
+; &cur_addr=V.VALUE(SA_LoggingIndex)
+; &wrap=V.VALUE((unsigned int)SA_Wrap)
+; &node_size=V.VALUE(SA_LoggingNodeSize)
+; &addon_cnt=V.VALUE(SA_AddonInfoCnt)
+; &header_size=&addon_cnt*V.SIZEOF(SA_FileHeader.addon_info[0])
+; &header_size=&header_size+V.SIZEOF(SA_FileHeader.main_desc)
+;
+; PRINT "SA_LoggingStart=0x" format.hex(8,&start_addr)
+; PRINT "SA_LoggingIndex=0x" format.hex(8,&cur_addr)
+; PRINT "SA_LoggingStop=0x" format.hex(8,&stop_addr)
+; PRINT "SA_Wrap=" &wrap
+;
+; IF (&node_size!=0)
+; (
+; IF (&wrap!=0)
+; (
+; &total_size=&stop_addr-&start_addr
+; &total_size=&total_size/&node_size
+; &total_size=&total_size*&node_size
+; &end_addr=&start_addr+&total_size
+;
+; PRINT "total_size=0x", format.hex(8,&total_size)
+; PRINT "end_addr=", format.hex(8,&end_addr)
+;
+; PRINT "dumping sla_mem_no_header.bin(part1)..."
+; data.save.binary "&store_folder\swla1.bin" &cur_addr--(&end_addr-1)
+; PRINT "dumping sla_mem_no_header.bin(part2)..."
+; data.save.binary "&store_folder\swla2.bin" &start_addr--(&cur_addr-1)
+;
+; OS.Area copy /b swla1.bin+swla2.bin &BINNAME
+; OS.Area del swla1.bin
+; OS.Area del swla2.bin
+; )
+; ELSE
+; (
+; &total_size=&cur_addr-&start_addr
+;
+; PRINT "total_size=0x" format.hex(8,&total_size)
+; PRINT "dumping &BINNAME..."
+; data.save.binary "&store_folder\&BINNAME" &start_addr--(&cur_addr-1)
+; )
+; )
+; ELSE
+; (
+; PRINT "SWLA not enabled"
+; )
+; )
+; ELSE
+; (
+; PRINT "SWLA not compiled"
+; )
+
+RETURN
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/ELBRUS/cosim/Gen_Elbrus_Bin_BASIC_COSIM.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/ELBRUS/cosim/Gen_Elbrus_Bin_BASIC_COSIM.cmm
new file mode 100644
index 0000000..a030436
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/ELBRUS/cosim/Gen_Elbrus_Bin_BASIC_COSIM.cmm
@@ -0,0 +1,99 @@
+;===============================================
+;CMM START
+;===============================================
+SETUP.BAKfile OFF
+
+; ======================
+; Reset all configuration
+; ======================
+winclear
+AREA.RESet
+AREA.Create dram
+AREA.Select dram
+AREA.view dram
+AREA.Clear dram
+SYStem.RESet //Reset all configuration
+
+; ======================
+; attach on PSCore
+; ======================
+; DO MD_P_Attach.cmm
+system.down
+;system.cpu MIPS4K
+system.cpu MIPSinterAptiv
+SYStem.OPTION Endianess little
+system.up
+
+; ======================
+; Load L1Core code
+; ======================
+; define and init elf,src,bin path
+GLOBAL &OPT_MD_P_ELF_PATH
+GLOBAL &OPT_MD_P_SRC_PATH
+GLOBAL &OPT_MD_P_BIN_PATH
+GLOBAL &L_CMM_RELATIVE_PATH
+
+;Path information
+GLOBAL &OPT_MD_ELF_PATH
+&OPT_MD_ELF_PATH="../bin/ELBRUS_FPGA_PCB01_P_ELBRUS_FPGAS00.elf"
+
+GLOBAL &OPT_MD_BIN_PATH
+&OPT_MD_BIN_PATH="../bin/sim/MD_IMAGE"
+
+GLOBAL &OPT_MD_SRC_PATH
+&OPT_MD_SRC_PATH="../../../../.."
+
+GLOBAL &CMM_RELATIVE_PATH
+&CMM_RELATIVE_PATH="../../cmm"
+
+
+;data.load.elf &OPT_MD_P_ELF_PATH
+D.LOAD.BINARY &OPT_MD_BIN_PATH
+D.LOAD.ELF &OPT_MD_ELF_PATH /RELPATH /PATH &OPT_MD_SRC_PATH /CODESEC /DWARF2 /GNU
+
+
+; ======================
+; Do region initialize
+; ======================
+;v INT_InitShareRegions()
+;v INT_InitRegions()
+
+; ======================
+; Backup 0x0 -- Image$$L1CORE_DUMP_REGION__ITCM$$Length
+; ======================
+;;GLOBAL &DSPRAM0_SIZE
+;;&DSPRAM0_SIZE=V.VALUE(&Image$$DSPRAM$$Length)
+;;data.copy 0x0--&DSPRAM0_SIZE VM:0x0
+
+; ======================
+; Save &Image$$EXTSRAM_DSP_RX$$Limit
+; ======================
+LOCAL &EXTSRAM_END
+&EXTSRAM_END=V.VALUE(&Image$$EXTSRAM_DSP_RX$$Limit)
+; ======================
+; Create ElbrusReleaseBin folder
+; ======================
+IF !OS.DIR(ElbrusReleaseBin)
+(
+ mkdir ./ElbrusReleaseBin
+)
+
+; ======================
+; dump all bins
+; ======================
+
+;;d.save.binary .\ElbrusReleaseBin\sw_emi.bin 0x00000000--&EXTSRAM_END
+d.save.binary .\ElbrusReleaseBin\sw_emi.load 0x00000000--&EXTSRAM_END
+PRINT "EXTSTAM:sw_emi.load generated"
+;;d.save.binary .\ElbrusReleaseBin\ispram_0.bin 0x9F800000--0x9F880000
+;;PRINT "CORE0:ispram_0 generated"
+;;d.save.binary .\ElbrusReleaseBin\dspram_0.bin 0x9F880000--0x9F900000
+;;PRINT "CORE0 TCM:dspram_0.bin generated"
+;;d.save.binary .\ElbrusReleaseBin\l2sram.bin Image$$L2SRAM_CODE$$Base--Image$$L2SRAM_DATA_ZI$$ZI$$Limit
+;;PRINT "L2SRAM:l2sram.bin generated"
+
+;===============================================
+;CMM END
+;===============================================
+PRINT "Init Done"
+ENDDO
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/codescape/load_all_fullload.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/codescape/load_all_fullload.py
new file mode 100644
index 0000000..9967fb8
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/codescape/load_all_fullload.py
@@ -0,0 +1,58 @@
+# <$ Name: Region Script $>
+
+import wx
+import os
+from imgtec import codescape
+from time import sleep
+
+umoly_path = ""
+class load_all_elf(wx.Frame):
+ def __init__(self, parent):
+ wx.Frame.__init__(self, parent, title="[FullLoad]LoadSymbolOnly")
+
+ # Initialize UI
+ button_width = 80
+ border_size = 5
+
+ self.load_all_elf_btn = wx.Button(self, pos=(0, 0), label='Load all', size=(button_width,-1))
+ self.Bind(wx.EVT_BUTTON, self.on_load_all_elf_button, self.load_all_elf_btn)
+
+ # load all elf
+ def on_load_all_elf_button(self, event):
+ fileDialog = wx.FileDialog(self)
+ fileDialog.ShowModal()
+ umoly_path = fileDialog.GetPath()
+ fileDialog.Destroy()
+
+ print "Start initialization ...."
+ print "Loading image: " + umoly_path
+ da = codescape.GetFirstProbe()
+
+ for core_idx in range(0, 3):
+ if(os.path.exists(umoly_path) == False):
+ print "[Error] UMOLY ELF doesn't exist: %s" %(umoly_path)
+ break
+
+ # stop all threads
+ #da.cores[core_idx].StopAll()
+
+ #set VPE0
+ thread = da.cores[core_idx].hwthreads[0]
+ #thread.Stop()
+ thread.LoadProgramFile(umoly_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE0] Load ELF successfully: %s" %(core_idx, umoly_path)
+
+ # set VPE1
+ thread = da.cores[core_idx].hwthreads[1]
+ #thread.Stop()
+ thread.LoadProgramFile(umoly_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE1] Load ELF successfully: %s" %(core_idx, umoly_path)
+
+
+ print "All loading is done"
+
+if __name__ == "__main__":
+ app = wx.App()
+ frame = load_all_elf(None);
+ frame.Show()
+ app.MainLoop()
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/codescape/load_all_modem_only.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/codescape/load_all_modem_only.py
new file mode 100644
index 0000000..7ec14e7
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/codescape/load_all_modem_only.py
@@ -0,0 +1,69 @@
+# <$ Name: Region Script $>
+
+import wx
+import os
+from imgtec import codescape
+from time import sleep
+
+umoly_path = ""
+class load_all_elf(wx.Frame):
+ def __init__(self, parent):
+ wx.Frame.__init__(self, parent, title="[ModemOnly]LoadBin&Symbol")
+
+ # Initialize UI
+ button_width = 80
+ border_size = 5
+
+ self.load_all_elf_btn = wx.Button(self, pos=(0, 0), label='Load all', size=(button_width,-1))
+ self.Bind(wx.EVT_BUTTON, self.on_load_all_elf_button, self.load_all_elf_btn)
+
+ # load all elf
+ def on_load_all_elf_button(self, event):
+ fileDialog = wx.FileDialog(self)
+ fileDialog.ShowModal()
+ umoly_path = fileDialog.GetPath()
+ fileDialog.Destroy()
+
+ print "Start initialization ...."
+ print "Loading image: " + umoly_path
+ da = codescape.GetFirstProbe()
+
+ for core_idx in range(0, 3):
+ if(os.path.exists(umoly_path) == False):
+ print "[Error] UMOLY ELF doesn't exist: %s" %(umoly_path)
+ break
+
+ # stop all threads
+ #da.cores[core_idx].StopAll()
+
+ if(core_idx == 0):
+ # load binary only on VPE0 of 0 core
+ thread = da.cores[core_idx].hwthreads[0]
+ thread.Stop()
+ thread.LoadProgramFile(umoly_path, False, 0x83, True, "")
+ print "[Core%d,VPE0] Load ELF successfully: %s" %(core_idx, umoly_path)
+
+ # set start addres
+ (sym, val) = thread.GetSymbolAndValue("INT_Vectors")
+ thread.WriteRegister('pc', val)
+ print "[Core%d,VPE0] Config PC=%s=0x%x" %(core_idx, "INT_Vectors", val)
+ else:
+ thread = da.cores[core_idx].hwthreads[0]
+ thread.Stop()
+ thread.LoadProgramFile(umoly_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE0] Load ELF successfully: %s" %(core_idx, umoly_path)
+
+ # set VPE1
+ thread = da.cores[core_idx].hwthreads[1]
+ thread.Stop()
+ thread.LoadProgramFile(umoly_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE1] Load ELF successfully: %s" %(core_idx, umoly_path)
+
+
+ print "All loading is done"
+
+if __name__ == "__main__":
+ app = wx.App()
+ frame = load_all_elf(None);
+ frame.Show()
+ app.MainLoop()
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/codescape/set_ex_breakpoint.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/codescape/set_ex_breakpoint.py
new file mode 100644
index 0000000..6e79c9e
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/codescape/set_ex_breakpoint.py
@@ -0,0 +1,45 @@
+# <$ Name: Region Script $>
+
+import wx
+import os
+from imgtec import codescape
+from time import sleep
+
+ex_stop_symbol= "general_ex_handler"
+class set_ex_bk(wx.Frame):
+ def __init__(self, parent):
+ wx.Frame.__init__(self, parent, title="Set ex_bk")
+
+ # Initialize UI
+ button_width = 80
+ border_size = 5
+
+ self.set_ex_bk_btn = wx.Button(self, pos=(0, 0), label='Set EX_BK', size=(button_width,-1))
+ self.Bind(wx.EVT_BUTTON, self.on_set_ex_bk_button, self.set_ex_bk_btn)
+
+ # set exception breakpoint
+ def on_set_ex_bk_button(self, event):
+
+ print "Start initialization ...."
+
+ da = codescape.GetFirstProbe()
+
+ for idx in range(0, 6):
+ core_idx = idx / 2
+ vpe_idx = idx % 2
+ # stop threads
+ thread = da.cores[core_idx].hwthreads[vpe_idx]
+ #thread.Stop()
+ # destroy all breakpoints
+ #bks = thread.GetBreakpoints()
+ #bks.DestroyAll()
+ # set hardware breakpoint
+ thread.CreateCodeBreakpoint(ex_stop_symbol, 2)
+ print "core %d, vpe %d set HW bkpts to %s" %(core_idx, vpe_idx, ex_stop_symbol)
+ print "All loading is done"
+
+if __name__ == "__main__":
+ app = wx.App()
+ frame = set_ex_bk(None);
+ frame.Show()
+ app.MainLoop()
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/fpga_emi_init.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/fpga_emi_init.cmm
new file mode 100755
index 0000000..e41240e
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/fpga_emi_init.cmm
@@ -0,0 +1,507 @@
+system.Method Manual
+system.cpu cortexr4
+system.multicore SWDP ON
+system.JtagClock 1MHz
+sys.m prepare
+LOCAL &TYPE
+LOCAL &BASE_MADDR_MDRGU
+IF DATA.LONG(DBG:0x41000000)==0x5BA02477 ; AP DAP
+(
+ &TYPE="EAHB"
+ &BASE_MADDR_MDRGU=0x800F0000
+)
+ELSE ; DATA.LONG(DBG:0x41000000)==0x6BA02477 ; MD DAP
+(
+ sys.m down
+ MULtiCore.DEBUGACCESSPORT 1
+ MULtiCore.AXIACCESSPORT 0
+ sys.m prepare
+ &TYPE="AXI"
+ &BASE_MADDR_MDRGU=0xA00F0000
+)
+
+; do orginal disable_WDT2_MIPS.cmm
+;&BASE_MADDR_MDRGU=0xA00F0000
+&BASE_MADDR_APRGU=0xC3670000
+D.S &TYPE:&BASE_MADDR_MDRGU+0x0100 %LE %LONG (0x55000000|data.long(&TYPE:&BASE_MADDR_MDRGU+0x0100)&~(0x3))
+D.S &TYPE:&BASE_MADDR_APRGU+0x0100 %LE %LONG (0x55000000|data.long(&TYPE:&BASE_MADDR_APRGU+0x0100)&~(0x1))
+
+; do orginal emi_init.cmm
+LOCAL &CHIP_VER ; 0 is for FPGA, 1 is for E1, and so on
+&CHIP_VER=0
+&BASE_ADDR_EMI=0xC3000000
+&BASE_ADDR_DRAMC=0xC3010000
+&BASE_ADDR_DDRPHY=0xC3020000
+&BASE_ADDR_MEMSYSAOREG_MISC=0xC3080000
+&BASE_ADDR_AP_CLKSW=0xC3750000
+
+; Check if initialize
+IF (DATA.LONG(&TYPE:&BASE_ADDR_EMI+0060)&0x00000400)==0x00000400
+(
+ PRINT "Warning: DRAM has be initialized, why ???"
+ ENDDO
+)
+
+; DRAM initialization
+GOSUB DRAM_INIT
+PRINT "DRAM initialization done !!!"
+
+
+D.S &TYPE:0x0E800000 %LE %LONG 0x00
+D.S &TYPE:0x00080000 %LE %LONG 0x00
+PRINT "Clear Dsp Header done !!!"
+
+ENDDO
+
+
+; =========================================================================================
+; Sub Function: DRAM_INIT
+; Description: initialize MEMPLL, DRAMC, DDRPHY, DRAM, EMI
+; =========================================================================================
+DRAM_INIT:
+ ; =MEMSYS_PASSWORD=
+ ; Unlock MEMSYS Password
+ D.S &TYPE:&BASE_ADDR_MEMSYSAOREG_MISC+0x3000 %LE %LONG 0x24541689
+ ;GOSUB MEMPLL_INIT
+ GOSUB DRAMC_INIT
+ GOSUB EMI_INIT
+ ; =MEMINFRA_SI_WAY_CTL=
+ ; Enable MEMINFRA EMI Path
+ ; [9:8] M7_sysram:M7_emi
+ ; [7:6] M6_sysram:M6_emi
+ ; [5:4] M4_mdmda_sysram:M4_mddma_emi
+ ; [3:2] M4_l1sys_sysram:M4_l1sys_emi
+ ; [1:0] M3_sysram:M3_emi
+ ®_val=DATA.LONG(&TYPE:&BASE_ADDR_MEMSYSAOREG_MISC+0x4000)
+ ®_val=®_val|0x00000155
+ D.S &TYPE:&BASE_ADDR_MEMSYSAOREG_MISC+0x4000 %LE %LONG ®_val
+ ; =EMI_ADDR_OFFSET=
+ ; EMI offset on address[31:24], unit is 16MB
+ &MD3_offset=0x00
+ &MD2_offset=0x00
+ &MD1_offset=0x10
+ &ap_offset=0x00
+ &emi_offset=(&MD3_offset<<0x18)+(&MD2_offset<<0x10)+(&MD1_offset<<0x08)+(&ap_offset<<0x00)
+ D.S &TYPE:&BASE_ADDR_MEMSYSAOREG_MISC+0x1000 %LE %LONG &emi_offset
+ ; =MEMSYS_PASSWORD=
+ ; Lock MEMSYS Password
+ D.S &TYPE:&BASE_ADDR_MEMSYSAOREG_MISC+0x3000 %LE %LONG 0x00000000
+ RETURN
+
+; =========================================================================================
+; Sub Function: MEMPLL_INIT
+; =========================================================================================
+MEMPLL_INIT:
+ DATA.LOAD.ELF &emi_elf_path
+ B.D /ALL
+ B.S custom_InitDRAM /HARD
+ GO
+ WAIT !RUN() 5.s
+ IF r(PC)==custom_InitDRAM
+ (
+ PRINT "MEMPLL Initialization Pass!"
+ RETURN
+ )
+ ELSE
+ (
+ PRINT "MEMPLL Initialization Failed!"
+ ENDDO
+ )
+
+; =========================================================================================
+; Sub Function: DRAMC_INIT
+; Description: initialize DRAMC, DDRPHY, and DRAM, but this function doesn't initialize EMI
+; =========================================================================================
+DRAMC_INIT:
+ ; =ACTIM0=
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0000 %LE %LONG 0x44584493
+ ; =CONF1=
+ ; [18][5][3] no use in TK6291
+ ; [9:8]MTYPE, DRAM column address width, 2'b01 (9-bit) -> 2'b10 (10-bit)
+ ; TODO: [AC Timing] 0x00048683
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0004 %LE %LONG 0xF0008681 ; 0xF0008481
+ ; =R0DELDLY=
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0018 %LE %LONG 0x10101010
+ ; =R1DELDLY=
+ ; [30:24][22:16][14:8][6:0] DQS3/2/1/0 input delay
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x001C %LE %LONG 0x12121212
+ ; =DLLCONF=
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0028 %LE %LONG 0x50000000
+ ; =TEST2_3=
+ ; [23] DQSICALI_NEW=0, using original dqs calibration
+ ; [7] TESTAUDPAT=0, ISI pattern can be set by TEST2_PAT0
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0044 %LE %LONG 0xBF080000
+ ; =TEST2_4=
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0048 %LE %LONG 0x1601110D
+ ; =DDR2CTL=
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x007C %LE %LONG 0x00003201
+ ; =MISC=
+ ; [23:21]: PHYRXDSL_PIPE3~1 are pipe stage selection for RDATA and RDSEL
+ ; DATLAT_DSEL = DATLAT - 2*2 when enabling two top pipe (for TK6291)
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0080 %LE %LONG 0x00AC08A0
+ ; =ZQCS=
+ ; [15:8]: ZQCSAD, [7:0]: ZQCSOP
+ ®_val=DATA.LONG(&TYPE:&BASE_ADDR_DRAMC+0x0084)&~0x0000FFFF
+ ®_val=®_val|0x00000A56
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0084 %LE %LONG ®_val
+ ; =CLK1DELAY=
+ ; [23]: PHYPIPE3EN, [22]: PHYPIPE2EN, [21]: PHYPIPE1EN
+ ®_val=DATA.LONG(&TYPE:&BASE_ADDR_DRAMC+0x008C)&~0x00E00000
+ ®_val=®_val|0x00A00000
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x008C %LE %LONG ®_val
+ ; =R0DQSIEN=
+ ; Gating Window for Rank0
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0094 %LE %LONG 0x31313131
+ ; =MCKDLY=
+ ; [23]: WODT has no load (useless)
+ ; [21]: DRAMEN has no load (useless)
+ ; [11:10] DQIENQKEND: DQ/DQS input enable window is larger than 6582. [11:10]=2'b00 => dle counter is 5'1f. =Others => dle counter is DATLAT-[11:10]+2
+ ; [4] DQIENLATEBEGIN, disable early begin, better for power saving
+ ; TODO: [20]: It is used for BST(Bus Termination), but TK6291 doesn't support the feature
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x00D8 %LE %LONG 0x40500510
+ ; =DQSCTL1=
+ ; [27:24]: DQSINCTL, DQS input range control by M_CK
+ ; [23:12][11:0]: DQS3CTL/DQS2CTL, control by DDRPHY (useless)
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x00E0 %LE %LONG 0x12200200
+ ; =GDDR3CTL1=
+ ; [24]: 8BKEN=1, 8-bank device enable
+ ®_val=DATA.LONG(&TYPE:&BASE_ADDR_DRAMC+0x00F4)|0x01000000
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x00F4 %LE %LONG ®_val
+ ; [28]: PHYSYNCM=1, SYNC MODE using inverted PHY_M_CK
+ ®_val=DATA.LONG(&TYPE:&BASE_ADDR_DDRPHY+0x00F4)|0x10000000
+ D.S &TYPE:&BASE_ADDR_DDRPHY+0x00F4 %LE %LONG ®_val
+ ; =MISCTL0=
+ ; [31]: REFP_ARB_EN2: per-bank refresh arbitration mask2
+ ; [30:28]: TXP, tXP Timing setting
+ ; [27] EMIPREEN: Enable advanced precharge function by EMI side-band signals, but TK6291 didn't support this feature.
+ ; [26] REFP_ARB_EN: per-bank refresh blocks in EMI arbitration
+ ; [25] REFA_ARB_EN: all-bank refresh blocks in EMI arbitration
+ ; [24] PBC_ARB_EN: block page-miss requests in EMI arbitration
+ ; [21]: REFA_ARB_EN2: all bank refresh arbtration mask enable option
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x00FC %LE %LONG 0x81080000
+ ; [17]: INTLBT=0, IO internal loop back (useless for TK6291)
+ ; [16]: RXLPDDR2=0, IO voltage operating condition = {0:1.2V, 1:1.8V}
+ ®_val=DATA.LONG(&TYPE:&BASE_ADDR_DDRPHY+0x00FC)&~0x00030000
+ D.S &TYPE:&BASE_ADDR_DDRPHY+0x00FC %LE %LONG ®_val
+ ; =OCDK=
+ ; [24]: DRVREF=1, drving change only when refresh cycle
+ ; [15]: DRDELSWEN=1, enable DQS input delay switching for different ranks
+ ; [8]: AUTOCALDRV=1, OCD calibration enable
+ ; [7:0]: AUTOKCNT, auto calibration counter
+ ; =RKCFG=
+ ; [7]: per-bank refresh for LPDDR2&3
+ ; TODO: [AC Timing] 0x004135C0
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0110 %LE %LONG 0x004121C0
+ ; =DQSCTL2=
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0118 %LE %LONG 0x00000002
+ ; =DQSGCTL=
+ ; [7:0] Old gating window course tune
+ ®_val=DATA.LONG(&TYPE:&BASE_ADDR_DRAMC+0x0124)&~0x000000FF
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0124 %LE %LONG ®_val
+ ; [31]: NEWDQSG_SEL, [30]:DQSGDUALP
+ ®_val=DATA.LONG(&TYPE:&BASE_ADDR_DDRPHY+0x0124)|0xC0000000
+ D.S &TYPE:&BASE_ADDR_DDRPHY+0x0124 %LE %LONG ®_val
+ ; =CLKCTRL=
+ ; [29]: CLK_EN_1, [28]: CLK_EN_0
+ ; TODO: we should only enable one CLK for TK6291
+ ®_val=DATA.LONG(&TYPE:&BASE_ADDR_DRAMC+0x0130)|0x30000000
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0130 %LE %LONG ®_val
+ ; =ARBCTL0=
+ ; [7:0]: maximum pending number to block the arbitration
+ ®_val=DATA.LONG(&TYPE:&BASE_ADDR_DRAMC+0x0168)&~0x000000FF
+ ®_val=®_val|0x00000080
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0168 %LE %LONG ®_val
+ ; =DQSCAL0=
+ ; [31]: DQS strobe calibration enable
+ ; [30]: Update tracking gating value to 2 ranks simultaneously
+ ; [15]: Rank0 DQS strobe calibration high-limit enable
+ ; [14:8]: Rank0 DQS strobe calibration high-limit value
+ ; [7]: Rank0 DQS strobe calibration low-limit enable
+ ; [6:0]: Rank0 DQS strobe calibration low-limit value
+ ®_val=DATA.LONG(&TYPE:&BASE_ADDR_DRAMC+0x01C0)&~0xC000FFFF
+ ®_val=®_val|0x80000000
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x01C0 %LE %LONG ®_val
+ ; =MEMSYSPIPE_CGF_CTL=
+ ; [2]: PIPE_CFG_EN, [0]: DRAMC_CFG_EN
+ ; PIPE_CGF_ON=0 (timing issue) EMI_CGF_ON=0(Gated function is already designed in EMI) DRAMC_CGF_ON=1
+ D.S &TYPE:&BASE_ADDR_MEMSYSAOREG_MISC+0x5000 %LE %LONG 0x00000001
+ ; =DRAMC_PD_CTRL=
+ ; [24] REFFRERUN, using freerun clock to count refresh period
+ ; [23:16] REFCNT_FR_CLK, refresh period based on DRAMC freerun clock cycles
+ ; [15:8] TXREFCNT, tXSR
+ IF &CHIP_VER==0
+ (
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x01DC %LE %LONG 0xC2002340
+ )
+ ELSE
+ (
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x01DC %LE %LONG 0xC3002340
+ )
+ ; =LPDDR2_3=
+ ; TODO: should set to 0x10000000, not 0x3600_0000?
+ ; [31]: DRAM address decode by DRAMC
+ ; [28]: LPDDR2 enable
+ ; [27]: enable register output data by DRAMC
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x01E0 %LE %LONG 0x36000000
+ ; [30]: Select IO O1 as output
+ ; [29&25:24&22:0]: DDR mode for pins
+ ; [26]: fast IO output enable
+ D.S &TYPE:&BASE_ADDR_DDRPHY+0x01E0 %LE %LONG 0x2601FFFF
+ ; =ACTIM1=
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x01E8 %LE %LONG 0x81000510
+ ; =PERFCTL0=
+ ; [0] dual schedulers
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x01EC %LE %LONG 0x0010CF11
+ ; TODO: AC_DERATING [0x01F0]
+ ; =RRRATE_CTL=, =MRR_CTL=
+ IF &CHIP_VER==0 ; Or LPDDR3
+ (
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x01F4 %LE %LONG 0x03020100
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x01Fc %LE %LONG 0x07060504
+ )
+ ELSE
+ (
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x01F4 %LE %LONG 0x02030100
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x01Fc %LE %LONG 0x04060705
+ )
+ ; =AC_TIME_05T=
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x01F8 %LE %LONG 0x04002600
+ ; =LPDDR2_4=
+ ; clock 1x phase selection
+ D.S &TYPE:&BASE_ADDR_DDRPHY+0x023C %LE %LONG 0x2201FFFF
+ ; =SELPH1=
+ ; TX 1x clock delay for CS1, RAS, CAS, WE, RESET, ODT, CKE, and CS
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0400 %LE %LONG 0x00000000
+ ; =SELPH2=
+ ; TX 1x clock delay for CKE1, DQSGATE_P1, CMD, DQSGATE, BA[2:0]
+ IF &CHIP_VER==0
+ (
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0404 %LE %LONG 0x00302000
+ )
+ ELSE
+ (
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0404 %LE %LONG 0x00101000
+ )
+ ; =SELPH3=
+ ; TX 1x clock delay for RA[7:0]
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0408 %LE %LONG 0x00000000
+ ; =SELPH4=
+ ; TX 1x clock delay for RA[15:8]
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x040C %LE %LONG 0x00000000
+ ; =SELPH5=
+ ; TX 0.5's 2x clock delay for CKE1, DQSGATE_P1, DQSGATE, BA[2:0], CS1, RAS, CAS, WE, RESET, ODT, CKE, CS
+ IF &CHIP_VER==0
+ (
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0410 %LE %LONG 0x00955555
+ )
+ ELSE
+ (
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0410 %LE %LONG 0x57755555
+ )
+ ; TODO: SELPH6 [0x0414]
+ ; =SELPH6_1=
+ ; TX 1x clock delay for DQSGATE_P1 and DQSGATE of rank1
+ ; TX 0.5's 2x clock delay for DQSGATE_P1 and DQSGATE of rank1
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0418 %LE %LONG 0x00000228
+ ; =SELPH7=
+ ; TX 1x clock delay for DQ byte output enable[3:0] and DQ byte[3:0]
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x041C %LE %LONG 0x11111111
+ ; =SELPH8=
+ ; TX 1x clock delay for DQM byte output enable[3:0] and DQM byte[3:0]
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0420 %LE %LONG 0x11111111
+ ; =SELPH9=
+ ; TX 1x clock delay for DQS byte output enable[3:0] and DQS byte[3:0]
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0424 %LE %LONG 0x11111111
+ ; =SELPH10=
+ ; TX 0.5's 2x clock delay for DQM output enable[3:0], DQ byte output enable[3:0], DQM[3:0], and DQ byte[3:0]
+ ; TODO: why we let output enable extra more 1.5 T not 0.5 DRAM clock?
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0428 %LE %LONG 0x0000FFFF
+ ; =SELPH11=
+ ; TX 0.5's 2x clock delay for DQS output enable[3:0] and DQS[3:0]
+ ; TODO: why we let output enable extra more 1.5 T not 0.5 DRAM clock?
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x042C %LE %LONG 0x000000FF
+ ; TODO: offset 0x430~0x438, Don't we need to set clock 05x phase selection?
+ ; =SELPH12=
+ ; clock 05x phase selection for CLK, DQSGATE, DQS[3:0], and DQM[3:0]
+ ; clock 1x phase selection for DQS[3:0], DQM[3:0], CLK, and DQSGATE
+ D.S &TYPE:&BASE_ADDR_DDRPHY+0x0430 %LE %LONG 0x10F010F0
+ ; =SELPH13=
+ ; clock 1x phase selection for DQ[31:0]
+ D.S &TYPE:&BASE_ADDR_DDRPHY+0x0434 %LE %LONG 0xFFFFFFFF
+ ; =SELPH14=
+ ; clock 05x phase selection for DQ[31:0]
+ D.S &TYPE:&BASE_ADDR_DDRPHY+0x0438 %LE %LONG 0xFFFFFFFF
+ ; =SELPH15=
+ ; OCV (On-Chip Variation that affect by PVT). It is removed in TK6291.
+ ; OCV mode for DQSGATE, DQS[3:0], DQ[31:0], CLK, and CA
+ D.S &TYPE:&BASE_ADDR_DDRPHY+0x043C %LE %LONG 0x0000001F
+ ; =MEMPLL_DIVIDER=
+ ; DDRPHY reset flow for 1X clock phase sync
+ ; [5]: MEMCLKENB, SW control. It is used for MEMPLL initialization. After initialization, CLKENB is controlled by HW mode.
+ ; [4]: RG_DMSS_PWDB, ALLCLK_EN. It is used for gated MEMPLL output during initialization. (=1 after initilization)
+ ; [0]: MEMCLKENB_SEL, memory clock sync enable bar selection, selection for [5] (=1 select[5])
+ IF &CHIP_VER!=0
+ (
+ ®_val=DATA.LONG(&TYPE:&BASE_ADDR_DDRPHY+0x0640)|0x00000031
+ D.S &TYPE:&BASE_ADDR_DDRPHY+0x0640 %LE %LONG ®_val
+ )
+ ; TODO: wait 500 sys_clock equal to 1.87us?
+ WAIT 2.us
+ GOSUB LPDDR2_INIT
+ IF &CHIP_VER==0
+ (
+ ; =CONF2=
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0008 %LE %LONG 0x0000631F
+ ; =DRAMC_PD_CTRL=
+ ;®_val=DATA.LONG(&TYPE:&BASE_ADDR_DRAMC+0x01DC)&~0x00FF0000
+ ;®_val=®_val|0x00350000
+ ;D.S &TYPE:&BASE_ADDR_DRAMC+0x01DC %LE %LONG ®_val
+ )
+ ELSE
+ (
+ ; =CONF2=
+ ; [23] FREBW_FREN, tREFBW use xtal clock counter enable
+ ; [17:8] FREBW_FR, 6720ns/(XTALFR_clock)-1
+ ; [7:0] REFCNT: AC Timing Calculation is 0x3F, but ESL use 0x3B
+ ; TODO: [AC Timing] 0x0000003F
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0008 %LE %LONG 0x03806D3B
+ ; =DRAMC_PD_CTRL=
+ ; [23:16] REFCNT_FR_CLK, refresh period based on DRAMC freerun clock cycles
+ ®_val=DATA.LONG(&TYPE:&BASE_ADDR_DRAMC+0x01DC)&~0x00FF0000
+ ®_val=®_val|0x00640000
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x01DC %LE %LONG ®_val
+ )
+ RETURN
+
+; =========================================================================================
+; Sub Function: EMI_INIT
+; =========================================================================================
+EMI_INIT:
+ ; =EMI_CONA=
+ ; [27]: RANK_POS=0, {rank,row,bank,col}
+ ; [17]: DUAL_RANK_EN=0
+ ; [15:14][13:12]: ROW2ND=1,ROW=1, 14-bit row address
+ ; [7:6][5:4]: COL2ND=1,COL=1, 10-bit column address
+ ; [1]: DW32_EN=1, 32-bit data bus
+ D.S &TYPE:&BASE_ADDR_EMI+0x0000 %LE %LONG 0x00005052
+ ; =EMI_ARBI=
+ D.S &TYPE:&BASE_ADDR_EMI+0x0140 %LE %LONG 0x20406188
+ ; =EMI_ARBI_2ND=
+ D.S &TYPE:&BASE_ADDR_EMI+0x0144 %LE %LONG 0x20406188
+ ; =EMI_ARBD=
+ D.S &TYPE:&BASE_ADDR_EMI+0x0118 %LE %LONG 0x0700704C
+ ; =EMI_ARBE=
+ D.S &TYPE:&BASE_ADDR_EMI+0x0120 %LE %LONG 0x40407068
+ ; =EMI_ARBG=
+ D.S &TYPE:&BASE_ADDR_EMI+0x0130 %LE %LONG 0xFFFF7045
+ ; =EMI_ARBH=
+ D.S &TYPE:&BASE_ADDR_EMI+0x0138 %LE %LONG 0xA0A07047
+ ; TODO: CSR is not defined?
+ D.S &TYPE:&BASE_ADDR_EMI+0x0040 %LE %LONG 0x80808807
+ ; =EMI_ARBJ=
+ ; TODO: it is not defined in CSRv0.9
+ D.S &TYPE:&BASE_ADDR_EMI+0x0148 %LE %LONG 0x9719595E
+ ; =EMI_ARBJ_2ND=
+ ; TODO: it is not defined in CSRv0.9
+ D.S &TYPE:&BASE_ADDR_EMI+0x014C %LE %LONG 0x9719595E
+ ; =EMI_TEST_D=
+ D.S &TYPE:&BASE_ADDR_EMI+0x00F8 %LE %LONG 0x00000000
+ ; =EMI_BMEN=
+ ; TODO: why do we need to enable BUS_MON_EN for DRAM Init?
+ D.S &TYPE:&BASE_ADDR_EMI+0x0400 %LE %LONG 0x00FF0001
+ ; =EMI_CONB=
+ D.S &TYPE:&BASE_ADDR_EMI+0x0008 %LE %LONG 0x17283544
+ ; =EMI_CONC=
+ D.S &TYPE:&BASE_ADDR_EMI+0x0010 %LE %LONG 0x0A1A0B1A
+ ; TODO: offset 0x18 is not defined in CSR.
+ D.S &TYPE:&BASE_ADDR_EMI+0x0018 %LE %LONG 0x00000000
+ ; =EMI_CONE=
+ ; TODO: it is not defined in CSRv0.9
+ D.S &TYPE:&BASE_ADDR_EMI+0x0020 %LE %LONG 0xFFFF0848
+ ; =EMI_CONG=
+ D.S &TYPE:&BASE_ADDR_EMI+0x0030 %LE %LONG 0x2B2B2A38
+ ; =EMI_CONH=
+ D.S &TYPE:&BASE_ADDR_EMI+0x0038 %LE %LONG 0x00000000
+ ; =EMI_SLCT=
+ ; TODO: Why do we enable [17]:M1_LLAT_EN?
+ D.S &TYPE:&BASE_ADDR_EMI+0x0158 %LE %LONG 0xFF02FF00
+ ; =EMI_MDCT=
+ ; TODO: why don't we enable [14]:MDMCU_SBR_EN and [12]:ULTRA_SBR_EN?
+ D.S &TYPE:&BASE_ADDR_EMI+0x0078 %LE %LONG 0x002F0C17
+ ; TODO: it is not defined in CSR.
+ D.S &TYPE:&BASE_ADDR_EMI+0x015C %LE %LONG 0x80030303
+ ; =EMI_EMI_ARBK=
+ ; TODO: it only defines [23:16] in CSRv0.9
+ D.S &TYPE:&BASE_ADDR_EMI+0x0150 %LE %LONG 0x64F3FC79
+ ; =EMI_ARBK_2ND=
+ ; TODO: it is not defined in CSRv0.9
+ D.S &TYPE:&BASE_ADDR_EMI+0x0154 %LE %LONG 0x64F3FC79
+ ; =EMI_TESTC=
+ ; TODO: it only enables [16:8] in CSRv0.9
+ D.S &TYPE:&BASE_ADDR_EMI+0x00F0 %LE %LONG 0x38470000
+ ; =EMI_TESTB=
+ ; TODO: it didn't define [2:0] in CSRv0.9
+ D.S &TYPE:&BASE_ADDR_EMI+0x00E8 %LE %LONG 0x00020027
+ // Enable slave error
+ D.S &TYPE:&BASE_ADDR_EMI+0x01C0 %LE %LONG 0x10000000
+ D.S &TYPE:&BASE_ADDR_EMI+0x01C8 %LE %LONG 0x10000000
+ D.S &TYPE:&BASE_ADDR_EMI+0x01D0 %LE %LONG 0x10000000
+ D.S &TYPE:&BASE_ADDR_EMI+0x0200 %LE %LONG 0x10000000
+ D.S &TYPE:&BASE_ADDR_EMI+0x02C0 %LE %LONG 0x10000000
+ D.S &TYPE:&BASE_ADDR_EMI+0x02C8 %LE %LONG 0x10000000
+ D.S &TYPE:&BASE_ADDR_EMI+0x02D0 %LE %LONG 0x10000000
+ D.S &TYPE:&BASE_ADDR_EMI+0x0300 %LE %LONG 0x10000000
+ ; =EMI_CONM=
+ ; [10]: EMI_ENABLE=1
+ D.S &TYPE:&BASE_ADDR_EMI+0x0060 %LE %LONG 0x000006B8
+ ; =EMI_ARBP=
+ ; EBM_MODE enable
+ D.S &TYPE:&BASE_ADDR_EMI+0x0A20 %LE %LONG 0x00010000
+ RETURN
+
+; =========================================================================================
+; Sub Function: LPDDR2_INIT
+; =========================================================================================
+LPDDR2_INIT:
+ ; =PADCTL4=
+ ; [2]: CKE always on, [0]: CKE control by controller
+ ; CKE always on
+ ®_val=DATA.LONG(&TYPE:&BASE_ADDR_DRAMC+0x00E4)|0x00000005
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x00E4 %LE %LONG ®_val
+ WAIT 200.us
+ ; LPDDR2 MRW RESET
+ GOSUB DRAMC_MRW 0x0000003F
+ WAIT 10.us
+ ; ZQ Init
+ GOSUB DRAMC_MRW 0x00FF000A
+ ; TODO: wait 1us after ZQ Initialization
+ WAIT 1.us
+ ; MRW MR1 => BL8, Sequential, Wrap, nWR=8
+ GOSUB DRAMC_MRW 0x00C30001
+ ; MRW MR2 => RL=8 and WL=4 for DDR1066
+ GOSUB DRAMC_MRW 0x00060002
+ ; MRW MR3 => 40-ohm typical
+ GOSUB DRAMC_MRW 0x00020003
+ ; =PADCTL4=
+ ; [2]: CKE always on, [0]: CKE control by controller
+ ; CKE is controlled by hardware
+ ®_val=DATA.LONG(&TYPE:&BASE_ADDR_DRAMC+0x00E4)&~0x00000004
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x00E4 %LE %LONG ®_val
+ RETURN
+
+; =========================================================================================
+; Sub Function: DRAMC_MRW
+; Description: DRAMC Mode Register Write
+; argument:
+; @mrs mode register write value
+; =========================================================================================
+DRAMC_MRW:
+ ENTRY &mrs
+ LOCAL &spcmd
+ &spcmd=0x00000001
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x0088 %LE %LONG &mrs
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x01E4 %LE %LONG &spcmd
+ WAIT (DATA.LONG(&TYPE:&BASE_ADDR_DRAMC+0x03B8)&(&spcmd))==&spcmd
+ D.S &TYPE:&BASE_ADDR_DRAMC+0x01E4 %LE %LONG 0x00000000
+ WAIT (DATA.LONG(&TYPE:&BASE_ADDR_DRAMC+0x03B8)&(&spcmd))==0x00000000
+ RETURN
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/fpga_emi_init.gdb b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/fpga_emi_init.gdb
new file mode 100755
index 0000000..0eb051d
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/fpga_emi_init.gdb
@@ -0,0 +1,522 @@
+set $CHIP_VER = 0
+set $BASE_ADDR_EMI = 0xC3000000
+set $BASE_ADDR_DRAMC = 0xC3010000
+set $BASE_ADDR_DDRPHY = 0xC3020000
+set $BASE_ADDR_MEMSYSAOREG_MISC = 0xC3080000
+set $BASE_ADDR_AP_CLKSW = 0xC3750000
+
+define delay_f32k
+ set $tgt = *0xa00d0850 + $arg0
+ while *0xa00d0850 <= $tgt
+ end
+end
+
+define DRAM_INIT
+ if (*($BASE_ADDR_EMI+0x0060) & 0x00000400) == 0x00000400
+ echo Warning: DRAM has be initialized, why ???\n
+ else
+ # =MEMSYS_PASSWORD=
+ # Unlock MEMSYS Password
+ set *($BASE_ADDR_MEMSYSAOREG_MISC+0x3000) = 0x24541689
+ DRAMC_INIT
+ EMI_INIT
+ MEMSYS_INIT
+ # =MEMSYS_PASSWORD=
+ # Lock MEMSYS Password
+ set *($BASE_ADDR_MEMSYSAOREG_MISC+0x3000) = 0x00000000
+ end
+end
+
+define DRAMC_INIT
+ echo DRAMC_INIT ...\n
+ # =ACTIM0=
+ set *($BASE_ADDR_DRAMC+0x0000) = 0x44584493
+ # =CONF1=
+ # [18][5][3] no use in TK6291
+ # [9:8]MTYPE, DRAM column address width, 2'b01 (9-bit) -> 2'b10 (10-bit)
+ # TODO: [AC Timing] 0x00048683 # 0xF0008481
+ set *($BASE_ADDR_DRAMC+0x0004) = 0xF0008681
+ # =R0DELDLY=
+ set *($BASE_ADDR_DRAMC+0x0018) = 0x10101010
+ # =R1DELDLY=
+ # [30:24][22:16][14:8][6:0] DQS3/2/1/0 input delay
+ set *($BASE_ADDR_DRAMC+0x001C) = 0x12121212
+ # =DLLCONF=
+ set *($BASE_ADDR_DRAMC+0x0028) = 0x50000000
+ # =TEST2_3=
+ # [23] DQSICALI_NEW=0, using original dqs calibration
+ # [7] TESTAUDPAT=0, ISI pattern can be set by TEST2_PAT0
+ set *($BASE_ADDR_DRAMC+0x0044) = 0xBF080000
+ # =TEST2_4=
+ set *($BASE_ADDR_DRAMC+0x0048) = 0x1601110D
+ # =DDR2CTL=
+ set *($BASE_ADDR_DRAMC+0x007C) = 0x00003201
+ # =MISC=
+ # [23:21]: PHYRXDSL_PIPE3~1 are pipe stage selection for RDATA and RDSEL
+ # DATLAT_DSEL = DATLAT - 2*2 when enabling two top pipe (for TK6291)
+ set *($BASE_ADDR_DRAMC+0x0080) = 0x00AC08A0
+ # =ZQCS=
+ # [15:8]: ZQCSAD, [7:0]: ZQCSOP
+ set $reg_val = *($BASE_ADDR_DRAMC+0x0084) & ~0x0000FFFF
+ set $reg_val = $reg_val | 0x00000A56
+ set *($BASE_ADDR_DRAMC+0x0084) = $reg_val
+ # =CLK1DELAY=
+ # [23]: PHYPIPE3EN, [22]: PHYPIPE2EN, [21]: PHYPIPE1EN
+ set $reg_val = *($BASE_ADDR_DRAMC+0x008C) & ~0x00E00000
+ set $reg_val = $reg_val | 0x00A00000
+ set *($BASE_ADDR_DRAMC+0x008C) = $reg_val
+ # =R0DQSIEN=
+ # Gating Window for Rank0
+ set *($BASE_ADDR_DRAMC+0x0094) = 0x31313131
+ # =MCKDLY=
+ # [23]: WODT has no load (useless)
+ # [21]: DRAMEN has no load (useless)
+ # [11:10] DQIENQKEND: DQ/DQS input enable window is larger than 6582. [11:10]=2'b00 => dle counter is 5'1f. =Others => dle counter is DATLAT-[11:10]+2
+ # [4] DQIENLATEBEGIN, disable early begin, better for power saving
+ # TODO: [20]: It is used for BST(Bus Termination), but TK6291 doesn't support the feature
+ set *($BASE_ADDR_DRAMC+0x00D8) = 0x40500510
+ # =DQSCTL1=
+ # [27:24]: DQSINCTL, DQS input range control by M_CK
+ # [23:12][11:0]: DQS3CTL/DQS2CTL, control by DDRPHY (useless)
+ set *($BASE_ADDR_DRAMC+0x00E0) = 0x12200200
+ # =GDDR3CTL1=
+ # [24]: 8BKEN=1, 8-bank device enable
+ set $reg_val = *($BASE_ADDR_DRAMC+0x00F4) | 0x01000000
+ set *($BASE_ADDR_DRAMC+0x00F4) = $reg_val
+ # [28]: PHYSYNCM=1, SYNC MODE using inverted PHY_M_CK
+ set $reg_val = *($BASE_ADDR_DDRPHY+0x00F4) | 0x10000000
+ set *($BASE_ADDR_DDRPHY+0x00F4) = $reg_val
+ # =MISCTL0=
+ # [31]: REFP_ARB_EN2: per-bank refresh arbitration mask2
+ # [30:28]: TXP, tXP Timing setting
+ # [27] EMIPREEN: Enable advanced precharge function by EMI side-band signals, but TK6291 didn't support this feature.
+ # [26] REFP_ARB_EN: per-bank refresh blocks in EMI arbitration
+ # [25] REFA_ARB_EN: all-bank refresh blocks in EMI arbitration
+ # [24] PBC_ARB_EN: block page-miss requests in EMI arbitration
+ # [21]: REFA_ARB_EN2: all bank refresh arbtration mask enable option
+ set *($BASE_ADDR_DRAMC+0x00FC) = 0x81080000
+ # [17]: INTLBT=0, IO internal loop back (useless for TK6291)
+ # [16]: RXLPDDR2=0, IO voltage operating condition = {0:1.2V, 1:1.8V}
+ set $reg_val = *($BASE_ADDR_DDRPHY+0x00FC) & ~0x00030000
+ set *($BASE_ADDR_DDRPHY+0x00FC) = $reg_val
+ # =OCDK=
+ # [24]: DRVREF=1, drving change only when refresh cycle
+ # [15]: DRDELSWEN=1, enable DQS input delay switching for different ranks
+ # [8]: AUTOCALDRV=1, OCD calibration enable
+ # [7:0]: AUTOKCNT, auto calibration counter
+ # =RKCFG=
+ # [7]: per-bank refresh for LPDDR2&3
+ # TODO: [AC Timing] 0x004135C0
+ set *($BASE_ADDR_DRAMC+0x0110) = 0x004121C0
+ # =DQSCTL2=
+ set *($BASE_ADDR_DRAMC+0x0118) = 0x00000002
+ # =DQSGCTL=
+ # [7:0] Old gating window course tune
+ set $reg_val = *($BASE_ADDR_DRAMC+0x0124) & ~0x000000FF
+ set *($BASE_ADDR_DRAMC+0x0124) = $reg_val
+ # [31]: NEWDQSG_SEL, [30]:DQSGDUALP
+ set $reg_val = *($BASE_ADDR_DDRPHY+0x0124) | 0xC0000000
+ set *($BASE_ADDR_DDRPHY+0x0124) = $reg_val
+ # =CLKCTRL=
+ # [29]: CLK_EN_1, [28]: CLK_EN_0
+ # TODO: we should only enable one CLK for TK6291
+ set $reg_val = *($BASE_ADDR_DRAMC+0x0130) | 0x30000000
+ set *($BASE_ADDR_DRAMC+0x0130) = $reg_val
+ # =ARBCTL0=
+ # [7:0]: maximum pending number to block the arbitration
+ set $reg_val = *($BASE_ADDR_DRAMC+0x0168) & ~0x000000FF
+ set $reg_val = $reg_val | 0x00000080
+ set *($BASE_ADDR_DRAMC+0x0168) = $reg_val
+ # =DQSCAL0=
+ # [31]: DQS strobe calibration enable
+ # [30]: Update tracking gating value to 2 ranks simultaneously
+ # [15]: Rank0 DQS strobe calibration high-limit enable
+ # [14:8]: Rank0 DQS strobe calibration high-limit value
+ # [7]: Rank0 DQS strobe calibration low-limit enable
+ # [6:0]: Rank0 DQS strobe calibration low-limit value
+ set $reg_val = *($BASE_ADDR_DRAMC+0x01C0) & ~0xC000FFFF
+ set $reg_val = $reg_val | 0x80000000
+ set *($BASE_ADDR_DRAMC+0x01C0) = $reg_val
+ # =MEMSYSPIPE_CGF_CTL=
+ # [2]: PIPE_CFG_EN, [0]: DRAMC_CFG_EN
+ # PIPE_CGF_ON=0 (timing issue) EMI_CGF_ON=0(Gated function is already designed in EMI) DRAMC_CGF_ON=1
+ set *($BASE_ADDR_MEMSYSAOREG_MISC+0x5000) = 0x00000001
+ # =DRAMC_PD_CTRL=
+ # [24] REFFRERUN, using freerun clock to count refresh period
+ # [23:16] REFCNT_FR_CLK, refresh period based on DRAMC freerun clock cycles
+ # [15:8] TXREFCNT, tXSR
+ if $CHIP_VER == 0
+ set *($BASE_ADDR_DRAMC+0x01DC) = 0xC2002340
+ else
+ set *($BASE_ADDR_DRAMC+0x01DC) = 0xC3002340
+ end
+ # =LPDDR2_3=
+ # TODO: should set to 0x10000000, not 0x3600_0000?
+ # [31]: DRAM address decode by DRAMC
+ # [28]: LPDDR2 enable
+ # [27]: enable register output data by DRAMC
+ set *($BASE_ADDR_DRAMC+0x01E0) = 0x36000000
+ # [30]: Select IO O1 as output
+ # [29&25:24&22:0]: DDR mode for pins
+ # [26]: fast IO output enable
+ set *($BASE_ADDR_DDRPHY+0x01E0) = 0x2601FFFF
+ # =ACTIM1=
+ set *($BASE_ADDR_DRAMC+0x01E8) = 0x81000510
+ # =PERFCTL0=
+ # [0] dual schedulers
+ set *($BASE_ADDR_DRAMC+0x01EC) = 0x0010CF11
+ # TODO: AC_DERATING [0x01F0]
+ # =RRRATE_CTL=, =MRR_CTL= # Or LPDDR3
+ if $CHIP_VER == 0
+ set *($BASE_ADDR_DRAMC+0x01F4) = 0x03020100
+ set *($BASE_ADDR_DRAMC+0x01Fc) = 0x07060504
+ else
+ set *($BASE_ADDR_DRAMC+0x01F4) = 0x02030100
+ set *($BASE_ADDR_DRAMC+0x01Fc) = 0x04060705
+ end
+ # =AC_TIME_05T=
+ set *($BASE_ADDR_DRAMC+0x01F8) = 0x04002600
+ # =LPDDR2_4=
+ # clock 1x phase selection
+ set *($BASE_ADDR_DDRPHY+0x023C) = 0x2201FFFF
+ # =SELPH1=
+ # TX 1x clock delay for CS1, RAS, CAS, WE, RESET, ODT, CKE, and CS
+ set *($BASE_ADDR_DRAMC+0x0400) = 0x00000000
+ # =SELPH2=
+ # TX 1x clock delay for CKE1, DQSGATE_P1, CMD, DQSGATE, BA[2:0]
+ if $CHIP_VER == 0
+ set *($BASE_ADDR_DRAMC+0x0404) = 0x00302000
+ else
+ set *($BASE_ADDR_DRAMC+0x0404) = 0x00101000
+ end
+ # =SELPH3=
+ # TX 1x clock delay for RA[7:0]
+ set *($BASE_ADDR_DRAMC+0x0408) = 0x00000000
+ # =SELPH4=
+ # TX 1x clock delay for RA[15:8]
+ set *($BASE_ADDR_DRAMC+0x040C) = 0x00000000
+ # =SELPH5=
+ # TX 0.5's 2x clock delay for CKE1, DQSGATE_P1, DQSGATE, BA[2:0], CS1, RAS, CAS, WE, RESET, ODT, CKE, CS
+ if $CHIP_VER == 0
+ set *($BASE_ADDR_DRAMC+0x0410) = 0x00955555
+ else
+ set *($BASE_ADDR_DRAMC+0x0410) = 0x57755555
+ end
+ # TODO: SELPH6 [0x0414]
+ # =SELPH6_1=
+ # TX 1x clock delay for DQSGATE_P1 and DQSGATE of rank1
+ # TX 0.5's 2x clock delay for DQSGATE_P1 and DQSGATE of rank1
+ set *($BASE_ADDR_DRAMC+0x0418) = 0x00000228
+ # =SELPH7=
+ # TX 1x clock delay for DQ byte output enable[3:0] and DQ byte[3:0]
+ set *($BASE_ADDR_DRAMC+0x041C) = 0x11111111
+ # =SELPH8=
+ # TX 1x clock delay for DQM byte output enable[3:0] and DQM byte[3:0]
+ set *($BASE_ADDR_DRAMC+0x0420) = 0x11111111
+ # =SELPH9=
+ # TX 1x clock delay for DQS byte output enable[3:0] and DQS byte[3:0]
+ set *($BASE_ADDR_DRAMC+0x0424) = 0x11111111
+ # =SELPH10=
+ # TX 0.5's 2x clock delay for DQM output enable[3:0], DQ byte output enable[3:0], DQM[3:0], and DQ byte[3:0]
+ # TODO: why we let output enable extra more 1.5 T not 0.5 DRAM clock?
+ set *($BASE_ADDR_DRAMC+0x0428) = 0x0000FFFF
+ # =SELPH11=
+ # TX 0.5's 2x clock delay for DQS output enable[3:0] and DQS[3:0]
+ # TODO: why we let output enable extra more 1.5 T not 0.5 DRAM clock?
+ set *($BASE_ADDR_DRAMC+0x042C) = 0x000000FF
+ # TODO: offset 0x430~0x438, Don't we need to set clock 05x phase selection?
+ # =SELPH12=
+ # clock 05x phase selection for CLK, DQSGATE, DQS[3:0], and DQM[3:0]
+ # clock 1x phase selection for DQS[3:0], DQM[3:0], CLK, and DQSGATE
+ set *($BASE_ADDR_DDRPHY+0x0430) = 0x10F010F0
+ # =SELPH13=
+ # clock 1x phase selection for DQ[31:0]
+ set *($BASE_ADDR_DDRPHY+0x0434) = 0xFFFFFFFF
+ # =SELPH14=
+ # clock 05x phase selection for DQ[31:0]
+ set *($BASE_ADDR_DDRPHY+0x0438) = 0xFFFFFFFF
+ # =SELPH15=
+ # OCV (On-Chip Variation that affect by PVT). It is removed in TK6291.
+ # OCV mode for DQSGATE, DQS[3:0], DQ[31:0], CLK, and CA
+ set *($BASE_ADDR_DDRPHY+0x043C) = 0x0000001F
+ # =MEMPLL_DIVIDER=
+ # DDRPHY reset flow for 1X clock phase sync
+ # [5]: MEMCLKENB, SW control. It is used for MEMPLL initialization. After initialization, CLKENB is controlled by HW mode.
+ # [4]: RG_DMSS_PWDB, ALLCLK_EN. It is used for gated MEMPLL output during initialization. (=1 after initilization)
+ # [0]: MEMCLKENB_SEL, memory clock sync enable bar selection, selection for [5] (=1 select[5])
+ if $CHIP_VER != 0
+ set $reg_val = *($BASE_ADDR_DDRPHY+0x0640) | 0x00000031
+ set *($BASE_ADDR_DDRPHY+0x0640) = $reg_val
+ end
+ # TODO: wait 500 sys_clock equal to 1.87us?
+ #WAIT 2.us
+ delay_f32k 1
+ LPDDR2_INIT
+ if $CHIP_VER == 0
+ # =CONF2=
+ set *($BASE_ADDR_DRAMC+0x0008) = 0x0000631F
+ # =DRAMC_PD_CTRL=
+ #set $reg_val = *($BASE_ADDR_DRAMC+0x01DC) & ~0x00FF0000
+ #set $reg_val = $reg_val | 0x00350000
+ #set *($BASE_ADDR_DRAMC+0x01DC) = $reg_val
+ else
+ # =CONF2=
+ # [23] FREBW_FREN, tREFBW use xtal clock counter enable
+ # [17:8] FREBW_FR, 6720ns/(XTALFR_clock)-1
+ # [7:0] REFCNT: AC Timing Calculation is 0x3F, but ESL use 0x3B
+ # TODO: [AC Timing] 0x0000003F
+ set *($BASE_ADDR_DRAMC+0x0008) = 0x03806D3B
+ # =DRAMC_PD_CTRL=
+ # [23:16] REFCNT_FR_CLK, refresh period based on DRAMC freerun clock cycles
+ set $reg_val = *($BASE_ADDR_DRAMC+0x01DC) & ~0x00FF0000
+ set $reg_val = $reg_val | 0x00640000
+ set *($BASE_ADDR_DRAMC+0x01DC) = $reg_val
+ end
+end
+
+define EMI_INIT
+ echo EMI_INIT ...\n
+ # =EMI_CONA=
+ # [27]: RANK_POS=0, {rank,row,bank,col}
+ # [17]: DUAL_RANK_EN=0
+ # [15:14][13:12]: ROW2ND=1,ROW=1, 14-bit row address
+ # [7:6][5:4]: COL2ND=1,COL=1, 10-bit column address
+ # [1]: DW32_EN=1, 32-bit data bus
+ set *($BASE_ADDR_EMI+0x0000) = 0x00005052
+ # =EMI_ARBI=
+ set *($BASE_ADDR_EMI+0x0140) = 0x20406188
+ # =EMI_ARBI_2ND=
+ set *($BASE_ADDR_EMI+0x0144) = 0x20406188
+ # =EMI_ARBD=
+ set *($BASE_ADDR_EMI+0x0118) = 0x0700704C
+ # =EMI_ARBE=
+ set *($BASE_ADDR_EMI+0x0120) = 0x40407068
+ # =EMI_ARBG=
+ set *($BASE_ADDR_EMI+0x0130) = 0xFFFF7045
+ # =EMI_ARBH=
+ set *($BASE_ADDR_EMI+0x0138) = 0xA0A07047
+ # TODO: CSR is not defined?
+ set *($BASE_ADDR_EMI+0x0040) = 0x80808807
+ # =EMI_ARBJ=
+ # TODO: it is not defined in CSRv0.9
+ set *($BASE_ADDR_EMI+0x0148) = 0x9719595E
+ # =EMI_ARBJ_2ND=
+ # TODO: it is not defined in CSRv0.9
+ set *($BASE_ADDR_EMI+0x014C) = 0x9719595E
+ # =EMI_TEST_D=
+ set *($BASE_ADDR_EMI+0x00F8) = 0x00000000
+ # =EMI_BMEN=
+ # TODO: why do we need to enable BUS_MON_EN for DRAM Init?
+ set *($BASE_ADDR_EMI+0x0400) = 0x00FF0001
+ # =EMI_CONB=
+ set *($BASE_ADDR_EMI+0x0008) = 0x17283544
+ # =EMI_CONC=
+ set *($BASE_ADDR_EMI+0x0010) = 0x0A1A0B1A
+ # TODO: offset 0x18 is not defined in CSR.
+ set *($BASE_ADDR_EMI+0x0018) = 0x00000000
+ # =EMI_CONE=
+ # TODO: it is not defined in CSRv0.9
+ set *($BASE_ADDR_EMI+0x0020) = 0xFFFF0848
+ # =EMI_CONG=
+ set *($BASE_ADDR_EMI+0x0030) = 0x2B2B2A38
+ # =EMI_CONH=
+ set *($BASE_ADDR_EMI+0x0038) = 0x00000000
+ # =EMI_SLCT=
+ # TODO: Why do we enable [17]:M1_LLAT_EN?
+ set *($BASE_ADDR_EMI+0x0158) = 0xFF02FF00
+ # =EMI_MDCT=
+ # TODO: why don't we enable [14]:MDMCU_SBR_EN and [12]:ULTRA_SBR_EN?
+ set *($BASE_ADDR_EMI+0x0078) = 0x002F0C17
+ # TODO: it is not defined in CSR.
+ set *($BASE_ADDR_EMI+0x015C) = 0x80030303
+ # =EMI_EMI_ARBK=
+ # TODO: it only defines [23:16] in CSRv0.9
+ set *($BASE_ADDR_EMI+0x0150) = 0x64F3FC79
+ # =EMI_ARBK_2ND=
+ # TODO: it is not defined in CSRv0.9
+ set *($BASE_ADDR_EMI+0x0154) = 0x64F3FC79
+ # =EMI_TESTC=
+ # TODO: it only enables [16:8] in CSRv0.9
+ set *($BASE_ADDR_EMI+0x00F0) = 0x38470000
+ # =EMI_TESTB=
+ # TODO: it didn't define [2:0] in CSRv0.9
+ set *($BASE_ADDR_EMI+0x00E8) = 0x00020027
+ # Enable slave error
+ set *($BASE_ADDR_EMI+0x01C0) = 0x10000000
+ set *($BASE_ADDR_EMI+0x01C8) = 0x10000000
+ set *($BASE_ADDR_EMI+0x01D0) = 0x10000000
+ set *($BASE_ADDR_EMI+0x0200) = 0x10000000
+ set *($BASE_ADDR_EMI+0x02C0) = 0x10000000
+ set *($BASE_ADDR_EMI+0x02C8) = 0x10000000
+ set *($BASE_ADDR_EMI+0x02D0) = 0x10000000
+ set *($BASE_ADDR_EMI+0x0300) = 0x10000000
+ # =EMI_CONM=
+ # [10]: EMI_ENABLE=1
+ set *($BASE_ADDR_EMI+0x0060) = 0x000006B8
+ # =EMI_ARBP=
+ # EBM_MODE enable
+ set *($BASE_ADDR_EMI+0x0A20) = 0x00010000
+end
+
+define MEMSYS_INIT
+ echo MEMSYS_INIT ...\n
+ # =MEMINFRA_SI_WAY_CTL=
+ # Enable MEMINFRA EMI Path
+ # [9:8] M7_sysram:M7_emi
+ # [7:6] M6_sysram:M6_emi
+ # [5:4] M4_mdmda_sysram:M4_mddma_emi
+ # [3:2] M4_l1sys_sysram:M4_l1sys_emi
+ # [1:0] M3_sysram:M3_emi
+ set $reg_val = *($BASE_ADDR_MEMSYSAOREG_MISC+0x4000)
+ set $reg_val = $reg_val | 0x00000155
+ set *($BASE_ADDR_MEMSYSAOREG_MISC+0x4000) = $reg_val
+ # =EMI_ADDR_OFFSET=
+ # EMI offset on address[31:24], unit is 16MB
+ set $MD3_offset = 0x00
+ set $MD2_offset = 0x00
+ set $MD1_offset = 0x10
+ set $ap_offset = 0x00
+ set $emi_offset = ($MD3_offset<<0x18)+($MD2_offset<<0x10)+($MD1_offset<<0x08)+($ap_offset<<0x00)
+ set *($BASE_ADDR_MEMSYSAOREG_MISC+0x1000) = $emi_offset
+end
+
+define LPDDR2_INIT
+ # =PADCTL4=
+ # [2]: CKE always on, [0]: CKE control by controller
+ # CKE always on
+ set $reg_val = *($BASE_ADDR_DRAMC+0x00E4) | 0x00000005
+ set *($BASE_ADDR_DRAMC+0x00E4) = $reg_val
+ #WAIT 200.us
+ delay_f32k 7
+ # LPDDR2 MRW RESET
+ DRAMC_MRW 0x0000003F
+ #WAIT 10.us
+ delay_f32k 1
+ # ZQ Init
+ DRAMC_MRW 0x00FF000A
+ # TODO: wait 1us after ZQ Initialization
+ #WAIT 1.us
+ delay_f32k 1
+ # MRW MR1 => BL8, Sequential, Wrap, nWR=8
+ DRAMC_MRW 0x00C30001
+ # MRW MR2 => RL=8 and WL=4 for DDR1066
+ DRAMC_MRW 0x00060002
+ # MRW MR3 => 40-ohm typical
+ DRAMC_MRW 0x00020003
+ # =PADCTL4=
+ # [2]: CKE always on, [0]: CKE control by controller
+ # CKE is controlled by hardware
+ set $reg_val = *($BASE_ADDR_DRAMC+0x00E4) & ~0x00000004
+ set *($BASE_ADDR_DRAMC+0x00E4) = $reg_val
+end
+
+define DRAMC_MRW
+ set $spcmd = 0x00000001
+ set *($BASE_ADDR_DRAMC+0x0088) = $arg0
+ set *($BASE_ADDR_DRAMC+0x01E4) = $spcmd
+ while (*($BASE_ADDR_DRAMC+0x03B8) & $spcmd) != $spcmd
+ end
+ set *($BASE_ADDR_DRAMC+0x01E4) = 0x00000000
+ while (*($BASE_ADDR_DRAMC+0x03B8) & $spcmd) != 0x00000000
+ end
+end
+
+define DRAM_TEST
+ # 0x0:infinite-loop# others:loop-N-times
+ set $TEST_LOOP = 0x2
+ # 0x0:config-and-start# others:bit-0:start,bit-1:pause,bit-2:resume.
+ set $TEST_CTRL = 0x0
+ # 0x0:pass# others:fail
+ set $TEST_RESULT = 0x0
+ # TRFG 0~3 offset 0x100
+ set $TRFG_BASE = 0xC3041000
+
+ if $TEST_CTRL != 0x0
+ set *(TRFG_BASE+0x000) = $TEST_CTRL
+ set *(TRFG_BASE+0x100) = $TEST_CTRL
+ set *(TRFG_BASE+0x200) = $TEST_CTRL
+ set *(TRFG_BASE+0x300) = $TEST_CTRL
+ #ENDDO
+ end
+
+ # Config and start
+ echo TRFG config and start ...\n
+ set $idx = 0x0
+ while $idx < 0x4
+ set $base = $TRFG_BASE + 0x100 * $idx
+ set $start_addr= 0x04000000 * $idx
+ set $pat_ctl = 0x58FF0017 + (($TEST_LOOP & 0xF) << 8)
+ # TRFG_STRAT_CTL, [0]:start, [1]:pause, [2]:resume
+ set *($base+0x00) = 0x00000000
+ # TRFG_INIT_PAT_MSB
+ set *($base+0x04) = 0x5A5A5A5A
+ # TRFG_INIT_PAT_LSB
+ set *($base+0x08) = 0xA5A5A5A5
+ # TRFG_START_ADDR
+ set *($base+0x0C) = $start_addr
+ # TRFG_TEST_LEN * 8 byte
+ set *($base+0x10) = 0x00800000
+ # TRFG_PAT_CTL, [11:8]:test_loop, [5:4]:pat_mode
+ set *($base+0x14) = $pat_ctl
+ # TRFG_BUS_CTL, [10:8]:domain, [3:0]:burst_len
+ set *($base+0x18) = 0x0000010F
+ # TRFG_STRAT_CTL, [0]:start, [1]:pause, [2]:resume
+ set *($base+0x00) = 0x00000001
+ set $idx++
+ end
+
+ # Wait done
+ echo Wait done
+ set $idx = 0x0
+ while $idx < 0x4
+ set $base = $TRFG_BASE + 0x100 * $idx
+ while (*($base+0x20) & 0x1) == 0x1
+ echo .\n
+ #WAIT 1.S
+ delay_f32k 32000
+ end
+ if (*($base+0x20) & 0x04) == 0x0
+ set $TEST_RESULT++
+ printf "=> TRFG %d test fail:\n", $idx
+ printf "FAIL_ADDR = 0x%08x\n", *($base+0x24)
+ printf "EXP_DATA_MSB = 0x%08x\n", *($base+0x28)
+ printf "EXP_DATA_LSB = 0x%08x\n", *($base+0x2C)
+ printf "FAIL_DATA_MSB = 0x%08x\n", *($base+0x30)
+ printf "FAIL_DATA_LSB = 0x%08x\n", *($base+0x34)
+ end
+ set $idx++
+ end
+
+ if $TEST_RESULT == 0x0
+ echo => Traffic-Gen dram test pass ...^_^\n
+ else
+ echo => Traffic-Gen dram test fail ...>^<\n
+ end
+end
+
+define WDT_Disable
+ echo WDT_Disable ...\n
+ set $mdrgu = 0xA00F0000 + 0x0100
+ set $aprgu = 0xC3670000 + 0x0100
+ set *$mdrgu = 0x55000000 | (*$mdrgu & ~0x03)
+ set *$aprgu = 0x55000000 | (*$aprgu & ~0x01)
+end
+
+define MIPS_INIT
+ echo MIPS_INIT ...\n
+ set *0x1F000020 = 0x0000000F
+ set *0x1F000090 = 0xA0000000
+ set *0x1F000098 = 0xE0000002
+ set *0x1F0000A0 = 0xC0000000
+ set *0x1F0000A8 = 0xC0000002
+ # fixed md mips domain ID hw bug
+ set *0xA0060060 = 0x03231111
+end
+
+# entry point
+set $f32k_str = *0xa00d0850
+MIPS_INIT
+WDT_Disable
+DRAM_INIT
+set $f32k_end = *0xa00d0850
+printf "Elapsed time: %.3f sec\n", ($f32k_end - $f32k_str) / 32.768 / 1000
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/fpga_emi_init.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/fpga_emi_init.py
new file mode 100755
index 0000000..c83bc69
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/fpga_emi_init.py
@@ -0,0 +1,646 @@
+from imgtec import codescape
+import sys
+import time
+import os
+
+def enable_fast_write(da):
+ # To accelerate load elf
+ # Configure C0_CDMMBASE = 0x01FC1407 to enable access
+ thread.WriteRegister('CDMMBase', 0x01FC1407)
+ # Default all segments are NC, then configure VA Bank8 to WB for speed up load elf
+ thread.memory.Write(0x1FC100D4, 0x02030202)
+ da.SetDASettingValue("Fast Monitor Address", 0x6F800000)
+ da.SetDASettingValue("Fast Writes", True)
+
+def disable_fast_write(da):
+ thread = da.cores[0].hwthreads[0]
+ # Restore Default all segments to NC
+ thread.memory.Write(0x1FC100D4, 0x02020202)
+ # Restore C0_CDMMBASE = 0x01FC1007
+ thread.WriteRegister('CDMMBase', 0x01FC1007)
+ da.SetDASettingValue("Fast Writes", False)
+
+# load all elf
+def load_all_elf(da, thread, elf_path):
+ enable_fast_write(da)
+ time_str = time.time()
+ print "=== Start Loading .elf ==="
+ print "Image path: " + elf_path
+ for core_idx in range(2):
+ if(os.path.exists(elf_path) == False):
+ print "[Error] UMOLY ELF doesn't exist: %s" %(elf_path)
+ break
+
+ if(core_idx == 0):
+ # load binary only on VPE0 of 0 core
+ thread = da.cores[core_idx].hwthreads[0]
+ thread.Stop()
+ thread.LoadProgramFile(elf_path, False, 0x83, True, "")
+ print "[Core%d,VPE0] Load ELF successfully" %(core_idx)
+ thread = da.cores[core_idx].hwthreads[1]
+ thread.Stop()
+ thread.LoadProgramFile(elf_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE1] Load ELF successfully" %(core_idx)
+ else:
+ thread = da.cores[core_idx].hwthreads[0]
+ thread.Stop()
+ thread.LoadProgramFile(elf_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE0] Load ELF successfully" %(core_idx)
+ thread = da.cores[core_idx].hwthreads[1]
+ thread.Stop()
+ thread.LoadProgramFile(elf_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE1] Load ELF successfully" %(core_idx)
+ time_end = time.time()
+ print("All loading is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+ disable_fast_write(da)
+
+# load dsp bin file
+def load_dsp_bin(da, thread, dsp_path,dsp_addr):
+ enable_fast_write(da)
+ time_str = time.time()
+ print "=== Start load dsp bin ==="
+ print "Dsp bin path: " + dsp_path
+ print "Dsp bin load address: " + dsp_addr
+
+ thread = da.cores[0].hwthreads[0]
+ thread.memory.LoadBinaryFile(dsp_path,dsp_addr,start_offset = 0, length = None)
+
+ time_end = time.time()
+ print("loading dsp is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+ disable_fast_write(da)
+
+
+
+def DRAM_INIT(thread):
+ """initialize DRAM, include DRAMC_INIT (-> LPDDR2_INIT) -> EMI_INIT -> MEMSYS_INIT
+ [in] thread, codescape thread object
+ """
+ BASE_ADDR_EMI = 0xC3000000
+ BASE_ADDR_DRAMC = 0xC3010000
+ BASE_ADDR_DDRPHY = 0xC3020000
+ BASE_ADDR_MEMSYSAOREG_MISC = 0xC3080000
+ BASE_ADDR_AP_CLKSW = 0xC3750000
+
+ usleep = lambda x: time.sleep(x/1000000.0) # usec delay
+
+ def DRAMC_INIT():
+ """initialize DRAMC, DDRPHY, and DRAM, exclude EMI
+ """
+ # =ACTIM0=
+ thread.memory.Write(BASE_ADDR_DRAMC+0x0000, 0x44584493)
+ # =CONF1=
+ # [18][5][3] no use in TK6291
+ # [9:8]MTYPE, DRAM column address width, 2'b01 (9-bit) -> 2'b10 (10-bit)
+ # TODO: [AC Timing] 0x00048683
+ thread.memory.Write(BASE_ADDR_DRAMC+0x0004, 0xF0008681)
+ # =R0DELDLY=
+ thread.memory.Write(BASE_ADDR_DRAMC+0x0018, 0x10101010)
+ # =R1DELDLY=
+ # [30:24][22:16][14:8][6:0] DQS3/2/1/0 input delay
+ thread.memory.Write(BASE_ADDR_DRAMC+0x001C, 0x12121212)
+ # =DLLCONF=
+ thread.memory.Write(BASE_ADDR_DRAMC+0x0028, 0x50000000)
+ # =TEST2_3=
+ # [23] DQSICALI_NEW=0, using original dqs calibration
+ # [7] TESTAUDPAT=0, ISI pattern can be set by TEST2_PAT0
+ thread.memory.Write(BASE_ADDR_DRAMC+0x0044, 0xBF080000)
+ # =TEST2_4=
+ thread.memory.Write(BASE_ADDR_DRAMC+0x0048, 0x1601110D)
+ # =DDR2CTL=
+ thread.memory.Write(BASE_ADDR_DRAMC+0x007C, 0x00003201)
+ # =MISC=
+ # [23:21]: PHYRXDSL_PIPE3~1 are pipe stage selection for RDATA and RDSEL
+ # DATLAT_DSEL = DATLAT - 2*2 when enabling two top pipe (for TK6291)
+ thread.memory.Write(BASE_ADDR_DRAMC+0x0080, 0x00AC08A0)
+ # =ZQCS=
+ # [15:8]: ZQCSAD, [7:0]: ZQCSOP
+ reg_val = thread.memory.Read(BASE_ADDR_DRAMC+0x0084) & ~0x0000FFFF
+ reg_val = reg_val | 0x00000A56
+ thread.memory.Write(BASE_ADDR_DRAMC+0x0084, reg_val)
+ # =CLK1DELAY=
+ # [23]: PHYPIPE3EN, [22]: PHYPIPE2EN, [21]: PHYPIPE1EN
+ reg_val = thread.memory.Read(BASE_ADDR_DRAMC+0x008C) & ~0x00E00000
+ reg_val = reg_val | 0x00A00000
+ thread.memory.Write(BASE_ADDR_DRAMC+0x008C, reg_val)
+ # =R0DQSIEN=
+ # Gating Window for Rank0
+ thread.memory.Write(BASE_ADDR_DRAMC+0x0094, 0x31313131)
+ # =MCKDLY=
+ # [23]: WODT has no load (useless)
+ # [21]: DRAMEN has no load (useless)
+ # [11:10] DQIENQKEND: DQ/DQS input enable window is larger than 6582. [11:10]=2'b00 => dle counter is 5'1f. =Others => dle counter is DATLAT-[11:10]+2
+ # [4] DQIENLATEBEGIN, disable early begin, better for power saving
+ # TODO: [20]: It is used for BST(Bus Termination), but TK6291 doesn't support the feature
+ thread.memory.Write(BASE_ADDR_DRAMC+0x00D8, 0x40500510)
+ # =DQSCTL1=
+ # [27:24]: DQSINCTL, DQS input range control by M_CK
+ # [23:12][11:0]: DQS3CTL/DQS2CTL, control by DDRPHY (useless)
+ thread.memory.Write(BASE_ADDR_DRAMC+0x00E0, 0x12200200)
+ # =GDDR3CTL1=
+ # [24]: 8BKEN=1, 8-bank device enable
+ reg_val = thread.memory.Read(BASE_ADDR_DRAMC+0x00F4) | 0x01000000
+ thread.memory.Write(BASE_ADDR_DRAMC+0x00F4, reg_val)
+ # [28]: PHYSYNCM=1, SYNC MODE using inverted PHY_M_CK
+ reg_val = thread.memory.Read(BASE_ADDR_DDRPHY+0x00F4) | 0x10000000
+ thread.memory.Write(BASE_ADDR_DDRPHY+0x00F4, reg_val)
+ # =MISCTL0=
+ # [31]: REFP_ARB_EN2: per-bank refresh arbitration mask2
+ # [30:28]: TXP, tXP Timing setting
+ # [27] EMIPREEN: Enable advanced precharge function by EMI side-band signals, but TK6291 didn't support this feature.
+ # [26] REFP_ARB_EN: per-bank refresh blocks in EMI arbitration
+ # [25] REFA_ARB_EN: all-bank refresh blocks in EMI arbitration
+ # [24] PBC_ARB_EN: block page-miss requests in EMI arbitration
+ # [21]: REFA_ARB_EN2: all bank refresh arbtration mask enable option
+ thread.memory.Write(BASE_ADDR_DRAMC+0x00FC, 0x81080000)
+ # [17]: INTLBT=0, IO internal loop back (useless for TK6291)
+ # [16]: RXLPDDR2=0, IO voltage operating condition = {0:1.2V, 1:1.8V}
+ reg_val = thread.memory.Read(BASE_ADDR_DDRPHY+0x00FC) & ~0x00030000
+ thread.memory.Write(BASE_ADDR_DDRPHY+0x00FC, reg_val)
+ # =OCDK=
+ # [24]: DRVREF=1, drving change only when refresh cycle
+ # [15]: DRDELSWEN=1, enable DQS input delay switching for different ranks
+ # [8]: AUTOCALDRV=1, OCD calibration enable
+ # [7:0]: AUTOKCNT, auto calibration counter
+ # =RKCFG=
+ # [7]: per-bank refresh for LPDDR2&3
+ # TODO: [AC Timing] 0x004135C0
+ thread.memory.Write(BASE_ADDR_DRAMC+0x0110, 0x004121C0)
+ # =DQSCTL2=
+ thread.memory.Write(BASE_ADDR_DRAMC+0x0118, 0x00000002)
+ # =DQSGCTL=
+ # [7:0] Old gating window course tune
+ reg_val = thread.memory.Read(BASE_ADDR_DRAMC+0x0124) & ~0x000000FF
+ thread.memory.Write(BASE_ADDR_DRAMC+0x0124, reg_val)
+ # [31]: NEWDQSG_SEL, [30]:DQSGDUALP
+ reg_val = thread.memory.Read(BASE_ADDR_DDRPHY+0x0124) | 0xC0000000
+ thread.memory.Write(BASE_ADDR_DDRPHY+0x0124, reg_val)
+ # =CLKCTRL=
+ # [29]: CLK_EN_1, [28]: CLK_EN_0
+ # TODO: we should only enable one CLK for TK6291
+ reg_val = thread.memory.Read(BASE_ADDR_DRAMC+0x0130) | 0x30000000
+ thread.memory.Write(BASE_ADDR_DRAMC+0x0130, reg_val)
+ # =ARBCTL0=
+ # [7:0]: maximum pending number to block the arbitration
+ reg_val = thread.memory.Read(BASE_ADDR_DRAMC+0x0168) & ~0x000000FF
+ reg_val = reg_val | 0x00000080
+ thread.memory.Write(BASE_ADDR_DRAMC+0x0168, reg_val)
+ # =DQSCAL0=
+ # [31]: DQS strobe calibration enable
+ # [30]: Update tracking gating value to 2 ranks simultaneously
+ # [15]: Rank0 DQS strobe calibration high-limit enable
+ # [14:8]: Rank0 DQS strobe calibration high-limit value
+ # [7]: Rank0 DQS strobe calibration low-limit enable
+ # [6:0]: Rank0 DQS strobe calibration low-limit value
+ reg_val = thread.memory.Read(BASE_ADDR_DRAMC+0x01C0) & ~0xC000FFFF
+ reg_val = reg_val | 0x80000000
+ thread.memory.Write(BASE_ADDR_DRAMC+0x01C0, reg_val)
+ # =MEMSYSPIPE_CGF_CTL=
+ # [2]: PIPE_CFG_EN, [0]: DRAMC_CFG_EN
+ # PIPE_CGF_ON=0 (timing issue) EMI_CGF_ON=0(Gated function is already designed in EMI) DRAMC_CGF_ON=1
+ thread.memory.Write(BASE_ADDR_MEMSYSAOREG_MISC+0x5000, 0x00000001)
+ # =DRAMC_PD_CTRL=
+ # [24] REFFRERUN, using freerun clock to count refresh period
+ # [23:16] REFCNT_FR_CLK, refresh period based on DRAMC freerun clock cycles
+ # [15:8] TXREFCNT, tXSR
+ thread.memory.Write(BASE_ADDR_DRAMC+0x01DC, 0xC2002340)
+ # =LPDDR2_3=
+ # TODO: should set to 0x10000000, not 0x3600_0000?
+ # [31]: DRAM address decode by DRAMC
+ # [28]: LPDDR2 enable
+ # [27]: enable register output data by DRAMC
+ thread.memory.Write(BASE_ADDR_DRAMC+0x01E0, 0x36000000)
+ # [30]: Select IO O1 as output
+ # [29&25:24&22:0]: DDR mode for pins
+ # [26]: fast IO output enable
+ thread.memory.Write(BASE_ADDR_DDRPHY+0x01E0, 0x2601FFFF)
+ # =ACTIM1=
+ thread.memory.Write(BASE_ADDR_DRAMC+0x01E8, 0x81000510)
+ # =PERFCTL0=
+ # [0] dual schedulers
+ thread.memory.Write(BASE_ADDR_DRAMC+0x01EC, 0x0010CF11)
+ # TODO: AC_DERATING [0x01F0]
+ # =RRRATE_CTL=, =MRR_CTL=
+ # Or LPDDR3
+ thread.memory.Write(BASE_ADDR_DRAMC+0x01F4, 0x03020100)
+ thread.memory.Write(BASE_ADDR_DRAMC+0x01Fc, 0x07060504)
+ # =AC_TIME_05T=
+ thread.memory.Write(BASE_ADDR_DRAMC+0x01F8, 0x04002600)
+ # =LPDDR2_4=
+ # clock 1x phase selection
+ thread.memory.Write(BASE_ADDR_DDRPHY+0x023C, 0x2201FFFF)
+ # =SELPH1=
+ # TX 1x clock delay for CS1, RAS, CAS, WE, RESET, ODT, CKE, and CS
+ thread.memory.Write(BASE_ADDR_DRAMC+0x0400, 0x00000000)
+ # =SELPH2=
+ # TX 1x clock delay for CKE1, DQSGATE_P1, CMD, DQSGATE, BA[2:0]
+ thread.memory.Write(BASE_ADDR_DRAMC+0x0404, 0x00302000)
+ # =SELPH3=
+ # TX 1x clock delay for RA[7:0]
+ thread.memory.Write(BASE_ADDR_DRAMC+0x0408, 0x00000000)
+ # =SELPH4=
+ # TX 1x clock delay for RA[15:8]
+ thread.memory.Write(BASE_ADDR_DRAMC+0x040C, 0x00000000)
+ # =SELPH5=
+ # TX 0.5's 2x clock delay for CKE1, DQSGATE_P1, DQSGATE, BA[2:0], CS1, RAS, CAS, WE, RESET, ODT, CKE, CS
+ thread.memory.Write(BASE_ADDR_DRAMC+0x0410, 0x00955555)
+ # TODO: SELPH6 [0x0414]
+ # =SELPH6_1=
+ # TX 1x clock delay for DQSGATE_P1 and DQSGATE of rank1
+ # TX 0.5's 2x clock delay for DQSGATE_P1 and DQSGATE of rank1
+ thread.memory.Write(BASE_ADDR_DRAMC+0x0418, 0x00000228)
+ # =SELPH7=
+ # TX 1x clock delay for DQ byte output enable[3:0] and DQ byte[3:0]
+ thread.memory.Write(BASE_ADDR_DRAMC+0x041C, 0x11111111)
+ # =SELPH8=
+ # TX 1x clock delay for DQM byte output enable[3:0] and DQM byte[3:0]
+ thread.memory.Write(BASE_ADDR_DRAMC+0x0420, 0x11111111)
+ # =SELPH9=
+ # TX 1x clock delay for DQS byte output enable[3:0] and DQS byte[3:0]
+ thread.memory.Write(BASE_ADDR_DRAMC+0x0424, 0x11111111)
+ # =SELPH10=
+ # TX 0.5's 2x clock delay for DQM output enable[3:0], DQ byte output enable[3:0], DQM[3:0], and DQ byte[3:0]
+ # TODO: why we let output enable extra more 1.5 T not 0.5 DRAM clock?
+ thread.memory.Write(BASE_ADDR_DRAMC+0x0428, 0x0000FFFF)
+ # =SELPH11=
+ # TX 0.5's 2x clock delay for DQS output enable[3:0] and DQS[3:0]
+ # TODO: why we let output enable extra more 1.5 T not 0.5 DRAM clock?
+ thread.memory.Write(BASE_ADDR_DRAMC+0x042C, 0x000000FF)
+ # TODO: offset 0x430~0x438, Don't we need to set clock 05x phase selection?
+ # =SELPH12=
+ # clock 05x phase selection for CLK, DQSGATE, DQS[3:0], and DQM[3:0]
+ # clock 1x phase selection for DQS[3:0], DQM[3:0], CLK, and DQSGATE
+ thread.memory.Write(BASE_ADDR_DDRPHY+0x0430, 0x10F010F0)
+ # =SELPH13=
+ # clock 1x phase selection for DQ[31:0]
+ thread.memory.Write(BASE_ADDR_DDRPHY+0x0434, 0xFFFFFFFF)
+ # =SELPH14=
+ # clock 05x phase selection for DQ[31:0]
+ thread.memory.Write(BASE_ADDR_DDRPHY+0x0438, 0xFFFFFFFF)
+ # =SELPH15=
+ # OCV (On-Chip Variation that affect by PVT). It is removed in TK6291.
+ # OCV mode for DQSGATE, DQS[3:0], DQ[31:0], CLK, and CA
+ thread.memory.Write(BASE_ADDR_DDRPHY+0x043C, 0x0000001F)
+ # =MEMPLL_DIVIDER=
+ # DDRPHY reset flow for 1X clock phase sync
+ # [5]: MEMCLKENB, SW control. It is used for MEMPLL initialization. After initialization, CLKENB is controlled by HW mode.
+ # [4]: RG_DMSS_PWDB, ALLCLK_EN. It is used for gated MEMPLL output during initialization. (=1 after initilization)
+ # [0]: MEMCLKENB_SEL, memory clock sync enable bar selection, selection for [5] (=1 select[5])
+ # TODO: wait 500 sys_clock equal to 1.87us?
+ usleep(2)
+ LPDDR2_INIT()
+ # =CONF2=
+ thread.memory.Write(BASE_ADDR_DRAMC+0x0008, 0x0000631F)
+ # =DRAMC_PD_CTRL=
+
+ def EMI_INIT():
+ """initialize EMI
+ """
+ # =EMI_CONA=
+ # [27]: RANK_POS=0, {rank,row,bank,col}
+ # [17]: DUAL_RANK_EN=0
+ # [15:14][13:12]: ROW2ND=1,ROW=1, 14-bit row address
+ # [7:6][5:4]: COL2ND=1,COL=1, 10-bit column address
+ # [1]: DW32_EN=1, 32-bit data bus
+ thread.memory.Write(BASE_ADDR_EMI+0x0000, 0x00005052)
+ # =EMI_ARBI=
+ thread.memory.Write(BASE_ADDR_EMI+0x0140, 0x20406188)
+ # =EMI_ARBI_2ND=
+ thread.memory.Write(BASE_ADDR_EMI+0x0144, 0x20406188)
+ # =EMI_ARBD=
+ thread.memory.Write(BASE_ADDR_EMI+0x0118, 0x0700704C)
+ # =EMI_ARBE=
+ thread.memory.Write(BASE_ADDR_EMI+0x0120, 0x40407068)
+ # =EMI_ARBG=
+ thread.memory.Write(BASE_ADDR_EMI+0x0130, 0xFFFF7045)
+ # =EMI_ARBH=
+ thread.memory.Write(BASE_ADDR_EMI+0x0138, 0xA0A07047)
+ # TODO: CSR is not defined?
+ thread.memory.Write(BASE_ADDR_EMI+0x0040, 0x80808807)
+ # =EMI_ARBJ=
+ # TODO: it is not defined in CSRv0.9
+ thread.memory.Write(BASE_ADDR_EMI+0x0148, 0x9719595E)
+ # =EMI_ARBJ_2ND=
+ # TODO: it is not defined in CSRv0.9
+ thread.memory.Write(BASE_ADDR_EMI+0x014C, 0x9719595E)
+ # =EMI_TEST_D=
+ thread.memory.Write(BASE_ADDR_EMI+0x00F8, 0x00000000)
+ # =EMI_BMEN=
+ # TODO: why do we need to enable BUS_MON_EN for DRAM Init?
+ thread.memory.Write(BASE_ADDR_EMI+0x0400, 0x00FF0001)
+ # =EMI_CONB=
+ thread.memory.Write(BASE_ADDR_EMI+0x0008, 0x17283544)
+ # =EMI_CONC=
+ thread.memory.Write(BASE_ADDR_EMI+0x0010, 0x0A1A0B1A)
+ # TODO: offset 0x18 is not defined in CSR.
+ thread.memory.Write(BASE_ADDR_EMI+0x0018, 0x00000000)
+ # =EMI_CONE=
+ # TODO: it is not defined in CSRv0.9
+ thread.memory.Write(BASE_ADDR_EMI+0x0020, 0xFFFF0848)
+ # =EMI_CONG=
+ thread.memory.Write(BASE_ADDR_EMI+0x0030, 0x2B2B2A38)
+ # =EMI_CONH=
+ thread.memory.Write(BASE_ADDR_EMI+0x0038, 0x00000000)
+ # =EMI_SLCT=
+ # TODO: Why do we enable [17]:M1_LLAT_EN?
+ thread.memory.Write(BASE_ADDR_EMI+0x0158, 0xFF02FF00)
+ # =EMI_MDCT=
+ # TODO: why don't we enable [14]:MDMCU_SBR_EN and [12]:ULTRA_SBR_EN?
+ thread.memory.Write(BASE_ADDR_EMI+0x0078, 0x002F0C17)
+ # TODO: it is not defined in CSR.
+ thread.memory.Write(BASE_ADDR_EMI+0x015C, 0x80030303)
+ # =EMI_EMI_ARBK=
+ # TODO: it only defines [23:16] in CSRv0.9
+ thread.memory.Write(BASE_ADDR_EMI+0x0150, 0x64F3FC79)
+ # =EMI_ARBK_2ND=
+ # TODO: it is not defined in CSRv0.9
+ thread.memory.Write(BASE_ADDR_EMI+0x0154, 0x64F3FC79)
+ # =EMI_TESTC=
+ # TODO: it only enables [16:8] in CSRv0.9
+ thread.memory.Write(BASE_ADDR_EMI+0x00F0, 0x38470000)
+ # =EMI_TESTB=
+ # TODO: it didn't define [2:0] in CSRv0.9
+ thread.memory.Write(BASE_ADDR_EMI+0x00E8, 0x00020027)
+ # Enable slave error
+ thread.memory.Write(BASE_ADDR_EMI+0x01C0, 0x10000000)
+ thread.memory.Write(BASE_ADDR_EMI+0x01C8, 0x10000000)
+ thread.memory.Write(BASE_ADDR_EMI+0x01D0, 0x10000000)
+ thread.memory.Write(BASE_ADDR_EMI+0x0200, 0x10000000)
+ thread.memory.Write(BASE_ADDR_EMI+0x02C0, 0x10000000)
+ thread.memory.Write(BASE_ADDR_EMI+0x02C8, 0x10000000)
+ thread.memory.Write(BASE_ADDR_EMI+0x02D0, 0x10000000)
+ thread.memory.Write(BASE_ADDR_EMI+0x0300, 0x10000000)
+ # =EMI_CONM=
+ # [10]: EMI_ENABLE=1
+ thread.memory.Write(BASE_ADDR_EMI+0x0060, 0x000006B8)
+ # =EMI_ARBP=
+ # EBM_MODE enable
+ thread.memory.Write(BASE_ADDR_EMI+0x0A20, 0x00010000)
+
+ def MEMSYS_INIT():
+ """initialize MEMSYS
+ """
+ # =MEMINFRA_SI_WAY_CTL=
+ # Enable MEMINFRA EMI Path
+ # [9:8] M7_sysram:M7_emi
+ # [7:6] M6_sysram:M6_emi
+ # [5:4] M4_mdmda_sysram:M4_mddma_emi
+ # [3:2] M4_l1sys_sysram:M4_l1sys_emi
+ # [1:0] M3_sysram:M3_emi
+ reg_val=thread.memory.Read(BASE_ADDR_MEMSYSAOREG_MISC+0x4000) | 0x00000155
+ thread.memory.Write(BASE_ADDR_MEMSYSAOREG_MISC+0x4000, reg_val)
+ # =EMI_ADDR_OFFSET=
+ # EMI offset on address[31:24], unit is 16MB
+ MD3_offset = 0x00
+ MD2_offset = 0x00
+ MD1_offset = 0x10
+ ap_offset = 0x00
+ emi_offset = (MD3_offset<<0x18) + (MD2_offset<<0x10) + (MD1_offset<<0x08) + (ap_offset<<0x00)
+ thread.memory.Write(BASE_ADDR_MEMSYSAOREG_MISC+0x1000, emi_offset)
+
+ def LPDDR2_INIT():
+ """initialize LPDDR2
+ """
+ # =PADCTL4=
+ # [2]: CKE always on, [0]: CKE control by controller
+ # CKE always on
+ reg_val = thread.memory.Read(BASE_ADDR_DRAMC+0x00E4) | 0x00000005
+ thread.memory.Write(BASE_ADDR_DRAMC+0x00E4, reg_val)
+ usleep(200)
+ # LPDDR2 MRW RESET
+ DRAMC_MRW(0x0000003F)
+ usleep(10)
+ # ZQ Init
+ DRAMC_MRW(0x00FF000A)
+ # TODO: wait 1us after ZQ Initialization
+ usleep(1)
+ # MRW MR1 => BL8, Sequential, Wrap, nWR=8
+ DRAMC_MRW(0x00C30001)
+ # MRW MR2 => RL=8 and WL=4 for DDR1066
+ DRAMC_MRW(0x00060002)
+ # MRW MR3 => 40-ohm typical
+ DRAMC_MRW(0x00020003)
+ # =PADCTL4=
+ # [2]: CKE always on, [0]: CKE control by controller
+ # CKE is controlled by hardware
+ reg_val = thread.memory.Read(BASE_ADDR_DRAMC+0x00E4) & ~0x00000004
+ thread.memory.Write(BASE_ADDR_DRAMC+0x00E4, reg_val)
+
+ def DRAMC_MRW(mrs):
+ """DMAMC mode register write
+ [in] mrs, mode register write value
+ """
+ spcmd = 0x00000001
+ thread.memory.Write(BASE_ADDR_DRAMC+0x0088, mrs)
+ thread.memory.Write(BASE_ADDR_DRAMC+0x01E4, spcmd)
+ while (thread.memory.Read(BASE_ADDR_DRAMC+0x03B8) & spcmd) != spcmd: pass
+ thread.memory.Write(BASE_ADDR_DRAMC+0x01E4, 0x00000000)
+ while (thread.memory.Read(BASE_ADDR_DRAMC+0x03B8) & spcmd) == spcmd: pass
+
+ print("DRAM_INIT ...")
+ if (thread.memory.Read(BASE_ADDR_EMI+0x0060) & 0x00000400) == 0x00000400:
+ return
+
+ thread.memory.Write(BASE_ADDR_MEMSYSAOREG_MISC+0x3000, 0x24541689) # MEMSYS_PASSWORD unlock
+ print("DRAMC_INIT ...")
+ DRAMC_INIT()
+ print("EMI_INIT ...")
+ EMI_INIT()
+ print("MEMSYS_INIT ...")
+ MEMSYS_INIT()
+ thread.memory.Write(BASE_ADDR_MEMSYSAOREG_MISC+0x3000, 0x00000000) # MEMSYS_PASSWORD lock
+ #DRAM_TEST(thread)
+
+
+def DRAM_TEST(thread, ctrl=0, loop=2):
+ """Use traffic-gen (TRFG) *4 to test DRAM, range 0x1000_0000 (256MB)
+ start_addr test_length domain
+ TRFG0 0x0000_0000 0x0400_0000 1
+ TRFG1 0x0400_0000 0x0400_0000 1
+ TRFG2 0x0800_0000 0x0400_0000 1
+ TRFG3 0x0C00_0000 0x0400_0000 1
+
+ [in] thread, codescape thread object
+ [in] ctrl, all-0: config and start
+ bit-0: start
+ bit-1: pause
+ bit-2: resume
+ [in] loop, test loop, 0:infinite, others:N-times
+ [out] 0:success, 1:fail
+ """
+ TRFG_BASE = 0xC3041000 # TRFG 0~3 offset 0x100
+
+ if ctrl != 0:
+ thread.memory.Write(TRFG_BASE+0x000, ctrl)
+ thread.memory.Write(TRFG_BASE+0x100, ctrl)
+ thread.memory.Write(TRFG_BASE+0x200, ctrl)
+ thread.memory.Write(TRFG_BASE+0x300, ctrl)
+ print("TRFG control done ...")
+ return 0
+
+ print("TRFG config and start ...")
+ for idx in range(4):
+ base = TRFG_BASE + 0x100 * idx
+ start_addr = 0x04000000 * idx
+ pat_ctl = 0x58FF0017 + ((loop & 0xF) << 8)
+ # TRFG_STRAT_CTL, [0]:start, [1]:pause, [2]:resume
+ thread.memory.Write(base+0x00, 0x00000000)
+ # TRFG_INIT_PAT_MSB
+ thread.memory.Write(base+0x04, 0x5A5A5A5A)
+ # TRFG_INIT_PAT_LSB
+ thread.memory.Write(base+0x08, 0xA5A5A5A5)
+ # TRFG_START_ADDR
+ thread.memory.Write(base+0x0C, start_addr)
+ # TRFG_TEST_LEN * 8 byte
+ thread.memory.Write(base+0x10, 0x00800000)
+ # TRFG_PAT_CTL, [11:8]:test_loop, [5:4]:pat_mode
+ thread.memory.Write(base+0x14, pat_ctl)
+ # TRFG_BUS_CTL, [10:8]:domain, [3:0]:burst_len
+ thread.memory.Write(base+0x18, 0x0000010F)
+ # TRFG_STRAT_CTL, [0]:start, [1]:pause, [2]:resume
+ thread.memory.Write(base+0x00, 0x00000001)
+
+ # Wait done
+ print("Wait done")
+ trfg = [None] * 4
+ while None in trfg:
+ print(".")
+ time.sleep(1)
+ for idx in range(4):
+ base=TRFG_BASE + 0x100 * idx
+ if trfg[idx] != None:
+ continue
+ if (thread.memory.Read(base+0x20) & 0x1) == 0x1:
+ continue
+ if (thread.memory.Read(base+0x20) & 0x4) == 0x0:
+ print("=> TRFG {} test fail:".format(idx))
+ print("FAIL_ADDR = 0x{:08X}".format(thread.memory.Read(base+0x24)))
+ print("EXP_DATA_MSB = 0x{:08X}".format(thread.memory.Read(base+0x28)))
+ print("EXP_DATA_LSB = 0x{:08X}".format(thread.memory.Read(base+0x2C)))
+ print("FAIL_DATA_MSB = 0x{:08X}".format(thread.memory.Read(base+0x30)))
+ print("FAIL_DATA_LSB = 0x{:08X}".format(thread.memory.Read(base+0x34)))
+ trfg[idx] = 1
+ else:
+ trfg[idx] = 0
+
+ if trfg == [0,0,0,0]:
+ print("=> TRFG dram test pass ...^_^")
+ return 0
+ else:
+ print("=> TRFG dram test fail ...>'<")
+ return 1
+
+
+def WDT_Disable(thread):
+ """diable WDT function
+ """
+ print("WDT disable ...")
+ mdrgu = 0xA00F0000 + 0x0100
+ aprgu = 0xC3670000 + 0x0100
+ thread.memory.Write(mdrgu, (thread.memory.Read(mdrgu) & 0xFFFFFFFC) | 0x55000000)
+ #print("0x{:08X}=0x{:08X}".format(mdrgu, thread.memory.Read(mdrgu))) #0x32
+ thread.memory.Write(aprgu, (thread.memory.Read(aprgu) & 0xFFFFFFFE) | 0x55000000)
+ #print("0x{:08X}=0x{:08X}".format(aprgu, thread.memory.Read(aprgu))) #0x00
+
+
+
+if __name__ == "__main__":
+ print "=== Start Initializing ==="
+ umolya_path = ""
+ dsp_path = ""
+
+ da = codescape.GetFirstProbe()
+ for idx in reversed(range(2)):
+ da.cores[idx].StopAll(False)
+ thread = da.cores[0].hwthreads[0]
+ da.SetDASettingValue("Fast Reads", False)
+ da.SetDASettingValue("Force MMU type MPU", True)
+ #da.SetDASettingValue("Lock Monitor in Cache", False)
+
+ thread.memory.Write(0x1F000020, 0xF)
+ thread.memory.Write(0x1F000090, 0xA0000000)
+ thread.memory.Write(0x1F000098, 0xE0000002)
+ thread.memory.Write(0x1F0000A0, 0xC0000000)
+ thread.memory.Write(0x1F0000A8, 0xC0000002)
+ # fixed md mips domain ID hw bug
+ thread.memory.Write(0xA0060060, 0x03231111)
+
+ time_str = time.time()
+ WDT_Disable(thread)
+ DRAM_INIT(thread)
+
+ #clear dsp header
+ print("Clear DSP Header...")
+ thread.memory.Write(0x0E800000, 0)
+ thread.memory.Write(0x00080000, 0)
+
+ time_end = time.time()
+ print("Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+
+ if codescape.environment == "codescape":
+ if codescape.is_script_region:
+ region_thread = codescape.GetRegionThread()
+ # This is a script region, set up events to wait for thread halted
+ import wx
+ class Frame(wx.Frame):
+
+ dsp_bin_addr = "0x0E800000"
+
+ def __init__(self, parent, thread):
+ wx.Frame.__init__(self, parent, title="[ModemOnly]LoadBin&Symbol")
+
+
+ # Initialize UI
+ button_width = 80
+ border_size = 6
+
+ load_all_elf_btn = wx.Button(self, pos=(0, 0), label='Load elf', size=(button_width,-1))
+ load_all_elf_btn.Bind(wx.EVT_BUTTON, self.on_load_all_elf_button)
+
+ button_width = 100
+ border_size = 6
+ load_dsp_btn = wx.Button(self, pos=(0, 35), label='Load DSP Bin', size=(button_width,-1))
+ load_dsp_btn.Bind(wx.EVT_BUTTON, self.on_load_dsp_button)
+
+ statictext = wx.StaticText(self, pos=(110, 40), label="dsp address:")
+
+ textctrl = wx.TextCtrl(self,pos=(190, 37), value = self.dsp_bin_addr)
+ textctrl.Bind(wx.EVT_TEXT, self.OnTextChanged)
+
+
+ # load all elf
+ def on_load_all_elf_button(self, event):
+ fileDialog = wx.FileDialog(self)
+ fileDialog.ShowModal()
+ umolya_path = fileDialog.GetPath()
+ fileDialog.Destroy()
+ thread = da.cores[0].hwthreads[0]
+ load_all_elf(da, thread, umolya_path)
+
+ # load dsp bin
+ def on_load_dsp_button(self, event):
+ print "Select dsp bin...."
+ fileDialog = wx.FileDialog(self)
+ fileDialog.ShowModal()
+ dsp_path = fileDialog.GetPath()
+
+ thread = da.cores[0].hwthreads[0]
+ load_dsp_bin(da, thread, dsp_path,self.dsp_bin_addr)
+
+ def OnTextChanged(self, event):
+ Frame.dsp_bin_addr = event.String
+ print "Dsp address: " + self.dsp_bin_addr
+
+
+ app = wx.App()
+ frame = Frame(None, region_thread);
+ frame.Show()
+ app.MainLoop()
+ sys.exit()
+ else:
+ if (len(sys.argv) == 2):
+ umolya_path = sys.argv[1]
+ load_all_elf(da, thread, umolya_path)
+ else:
+ # WDT_Disable and DRAM_INIT done
+ sys.exit("[Reminder] Remember to load .elf")
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/fpga_emi_init_coreTracer.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/fpga_emi_init_coreTracer.cmm
new file mode 100755
index 0000000..c62a247
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/fpga_emi_init_coreTracer.cmm
@@ -0,0 +1,571 @@
+;sys.m prepare
+;LOCAL &TYPE
+LOCAL &BASE_MADDR_MDRGU
+LOCAL &BASE_MADDR_APRGU
+;IF DATA.LONG(DBG:0x41000000)==0x5BA02477 ; AP DAP
+;(
+; &TYPE="EAHB"
+; &BASE_MADDR_MDRGU=0x800F0000
+;)
+;ELSE ; DATA.LONG(DBG:0x41000000)==0x6BA02477 ; MD DAP
+;(
+; sys.m down
+; MULtiCore.DEBUGACCESSPORT 1
+; MULtiCore.AXIACCESSPORT 0
+; sys.m prepare
+; &TYPE="AXI"
+; &BASE_MADDR_MDRGU=0xA00F0000
+;)
+
+system.mode attach
+
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+; fixed md mips domain ID hw bug
+D.S 0xA0060060 %LE %LONG 0x03231111
+
+
+; do orginal disable_WDT2_MIPS.cmm
+&BASE_MADDR_MDRGU=0xA00F0000
+&BASE_MADDR_APRGU=0xC3670000
+
+;D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG (0x55000000|data.long(&BASE_MADDR_MDRGU+0x0100)&~(0x3))
+&temp=data.long(&BASE_MADDR_MDRGU+0x0100)
+&temp=&temp | 0x55000000
+&temp=&temp & ~(0x3)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG &temp
+
+
+;D.S &BASE_MADDR_APRGU+0x0100 %LE %LONG (0x55000000|data.long(&BASE_MADDR_APRGU+0x0100)&~(0x1))
+&temp=data.long(&BASE_MADDR_MDRGU+0x0100)
+&temp=&temp | 0x55000000
+&temp=&temp & ~(0x1)
+D.S &BASE_MADDR_APRGU+0x0100 %LE %LONG &temp
+
+
+
+; do orginal emi_init.cmm
+LOCAL &CHIP_VER ; 0 is for FPGA, 1 is for E1, and so on
+&CHIP_VER=0
+&BASE_ADDR_EMI=0xC3000000
+&BASE_ADDR_DRAMC=0xC3010000
+&BASE_ADDR_DDRPHY=0xC3020000
+&BASE_ADDR_MEMSYSAOREG_MISC=0xC3080000
+&BASE_ADDR_AP_CLKSW=0xC3750000
+
+; Check if initialize
+
+
+&temp=DATA.LONG(&BASE_ADDR_EMI+0060)
+&temp=&temp & 0x00000400
+IF (&temp == 0x00000400)
+(
+ ENDDO
+)
+
+;DRAM initialization
+
+GOSUB DRAM_INIT
+
+PRINT "=============================="
+PRINT "EMI Initialization Pass!"
+PRINT "=============================="
+
+D.S 0x0E800000 %LE %LONG 0x00
+D.S 0x00080000 %LE %LONG 0x00
+
+PRINT "=============================="
+PRINT "Clear Dsp Header!"
+PRINT "=============================="
+
+
+;Enalbe cache to speed loading
+register.set cdmmbase 0x1fc1407
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor adapter_khz 1100
+steal monitor mips32 fastchannel 0 1 0x6f800000
+
+
+PRINT "=============================="
+PRINT "Start to Load elf !"
+PRINT "=============================="
+
+
+steal lo
+
+steal monitor mips32 fastchannel 0 0 0x6f800000
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+
+PRINT "=============================="
+PRINT "Load elf Done!"
+PRINT "=============================="
+
+;thread.select 1
+
+;&tt=var.address(INT_Initialize_Phase1)
+;register.set pc &tt
+;steal flushreg
+
+;steal p/x $pc
+;&t=r(pc)
+;PRINT "=============================="
+;PRINT "Set PC to INT_Initialize_Phase1: &t"
+;PRINT "=============================="
+
+ENDDO
+
+
+; =========================================================================================
+; Sub Function: DRAM_INIT
+; Description: initialize MEMPLL, DRAMC, DDRPHY, DRAM, EMI
+; =========================================================================================
+DRAM_INIT:
+ ; =MEMSYS_PASSWORD=
+ ; Unlock MEMSYS Password
+ D.S &BASE_ADDR_MEMSYSAOREG_MISC+0x3000 %LE %LONG 0x24541689
+ ;GOSUB MEMPLL_INIT
+ GOSUB DRAMC_INIT
+ GOSUB EMI_INIT
+ ; =MEMINFRA_SI_WAY_CTL=
+ ; Enable MEMINFRA EMI Path
+ ; [9:8] M7_sysram:M7_emi
+ ; [7:6] M6_sysram:M6_emi
+ ; [5:4] M4_mdmda_sysram:M4_mddma_emi
+ ; [3:2] M4_l1sys_sysram:M4_l1sys_emi
+ ; [1:0] M3_sysram:M3_emi
+ ®_val=DATA.LONG(&BASE_ADDR_MEMSYSAOREG_MISC+0x4000)
+ ®_val=®_val|0x00000155
+ D.S &BASE_ADDR_MEMSYSAOREG_MISC+0x4000 %LE %LONG ®_val
+ ; =EMI_ADDR_OFFSET=
+ ; EMI offset on address[31:24], unit is 16MB
+ &MD3_offset=0x00
+ &MD2_offset=0x00
+ &MD1_offset=0x10
+ &ap_offset=0x00
+ &emi_offset=(&MD3_offset<<0x18)+(&MD2_offset<<0x10)+(&MD1_offset<<0x08)+(&ap_offset<<0x00)
+ D.S &BASE_ADDR_MEMSYSAOREG_MISC+0x1000 %LE %LONG &emi_offset
+ ; =MEMSYS_PASSWORD=
+ ; Lock MEMSYS Password
+ D.S &BASE_ADDR_MEMSYSAOREG_MISC+0x3000 %LE %LONG 0x00000000
+ RETURN
+
+; =========================================================================================
+; Sub Function: MEMPLL_INIT
+; =========================================================================================
+MEMPLL_INIT:
+ DATA.LOAD.ELF &emi_elf_path
+ B.D /ALL
+ B.S custom_InitDRAM /HARD
+ GO
+ WAIT !RUN() 5.s
+ IF r(PC)==custom_InitDRAM
+ (
+ PRINT "MEMPLL Initialization Pass!"
+ RETURN
+ )
+ ELSE
+ (
+ PRINT "MEMPLL Initialization Failed!"
+ ENDDO
+ )
+
+; =========================================================================================
+; Sub Function: DRAMC_INIT
+; Description: initialize DRAMC, DDRPHY, and DRAM, but this function doesn't initialize EMI
+; =========================================================================================
+DRAMC_INIT:
+ ; =ACTIM0=
+ D.S &BASE_ADDR_DRAMC+0x0000 %LE %LONG 0x44584493
+ ; =CONF1=
+ ; [18][5][3] no use in TK6291
+ ; [9:8]MTYPE, DRAM column address width, 2'b01 (9-bit) -> 2'b10 (10-bit)
+ ; TODO: [AC Timing] 0x00048683
+ D.S &BASE_ADDR_DRAMC+0x0004 %LE %LONG 0xF0008681 ; 0xF0008481
+ ; =R0DELDLY=
+ D.S &BASE_ADDR_DRAMC+0x0018 %LE %LONG 0x10101010
+ ; =R1DELDLY=
+ ; [30:24][22:16][14:8][6:0] DQS3/2/1/0 input delay
+ D.S &BASE_ADDR_DRAMC+0x001C %LE %LONG 0x12121212
+ ; =DLLCONF=
+ D.S &BASE_ADDR_DRAMC+0x0028 %LE %LONG 0x50000000
+ ; =TEST2_3=
+ ; [23] DQSICALI_NEW=0, using original dqs calibration
+ ; [7] TESTAUDPAT=0, ISI pattern can be set by TEST2_PAT0
+ D.S &BASE_ADDR_DRAMC+0x0044 %LE %LONG 0xBF080000
+ ; =TEST2_4=
+ D.S &BASE_ADDR_DRAMC+0x0048 %LE %LONG 0x1601110D
+ ; =DDR2CTL=
+ D.S &BASE_ADDR_DRAMC+0x007C %LE %LONG 0x00003201
+ ; =MISC=
+ ; [23:21]: PHYRXDSL_PIPE3~1 are pipe stage selection for RDATA and RDSEL
+ ; DATLAT_DSEL = DATLAT - 2*2 when enabling two top pipe (for TK6291)
+ D.S &BASE_ADDR_DRAMC+0x0080 %LE %LONG 0x00AC08A0
+ ; =ZQCS=
+ ; [15:8]: ZQCSAD, [7:0]: ZQCSOP
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x0084) & ~0x0000FFFF
+ ®_val=®_val|0x00000A56
+ D.S &BASE_ADDR_DRAMC+0x0084 %LE %LONG ®_val
+ ; =CLK1DELAY=
+ ; [23]: PHYPIPE3EN, [22]: PHYPIPE2EN, [21]: PHYPIPE1EN
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x008C) & ~0x00E00000
+ ®_val=®_val|0x00A00000
+ D.S &BASE_ADDR_DRAMC+0x008C %LE %LONG ®_val
+ ; =R0DQSIEN=
+ ; Gating Window for Rank0
+ D.S &BASE_ADDR_DRAMC+0x0094 %LE %LONG 0x31313131
+ ; =MCKDLY=
+ ; [23]: WODT has no load (useless)
+ ; [21]: DRAMEN has no load (useless)
+ ; [11:10] DQIENQKEND: DQ/DQS input enable window is larger than 6582. [11:10]=2'b00 => dle counter is 5'1f. =Others => dle counter is DATLAT-[11:10]+2
+ ; [4] DQIENLATEBEGIN, disable early begin, better for power saving
+ ; TODO: [20]: It is used for BST(Bus Termination), but TK6291 doesn't support the feature
+ D.S &BASE_ADDR_DRAMC+0x00D8 %LE %LONG 0x40500510
+ ; =DQSCTL1=
+ ; [27:24]: DQSINCTL, DQS input range control by M_CK
+ ; [23:12][11:0]: DQS3CTL/DQS2CTL, control by DDRPHY (useless)
+ D.S &BASE_ADDR_DRAMC+0x00E0 %LE %LONG 0x12200200
+ ; =GDDR3CTL1=
+ ; [24]: 8BKEN=1, 8-bank device enable
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x00F4) | 0x01000000
+ D.S &BASE_ADDR_DRAMC+0x00F4 %LE %LONG ®_val
+ ; [28]: PHYSYNCM=1, SYNC MODE using inverted PHY_M_CK
+ ®_val=DATA.LONG(&BASE_ADDR_DDRPHY+0x00F4) | 0x10000000
+ D.S &BASE_ADDR_DDRPHY+0x00F4 %LE %LONG ®_val
+ ; =MISCTL0=
+ ; [31]: REFP_ARB_EN2: per-bank refresh arbitration mask2
+ ; [30:28]: TXP, tXP Timing setting
+ ; [27] EMIPREEN: Enable advanced precharge function by EMI side-band signals, but TK6291 didn't support this feature.
+ ; [26] REFP_ARB_EN: per-bank refresh blocks in EMI arbitration
+ ; [25] REFA_ARB_EN: all-bank refresh blocks in EMI arbitration
+ ; [24] PBC_ARB_EN: block page-miss requests in EMI arbitration
+ ; [21]: REFA_ARB_EN2: all bank refresh arbtration mask enable option
+ D.S &BASE_ADDR_DRAMC+0x00FC %LE %LONG 0x81080000
+ ; [17]: INTLBT=0, IO internal loop back (useless for TK6291)
+ ; [16]: RXLPDDR2=0, IO voltage operating condition = {0:1.2V, 1:1.8V}
+ ®_val=DATA.LONG(&BASE_ADDR_DDRPHY+0x00FC) & ~0x00030000
+ D.S &BASE_ADDR_DDRPHY+0x00FC %LE %LONG ®_val
+ ; =OCDK=
+ ; [24]: DRVREF=1, drving change only when refresh cycle
+ ; [15]: DRDELSWEN=1, enable DQS input delay switching for different ranks
+ ; [8]: AUTOCALDRV=1, OCD calibration enable
+ ; [7:0]: AUTOKCNT, auto calibration counter
+ ; =RKCFG=
+ ; [7]: per-bank refresh for LPDDR2&3
+ ; TODO: [AC Timing] 0x004135C0
+ D.S &BASE_ADDR_DRAMC+0x0110 %LE %LONG 0x004121C0
+ ; =DQSCTL2=
+ D.S &BASE_ADDR_DRAMC+0x0118 %LE %LONG 0x00000002
+ ; =DQSGCTL=
+ ; [7:0] Old gating window course tune
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x0124) & ~0x000000FF
+ D.S &BASE_ADDR_DRAMC+0x0124 %LE %LONG ®_val
+ ; [31]: NEWDQSG_SEL, [30]:DQSGDUALP
+ ®_val=DATA.LONG(&BASE_ADDR_DDRPHY+0x0124) | 0xC0000000
+ D.S &BASE_ADDR_DDRPHY+0x0124 %LE %LONG ®_val
+ ; =CLKCTRL=
+ ; [29]: CLK_EN_1, [28]: CLK_EN_0
+ ; TODO: we should only enable one CLK for TK6291
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x0130) | 0x30000000
+ D.S &BASE_ADDR_DRAMC+0x0130 %LE %LONG ®_val
+ ; =ARBCTL0=
+ ; [7:0]: maximum pending number to block the arbitration
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x0168) & ~0x000000FF
+ ®_val=®_val|0x00000080
+ D.S &BASE_ADDR_DRAMC+0x0168 %LE %LONG ®_val
+ ; =DQSCAL0=
+ ; [31]: DQS strobe calibration enable
+ ; [30]: Update tracking gating value to 2 ranks simultaneously
+ ; [15]: Rank0 DQS strobe calibration high-limit enable
+ ; [14:8]: Rank0 DQS strobe calibration high-limit value
+ ; [7]: Rank0 DQS strobe calibration low-limit enable
+ ; [6:0]: Rank0 DQS strobe calibration low-limit value
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x01C0) & ~0xC000FFFF
+ ®_val=®_val | 0x80000000
+ D.S &BASE_ADDR_DRAMC+0x01C0 %LE %LONG ®_val
+ ; =MEMSYSPIPE_CGF_CTL=
+ ; [2]: PIPE_CFG_EN, [0]: DRAMC_CFG_EN
+ ; PIPE_CGF_ON=0 (timing issue) EMI_CGF_ON=0(Gated function is already designed in EMI) DRAMC_CGF_ON=1
+ D.S &BASE_ADDR_MEMSYSAOREG_MISC+0x5000 %LE %LONG 0x00000001
+ ; =DRAMC_PD_CTRL=
+ ; [24] REFFRERUN, using freerun clock to count refresh period
+ ; [23:16] REFCNT_FR_CLK, refresh period based on DRAMC freerun clock cycles
+ ; [15:8] TXREFCNT, tXSR
+ IF (&CHIP_VER==0)
+ (
+ D.S &BASE_ADDR_DRAMC+0x01DC %LE %LONG 0xC2002340
+ )
+ ELSE
+ (
+ D.S &BASE_ADDR_DRAMC+0x01DC %LE %LONG 0xC3002340
+ )
+ ; =LPDDR2_3=
+ ; TODO: should set to 0x10000000, not 0x3600_0000?
+ ; [31]: DRAM address decode by DRAMC
+ ; [28]: LPDDR2 enable
+ ; [27]: enable register output data by DRAMC
+ D.S &BASE_ADDR_DRAMC+0x01E0 %LE %LONG 0x36000000
+ ; [30]: Select IO O1 as output
+ ; [29&25:24&22:0]: DDR mode for pins
+ ; [26]: fast IO output enable
+ D.S &BASE_ADDR_DDRPHY+0x01E0 %LE %LONG 0x2601FFFF
+ ; =ACTIM1=
+ D.S &BASE_ADDR_DRAMC+0x01E8 %LE %LONG 0x81000510
+ ; =PERFCTL0=
+ ; [0] dual schedulers
+ D.S &BASE_ADDR_DRAMC+0x01EC %LE %LONG 0x0010CF11
+ ; TODO: AC_DERATING [0x01F0]
+ ; =RRRATE_CTL=, =MRR_CTL=
+ IF (&CHIP_VER==0) ; Or LPDDR3
+ (
+ D.S &BASE_ADDR_DRAMC+0x01F4 %LE %LONG 0x03020100
+ D.S &BASE_ADDR_DRAMC+0x01Fc %LE %LONG 0x07060504
+ )
+ ELSE
+ (
+ D.S &BASE_ADDR_DRAMC+0x01F4 %LE %LONG 0x02030100
+ D.S &BASE_ADDR_DRAMC+0x01Fc %LE %LONG 0x04060705
+ )
+ ; =AC_TIME_05T=
+ D.S &BASE_ADDR_DRAMC+0x01F8 %LE %LONG 0x04002600
+ ; =LPDDR2_4=
+ ; clock 1x phase selection
+ D.S &BASE_ADDR_DDRPHY+0x023C %LE %LONG 0x2201FFFF
+ ; =SELPH1=
+ ; TX 1x clock delay for CS1, RAS, CAS, WE, RESET, ODT, CKE, and CS
+ D.S &BASE_ADDR_DRAMC+0x0400 %LE %LONG 0x00000000
+ ; =SELPH2=
+ ; TX 1x clock delay for CKE1, DQSGATE_P1, CMD, DQSGATE, BA[2:0]
+ IF (&CHIP_VER==0)
+ (
+ D.S &BASE_ADDR_DRAMC+0x0404 %LE %LONG 0x00302000
+ )
+ ELSE
+ (
+ D.S &BASE_ADDR_DRAMC+0x0404 %LE %LONG 0x00101000
+ )
+ ; =SELPH3=
+ ; TX 1x clock delay for RA[7:0]
+ D.S &BASE_ADDR_DRAMC+0x0408 %LE %LONG 0x00000000
+ ; =SELPH4=
+ ; TX 1x clock delay for RA[15:8]
+ D.S &BASE_ADDR_DRAMC+0x040C %LE %LONG 0x00000000
+ ; =SELPH5=
+ ; TX 0.5's 2x clock delay for CKE1, DQSGATE_P1, DQSGATE, BA[2:0], CS1, RAS, CAS, WE, RESET, ODT, CKE, CS
+ IF (&CHIP_VER==0)
+ (
+ D.S &BASE_ADDR_DRAMC+0x0410 %LE %LONG 0x00955555
+ )
+ ELSE
+ (
+ D.S &BASE_ADDR_DRAMC+0x0410 %LE %LONG 0x57755555
+ )
+ ; TODO: SELPH6 [0x0414]
+ ; =SELPH6_1=
+ ; TX 1x clock delay for DQSGATE_P1 and DQSGATE of rank1
+ ; TX 0.5's 2x clock delay for DQSGATE_P1 and DQSGATE of rank1
+ D.S &BASE_ADDR_DRAMC+0x0418 %LE %LONG 0x00000228
+ ; =SELPH7=
+ ; TX 1x clock delay for DQ byte output enable[3:0] and DQ byte[3:0]
+ D.S &BASE_ADDR_DRAMC+0x041C %LE %LONG 0x11111111
+ ; =SELPH8=
+ ; TX 1x clock delay for DQM byte output enable[3:0] and DQM byte[3:0]
+ D.S &BASE_ADDR_DRAMC+0x0420 %LE %LONG 0x11111111
+ ; =SELPH9=
+ ; TX 1x clock delay for DQS byte output enable[3:0] and DQS byte[3:0]
+ D.S &BASE_ADDR_DRAMC+0x0424 %LE %LONG 0x11111111
+ ; =SELPH10=
+ ; TX 0.5's 2x clock delay for DQM output enable[3:0], DQ byte output enable[3:0], DQM[3:0], and DQ byte[3:0]
+ ; TODO: why we let output enable extra more 1.5 T not 0.5 DRAM clock?
+ D.S &BASE_ADDR_DRAMC+0x0428 %LE %LONG 0x0000FFFF
+ ; =SELPH11=
+ ; TX 0.5's 2x clock delay for DQS output enable[3:0] and DQS[3:0]
+ ; TODO: why we let output enable extra more 1.5 T not 0.5 DRAM clock?
+ D.S &BASE_ADDR_DRAMC+0x042C %LE %LONG 0x000000FF
+ ; TODO: offset 0x430~0x438, Don't we need to set clock 05x phase selection?
+ ; =SELPH12=
+ ; clock 05x phase selection for CLK, DQSGATE, DQS[3:0], and DQM[3:0]
+ ; clock 1x phase selection for DQS[3:0], DQM[3:0], CLK, and DQSGATE
+ D.S &BASE_ADDR_DDRPHY+0x0430 %LE %LONG 0x10F010F0
+ ; =SELPH13=
+ ; clock 1x phase selection for DQ[31:0]
+ D.S &BASE_ADDR_DDRPHY+0x0434 %LE %LONG 0xFFFFFFFF
+ ; =SELPH14=
+ ; clock 05x phase selection for DQ[31:0]
+ D.S &BASE_ADDR_DDRPHY+0x0438 %LE %LONG 0xFFFFFFFF
+ ; =SELPH15=
+ ; OCV (On-Chip Variation that affect by PVT). It is removed in TK6291.
+ ; OCV mode for DQSGATE, DQS[3:0], DQ[31:0], CLK, and CA
+ D.S &BASE_ADDR_DDRPHY+0x043C %LE %LONG 0x0000001F
+ ; =MEMPLL_DIVIDER=
+ ; DDRPHY reset flow for 1X clock phase sync
+ ; [5]: MEMCLKENB, SW control. It is used for MEMPLL initialization. After initialization, CLKENB is controlled by HW mode.
+ ; [4]: RG_DMSS_PWDB, ALLCLK_EN. It is used for gated MEMPLL output during initialization. (=1 after initilization)
+ ; [0]: MEMCLKENB_SEL, memory clock sync enable bar selection, selection for [5] (=1 select[5])
+ IF (&CHIP_VER!=0)
+ (
+ ®_val=DATA.LONG(&BASE_ADDR_DDRPHY+0x0640) | 0x00000031
+ D.S &BASE_ADDR_DDRPHY+0x0640 %LE %LONG ®_val
+ )
+ ; TODO: wait 500 sys_clock equal to 1.87us?
+ WAIT 2.us
+ GOSUB LPDDR2_INIT
+ IF (&CHIP_VER==0)
+ (
+ ; =CONF2=
+ D.S &BASE_ADDR_DRAMC+0x0008 %LE %LONG 0x0000631F
+ ; =DRAMC_PD_CTRL=
+ ;®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x01DC)&~0x00FF0000
+ ;®_val=®_val|0x00350000
+ ;D.S &BASE_ADDR_DRAMC+0x01DC %LE %LONG ®_val
+ )
+ ELSE
+ (
+ ; =CONF2=
+ ; [23] FREBW_FREN, tREFBW use xtal clock counter enable
+ ; [17:8] FREBW_FR, 6720ns/(XTALFR_clock)-1
+ ; [7:0] REFCNT: AC Timing Calculation is 0x3F, but ESL use 0x3B
+ ; TODO: [AC Timing] 0x0000003F
+ D.S &BASE_ADDR_DRAMC+0x0008 %LE %LONG 0x03806D3B
+ ; =DRAMC_PD_CTRL=
+ ; [23:16] REFCNT_FR_CLK, refresh period based on DRAMC freerun clock cycles
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x01DC) & ~0x00FF0000
+ ®_val=®_val | 0x00640000
+ D.S &BASE_ADDR_DRAMC+0x01DC %LE %LONG ®_val
+ )
+ RETURN
+
+; =========================================================================================
+; Sub Function: EMI_INIT
+; =========================================================================================
+EMI_INIT:
+ ; =EMI_CONA=
+ ; [27]: RANK_POS=0, {rank,row,bank,col}
+ ; [17]: DUAL_RANK_EN=0
+ ; [15:14][13:12]: ROW2ND=1,ROW=1, 14-bit row address
+ ; [7:6][5:4]: COL2ND=1,COL=1, 10-bit column address
+ ; [1]: DW32_EN=1, 32-bit data bus
+ D.S &BASE_ADDR_EMI+0x0000 %LE %LONG 0x00005052
+ ; =EMI_ARBI=
+ D.S &BASE_ADDR_EMI+0x0140 %LE %LONG 0x20406188
+ ; =EMI_ARBI_2ND=
+ D.S &BASE_ADDR_EMI+0x0144 %LE %LONG 0x20406188
+ ; =EMI_ARBD=
+ D.S &BASE_ADDR_EMI+0x0118 %LE %LONG 0x0700704C
+ ; =EMI_ARBE=
+ D.S &BASE_ADDR_EMI+0x0120 %LE %LONG 0x40407068
+ ; =EMI_ARBG=
+ D.S &BASE_ADDR_EMI+0x0130 %LE %LONG 0xFFFF7045
+ ; =EMI_ARBH=
+ D.S &BASE_ADDR_EMI+0x0138 %LE %LONG 0xA0A07047
+ ; TODO: CSR is not defined?
+ D.S &BASE_ADDR_EMI+0x0040 %LE %LONG 0x80808807
+ ; =EMI_ARBJ=
+ ; TODO: it is not defined in CSRv0.9
+ D.S &BASE_ADDR_EMI+0x0148 %LE %LONG 0x9719595E
+ ; =EMI_ARBJ_2ND=
+ ; TODO: it is not defined in CSRv0.9
+ D.S &BASE_ADDR_EMI+0x014C %LE %LONG 0x9719595E
+ ; =EMI_TEST_D=
+ D.S &BASE_ADDR_EMI+0x00F8 %LE %LONG 0x00000000
+ ; =EMI_BMEN=
+ ; TODO: why do we need to enable BUS_MON_EN for DRAM Init?
+ D.S &BASE_ADDR_EMI+0x0400 %LE %LONG 0x00FF0001
+ ; =EMI_CONB=
+ D.S &BASE_ADDR_EMI+0x0008 %LE %LONG 0x17283544
+ ; =EMI_CONC=
+ D.S &BASE_ADDR_EMI+0x0010 %LE %LONG 0x0A1A0B1A
+ ; TODO: offset 0x18 is not defined in CSR.
+ D.S &BASE_ADDR_EMI+0x0018 %LE %LONG 0x00000000
+ ; =EMI_CONE=
+ ; TODO: it is not defined in CSRv0.9
+ D.S &BASE_ADDR_EMI+0x0020 %LE %LONG 0xFFFF0848
+ ; =EMI_CONG=
+ D.S &BASE_ADDR_EMI+0x0030 %LE %LONG 0x2B2B2A38
+ ; =EMI_CONH=
+ D.S &BASE_ADDR_EMI+0x0038 %LE %LONG 0x00000000
+ ; =EMI_SLCT=
+ ; TODO: Why do we enable [17]:M1_LLAT_EN?
+ D.S &BASE_ADDR_EMI+0x0158 %LE %LONG 0xFF02FF00
+ ; =EMI_MDCT=
+ ; TODO: why don't we enable [14]:MDMCU_SBR_EN and [12]:ULTRA_SBR_EN?
+ D.S &BASE_ADDR_EMI+0x0078 %LE %LONG 0x002F0C17
+ ; TODO: it is not defined in CSR.
+ D.S &BASE_ADDR_EMI+0x015C %LE %LONG 0x80030303
+ ; =EMI_EMI_ARBK=
+ ; TODO: it only defines [23:16] in CSRv0.9
+ D.S &BASE_ADDR_EMI+0x0150 %LE %LONG 0x64F3FC79
+ ; =EMI_ARBK_2ND=
+ ; TODO: it is not defined in CSRv0.9
+ D.S &BASE_ADDR_EMI+0x0154 %LE %LONG 0x64F3FC79
+ ; =EMI_TESTC=
+ ; TODO: it only enables [16:8] in CSRv0.9
+ D.S &BASE_ADDR_EMI+0x00F0 %LE %LONG 0x38470000
+ ; =EMI_TESTB=
+ ; TODO: it didn't define [2:0] in CSRv0.9
+ D.S &BASE_ADDR_EMI+0x00E8 %LE %LONG 0x00020027
+ // Enable slave error
+ D.S &BASE_ADDR_EMI+0x01C0 %LE %LONG 0x10000000
+ D.S &BASE_ADDR_EMI+0x01C8 %LE %LONG 0x10000000
+ D.S &BASE_ADDR_EMI+0x01D0 %LE %LONG 0x10000000
+ D.S &BASE_ADDR_EMI+0x0200 %LE %LONG 0x10000000
+ D.S &BASE_ADDR_EMI+0x02C0 %LE %LONG 0x10000000
+ D.S &BASE_ADDR_EMI+0x02C8 %LE %LONG 0x10000000
+ D.S &BASE_ADDR_EMI+0x02D0 %LE %LONG 0x10000000
+ D.S &BASE_ADDR_EMI+0x0300 %LE %LONG 0x10000000
+ ; =EMI_CONM=
+ ; [10]: EMI_ENABLE=1
+ D.S &BASE_ADDR_EMI+0x0060 %LE %LONG 0x000006B8
+ ; =EMI_ARBP=
+ ; EBM_MODE enable
+ D.S &BASE_ADDR_EMI+0x0A20 %LE %LONG 0x00010000
+ RETURN
+
+; =========================================================================================
+; Sub Function: LPDDR2_INIT
+; =========================================================================================
+LPDDR2_INIT:
+ ; =PADCTL4=
+ ; [2]: CKE always on, [0]: CKE control by controller
+ ; CKE always on
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x00E4) | 0x00000005
+ D.S &BASE_ADDR_DRAMC+0x00E4 %LE %LONG ®_val
+ WAIT 200.us
+ ; LPDDR2 MRW RESET
+ GOSUB DRAMC_MRW 0x0000003F
+ WAIT 10.us
+ ; ZQ Init
+ GOSUB DRAMC_MRW 0x00FF000A
+ ; TODO: wait 1us after ZQ Initialization
+ WAIT 1.us
+ ; MRW MR1 => BL8, Sequential, Wrap, nWR=8
+ GOSUB DRAMC_MRW 0x00C30001
+ ; MRW MR2 => RL=8 and WL=4 for DDR1066
+ GOSUB DRAMC_MRW 0x00060002
+ ; MRW MR3 => 40-ohm typical
+ GOSUB DRAMC_MRW 0x00020003
+ ; =PADCTL4=
+ ; [2]: CKE always on, [0]: CKE control by controller
+ ; CKE is controlled by hardware
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x00E4) & ~0x00000004
+ D.S &BASE_ADDR_DRAMC+0x00E4 %LE %LONG ®_val
+ RETURN
+
+; =========================================================================================
+; Sub Function: DRAMC_MRW
+; Description: DRAMC Mode Register Write
+; argument:
+; @mrs mode register write value
+; =========================================================================================
+DRAMC_MRW:
+ ENTRY &mrs
+ LOCAL &spcmd
+ &spcmd=0x00000001
+ D.S &BASE_ADDR_DRAMC+0x0088 %LE %LONG &mrs
+ D.S &BASE_ADDR_DRAMC+0x01E4 %LE %LONG &spcmd
+ WAIT (DATA.LONG(&BASE_ADDR_DRAMC+0x03B8)&(&spcmd))==&spcmd
+ D.S &BASE_ADDR_DRAMC+0x01E4 %LE %LONG 0x00000000
+ WAIT (DATA.LONG(&BASE_ADDR_DRAMC+0x03B8)&(&spcmd))==0x00000000
+ RETURN
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/fpga_emi_test.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/fpga_emi_test.cmm
new file mode 100755
index 0000000..0d0ef87
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/fpga_emi_test.cmm
@@ -0,0 +1,102 @@
+; Use traffic-gen (TRFG) *4 to test DRAM, range 0x1000_0000 (256MB)
+; CVD repare mode
+; Use EAHB to config TRFG*4
+; start_addr test_length domain
+; TRFG0 0x0000_0000 0x0400_0000 1
+; TRFG1 0x0400_0000 0x0400_0000 1
+; TRFG2 0x0800_0000 0x0400_0000 1
+; TRFG3 0x0C00_0000 0x0400_0000 1
+; <VERSION-20150901A>
+
+system.Method Manual
+system.cpu cortexr4
+system.multicore SWDP ON
+system.JtagClock 1MHz
+sys.m prepare
+LOCAL &TYPE
+LOCAL &BASE_MADDR_MDRGU
+IF DATA.LONG(DBG:0x41000000)==0x5BA02477 ; AP DAP
+(
+ &TYPE="EAHB"
+ &BASE_MADDR_MDRGU=0x800F0000
+)
+ELSE ; DATA.LONG(DBG:0x41000000)==0x6BA02477 ; MD DAP
+(
+ sys.m down
+ MULtiCore.DEBUGACCESSPORT 1
+ MULtiCore.AXIACCESSPORT 0
+ sys.m prepare
+ &TYPE="AXI"
+ &BASE_MADDR_MDRGU=0xA00F0000
+)
+
+&TEST_LOOP=0x2 ; 0x0:infinite-loop; others:loop-N-times
+&TEST_CTRL=0x0 ; 0x0:config-and-start; others:bit-0:start,bit-1:pause,bit-2:resume.
+&TEST_RESULT=0x0 ; 0x0:pass; others:fail
+&TRFG_BASE=0xC3041000 ; TRFG 0~3 offset 0x100
+
+IF &TEST_CTRL!=0x0
+(
+ D.S &TYPE:&TRFG_BASE+0x000 %LONG %LE &TEST_CTRL
+ D.S &TYPE:&TRFG_BASE+0x100 %LONG %LE &TEST_CTRL
+ D.S &TYPE:&TRFG_BASE+0x200 %LONG %LE &TEST_CTRL
+ D.S &TYPE:&TRFG_BASE+0x300 %LONG %LE &TEST_CTRL
+ ENDDO
+)
+
+AREA.RESet
+AREA.Create TRFG_TEST
+AREA.Select TRFG_TEST
+AREA.View TRFG_TEST
+AREA.Clear TRFG_TEST
+
+; Config and start
+PRINT "TRFG config and start ..."
+&idx=0x0
+WHILE &idx<0x4
+(
+ &base=&TRFG_BASE+0x100*&idx
+ &start_addr=0x04000000*&idx
+ &pat_ctl=0x58FF0017+(&TEST_LOOP&0xF)<<8
+ D.S &TYPE:&base+0x00 %LONG %LE 0x00000000 ; TRFG_STRAT_CTL, [0]:start, [1]:pause, [2]:resume
+ D.S &TYPE:&base+0x04 %LONG %LE 0x5A5A5A5A ; TRFG_INIT_PAT_MSB
+ D.S &TYPE:&base+0x08 %LONG %LE 0xA5A5A5A5 ; TRFG_INIT_PAT_LSB
+ D.S &TYPE:&base+0x0C %LONG %LE &start_addr ; TRFG_START_ADDR
+ D.S &TYPE:&base+0x10 %LONG %LE 0x00800000 ; TRFG_TEST_LEN * 8 byte
+ D.S &TYPE:&base+0x14 %LONG %LE &pat_ctl ; TRFG_PAT_CTL, [11:8]:test_loop, [5:4]:pat_mode
+ D.S &TYPE:&base+0x18 %LONG %LE 0x0000010F ; TRFG_BUS_CTL, [10:8]:domain, [3:0]:burst_len
+ D.S &TYPE:&base+0x00 %LONG %LE 0x00000001 ; TRFG_STRAT_CTL, [0]:start, [1]:pause, [2]:resume
+ &idx=&idx+0x1
+)
+; Wait done
+PRINT "Wait done"
+&idx=0x0
+WHILE &idx<0x4
+(
+ &base=&TRFG_BASE+0x100*&idx
+ WHILE (D.L(&TYPE:&base+0x20)&0x1)==0x1
+ (
+ PRINT "."
+ WAIT 1.S
+ )
+ IF (D.L(&TYPE:&base+0x20)&0x04)==0x0
+ (
+ &TEST_RESULT=&TEST_RESULT+0x1
+ PRINT "=> TRFG &idx test fail:"
+ PRINT "FAIL_ADDR = " D.L(&TYPE:&base+0x24)
+ PRINT "EXP_DATA_MSB = " D.L(&TYPE:&base+0x28)
+ PRINT "EXP_DATA_LSB = " D.L(&TYPE:&base+0x2C)
+ PRINT "FAIL_DATA_MSB = " D.L(&TYPE:&base+0x30)
+ PRINT "FAIL_DATA_LSB = " D.L(&TYPE:&base+0x34)
+ )
+ &idx=&idx+0x1
+)
+
+IF &TEST_RESULT==0x0
+(
+ PRINT "=> Traffic-Gen dram test pass ...^_^"
+)
+ELSE
+(
+ PRINT "=> Traffic-Gen dram test fail ...>'<"
+)
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/load_dsp_bin.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/load_dsp_bin.cmm
new file mode 100644
index 0000000..fc76bce
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/GEN93M17/load_dsp_bin.cmm
@@ -0,0 +1,19 @@
+
+system.mode attach
+&dsp_bin="D:/dsp.bin"
+&load_addr=0x0E800000
+
+
+PRINT "-----------Start load DSP!--------------"
+
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor mips32 fastchannel 0 1 0x6f800000
+
+DATA.LOAD.BINARY "&dsp_bin" &load_addr
+
+steal monitor mips32 fastchannel 0 0 0x6f800000
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+
+PRINT "-----------Load DSP Done!--------------"
+
+ENDDO
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/APView_MT3967_EVB_UART_Test.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/APView_MT3967_EVB_UART_Test.cmm
new file mode 100755
index 0000000..a12d20c
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/APView_MT3967_EVB_UART_Test.cmm
@@ -0,0 +1,35 @@
+;Eiger MD_UART0 port test
+;You should make sure GPIO13 has connected to UART port RXD pin,GPIO14 has connected to UART port TXD pin
+
+;port: MDUART0
+;Baudrate: 115200
+;&BASE_ADDR_MDUART0=0xB0010000
+sys.m prepare
+&BASE_ADDR_MDUART0=0x20010000
+&BASE_ADDR_MDGPIO=0x10005000
+&BASE_ADDR_IOCFG=0x11F80000
+
+D.S AXI:&BASE_ADDR_MDGPIO+0x318 %LE %LONG 0x7700000 ;//clear GPIO13 and GPIO14 to GPIO mode.
+D.S AXI:&BASE_ADDR_MDGPIO+0x314 %LE %LONG 0x4400000 ;//set GPIO13 to MD_URXD0 mode,set GPIO14 to MD_UTXD0 mode,
+D.S AXI:&BASE_ADDR_IOCFG+0x58 %LE %LONG 0x06 ;//MD_URXD0/MD_UTXD0 PD clear
+D.S AXI:&BASE_ADDR_IOCFG+0x64 %LE %LONG 0x02 ;//MD_URXD0 PU set
+
+D.S AXI:&BASE_ADDR_MDUART0+0x24 %LE %LONG 0x03 ;//High Speed X
+D.S AXI:&BASE_ADDR_MDUART0+0x28 %LE %LONG 0xE1 ;//Sample count
+D.S AXI:&BASE_ADDR_MDUART0+0x2C %LE %LONG 0x71 ;//sample point
+D.S AXI:&BASE_ADDR_MDUART0+0x0C %LE %LONG 0x83 ;//Enable Divisor latch acess bit, and set 8bit length.
+D.S AXI:&BASE_ADDR_MDUART0+0x00 %LE %LONG 0x01 ;//sample point
+D.S AXI:&BASE_ADDR_MDUART0+0x04 %LE %LONG 0x00 ;//sample point
+D.S AXI:&BASE_ADDR_MDUART0+0x0C %LE %LONG 0x03 ;//Clear Divisor latch acess bit, and set 8bit length.
+
+&uart_lsr=0x0
+&uart_rxd=0x0
+PRINT "Please put char "U" from PC to EVB UART! Note: ASCII "U" remap to HEX is 0x55 "
+WHILE (&uart_lsr&0x01)!=0x01
+(
+ &uart_lsr=data.long(AXI:&BASE_ADDR_MDUART0+0x14)
+)
+&uart_rxd=data.long(AXI:&BASE_ADDR_MDUART0+0x0)
+PRINT "EVB UART Get data: &uart_rxd"
+D.S AXI:&BASE_ADDR_MDUART0+0x00 %LE %LONG &uart_rxd ;//Write data to UART, please check console.
+PRINT "EVB UART will send data to PC,please check!"
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/APview_MT3967_Frequency_Meter.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/APview_MT3967_Frequency_Meter.cmm
new file mode 100755
index 0000000..7c47864
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/APview_MT3967_Frequency_Meter.cmm
@@ -0,0 +1,540 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; EIGER MD Frequency Meter
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;;Select PLL
+LOCAL &key_in
+&key_in=0
+
+LOCAL &opt_cvd_connect
+&opt_cvd_connect="debug"
+
+;;;;;;;;;;;;;;;;;;;;;;;Below you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+LOCAL &mclass ;; Memory Class
+&mclass="axi"
+;&mclass="pm"
+
+LOCAL &clksw_base ;; MD CLKSW base address
+;&clksw_base=0xA0150000 ;; MD view APB
+;&clksw_base=0xA0096000 ;; MD view debug APB
+&clksw_base=0x20150000 ;; AP view MD system bus
+;&clksw_base=0x0D0D6000 ;; AP view MD debug sys
+
+LOCAL &pll_base ;; MD PLLMIXED base address
+;&pll_base=0xA0140000 ;; MD view APB
+;&pll_base=0xA0094000 ;; MD view debug APB
+&pll_base=0x20140000 ;; AP view MD system bus
+;&pll_base=0x0D0D4000 ;; AP view MD debug sys
+
+&fqmtr_fcksel_32k_index=0x17
+;;;;;;;;;;;;;;;;;;;;;;;Above you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LOCAL &fqmtr_winset ;; Frequency Meter Windoiw Setting (= Number of FIXED clock cycle)
+&fqmtr_winset=0x1ff
+&fqmtr_winset_for_32k=0x1E000
+
+LOCAL &fqmtr_fcksel_val ;; Frequency Meter FIXED clock selection
+&fqmtr_fcksel_val=0x1a ;; Select 26Mhz by default
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;All the PLL you could select;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+&SRC_STR_1="Reserved"
+&SRC_STR_2="Reserved"
+&SRC_STR_3="Reserved"
+&SRC_STR_4="MDBPI_PLL_D4"
+&SRC_STR_5="MDBPI_PLL_D6"
+&SRC_STR_6="mdsys_mml2_ck"
+&SRC_STR_7="fesys_rxagc_ck"
+&SRC_STR_8="mdrxsys_dfesync_ck"
+&SRC_STR_9="fesys_f208m_ck"
+&SRC_STR_10="TRACE_MON_clock"
+&SRC_STR_11="MDSYS_208M_clock"
+&SRC_STR_12="mdrxsys_rake_ck"
+&SRC_STR_13="mdrxsys_brp_ck"
+&SRC_STR_14="mdrxsys_vdsp_ck"
+&SRC_STR_15="mdtop_log_atb_ck"
+&SRC_STR_16="fesys_csys_ck"
+&SRC_STR_17="Reserved"
+&SRC_STR_18="fesys_bsi_ck"
+&SRC_STR_19="mdsys_mdcore_ck"
+&SRC_STR_20="mdsys_bus2x_nodcm_ck"
+&SRC_STR_21="mdsys_bus2x_ck"
+&SRC_STR_22="mdtop_dbg_ck"
+&SRC_STR_23="mdtop_f32k_ck"
+&SRC_STR_24="AD_MDBPIPLL_D7"
+&SRC_STR_25="AD_MDBPIPLL_D5"
+&SRC_STR_26="AD_MDBPIPLL_D4"
+&SRC_STR_27="AD_MDBPIPLL_D3"
+&SRC_STR_28="AD_MDBPIPLL_D2"
+&SRC_STR_29="AD_MDBRPPLL"
+&SRC_STR_30="AD_MDVDSPPLL"
+&SRC_STR_31="AD_MDMCUPLL"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+DIALOG
+(&
+ HEADER "PLL Frequency Meter"
+ ICON ":chip"
+
+ POS 0. 0. 20. 1.
+ LINE "FQMTR Selection"
+ ; x y w h
+ POS 0. 1. 20. 1.
+ SEL.NONE: CHOOSEBOX "None"
+ (
+ &key_in=0x00
+ )
+;; SEL.1: CHOOSEBOX "&SRC_STR_1"
+;; (
+;; &key_in=0x1
+;; &key_str="&SRC_STR_1"
+;; )
+;; SEL.2: CHOOSEBOX "&SRC_STR_2"
+;; (
+;; &key_in=0x2
+;; &key_str="&SRC_STR_2"
+;; )
+;; SEL.3: CHOOSEBOX "&SRC_STR_3"
+;; (
+;; &key_in=0x3
+;; &key_str="&SRC_STR_3"
+;; )
+ SEL.4: CHOOSEBOX "&SRC_STR_4"
+ (
+ &key_in=0x4
+ &key_str="&SRC_STR_4"
+ )
+ SEL.5: CHOOSEBOX "&SRC_STR_5"
+ (
+ &key_in=0x5
+ &key_str="&SRC_STR_5"
+ )
+ SEL.6: CHOOSEBOX "&SRC_STR_6"
+ (
+ &key_in=0x6
+ &key_str="&SRC_STR_6"
+ )
+ SEL.7: CHOOSEBOX "&SRC_STR_7"
+ (
+ &key_in=0x7
+ &key_str="&SRC_STR_7"
+ )
+ SEL.8: CHOOSEBOX "&SRC_STR_8"
+ (
+ &key_in=0x8
+ &key_str="&SRC_STR_8"
+ )
+ SEL.9: CHOOSEBOX "&SRC_STR_9"
+ (
+ &key_in=0x9
+ &key_str="&SRC_STR_9"
+ )
+ SEL.10: CHOOSEBOX "&SRC_STR_10"
+ (
+ &key_in=0xA
+ &key_str="&SRC_STR_10"
+ )
+ SEL.11: CHOOSEBOX "&SRC_STR_11"
+ (
+ &key_in=0xB
+ &key_str="&SRC_STR_11"
+ )
+ SEL.12: CHOOSEBOX "&SRC_STR_12"
+ (
+ &key_in=0xC
+ &key_str="&SRC_STR_12"
+ )
+ SEL.13: CHOOSEBOX "&SRC_STR_13"
+ (
+ &key_in=0xD
+ &key_str="&SRC_STR_13"
+ )
+ SEL.14: CHOOSEBOX "&SRC_STR_14"
+ (
+ &key_in=0xE
+ &key_str="&SRC_STR_14"
+ )
+ SEL.15: CHOOSEBOX "&SRC_STR_15"
+ (
+ &key_in=0xF
+ &key_str="&SRC_STR_15"
+ )
+ SEL.16: CHOOSEBOX "&SRC_STR_16"
+ (
+ &key_in=0x10
+ &key_str="&SRC_STR_16"
+ )
+;; SEL.17: CHOOSEBOX "&SRC_STR_17"
+;; (
+;; &key_in=0x11
+;; &key_str="&SRC_STR_17"
+;; )
+ SEL.18: CHOOSEBOX "&SRC_STR_18"
+ (
+ &key_in=0x12
+ &key_str="&SRC_STR_18"
+ )
+ SEL.19: CHOOSEBOX "&SRC_STR_19"
+ (
+ &key_in=0x13
+ &key_str="&SRC_STR_19"
+ )
+ SEL.20: CHOOSEBOX "&SRC_STR_20"
+ (
+ &key_in=0x14
+ &key_str="&SRC_STR_20"
+ )
+ SEL.21: CHOOSEBOX "&SRC_STR_21"
+ (
+ &key_in=0x15
+ &key_str="&SRC_STR_21"
+ )
+ SEL.22: CHOOSEBOX "&SRC_STR_22"
+ (
+ &key_in=0x16
+ &key_str="&SRC_STR_22"
+ )
+ SEL.23: CHOOSEBOX "&SRC_STR_23"
+ (
+ &key_in=0x17
+ &key_str="&SRC_STR_23"
+ )
+ SEL.24: CHOOSEBOX "&SRC_STR_24"
+ (
+ &key_in=0x18
+ &key_str="&SRC_STR_24"
+ )
+ SEL.25: CHOOSEBOX "&SRC_STR_25"
+ (
+ &key_in=0x19
+ &key_str="&SRC_STR_25"
+ )
+ SEL.26: CHOOSEBOX "&SRC_STR_26"
+ (
+ &key_in=0x1A
+ &key_str="&SRC_STR_26"
+ )
+ SEL.27: CHOOSEBOX "&SRC_STR_27"
+ (
+ &key_in=0x1B
+ &key_str="&SRC_STR_27"
+ )
+ SEL.28: CHOOSEBOX "&SRC_STR_28"
+ (
+ &key_in=0x1C
+ &key_str="&SRC_STR_28"
+ )
+ SEL.29: CHOOSEBOX "&SRC_STR_29"
+ (
+ &key_in=0x1D
+ &key_str="&SRC_STR_29"
+ )
+ SEL.30: CHOOSEBOX "&SRC_STR_30"
+ (
+ &key_in=0x1E
+ &key_str="&SRC_STR_30"
+ )
+ SEL.31: CHOOSEBOX "&SRC_STR_31"
+ (
+ &key_in=0x1F
+ &key_str="&SRC_STR_31"
+ )
+
+ POS 21. 0. 20. 1.
+ LINE "FQMTR Information"
+ INFO1: EDIT "Window Seting: &fqmtr_winset" ""
+ INFO2: EDIT "Fixed Clock: &fqmtr_fcksel_val" ""
+ INFO3: EDIT "32K measure support" ""
+
+ POSY 1. 20. 1.
+ LINE "FQMTR Result"
+ RESULT: EDIT "" ""
+
+ POSY 1. 20. 1.
+ DEFBUTTON "OK"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ IF &key_in!=0
+ (
+ GOSUB fqmtr_query &key_in &key_str 1
+ )
+ )
+
+ DEFBUTTON "LIST ALL"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ GOSUB fqmtr_list_all
+ )
+
+ DEFBUTTON "Force LIST main clk"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ GOSUB fqmtr_force_list_all
+ )
+
+ CLOSE
+ (
+ PRINT "bye~"
+ DIALOG.END
+ )
+)
+
+ ;; Disable EDIT of showing information
+ DIALOG.Disable INFO1
+ DIALOG.Disable INFO2
+ DIALOG.Disable INFO3
+ ;DIALOG.Disable RESULT
+STOP
+ENDDO
+
+;;;;;The main function to get the Frequency. &idx==> the clock you select, &str==> clock name, &info==>list more info and wait 5ms in the function
+;; &info=1 ==> for printing many PLLs at one time
+fqmtr_query:
+ENTRY &idx &str &info
+(
+ IF &info!=0
+ (
+ PRINT "&str: &idx"
+ PRINT "fqmtrsrc: 0x" FORMAT.HEX(2,&idx)
+ PRINT "opt_cvd_connect: &opt_cvd_connect"
+ )
+
+ LOCAL &unit
+ LOCAL &fqmtr_winset_26M
+ LOCAL &fqmtr_result
+ LOCAL &fqmtr_result_raw
+ LOCAL &fqmtr_result_str
+ LOCAL &safe_wait_cnt
+ LOCAL &safe_wait_cnt_max
+ LOCAL &fqmtr_busy
+
+ &safe_wait_cnt=0
+
+ IF &fqmtr_fcksel_val==0x1a ;; base on 26M, unit:MHz
+ (
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &unit="Khz"
+ &fqmtr_winset_26M=&fqmtr_winset_for_32k
+ &safe_wait_cnt_max=500 ;;5000 ms = 5s ==> in real test, longer than 5s, so reduce it
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &unit="Mhz"
+ &fqmtr_winset_26M=&fqmtr_winset
+ &safe_wait_cnt_max=32 ;;32 ms
+ )
+ )
+ ELSE
+ (
+ &unit=""
+ )
+
+ IF "&opt_cvd_connect"=="none"
+ (
+ sys.m prepare
+ )
+ ELSE IF "&opt_cvd_connect"=="debug"
+ (
+ ; do nothing
+ )
+ ELSE
+ (
+ IF &info!=0
+ (
+ PRINT "No explicit CVD connection, use current status"
+ )
+ )
+
+ IF &idx==0
+ (
+ ;; This is used for connect CVD only, no FQMTR test
+ RETURN
+ )
+
+ ;;select source to a valid clock to let reset success.
+ Data.Set &mclass:(&clksw_base+0x0200) %LE %LONG 0x13
+ Data.Set &mclass:(&clksw_base+0x0204) %LE %LONG 0x0 ;reset frequency meter
+ WAIT 1ms
+
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ ;;For accurate, don't div 8 for 32K
+ Data.Set &mclass:(&clksw_base+0x0200) %LE %LONG (&idx)
+ )
+ ELSE ;; measure PLL and other module
+ (
+ ;;div 8 and select src
+ Data.Set &mclass:(&clksw_base+0x0200) %LE %LONG (0x0300)|(&idx)
+ )
+
+ Data.Set &mclass:(&clksw_base+0x0208) %LE %LONG &fqmtr_winset_26M
+ Data.Set &mclass:(&clksw_base+0x0204) %LE %LONG 0x1 ;enable frequency meter
+
+ ;; read status, to check polling done or not
+ &fqmtr_busy=DATA.LONG(&mclass:(&clksw_base+0x0204))&(1<<1)
+ WHILE &fqmtr_busy==0
+ (
+ ;PRINT ". &fqmtr_busy"
+ &fqmtr_busy=DATA.LONG(&mclass:(&clksw_base+0x0204))&(1<<1)
+ &safe_wait_cnt=&safe_wait_cnt+1
+ IF &safe_wait_cnt==&safe_wait_cnt_max
+ (
+ PRINT "[&str] Wait Fail, exit"
+ DIALOG.Set RESULT "Wait Fail(No clock), exit"
+ RETURN
+ )
+ ELSE
+ (
+;; PRINT "Waiting result. safe_wait_cnt=" "&safe_wait_cnt"
+ )
+ WAIT 1ms
+ )
+
+ ;; Calculate the result
+ &fqmtr_result_raw=DATA.LONG(&mclass:(&clksw_base+0x20c))
+
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*(0x3E8)/&fqmtr_winset_26M
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*8/&fqmtr_winset_26M
+ )
+
+ &fqmtr_result_dec=FORMAT.DECIMAL(0,&fqmtr_result)
+ &fqmtr_result_str=""+FORMAT.DECIMAL(0,&fqmtr_result)+" &unit"
+ IF &info==0
+ (
+ PRINT "0x" FORMAT.HEX(2,&idx) ",&fqmtr_result_dec,&unit,&str,&fqmtr_result_raw,"
+ )
+ ELSE
+ (
+ PRINT "Frequency Meter Result: &fqmtr_result_str (&fqmtr_result_raw)"
+ PRINT ""
+ )
+ DIALOG.Set RESULT "&fqmtr_result_str"
+
+ IF &info==0
+ (
+ WAIT 5ms
+ )
+
+ RETURN
+)
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+fqmtr_create_win:
+(
+ AREA.RESet
+ AREA.Create PLL_FMETER
+ AREA.Select PLL_FMETER
+ WinPOS 10.,0.,50.,35.,,, FMETER
+ AREA.view PLL_FMETER
+ AREA.Clear PLL_FMETER
+ RETURN
+)
+
+fqmtr_list_all:
+(
+ GOSUB fqmtr_create_win
+
+ ;GOSUB fqmtr_query 0x1 &SRC_STR_1 0
+ ;GOSUB fqmtr_query 0x2 &SRC_STR_2 0
+ ;GOSUB fqmtr_query 0x3 &SRC_STR_3 0
+ GOSUB fqmtr_query 0x4 &SRC_STR_4 0
+ GOSUB fqmtr_query 0x5 &SRC_STR_5 0
+ GOSUB fqmtr_query 0x6 &SRC_STR_6 0
+ GOSUB fqmtr_query 0x7 &SRC_STR_7 0
+ GOSUB fqmtr_query 0x8 &SRC_STR_8 0
+ GOSUB fqmtr_query 0x9 &SRC_STR_9 0
+ GOSUB fqmtr_query 0xA &SRC_STR_10 0
+ GOSUB fqmtr_query 0xB &SRC_STR_11 0
+ GOSUB fqmtr_query 0xC &SRC_STR_12 0
+ GOSUB fqmtr_query 0xD &SRC_STR_13 0
+ GOSUB fqmtr_query 0xE &SRC_STR_14 0
+ GOSUB fqmtr_query 0xF &SRC_STR_15 0
+ GOSUB fqmtr_query 0x10 &SRC_STR_16 0
+ ;GOSUB fqmtr_query 0x11 &SRC_STR_17 0
+ GOSUB fqmtr_query 0x12 &SRC_STR_18 0
+ GOSUB fqmtr_query 0x13 &SRC_STR_19 0
+ GOSUB fqmtr_query 0x14 &SRC_STR_20 0
+ GOSUB fqmtr_query 0x15 &SRC_STR_21 0
+ GOSUB fqmtr_query 0x16 &SRC_STR_22 0
+ GOSUB fqmtr_query 0x17 &SRC_STR_23 0
+ GOSUB fqmtr_query 0x18 &SRC_STR_24 0
+ GOSUB fqmtr_query 0x19 &SRC_STR_25 0
+ GOSUB fqmtr_query 0x1A &SRC_STR_26 0
+ GOSUB fqmtr_query 0x1B &SRC_STR_27 0
+ GOSUB fqmtr_query 0x1C &SRC_STR_28 0
+ GOSUB fqmtr_query 0x1D &SRC_STR_29 0
+ GOSUB fqmtr_query 0x1E &SRC_STR_30 0
+ GOSUB fqmtr_query 0x1F &SRC_STR_31 0
+ RETURN
+)
+
+fqmtr_force_list_all:
+(
+ GOSUB fqmtr_create_win
+
+ LOCAL &original_reg
+ LOCAL &original_reg1
+ LOCAL &original_reg2
+
+ &original_reg=DATA.LONG(&mclass:(&pll_base+0x10))
+ &original_reg1=DATA.LONG(&mclass:(&clksw_base+0x10))
+ &original_reg2=DATA.LONG(&mclass:(&clksw_base+0x14))
+
+ ; S/W force on all PLL
+ Data.Set &mclass:(&pll_base+0x10) %LE %LONG 0xFFFFFFFF
+
+ ; S/W force on all module clock
+ Data.Set &mclass:(&clksw_base+0x10) %LE %LONG 0xFFFFFFFF
+ Data.Set &mclass:(&clksw_base+0x14) %LE %LONG 0xFFFFFFFF
+
+ WAIT 1.s
+
+ ;GOSUB fqmtr_query 0x1 &SRC_STR_1 0
+ ;GOSUB fqmtr_query 0x2 &SRC_STR_2 0
+ ;GOSUB fqmtr_query 0x3 &SRC_STR_3 0
+ GOSUB fqmtr_query 0x4 &SRC_STR_4 0
+ GOSUB fqmtr_query 0x5 &SRC_STR_5 0
+ GOSUB fqmtr_query 0x6 &SRC_STR_6 0
+ GOSUB fqmtr_query 0x7 &SRC_STR_7 0
+ GOSUB fqmtr_query 0x8 &SRC_STR_8 0
+ GOSUB fqmtr_query 0x9 &SRC_STR_9 0
+ GOSUB fqmtr_query 0xA &SRC_STR_10 0
+ GOSUB fqmtr_query 0xB &SRC_STR_11 0
+ GOSUB fqmtr_query 0xC &SRC_STR_12 0
+ GOSUB fqmtr_query 0xD &SRC_STR_13 0
+ GOSUB fqmtr_query 0xE &SRC_STR_14 0
+ GOSUB fqmtr_query 0xF &SRC_STR_15 0
+ GOSUB fqmtr_query 0x10 &SRC_STR_16 0
+ ;GOSUB fqmtr_query 0x11 &SRC_STR_17 0
+ GOSUB fqmtr_query 0x12 &SRC_STR_18 0
+ GOSUB fqmtr_query 0x13 &SRC_STR_19 0
+ GOSUB fqmtr_query 0x14 &SRC_STR_20 0
+ GOSUB fqmtr_query 0x15 &SRC_STR_21 0
+ GOSUB fqmtr_query 0x16 &SRC_STR_22 0
+ GOSUB fqmtr_query 0x17 &SRC_STR_23 0
+ GOSUB fqmtr_query 0x18 &SRC_STR_24 0
+ GOSUB fqmtr_query 0x19 &SRC_STR_25 0
+ GOSUB fqmtr_query 0x1A &SRC_STR_26 0
+ GOSUB fqmtr_query 0x1B &SRC_STR_27 0
+ GOSUB fqmtr_query 0x1C &SRC_STR_28 0
+ GOSUB fqmtr_query 0x1D &SRC_STR_29 0
+ GOSUB fqmtr_query 0x1E &SRC_STR_30 0
+ GOSUB fqmtr_query 0x1F &SRC_STR_31 0
+
+ ; Revert to original value
+ Data.Set &mclass:(&pll_base+0x10) %LE %LONG &original_reg
+ Data.Set &mclass:(&clksw_base+0x10) %LE %LONG &original_reg1
+ Data.Set &mclass:(&clksw_base+0x14) %LE %LONG &original_reg2
+
+ WAIT 1.s
+
+ RETURN
+)
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/APview_MT3967_GPIO_MDUART0.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/APview_MT3967_GPIO_MDUART0.cmm
new file mode 100755
index 0000000..436d4c6
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/APview_MT3967_GPIO_MDUART0.cmm
@@ -0,0 +1,15 @@
+;Eiger MD_UART0 port IOPAD configure
+;You should make sure GPIO13 has connected to UART port RXD pin,GPIO14 has connected to UART port TXD pin
+
+;port: MDUART0
+;Baudrate: 1500000
+;&BASE_ADDR_MDUART0=0xB0010000
+sys.m prepare
+&BASE_ADDR_MDUART0=0x20010000
+&BASE_ADDR_MDGPIO=0x10005000
+&BASE_ADDR_IOCFG=0x11F80000
+
+D.S AXI:&BASE_ADDR_MDGPIO+0x318 %LE %LONG 0x7700000 ;//clear GPIO13 and GPIO14 to GPIO mode.
+D.S AXI:&BASE_ADDR_MDGPIO+0x314 %LE %LONG 0x4400000 ;//set GPIO13 to MD_URXD0 mode,set GPIO14 to MD_UTXD0 mode,
+D.S AXI:&BASE_ADDR_IOCFG+0x58 %LE %LONG 0x06 ;//MD_URXD0/MD_UTXD0 PD clear
+D.S AXI:&BASE_ADDR_IOCFG+0x64 %LE %LONG 0x02 ;//MD_URXD0 PU set
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/APview_MT3967_GPIO_SIM.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/APview_MT3967_GPIO_SIM.cmm
new file mode 100755
index 0000000..4e9ce21
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/APview_MT3967_GPIO_SIM.cmm
@@ -0,0 +1,15 @@
+// SIM2 GPIO
+d.s &MEM_CLASS:0x10005370 %long %le data.long(&MEM_CLASS:0x10005370)&(0x000FFFFF)
+d.s &MEM_CLASS:0x10005370 %long %le data.long(&MEM_CLASS:0x10005370)|(0x11100000)
+
+// SIM1 GPIO
+d.s &MEM_CLASS:0x10005380 %long %le data.long(&MEM_CLASS:0x10005380)&(0xFFFFF000)
+d.s &MEM_CLASS:0x10005380 %long %le data.long(&MEM_CLASS:0x10005380)|(0x00000111)
+
+// SIM2 PUPD
+d.s &MEM_CLASS:0x11E700A0 %long %le data.long(&MEM_CLASS:0x11E700A0)&(0x0000003F)
+d.s &MEM_CLASS:0x11E700A0 %long %le data.long(&MEM_CLASS:0x11E700A0)|(0x00000140)
+
+// SIM1 PUPD
+d.s &MEM_CLASS:0x11D10080 %long %le data.long(&MEM_CLASS:0x11D10080)&(0x00000000)
+d.s &MEM_CLASS:0x11D10080 %long %le data.long(&MEM_CLASS:0x11D10080)|(0x00000005)
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/APview_MT3967_MD_ForceOnDebugSys.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/APview_MT3967_MD_ForceOnDebugSys.cmm
new file mode 100755
index 0000000..32fce9b
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/APview_MT3967_MD_ForceOnDebugSys.cmm
@@ -0,0 +1,16 @@
+;Core1 force on
+d.s &MEM_CLASS:0x200D0004 %long %le 0xB2002482
+;Core2 force on
+d.s &MEM_CLASS:0x200D0008 %long %le 0xB2002382
+;ForceOn debug sys
+d.s &MEM_CLASS:0x20150010 %long %le data.long(&MEM_CLASS:0x20150010)|(0x00080008)
+d.s &MEM_CLASS:0x200D04B0 %long %le data.long(&MEM_CLASS:0x200D04B0)|(0x00000008)
+&temp=data.long(&MEM_CLASS:0x200D0590)
+IF (&temp&0x8)!=0x8
+(
+ PRINT "Force on debug sys clock fail"
+)
+ELSE
+(
+ PRINT "Force on debug sys clock success"
+)
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/APview_MT3967_MD_PLL_Init.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/APview_MT3967_MD_PLL_Init.cmm
new file mode 100755
index 0000000..778e859
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/APview_MT3967_MD_PLL_Init.cmm
@@ -0,0 +1,95 @@
+; /* Step 6 config PLL setting */
+;;==============================PLL init start==================================================
+;;sys.m prepare
+&MEM_CLASS="AXI"
+
+&BASE_MADDR_APMIXEDSYS=(0x1000C000)
+&BASE_MADDR_MDTOP_PLLMIXED=(0x20140000)
+&BASE_MADDR_MDTOP_CLKSW=(0x20150000)
+
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+
+®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+®_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x60)
+®_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x70)
+®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0xA4)
+
+&MD_PLL_MAGIC_NUM=(0x62950000)
+
+;;//Enables clock square1 low-pass filter for 26M quality.
+d.s &MEM_CLASS:®_APMIXEDSYS_AP_PLL_CON0 %long %le data.long(&MEM_CLASS:®_APMIXEDSYS_AP_PLL_CON0)|0x2
+;;// 100us
+wait 1.ms
+
+;;// Default md_srclkena_ack settle time = 124T 32K
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E7C
+
+;;// Fixed Fvco = 1800Mhz. (/2)900M, (/3)600M, (/4)450M, (/5)360M, (/6)300M, (/7)257M
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x80114EC5
+;;// Fvco = 3600Mhz. 3600/6 = 600Mhz
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80229E00
+;;// Fvco = 3400Mhz. 3400/4 = 850Mhz
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x8020B200
+;;// Fvco = 3600Mhz. 3600/4 = 900Mhz
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x80229E00
+
+;;// LOG_ATB = 100Mhz (mdbpipll_d3_div2_ck/3)
+d.s &MEM_CLASS:®_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL %long %le 0x00000002
+;;// MML2_DFS_PLLSEL=MDBPIPLL_D4 ; MML2_DFS_DIVSEL=divided-by 1
+d.s &MEM_CLASS:®_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL %long %le 0x00000010
+
+;;// Polling until MDMCUPLL complete frequency adjustment
+;WHILE ((data.long(&MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0()
+wait 1.ms
+
+;; PLL ON controlled by HW
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x00000000
+
+;; Update ABB MDPLL control register default value
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x4C43100
+
+;; /*
+;; * Wait MD bus clock ready
+;; * Once MD bus ready, other clock should be ready too
+;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+;; */
+;WHILE (data.long(&MEM_CLASS:®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000()
+wait 1.ms
+
+;;=================Switch clock source to PLL====================
+;;// Switch MDMCU & MD BUS clock to PLL frequency
+d.s &MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL)|(0x3)
+
+;;// Switch all clock to PLL frequency
+d.s &MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL)|(0x31811F5C)
+
+;;// Turn off all SW clock request, except ATB
+d.s &MEM_CLASS:®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+;;// Switch SDF clock to PLL frequency
+d.s &MEM_CLASS:®_MDTOP_CLKSW_SDF_CK_CTL %long %le data.long(&MEM_CLASS:®_MDTOP_CLKSW_SDF_CK_CTL)|(0x11)
+
+;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+;;// Mask all PLL ADJ RDY IRQ
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+;;// Make a record that means MD pll has been initialized.
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/APview_MT3967_disable_WDT.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/APview_MT3967_disable_WDT.cmm
new file mode 100755
index 0000000..6ea39f8
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/APview_MT3967_disable_WDT.cmm
@@ -0,0 +1,11 @@
+;/* Step 8 Disable MD WDT */
+&MEM_CLASS="AXI"
+
+;&BASE_MADDR_MDRGU=0xA00F0000
+;&BASE_MADDR_APRGU=0xC0007000
+&BASE_MADDR_MDRGU=0x200F0000
+;&BASE_MADDR_APRGU=0x10007000
+
+D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+;D.S &MEM_CLASS:&BASE_MADDR_APRGU %LE %LONG 0x22000064
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/APview_MT3967_md_srclkena.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/APview_MT3967_md_srclkena.cmm
new file mode 100755
index 0000000..6288805
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/APview_MT3967_md_srclkena.cmm
@@ -0,0 +1,22 @@
+; /* Step 3 config md_srclkena setting */
+&MEM_CLASS="AXI"
+
+; /* SPM base */
+&SPM_REG=(0x10006000)
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(0x10001F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+; /* (1) INFRA_MISC2 */
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 [3:0] : mdsrc_req_0_en = 4'b0001 */
+®_temp=data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFF00)
+D.S (&MEM_CLASS:&INFRA_MISC2) %long %le (®_temp)|(0x00000021)
+
+; /* (2) SRCLKEN_O1 force on */
+D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x80215830 //set src clkena1 force on
+
+wait 1.ms
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/CoreTracer_MT3967_Disable_WDT.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/CoreTracer_MT3967_Disable_WDT.cmm
new file mode 100755
index 0000000..88cbcb9
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/CoreTracer_MT3967_Disable_WDT.cmm
@@ -0,0 +1,34 @@
+;sys.m prepare
+;LOCAL &TYPE
+
+
+system.mode attach
+
+; configure GCR_ACCESS Register
+; CoreTracer will access MO port via CPU to do following configuration
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+
+
+
+; do orginal APview_MT3967_disable_WDT.cmm
+LOCAL &BASE_MADDR_MDRGU
+&BASE_MADDR_MDRGU=0xA00F0000
+
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG 0x55000030
+
+PRINT "=============================="
+PRINT "Done disable MD WDT!"
+PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/Coretracer_MT3967_Frequency_Meter.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/Coretracer_MT3967_Frequency_Meter.cmm
new file mode 100755
index 0000000..f91c643
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/Coretracer_MT3967_Frequency_Meter.cmm
@@ -0,0 +1,240 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; MT6295M MD Frequency Meter
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+system.mode attach
+
+;;;;;;;;;;;;;;;;;;;;;;;Below you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LOCAL &clksw_base ;; MD CLKSW base address
+&clksw_base=0xA0150000 ;; MD view APB
+;&clksw_base=0xA0096000 ;; MD view debug APB
+;&clksw_base=0x20150000 ;; AP view MD system bus
+;&clksw_base=0x0D0D6000 ;; AP view MD debug sys
+
+LOCAL &pll_base ;; MD PLLMIXED base address
+&pll_base=0xA0140000 ;; MD view APB
+;&pll_base=0xA0094000 ;; MD view debug APB
+;&pll_base=0x20140000 ;; AP view MD system bus
+;&pll_base=0x0D0D4000 ;; AP view MD debug sys
+
+&fqmtr_fcksel_32k_index=0x17
+
+;;;;;;;;;;;;;;;;;;;;;;;Above you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LOCAL &fqmtr_winset ;; Frequency Meter Windoiw Setting (= Number of FIXED clock cycle)
+&fqmtr_winset=0x1ff
+&fqmtr_winset_for_32k=0x1E000
+
+LOCAL &fqmtr_fcksel_val ;; Frequency Meter FIXED clock selection
+&fqmtr_fcksel_val=0x1a ;; Select 26Mhz by default
+
+&SRC_STR_4="MDBPI_PLL_D4"
+&SRC_STR_5="MDBPI_PLL_D6"
+&SRC_STR_6="mdsys_mml2_ck"
+&SRC_STR_7="fesys_rxagc_ck"
+&SRC_STR_8="mdrxsys_dfesync_ck"
+&SRC_STR_9="fesys_f208m_ck"
+&SRC_STR_10="TRACE_MON_clock"
+&SRC_STR_11="MDSYS_208M_clock"
+&SRC_STR_12="mdrxsys_rake_ck"
+&SRC_STR_13="mdrxsys_brp_ck"
+&SRC_STR_14="mdrxsys_vdsp_ck"
+&SRC_STR_15="mdtop_log_atb_ck"
+&SRC_STR_16="fesys_csys_ck"
+&SRC_STR_18="fesys_bsi_ck"
+&SRC_STR_19="mdsys_mdcore_ck"
+&SRC_STR_20="mdsys_bus2x_nodcm_ck"
+&SRC_STR_21="mdsys_bus2x_ck"
+&SRC_STR_22="mdtop_dbg_ck"
+&SRC_STR_23="mdtop_f32k_ck"
+&SRC_STR_24="AD_MDBPIPLL_D7"
+&SRC_STR_25="AD_MDBPIPLL_D5"
+&SRC_STR_26="AD_MDBPIPLL_D4"
+&SRC_STR_27="AD_MDBPIPLL_D3"
+&SRC_STR_28="AD_MDBPIPLL_D2"
+&SRC_STR_29="AD_MDBRPPLL"
+&SRC_STR_30="AD_MDVDSPPLL"
+&SRC_STR_31="AD_MDMCUPLL"
+
+LOCAL &idx
+LOCAL &str
+&idx = 0x4;
+&str = "MDBPI_PLL_D4"
+GOSUB fqmtr_query
+&idx = 0x5;
+&str = "MDBPI_PLL_D6"
+GOSUB fqmtr_query
+&idx = 0x6;
+&str = "mdsys_mml2_ck"
+GOSUB fqmtr_query
+&idx = 0x7;
+&str = "fesys_rxagc_ck"
+GOSUB fqmtr_query
+&idx = 0x8;
+&str = "mdrxsys_dfesync_ck"
+GOSUB fqmtr_query
+&idx = 0x9;
+&str = "fesys_f208m_ck"
+GOSUB fqmtr_query
+&idx = 0xA;
+&str = "TRACE_MON_clock"
+GOSUB fqmtr_query
+&idx = 0xB;
+&str = "MDSYS_208M_clock"
+GOSUB fqmtr_query
+&idx = 0xC;
+&str = "mdrxsys_rake_ck"
+GOSUB fqmtr_query
+&idx = 0xD;
+&str = "mdrxsys_brp_ck"
+GOSUB fqmtr_query
+&idx = 0xE;
+&str = "mdrxsys_vdsp_ck"
+GOSUB fqmtr_query
+&idx = 0xF;
+&str = "mdtop_log_atb_ck"
+GOSUB fqmtr_query
+&idx = 0x10;
+&str = "fesys_csys_ck"
+GOSUB fqmtr_query
+&idx = 0x12;
+&str = "fesys_bsi_ck"
+GOSUB fqmtr_query
+&idx = 0x13;
+&str = "mdsys_mdcore_ck"
+GOSUB fqmtr_query
+&idx = 0x14;
+&str = "mdsys_bus2x_nodcm_ck"
+GOSUB fqmtr_query
+&idx = 0x15;
+&str = "mdsys_bus2x_ck"
+GOSUB fqmtr_query
+&idx = 0x16;
+&str = "mdtop_dbg_ck"
+GOSUB fqmtr_query
+&idx = 0x17;
+&str = "mdtop_f32k_ck"
+GOSUB fqmtr_query
+&idx = 0x18;
+&str = "AD_MDBPIPLL_D7"
+GOSUB fqmtr_query
+&idx = 0x19;
+&str = "AD_MDBPIPLL_D5"
+GOSUB fqmtr_query
+&idx = 0x1A;
+&str = "AD_MDBPIPLL_D4"
+GOSUB fqmtr_query
+&idx = 0x1B;
+&str = "AD_MDBPIPLL_D3"
+GOSUB fqmtr_query
+&idx = 0x1C;
+&str = "AD_MDBPIPLL_D2"
+GOSUB fqmtr_query
+&idx = 0x1D;
+&str = "AD_MDBRPPLL"
+GOSUB fqmtr_query
+&idx = 0x1E;
+&str = "AD_MDVDSPPLL"
+GOSUB fqmtr_query
+&idx = 0x1F;
+&str = "AD_MDMCUPLL"
+GOSUB fqmtr_query
+
+&idx = 0x20;
+
+;;;;;The main function to get the Frequency. &idx==> the clock you select, &str==> clock name, &info==>list more info and wait 5ms in the function
+;; &info=1 ==> for printing many PLLs at one time
+fqmtr_query:
+ LOCAL &unit
+ LOCAL &fqmtr_winset_26M
+ LOCAL &fqmtr_result
+ LOCAL &fqmtr_result_raw
+ LOCAL &safe_wait_cnt
+ LOCAL &safe_wait_cnt_max
+ LOCAL &fqmtr_busy
+
+ &safe_wait_cnt=0
+ IF &idx==0x20
+ (
+ RETURN
+ )
+ ELSE
+ (
+ IF &fqmtr_fcksel_val==0x1a ;; base on 26M, unit:MHz
+ (
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &unit="Khz"
+ &fqmtr_winset_26M=&fqmtr_winset_for_32k
+ &safe_wait_cnt_max=500 ;;5000 ms = 5s ==> in real test, longer than 5s, so reduce it
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &unit="Mhz"
+ &fqmtr_winset_26M=&fqmtr_winset
+ &safe_wait_cnt_max=32 ;;32 ms
+ )
+ )
+
+ ;;select source to a valid clock to let reset success.
+ Data.Set (&clksw_base+0x0200) %LE %LONG 0x13
+ Data.Set (&clksw_base+0x0204) %LE %LONG 0x0 ;reset frequency meter
+ WAIT 1000.us
+
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ ;;For accurate, don't div 8 for 32K
+ Data.Set (&clksw_base+0x0200) %LE %LONG (&idx)
+ )
+ ELSE ;; measure PLL and other module
+ (
+ ;;div 8 and select src
+ Data.Set (&clksw_base+0x0200) %LE %LONG (0x0300)|(&idx)
+ )
+
+ Data.Set (&clksw_base+0x0208) %LE %LONG &fqmtr_winset_26M
+ Data.Set (&clksw_base+0x0204) %LE %LONG 0x1 ;enable frequency meter
+
+ ;; read status, to check polling done or not
+ &fqmtr_busy=DATA.LONG(&clksw_base+0x0204)&(1<<1)
+
+ WHILE &fqmtr_busy==0
+ (
+; PRINT ". &fqmtr_busy"
+ &fqmtr_busy=DATA.LONG(&clksw_base+0x0204)&(1<<1)
+ &safe_wait_cnt=&safe_wait_cnt+1
+ IF &safe_wait_cnt==&safe_wait_cnt_max
+ (
+ PRINT "[&str] Wait Fail, exit"
+ RETURN
+ )
+ ELSE
+ (
+; PRINT "Waiting result. safe_wait_cnt=" "&safe_wait_cnt"
+ )
+ WAIT 1000.us
+
+ )
+
+ ;; Calculate the result
+ &fqmtr_result_raw=DATA.LONG(&clksw_base+0x20c)
+
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*(0x3E8)/(&fqmtr_winset_26M+3)
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*8/(&fqmtr_winset_26M+3)
+ )
+
+ &fqmtr_result_dec=&fqmtr_result
+ &fqmtr_result_dec=FORMAT.DECIMAL( 0 , &fqmtr_result )
+
+ PRINT " &idx , &fqmtr_result_dec &unit , &str "
+
+ WAIT 1000.us
+
+ RETURN
+ )
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/Coretracer_PMIC_Golden_Setting_Dump.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/Coretracer_PMIC_Golden_Setting_Dump.cmm
new file mode 100755
index 0000000..7c8c5c6
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/Coretracer_PMIC_Golden_Setting_Dump.cmm
@@ -0,0 +1,216 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; MT3967 PMIC golden setting dump
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+system.mode attach
+
+;; CLOCK & RESET
+PRINT "=== CLOCK & RESET ==="
+&MODULE_SW_CG_0_STA=0xC0001090
+&MODULE_SW_CG_2_STA=0xC00010AC
+&ULPOSC_CON=0xC0006458
+&PMICW_CTRL=0xC05C4034
+&PMICW_CLOCK_CTRL=0xC0001108
+&INFRA_GLOBALCON_RST2_STA=0xC0001148
+&CLK_CFG_5=0xC0000090
+
+&tmp=DATA.LONG(&MODULE_SW_CG_0_STA)
+IF ((&tmp) & (0xF))!=0
+(
+ PRINT "FAIL!! MODULE_SW_CG_0_STA &MODULE_SW_CG_0_STA = &tmp , [3:0] != 0"
+)
+ELSE
+(
+ PRINT "Pass. MODULE_SW_CG_0_STA &MODULE_SW_CG_0_STA = &tmp"
+)
+
+&tmp=DATA.LONG(&MODULE_SW_CG_2_STA)
+IF ((&tmp) & (0x100))!=0
+(
+ PRINT "FAIL!! MODULE_SW_CG_2_STA &MODULE_SW_CG_2_STA = &tmp , [8] != 0"
+)
+ELSE
+(
+ PRINT "Pass. MODULE_SW_CG_2_STA &MODULE_SW_CG_2_STA = &tmp"
+)
+
+&tmp=DATA.LONG(&ULPOSC_CON)
+IF ((&tmp) & (0x8))!=0
+(
+ PRINT "FAIL!! ULPOSC_CON &ULPOSC_CON = &tmp , [3] != 0"
+)
+ELSE
+(
+ PRINT "Pass. ULPOSC_CON &ULPOSC_CON = &tmp"
+)
+
+&tmp=DATA.LONG(&PMICW_CTRL)
+IF ((&tmp) & (0x100))!=0
+(
+ PRINT "FAIL!! PMICW_CTRL &PMICW_CTRL = &tmp , [8] != 0"
+)
+ELSE
+(
+ PRINT "Pass. PMICW_CTRL &PMICW_CTRL = &tmp"
+)
+
+&tmp=DATA.LONG(&PMICW_CLOCK_CTRL)
+IF ((&tmp) & (0xF))!=0xD
+(
+ PRINT "FAIL!! PMICW_CLOCK_CTRL &PMICW_CLOCK_CTRL = &tmp , [3:0] != 0xD"
+)
+ELSE
+(
+ PRINT "Pass. PMICW_CLOCK_CTRL &PMICW_CLOCK_CTRL = &tmp"
+)
+
+&tmp=DATA.LONG(&INFRA_GLOBALCON_RST2_STA)
+IF ((&tmp) & (0x1))!=0x0
+(
+ PRINT "FAIL!! INFRA_GLOBALCON_RST2_STA &INFRA_GLOBALCON_RST2_STA = &tmp , [0] != 0"
+)
+ELSE
+(
+ PRINT "Pass. INFRA_GLOBALCON_RST2_STA &INFRA_GLOBALCON_RST2_STA = &tmp"
+)
+
+&tmp=DATA.LONG(&CLK_CFG_5)
+IF ((&tmp) & (0x93000000))!=0x1000000
+(
+ PRINT "FAIL!! CLK_CFG_5 &CLK_CFG_5 = &tmp , [25:24] != 1, [28] != 0, [31] != 0"
+)
+ELSE
+(
+ PRINT "Pass. CLK_CFG_5 &CLK_CFG_5 = &tmp"
+)
+
+
+;; GPIO
+PRINT "=== GPIO ==="
+&GPIO_GPIO_MODE21=0xC0005450
+&IOCFG_LM_DRV_CFG1=0xC1F20010
+
+&tmp=DATA.LONG(&GPIO_GPIO_MODE21)
+IF ((&tmp) & (0xFFFF000))!=0x1111000
+(
+ PRINT "FAIL!! GPIO_GPIO_MODE21 &GPIO_GPIO_MODE21 = &tmp , [15:12] != 1, [19:16] != 1, [23:20] != 1, [27:24] != 1"
+)
+ELSE
+(
+ PRINT "Pass. GPIO_GPIO_MODE21 &GPIO_GPIO_MODE21 = &tmp"
+)
+
+&tmp=DATA.LONG(&IOCFG_LM_DRV_CFG1)
+IF ((&tmp) & (0x7FF8))!=0x1248
+(
+ PRINT "FAIL!! IOCFG_LM_DRV_CFG1 &IOCFG_LM_DRV_CFG1 = &tmp , [5:3] != 1, [8:6] != 1, [11:9] != 1, [14:12] != 1"
+)
+ELSE
+(
+ PRINT "Pass. IOCFG_LM_DRV_CFG1 &IOCFG_LM_DRV_CFG1 = &tmp"
+)
+
+
+;; PMIC_WRAP
+PRINT "=== PMIC_WRAP ==="
+&MUX_SEL=0xC000D000
+&WRAP_EN=0xC000D004
+&HPRIO_ARB_EN=0xC000D06C
+&WACS0_EN=0xC000D08C
+&INIT_DONE0=0xC000D090
+&WACS0_RDATA=0xC000DC04
+&WACS2_EN=0xC000D09C
+&INIT_DONE2=0xC000D0A0
+&WACS2_RDATA=0xC000DC24
+
+&tmp=DATA.LONG(&MUX_SEL)
+IF ((&tmp) & (0x1))!=0x0
+(
+ PRINT "FAIL!! MUX_SEL &MUX_SEL = &tmp , [0] != 0"
+)
+ELSE
+(
+ PRINT "Pass. MUX_SEL &MUX_SEL = &tmp"
+)
+
+&tmp=DATA.LONG(&WRAP_EN)
+IF ((&tmp) & (0x1))!=0x1
+(
+ PRINT "FAIL!! WRAP_EN &WRAP_EN = &tmp , [0] != 1"
+)
+ELSE
+(
+ PRINT "Pass. WRAP_EN &WRAP_EN = &tmp"
+)
+
+&tmp=DATA.LONG(&HPRIO_ARB_EN)
+IF &tmp!=0x7D9BD
+(
+ PRINT "FAIL!! HPRIO_ARB_EN &HPRIO_ARB_EN = &tmp != 0x7D9BD"
+)
+ELSE
+(
+ PRINT "Pass. HPRIO_ARB_EN &HPRIO_ARB_EN = &tmp"
+)
+
+&tmp=DATA.LONG(&WACS0_EN)
+IF ((&tmp) & (0x1))!=0x1
+(
+ PRINT "FAIL!! WACS0_EN &WACS0_EN = &tmp , [0] != 1"
+)
+ELSE
+(
+ PRINT "Pass. WACS0_EN &WACS0_EN = &tmp"
+)
+
+&tmp=DATA.LONG(&INIT_DONE0)
+IF ((&tmp) & (0x1))!=0x1
+(
+ PRINT "FAIL!! INIT_DONE0 &INIT_DONE0 = &tmp , [0] != 1"
+)
+ELSE
+(
+ PRINT "Pass. INIT_DONE0 &INIT_DONE0 = &tmp"
+)
+
+&tmp=DATA.LONG(&WACS0_RDATA)
+IF ((&tmp) & (0x600000))!=0x600000
+(
+ PRINT "FAIL!! WACS0_RDATA &WACS0_RDATA = &tmp , [21] != 1, [22] != 1"
+)
+ELSE
+(
+ PRINT "Pass. WACS0_RDATA &WACS0_RDATA = &tmp"
+)
+
+&tmp=DATA.LONG(&WACS2_EN)
+IF ((&tmp) & (0x1))!=0x1
+(
+ PRINT "FAIL!! WACS2_EN &WACS2_EN = &tmp, [0] != 1"
+)
+ELSE
+(
+ PRINT "Pass. WACS2_EN &WACS2_EN = &tmp"
+)
+
+&tmp=DATA.LONG(&INIT_DONE2)
+IF ((&tmp) & (0x1))!=0x1
+(
+ PRINT "FAIL!! INIT_DONE2 &INIT_DONE2 = &tmp , [0] != 1"
+)
+ELSE
+(
+ PRINT "Pass. INIT_DONE2 &INIT_DONE2 = &tmp"
+)
+
+&tmp=DATA.LONG(&WACS2_RDATA)
+IF ((&tmp) & (0x600000))!=0x600000
+(
+ PRINT "FAIL!! WACS2_RDATA &WACS2_RDATA = &tmp , [21] != 1, [22] != 1"
+)
+ELSE
+(
+ PRINT "Pass. WACS2_RDATA &WACS2_RDATA = &tmp"
+)
+
+ENDDO
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/MT3967_EVB_Load_MD_Elf.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/MT3967_EVB_Load_MD_Elf.cmm
new file mode 100755
index 0000000..badad43
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/MT3967_EVB_Load_MD_Elf.cmm
@@ -0,0 +1,292 @@
+;sys.m prepare
+;LOCAL &TYPE
+
+system.mode attach
+
+; configure GCR_ACCESS Register++++++++++++++++++++++++++++++++++++++++++++++
+; CoreTracer will access MO port via CPU to do following configuration
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+; do orginal APview_MT3967_disable_WDT.cmm+++++++++++++++++++++++++++++++++++
+LOCAL &BASE_MADDR_MDRGU
+&BASE_MADDR_MDRGU=0xA00F0000
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG 0x55000030
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+; /* Step 3 config md_srclkena setting */++++++++++++++++++++++++++++++++++++
+PRINT "=============================="
+PRINT "config md_srclkena setting"
+PRINT "=============================="
+; /* SPM base */
+&SPM_REG=(0xC0006000)
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(0xC0001F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+; /* (1) INFRA_MISC2 */
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 [3:0] : mdsrc_req_0_en = 4'b0001 */
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp & (0xFFFFFF00)
+D.S &INFRA_MISC2 %LE %LONG (&temp)|(0x00000021)
+
+; /* (2) SRCLKEN_O1 force on */
+;D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+;D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x80215830 //set src clkena1 force on
+D.S &POWERON_CONFIG_EN %LE %LONG 0x0B160001
+D.S &SPM_POWER_ON_VAL1 %LE %LONG 0x80215830
+
+wait 1.ms
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+; MD PLL related, init 26M quality++++++++++++++++++++++++++++++++++++++++++
+PRINT "=============================="
+PRINT "initial CLKSQ_LPF for 26M quality"
+PRINT "=============================="
+&BASE_MADDR_APMIXEDSYS=(0xC000C000)
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+;;// initial CLKSQ_LPF
+&temp=data.long(®_APMIXEDSYS_AP_PLL_CON0)
+&temp=&temp|0x2
+D.S ®_APMIXEDSYS_AP_PLL_CON0 %long %le &temp
+
+wait 1.ms
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+; MD PLL init ==> It could cancel from Gen95..
+&pll_init = 0x0
+IF &pll_init==0x1 ;; MD PLL init
+(
+ &BASE_MADDR_MDTOP_PLLMIXED=(0xA0140000)
+ &BASE_MADDR_MDTOP_CLKSW=(0xA0150000)
+
+ ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+ ®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+ ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+ ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+ ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+ ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+ ®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+ ®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+ ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+ ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+ ®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+ ®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+ ®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+ ®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+ ®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+ ®_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x60)
+ ®_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x70)
+ ®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0xA4)
+
+ &MD_PLL_MAGIC_NUM=(0x62950000)
+ ;;-------------------------------------------------------
+
+ ;;// Default md_srclkena_ack settle time = 124T 32K
+ D.S ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E7C
+
+ ;;// Fixed Fvco = 1800Mhz. (/2)900M, (/3)600M, (/4)450M, (/5)360M, (/6)300M, (/7)257M
+ D.S ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x80114EC5
+ ;;// Fvco = 3600Mhz. 3600/6 = 600Mhz
+ D.S ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80229E00
+ ;;// Fvco = 3400Mhz. 3400/4 = 850Mhz
+ D.S ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x8020B200
+ ;;// Fvco = 3600Mhz. 3600/4 = 900Mhz
+ D.S ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x80229E00
+
+ ;;// LOG_ATB = 100Mhz (mdbpipll_d3_div2_ck/3)
+ D.S ®_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL %long %le 0x00000002
+ ;;// MML2_DFS_PLLSEL=MDBPIPLL_D4 ; MML2_DFS_DIVSEL=divided-by 1
+ D.S ®_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL %long %le 0x00000010
+
+ ;;// Polling until MDMCUPLL complete frequency adjustment
+ ;WHILE ((data.long(&MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0()
+ wait 1.ms
+
+ ;; PLL ON controlled by HW
+ D.S ®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x00000000
+
+ ;; Update ABB MDPLL control register default value
+ D.S ®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x4C43100
+
+ ;; /*
+ ;; * Wait MD bus clock ready
+ ;; * Once MD bus ready, other clock should be ready too
+ ;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+ ;; */
+ ;WHILE (data.long(&MEM_CLASS:®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000()
+ wait 1.ms
+
+ ;;=================Switch clock source to PLL====================
+ ;;// Switch MDMCU & MD BUS clock to PLL frequency
+ ;D.S ®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(®_MDTOP_CLKSW_CLKSEL_CTL)|(0x3)
+ &temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+ &temp=&temp|0x3
+ D.S ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+ ;;// Switch all clock to PLL frequency
+ ;D.S ®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(®_MDTOP_CLKSW_CLKSEL_CTL)|(0x31811F5C)
+ &temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+ &temp=&temp|0x31811F5C
+ D.S ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+ ;;// Turn off all SW clock request, except ATB
+ D.S ®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+ ;;// Switch SDF clock to PLL frequency
+ ;D.S ®_MDTOP_CLKSW_SDF_CK_CTL %long %le data.long(®_MDTOP_CLKSW_SDF_CK_CTL)|(0x11)
+ &temp=data.long(®_MDTOP_CLKSW_SDF_CK_CTL)
+ &temp=&temp|0x11
+ D.S ®_MDTOP_CLKSW_SDF_CK_CTL %long %le &temp
+
+ ;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+ D.S ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+ ;;// Mask all PLL ADJ RDY IRQ
+ D.S ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+ ;;// Make a record that means MD pll has been initialized.
+ D.S ®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+)
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+;;// Set GPIO +++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;;APview_MT3967_GPIO_MDUART0.cmm
+PRINT "=============================="
+PRINT "Set GPIO!"
+PRINT "=============================="
+&BASE_ADDR_MDGPIO=0xC0005000
+&BASE_ADDR_IOCFG=0xC1F80000
+
+;;// MD UART GPIO ==> config GPIO and power up
+;;D.S AXI:&BASE_ADDR_MDGPIO+0x318 %LE %LONG 0x7700000 ;//clear GPIO13 and GPIO14 to GPIO mode.
+;;D.S AXI:&BASE_ADDR_MDGPIO+0x314 %LE %LONG 0x4400000 ;//set GPIO13 to MD_URXD0 mode,set GPIO14 to MD_UTXD0 mode,
+;;D.S AXI:&BASE_ADDR_IOCFG+0x58 %LE %LONG 0x06 ;//MD_URXD0/MD_UTXD0 PD clear
+;;D.S AXI:&BASE_ADDR_IOCFG+0x64 %LE %LONG 0x02 ;//MD_URXD0 PU set
+D.S &BASE_ADDR_MDGPIO+0x318 %LE %LONG 0x7700000
+D.S &BASE_ADDR_MDGPIO+0x314 %LE %LONG 0x4400000
+D.S &BASE_ADDR_IOCFG+0x58 %LE %LONG 0x6
+D.S &BASE_ADDR_IOCFG+0x64 %LE %LONG 0x2
+
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+;;APview_MT3967_GPIO_SIM.cmm++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;;// SIM2 GPIO
+;d.s &MEM_CLASS:0x10005370 %long %le data.long(&MEM_CLASS:0x10005370)&(0x000FFFFF)
+;d.s &MEM_CLASS:0x10005370 %long %le data.long(&MEM_CLASS:0x10005370)|(0x11100000)
+
+&temp=data.long(0xC0005370)
+&temp=&temp & (0x000FFFFF)
+D.S 0xC0005370 %LE %LONG &temp
+
+&temp=data.long(0xC0005370)
+&temp=&temp | (0x11100000)
+D.S 0xC0005370 %LE %LONG &temp
+
+;;// SIM1 GPIO
+;d.s &MEM_CLASS:0x10005380 %long %le data.long(&MEM_CLASS:0x10005380)&(0xFFFFF000)
+;d.s &MEM_CLASS:0x10005380 %long %le data.long(&MEM_CLASS:0x10005380)|(0x00000111)
+
+&temp=data.long(0xC0005380)
+&temp=&temp & (0xFFFFF000)
+D.S 0xC0005380 %LE %LONG &temp
+
+&temp=data.long(0xC0005380)
+&temp=&temp | (0x00000111)
+D.S 0xC0005380 %LE %LONG &temp
+
+;;// SIM2 PUPD
+;d.s &MEM_CLASS:0x11E700A0 %long %le data.long(&MEM_CLASS:0x11E700A0)&(0x0000003F)
+;d.s &MEM_CLASS:0x11E700A0 %long %le data.long(&MEM_CLASS:0x11E700A0)|(0x00000140)
+
+&temp=data.long(0xC1E700A0)
+&temp=&temp & (0x0000003F)
+D.S 0xC1E700A0 %LE %LONG &temp
+
+&temp=data.long(0xC1E700A0)
+&temp=&temp | (0x00000140)
+D.S 0xC1E700A0 %LE %LONG &temp
+
+;;// SIM1 PUPD
+;d.s &MEM_CLASS:0x11D10080 %long %le data.long(&MEM_CLASS:0x11D10080)&(0x00000000)
+;d.s &MEM_CLASS:0x11D10080 %long %le data.long(&MEM_CLASS:0x11D10080)|(0x00000005)
+
+&temp=data.long(0xC1D10080)
+&temp=&temp & (0x00000000)
+D.S 0xC1D10080 %LE %LONG &temp
+
+&temp=data.long(0xC1D10080)
+&temp=&temp | (0x00000005)
+D.S 0xC1D10080 %LE %LONG &temp
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+;set MD EMI remap address(owner: AP CCCI, Yanjie Jiang)+++++++++++++++++++++++++++++++++
+PRINT "=============================="
+PRINT "Set MD EMI Remap!"
+PRINT "=============================="
+;d.s &MEM_CLASS:0xC0001300 %long %le 0x00430041
+;d.s &MEM_CLASS:0xC0001304 %long %le 0x00470045
+;d.s &MEM_CLASS:0xC0001308 %long %le 0x004b0049
+;d.s &MEM_CLASS:0xC000130c %long %le 0x004f004d
+D.S 0xC0001300 %LE %LONG 0x00430041
+D.S 0xC0001304 %LE %LONG 0x00470045
+D.S 0xC0001308 %LE %LONG 0x004b0049
+D.S 0xC000130c %LE %LONG 0x004f004d
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+;Enalbe cache to speed loading & load ELF++++++++++++++++++++++++++++++++++++++++++++++++
+;By setting bank 6 segment control attribute
+register.set cdmmbase 0x1fc1407
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor adapter_khz 2000
+steal monitor mips32 fastchannel 0 1 0x6f800000
+
+PRINT "=============================="
+PRINT "Start to Load elf !"
+PRINT "=============================="
+
+thread.select 1
+steal lo
+
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+PRINT "=============================="
+PRINT "Load elf Done!"
+PRINT "=============================="
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+thread.select 1
+
+;&t=var.address(INT_Initialize_Phase1)
+;wait 20.ms
+;stop
+;steal set $pc = &INT_Initialize_Phase1
+;register.set pc &t
+
+;PRINT "=============================="
+;PRINT "Set PC to INT_Initialize_Phase1: &t"
+;PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/MT3967_EVB_Load_MD_Elf_BigRam_Load.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/MT3967_EVB_Load_MD_Elf_BigRam_Load.cmm
new file mode 100755
index 0000000..91b6724
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/MT3967_EVB_Load_MD_Elf_BigRam_Load.cmm
@@ -0,0 +1,325 @@
+;sys.m prepare
+;LOCAL &TYPE
+
+system.mode attach
+
+; configure GCR_ACCESS Register++++++++++++++++++++++++++++++++++++++++++++++
+; CoreTracer will access MO port via CPU to do following configuration
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+; do orginal APview_MT3967_disable_WDT.cmm+++++++++++++++++++++++++++++++++++
+LOCAL &BASE_MADDR_MDRGU
+&BASE_MADDR_MDRGU=0xA00F0000
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG 0x55000030
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+; /* Step 3 config md_srclkena setting */++++++++++++++++++++++++++++++++++++
+PRINT "=============================="
+PRINT "config md_srclkena setting"
+PRINT "=============================="
+; /* SPM base */
+&SPM_REG=(0xC0006000)
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(0xC0001F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+; /* (1) INFRA_MISC2 */
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 [3:0] : mdsrc_req_0_en = 4'b0001 */
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp & (0xFFFFFF00)
+D.S &INFRA_MISC2 %LE %LONG (&temp)|(0x00000021)
+
+; /* (2) SRCLKEN_O1 force on */
+;D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+;D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x80215830 //set src clkena1 force on
+D.S &POWERON_CONFIG_EN %LE %LONG 0x0B160001
+D.S &SPM_POWER_ON_VAL1 %LE %LONG 0x80215830
+
+wait 1.ms
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+; MD PLL related, init 26M quality++++++++++++++++++++++++++++++++++++++++++
+PRINT "=============================="
+PRINT "initial CLKSQ_LPF for 26M quality"
+PRINT "=============================="
+&BASE_MADDR_APMIXEDSYS=(0xC000C000)
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+;;// initial CLKSQ_LPF
+&temp=data.long(®_APMIXEDSYS_AP_PLL_CON0)
+&temp=&temp|0x2
+D.S ®_APMIXEDSYS_AP_PLL_CON0 %long %le &temp
+
+wait 1.ms
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+; MD PLL init ==> It could cancel from Gen95..
+&pll_init = 0x0
+IF &pll_init==0x1 ;; MD PLL init
+(
+ &BASE_MADDR_MDTOP_PLLMIXED=(0xA0140000)
+ &BASE_MADDR_MDTOP_CLKSW=(0xA0150000)
+
+ ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+ ®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+ ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+ ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+ ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+ ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+ ®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+ ®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+ ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+ ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+ ®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+ ®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+ ®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+ ®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+ ®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+ ®_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x60)
+ ®_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x70)
+ ®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0xA4)
+
+ &MD_PLL_MAGIC_NUM=(0x62950000)
+ ;;-------------------------------------------------------
+
+ ;;// Default md_srclkena_ack settle time = 124T 32K
+ D.S ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E7C
+
+ ;;// Fixed Fvco = 1800Mhz. (/2)900M, (/3)600M, (/4)450M, (/5)360M, (/6)300M, (/7)257M
+ D.S ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x80114EC5
+ ;;// Fvco = 3600Mhz. 3600/6 = 600Mhz
+ D.S ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80229E00
+ ;;// Fvco = 3400Mhz. 3400/4 = 850Mhz
+ D.S ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x8020B200
+ ;;// Fvco = 3600Mhz. 3600/4 = 900Mhz
+ D.S ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x80229E00
+
+ ;;// LOG_ATB = 100Mhz (mdbpipll_d3_div2_ck/3)
+ D.S ®_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL %long %le 0x00000002
+ ;;// MML2_DFS_PLLSEL=MDBPIPLL_D4 ; MML2_DFS_DIVSEL=divided-by 1
+ D.S ®_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL %long %le 0x00000010
+
+ ;;// Polling until MDMCUPLL complete frequency adjustment
+ ;WHILE ((data.long(&MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0()
+ wait 1.ms
+
+ ;; PLL ON controlled by HW
+ D.S ®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x00000000
+
+ ;; Update ABB MDPLL control register default value
+ D.S ®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x4C43100
+
+ ;; /*
+ ;; * Wait MD bus clock ready
+ ;; * Once MD bus ready, other clock should be ready too
+ ;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+ ;; */
+ ;WHILE (data.long(&MEM_CLASS:®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000()
+ wait 1.ms
+
+ ;;=================Switch clock source to PLL====================
+ ;;// Switch MDMCU & MD BUS clock to PLL frequency
+ ;D.S ®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(®_MDTOP_CLKSW_CLKSEL_CTL)|(0x3)
+ &temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+ &temp=&temp|0x3
+ D.S ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+ ;;// Switch all clock to PLL frequency
+ ;D.S ®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(®_MDTOP_CLKSW_CLKSEL_CTL)|(0x31811F5C)
+ &temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+ &temp=&temp|0x31811F5C
+ D.S ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+ ;;// Turn off all SW clock request, except ATB
+ D.S ®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+ ;;// Switch SDF clock to PLL frequency
+ ;D.S ®_MDTOP_CLKSW_SDF_CK_CTL %long %le data.long(®_MDTOP_CLKSW_SDF_CK_CTL)|(0x11)
+ &temp=data.long(®_MDTOP_CLKSW_SDF_CK_CTL)
+ &temp=&temp|0x11
+ D.S ®_MDTOP_CLKSW_SDF_CK_CTL %long %le &temp
+
+ ;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+ D.S ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+ ;;// Mask all PLL ADJ RDY IRQ
+ D.S ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+ ;;// Make a record that means MD pll has been initialized.
+ D.S ®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+)
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+;;// Set GPIO +++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;;APview_MT3967_GPIO_MDUART0.cmm
+PRINT "=============================="
+PRINT "Set GPIO!"
+PRINT "=============================="
+&BASE_ADDR_MDGPIO=0xC0005000
+&BASE_ADDR_IOCFG=0xC1F80000
+
+;;// MD UART GPIO ==> config GPIO and power up
+;;D.S AXI:&BASE_ADDR_MDGPIO+0x318 %LE %LONG 0x7700000 ;//clear GPIO13 and GPIO14 to GPIO mode.
+;;D.S AXI:&BASE_ADDR_MDGPIO+0x314 %LE %LONG 0x4400000 ;//set GPIO13 to MD_URXD0 mode,set GPIO14 to MD_UTXD0 mode,
+;;D.S AXI:&BASE_ADDR_IOCFG+0x58 %LE %LONG 0x06 ;//MD_URXD0/MD_UTXD0 PD clear
+;;D.S AXI:&BASE_ADDR_IOCFG+0x64 %LE %LONG 0x02 ;//MD_URXD0 PU set
+D.S &BASE_ADDR_MDGPIO+0x318 %LE %LONG 0x7700000
+D.S &BASE_ADDR_MDGPIO+0x314 %LE %LONG 0x4400000
+D.S &BASE_ADDR_IOCFG+0x58 %LE %LONG 0x6
+D.S &BASE_ADDR_IOCFG+0x64 %LE %LONG 0x2
+
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+;;APview_MT3967_GPIO_SIM.cmm++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;;// SIM2 GPIO
+;d.s &MEM_CLASS:0x10005370 %long %le data.long(&MEM_CLASS:0x10005370)&(0x000FFFFF)
+;d.s &MEM_CLASS:0x10005370 %long %le data.long(&MEM_CLASS:0x10005370)|(0x11100000)
+
+&temp=data.long(0xC0005370)
+&temp=&temp & (0x000FFFFF)
+D.S 0xC0005370 %LE %LONG &temp
+
+&temp=data.long(0xC0005370)
+&temp=&temp | (0x11100000)
+D.S 0xC0005370 %LE %LONG &temp
+
+;;// SIM1 GPIO
+;d.s &MEM_CLASS:0x10005380 %long %le data.long(&MEM_CLASS:0x10005380)&(0xFFFFF000)
+;d.s &MEM_CLASS:0x10005380 %long %le data.long(&MEM_CLASS:0x10005380)|(0x00000111)
+
+&temp=data.long(0xC0005380)
+&temp=&temp & (0xFFFFF000)
+D.S 0xC0005380 %LE %LONG &temp
+
+&temp=data.long(0xC0005380)
+&temp=&temp | (0x00000111)
+D.S 0xC0005380 %LE %LONG &temp
+
+;;// SIM2 PUPD
+;d.s &MEM_CLASS:0x11E700A0 %long %le data.long(&MEM_CLASS:0x11E700A0)&(0x0000003F)
+;d.s &MEM_CLASS:0x11E700A0 %long %le data.long(&MEM_CLASS:0x11E700A0)|(0x00000140)
+
+&temp=data.long(0xC1E700A0)
+&temp=&temp & (0x0000003F)
+D.S 0xC1E700A0 %LE %LONG &temp
+
+&temp=data.long(0xC1E700A0)
+&temp=&temp | (0x00000140)
+D.S 0xC1E700A0 %LE %LONG &temp
+
+;;// SIM1 PUPD
+;d.s &MEM_CLASS:0x11D10080 %long %le data.long(&MEM_CLASS:0x11D10080)&(0x00000000)
+;d.s &MEM_CLASS:0x11D10080 %long %le data.long(&MEM_CLASS:0x11D10080)|(0x00000005)
+
+&temp=data.long(0xC1D10080)
+&temp=&temp & (0x00000000)
+D.S 0xC1D10080 %LE %LONG &temp
+
+&temp=data.long(0xC1D10080)
+&temp=&temp | (0x00000005)
+D.S 0xC1D10080 %LE %LONG &temp
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+;set MD EMI remap address(owner: AP CCCI, Yanjie Jiang)+++++++++++++++++++++++++++++++++
+PRINT "=============================="
+PRINT "Set MD EMI Remap!"
+PRINT "=============================="
+;d.s &MEM_CLASS:0xC0001300 %long %le 0x00430041
+;d.s &MEM_CLASS:0xC0001304 %long %le 0x00470045
+;d.s &MEM_CLASS:0xC0001308 %long %le 0x004b0049
+;d.s &MEM_CLASS:0xC000130c %long %le 0x004f004d
+D.S 0xC0001300 %LE %LONG 0x00430041
+D.S 0xC0001304 %LE %LONG 0x00470045
+D.S 0xC0001308 %LE %LONG 0x004b0049
+D.S 0xC000130c %LE %LONG 0x004f004d
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+&BASE_ADDR_BUS=0xA0330000
+
+;;Power on BigRam
+PRINT "=============================="
+PRINT "Power on BigRam ..."
+PRINT "=============================="
+DATA.SET 0xAB810008 %LE %LONG 0x7FF
+DATA.SET 0xAB830000 %LE %LONG 0x1
+
+;;;;;;;;;;Disable EMI Path
+PRINT "=============================="
+PRINT "Disable EMI Path"
+PRINT "=============================="
+;;1)mask other si decerr
+®_value=DATA.LONG(&BASE_ADDR_BUS+0x24)|0x3C
+DATA.SET (&BASE_ADDR_BUS+0x24) %LE %LONG ®_value
+
+;;2)reset and clear all decerr status
+®_value=DATA.LONG(&BASE_ADDR_BUS+0x10) & (0xFFFFFFE0)
+DATA.SET (&BASE_ADDR_BUS+0x10) %LE %LONG ®_value
+®_value=DATA.LONG(&BASE_ADDR_BUS+0x10) | 0x1F
+DATA.SET (&BASE_ADDR_BUS+0x10) %LE %LONG ®_value
+
+;;3)disable mm port to emi path (mm_1x4_way_en)
+®_value=DATA.LONG(&BASE_ADDR_BUS) & (0xFFFFFFFD)
+DATA.SET &BASE_ADDR_BUS %LE %LONG ®_value
+
+;;4)enable bus decerr enable (bus_dec_err_en)
+®_value=DATA.LONG(&BASE_ADDR_BUS+0x10) | 0x40000000
+DATA.SET (&BASE_ADDR_BUS+0x10) %LE %LONG ®_value
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;Enalbe cache to speed loading & load ELF++++++++++++++++++++++++++++++++++++++++++++++++
+;By setting bank 6 segment control attribute
+;register.set cdmmbase 0x1fc1407
+;D.S 0x1FC100D4 %LE %LONG 0x02030202
+;steal monitor adapter_khz 2000
+
+;Disable fastchannel to access EMI
+steal monitor mips32 fastchannel 0 0 0x6f800000
+
+PRINT "=============================="
+PRINT "Start to Load elf !"
+PRINT "=============================="
+
+thread.select 1
+steal lo
+
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+PRINT "=============================="
+PRINT "Load elf Done!"
+PRINT "=============================="
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+thread.select 1
+
+&tt=var.address(INT_Vectors)
+register.set pc &tt
+steal flushreg
+
+;PRINT "=============================="
+;PRINT "Set PC to INT_Vectors: &t"
+;PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/MT3967_EVB_Load_MD_Elf_With_DSP.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/MT3967_EVB_Load_MD_Elf_With_DSP.cmm
new file mode 100755
index 0000000..cef8f65
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/MT3967_EVB_Load_MD_Elf_With_DSP.cmm
@@ -0,0 +1,299 @@
+;sys.m prepare
+;LOCAL &TYPE
+
+system.mode attach
+
+; configure GCR_ACCESS Register++++++++++++++++++++++++++++++++++++++++++++++
+; CoreTracer will access MO port via CPU to do following configuration
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+; do orginal APview_MT3967_disable_WDT.cmm+++++++++++++++++++++++++++++++++++
+LOCAL &BASE_MADDR_MDRGU
+&BASE_MADDR_MDRGU=0xA00F0000
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG 0x55000030
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+; /* Step 3 config md_srclkena setting */++++++++++++++++++++++++++++++++++++
+PRINT "=============================="
+PRINT "config md_srclkena setting"
+PRINT "=============================="
+; /* SPM base */
+&SPM_REG=(0xC0006000)
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(0xC0001F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+; /* (1) INFRA_MISC2 */
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 [3:0] : mdsrc_req_0_en = 4'b0001 */
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp & (0xFFFFFF00)
+D.S &INFRA_MISC2 %LE %LONG (&temp)|(0x00000021)
+
+; /* (2) SRCLKEN_O1 force on */
+;D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+;D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x80215830 //set src clkena1 force on
+D.S &POWERON_CONFIG_EN %LE %LONG 0x0B160001
+D.S &SPM_POWER_ON_VAL1 %LE %LONG 0x80215830
+
+wait 1.ms
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+; MD PLL related, init 26M quality++++++++++++++++++++++++++++++++++++++++++
+PRINT "=============================="
+PRINT "initial CLKSQ_LPF for 26M quality"
+PRINT "=============================="
+&BASE_MADDR_APMIXEDSYS=(0xC000C000)
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+;;// initial CLKSQ_LPF
+&temp=data.long(®_APMIXEDSYS_AP_PLL_CON0)
+&temp=&temp|0x2
+D.S ®_APMIXEDSYS_AP_PLL_CON0 %long %le &temp
+
+wait 1.ms
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+; MD PLL init ==> It could cancel from Gen95..
+&pll_init = 0x0
+IF &pll_init==0x1 ;; MD PLL init
+(
+ &BASE_MADDR_MDTOP_PLLMIXED=(0xA0140000)
+ &BASE_MADDR_MDTOP_CLKSW=(0xA0150000)
+
+ ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+ ®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+ ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+ ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+ ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+ ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+ ®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+ ®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+ ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+ ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+ ®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+ ®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+ ®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+ ®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+ ®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+ ®_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x60)
+ ®_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x70)
+ ®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0xA4)
+
+ &MD_PLL_MAGIC_NUM=(0x62950000)
+ ;;-------------------------------------------------------
+
+ ;;// Default md_srclkena_ack settle time = 124T 32K
+ D.S ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E7C
+
+ ;;// Fixed Fvco = 1800Mhz. (/2)900M, (/3)600M, (/4)450M, (/5)360M, (/6)300M, (/7)257M
+ D.S ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x80114EC5
+ ;;// Fvco = 3600Mhz. 3600/6 = 600Mhz
+ D.S ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80229E00
+ ;;// Fvco = 3400Mhz. 3400/4 = 850Mhz
+ D.S ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x8020B200
+ ;;// Fvco = 3600Mhz. 3600/4 = 900Mhz
+ D.S ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x80229E00
+
+ ;;// LOG_ATB = 100Mhz (mdbpipll_d3_div2_ck/3)
+ D.S ®_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL %long %le 0x00000002
+ ;;// MML2_DFS_PLLSEL=MDBPIPLL_D4 ; MML2_DFS_DIVSEL=divided-by 1
+ D.S ®_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL %long %le 0x00000010
+
+ ;;// Polling until MDMCUPLL complete frequency adjustment
+ ;WHILE ((data.long(&MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0()
+ wait 1.ms
+
+ ;; PLL ON controlled by HW
+ D.S ®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x00000000
+
+ ;; Update ABB MDPLL control register default value
+ D.S ®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x4C43100
+
+ ;; /*
+ ;; * Wait MD bus clock ready
+ ;; * Once MD bus ready, other clock should be ready too
+ ;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+ ;; */
+ ;WHILE (data.long(&MEM_CLASS:®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000()
+ wait 1.ms
+
+ ;;=================Switch clock source to PLL====================
+ ;;// Switch MDMCU & MD BUS clock to PLL frequency
+ ;D.S ®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(®_MDTOP_CLKSW_CLKSEL_CTL)|(0x3)
+ &temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+ &temp=&temp|0x3
+ D.S ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+ ;;// Switch all clock to PLL frequency
+ ;D.S ®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(®_MDTOP_CLKSW_CLKSEL_CTL)|(0x31811F5C)
+ &temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+ &temp=&temp|0x31811F5C
+ D.S ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+ ;;// Turn off all SW clock request, except ATB
+ D.S ®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+ ;;// Switch SDF clock to PLL frequency
+ ;D.S ®_MDTOP_CLKSW_SDF_CK_CTL %long %le data.long(®_MDTOP_CLKSW_SDF_CK_CTL)|(0x11)
+ &temp=data.long(®_MDTOP_CLKSW_SDF_CK_CTL)
+ &temp=&temp|0x11
+ D.S ®_MDTOP_CLKSW_SDF_CK_CTL %long %le &temp
+
+ ;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+ D.S ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+ ;;// Mask all PLL ADJ RDY IRQ
+ D.S ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+ ;;// Make a record that means MD pll has been initialized.
+ D.S ®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+)
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+;;// Set GPIO +++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;;APview_MT3967_GPIO_MDUART0.cmm
+PRINT "=============================="
+PRINT "Set GPIO!"
+PRINT "=============================="
+&BASE_ADDR_MDGPIO=0xC0005000
+&BASE_ADDR_IOCFG=0xC1F80000
+
+;;// MD UART GPIO ==> config GPIO and power up
+;;D.S AXI:&BASE_ADDR_MDGPIO+0x318 %LE %LONG 0x7700000 ;//clear GPIO13 and GPIO14 to GPIO mode.
+;;D.S AXI:&BASE_ADDR_MDGPIO+0x314 %LE %LONG 0x4400000 ;//set GPIO13 to MD_URXD0 mode,set GPIO14 to MD_UTXD0 mode,
+;;D.S AXI:&BASE_ADDR_IOCFG+0x58 %LE %LONG 0x06 ;//MD_URXD0/MD_UTXD0 PD clear
+;;D.S AXI:&BASE_ADDR_IOCFG+0x64 %LE %LONG 0x02 ;//MD_URXD0 PU set
+D.S &BASE_ADDR_MDGPIO+0x318 %LE %LONG 0x7700000
+D.S &BASE_ADDR_MDGPIO+0x314 %LE %LONG 0x4400000
+D.S &BASE_ADDR_IOCFG+0x58 %LE %LONG 0x6
+D.S &BASE_ADDR_IOCFG+0x64 %LE %LONG 0x2
+
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+;;APview_MT3967_GPIO_SIM.cmm++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;;// SIM2 GPIO
+;d.s &MEM_CLASS:0x10005370 %long %le data.long(&MEM_CLASS:0x10005370)&(0x000FFFFF)
+;d.s &MEM_CLASS:0x10005370 %long %le data.long(&MEM_CLASS:0x10005370)|(0x11100000)
+
+&temp=data.long(0xC0005370)
+&temp=&temp & (0x000FFFFF)
+D.S 0xC0005370 %LE %LONG &temp
+
+&temp=data.long(0xC0005370)
+&temp=&temp | (0x11100000)
+D.S 0xC0005370 %LE %LONG &temp
+
+;;// SIM1 GPIO
+;d.s &MEM_CLASS:0x10005380 %long %le data.long(&MEM_CLASS:0x10005380)&(0xFFFFF000)
+;d.s &MEM_CLASS:0x10005380 %long %le data.long(&MEM_CLASS:0x10005380)|(0x00000111)
+
+&temp=data.long(0xC0005380)
+&temp=&temp & (0xFFFFF000)
+D.S 0xC0005380 %LE %LONG &temp
+
+&temp=data.long(0xC0005380)
+&temp=&temp | (0x00000111)
+D.S 0xC0005380 %LE %LONG &temp
+
+;;// SIM2 PUPD
+;d.s &MEM_CLASS:0x11E700A0 %long %le data.long(&MEM_CLASS:0x11E700A0)&(0x0000003F)
+;d.s &MEM_CLASS:0x11E700A0 %long %le data.long(&MEM_CLASS:0x11E700A0)|(0x00000140)
+
+&temp=data.long(0xC1E700A0)
+&temp=&temp & (0x0000003F)
+D.S 0xC1E700A0 %LE %LONG &temp
+
+&temp=data.long(0xC1E700A0)
+&temp=&temp | (0x00000140)
+D.S 0xC1E700A0 %LE %LONG &temp
+
+;;// SIM1 PUPD
+;d.s &MEM_CLASS:0x11D10080 %long %le data.long(&MEM_CLASS:0x11D10080)&(0x00000000)
+;d.s &MEM_CLASS:0x11D10080 %long %le data.long(&MEM_CLASS:0x11D10080)|(0x00000005)
+
+&temp=data.long(0xC1D10080)
+&temp=&temp & (0x00000000)
+D.S 0xC1D10080 %LE %LONG &temp
+
+&temp=data.long(0xC1D10080)
+&temp=&temp | (0x00000005)
+D.S 0xC1D10080 %LE %LONG &temp
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+;set MD EMI remap address(owner: AP CCCI, Yanjie Jiang)+++++++++++++++++++++++++++++++++
+PRINT "=============================="
+PRINT "Set MD EMI Remap!"
+PRINT "=============================="
+;d.s &MEM_CLASS:0xC0001300 %long %le 0x00430041
+;d.s &MEM_CLASS:0xC0001304 %long %le 0x00470045
+;d.s &MEM_CLASS:0xC0001308 %long %le 0x004b0049
+;d.s &MEM_CLASS:0xC000130c %long %le 0x004f004d
+D.S 0xC0001300 %LE %LONG 0x00430041
+D.S 0xC0001304 %LE %LONG 0x00470045
+D.S 0xC0001308 %LE %LONG 0x004b0049
+D.S 0xC000130c %LE %LONG 0x004f004d
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+;Enalbe cache to speed loading & load ELF++++++++++++++++++++++++++++++++++++++++++++++++
+;By setting bank 6 segment control attribute
+register.set cdmmbase 0x1fc1407
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor adapter_khz 2000
+steal monitor mips32 fastchannel 0 1 0x6f800000
+
+PRINT "=============================="
+PRINT "Start to Load elf !"
+PRINT "=============================="
+
+thread.select 1
+steal lo
+
+PRINT "=============================="
+PRINT "Load MD elf Done."
+PRINT "Please start to load DSP bin!"
+PRINT "=============================="
+
+steal source ../cmm/coretracer\config\easyLoader\load_dsp.py
+
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+PRINT "=============================="
+PRINT "Load DSP bin Done!"
+PRINT "=============================="
+;;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+thread.select 1
+
+;&t=var.address(INT_Initialize_Phase1)
+;wait 20.ms
+;stop
+;steal set $pc = &INT_Initialize_Phase1
+;register.set pc &t
+
+;PRINT "=============================="
+;PRINT "Set PC to INT_Initialize_Phase1: &t"
+;PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/MT3967_MD_Only.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/MT3967_MD_Only.cmm
new file mode 100755
index 0000000..feb898a
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/MT3967_MD_Only.cmm
@@ -0,0 +1,42 @@
+;AP pmic workaround
+&MEM_CLASS="AXI"
+sys.m prepare
+wait 1.ms
+
+; Step 1 config MD related Buck
+; [Note] CVD script do NOT need this step
+; skip
+
+; Step 2 power on MTCMOS
+; [Note] CVD script do NOT need this step
+; skip
+
+; Step 3 config md_srclkena setting
+do APview_MT3967_md_srclkena.cmm
+
+; Step 4 config PLL setting ==> only need to config 26M quality
+&BASE_MADDR_APMIXEDSYS=(0x1000C000)
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+;;//Enables clock square1 low-pass filter for 26M quality.
+d.s &MEM_CLASS:®_APMIXEDSYS_AP_PLL_CON0 %long %le data.long(&MEM_CLASS:®_APMIXEDSYS_AP_PLL_CON0)|0x2
+wait 1.ms
+;;do APview_MT3967_MD_PLL_Init.cmm ;;PLL init ==> no need from Gen95
+
+; Step 4.5 Disable MD WDT
+do APview_MT3967_disable_WDT.cmm
+
+; Step 5 set GPIO
+do APview_MT3967_GPIO_MDUART0.cmm
+do APview_MT3967_GPIO_SIM.cmm
+
+;Step 6 Force on Debug Sys clock
+;do APview_MT3967_MD_ForceOnDebugSys.cmm
+
+;Step 7 set MD EMI remap address (MD view: step 9)
+d.s &MEM_CLASS:0x10001300 %long %le 0x00430041
+d.s &MEM_CLASS:0x10001304 %long %le 0x00470045
+d.s &MEM_CLASS:0x10001308 %long %le 0x004b0049
+d.s &MEM_CLASS:0x1000130c %long %le 0x004f004d
+
+; Final Step: Trigger MD MCU to run
+; skip
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/L2CacheTag_Parser/Customize.dtd b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/L2CacheTag_Parser/Customize.dtd
new file mode 100644
index 0000000..977cb81
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/L2CacheTag_Parser/Customize.dtd
@@ -0,0 +1,17 @@
+<!ELEMENT Customize (Toolbar*,MainMenu*)>
+<!ELEMENT Toolbar (GDB*,SHELL*,PYSWTBOT*,CMM*,Menu*,MenuItem*)>
+<!ELEMENT MainMenu (Menu*,MenuItem*)>
+<!ELEMENT Menu (Menu*,MenuItem*)>
+<!ELEMENT MenuItem (GDB*,SHELL*,PYSWTBOT*,CMM*)>
+<!ATTLIST Toolbar name CDATA #REQUIRED>
+<!ATTLIST Toolbar icon CDATA #REQUIRED>
+<!ATTLIST MainMenu name CDATA #REQUIRED>
+<!ATTLIST MainMenu icon CDATA #REQUIRED>
+<!ATTLIST Menu name CDATA #REQUIRED>
+<!ATTLIST Menu icon CDATA #REQUIRED>
+<!ATTLIST MenuItem name CDATA #REQUIRED>
+<!ATTLIST MenuItem icon CDATA #REQUIRED>
+<!ELEMENT GDB (#PCDATA)>
+<!ELEMENT SHELL (#PCDATA)>
+<!ELEMENT PYSWTBOT (#PCDATA)>
+<!ELEMENT CMM (#PCDATA)>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/L2CacheTag_Parser/L2cacheTag.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/L2CacheTag_Parser/L2cacheTag.act
new file mode 100644
index 0000000..bf63f8e
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/L2CacheTag_Parser/L2cacheTag.act
@@ -0,0 +1,6 @@
+<?xml version="1.0"?>
+<Customize>
+ <Action name="L2cacheTag">
+ <GDBSource>L2cacheTag.py</GDBSource>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/L2CacheTag_Parser/L2cacheTag.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/L2CacheTag_Parser/L2cacheTag.py
new file mode 100644
index 0000000..b3cbbb9
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/L2CacheTag_Parser/L2cacheTag.py
@@ -0,0 +1,221 @@
+import sys
+import time
+import os
+sys.path.append(os.path.dirname(os.path.realpath(__file__)))
+import gdb
+import struct
+from operator import itemgetter, attrgetter
+from TCF import Event, Result
+import TCF as client
+
+
+host = 'localhost'
+port = 1534
+
+result = gdb.execute('show env tcfport', to_string=True)
+if not result == None:
+ portstr = str(result)
+ try:
+ port = int(portstr[portstr.index('=')+2:])
+ except:
+ print 'parse fail: ' + portstr
+
+output = ''
+
+def parse_core(var, array_index, array_index_2):
+ global output
+ gdb_cmd = "x/1x " + var + "[%d]" %(array_index)
+ if array_index_2 >= 0:
+ gdb_cmd += "[%d]" %(array_index_2)
+ content = gdb.execute(gdb_cmd, True, to_string=True)
+ content = content.replace(":", " ")
+ content = content.split(" ")[0]
+ content = int(content,16)
+ return content
+
+def parse_array(var, index_num):
+ global output
+ result_array = []
+ for i in range(index_num):
+ result_array.append(parse_core(var, i, -1))
+ return result_array
+
+def parse_array_2dim(var, index_num1, index_num2):
+ global output
+ result_array = []
+ for i in range(index_num1):
+ for j in range(index_num2):
+ result_array.append(parse_core(var, i, j))
+ return result_array
+
+def parse_global_variable(var):
+ global output
+ gdb_cmd = "p/x " + var
+ content = gdb.execute(gdb_cmd, True, to_string=True)
+ content = content.split(" ")
+ if len(content) == 3:
+ return int(content[2],16)
+ else:
+ var_len = len(content) - 2
+ if var_len>=200:
+ output += "Fail with var_len larger than 200\n"
+ return parse_array(var, var_len)
+
+ gdb_cmd = "x/" + str(var_len) + "x " + var
+ content = gdb.execute(gdb_cmd, True, to_string=True)
+ # format GDB x/x command results
+ content = content.replace(":", "")
+ content = content.replace("\n", "\t")
+ content = content.split("\t")
+
+ for i in range(0,len(content),1):
+ output += str(i) + ": " + content[i] + "\n"
+
+ # # remove redundant gdb information
+ del content[-1] # The last one is always empty because the '\t'
+
+ loop_num = var_len/4 + var_len
+
+ if var_len%4 != 0:
+ loop_num -= var_len%4
+ else:
+ loop_num -= 5
+
+
+ del content[0]
+
+ return content
+ return str(len(content))
+
+def print_array(name_str, array_var):
+ global output
+
+ if type(array_var) is int:
+ output += name_str + ": %8X" %(array_var) + "\n"
+
+ elif type(array_var) is list:
+ output += name_str + ": \n"
+ var_len = len(array_var)
+ for i in range(0,var_len,1):
+ output += str(i) + ": %8X" %(array_var[i]) + "\n"
+ output += "\n"
+
+def parse_l2cache_tag_all():
+ l2cahe_line_num = 8*2048
+ parse_loop_num = l2cahe_line_num/200
+ last_parse_num = l2cahe_line_num%200
+
+
+
+def parse_tag(L23TagLo):
+ global output
+
+ tag=((L23TagLo>>0xF)<<0xF)
+ valid=((L23TagLo)&(1<<0x7))>>(0x7)
+ dirty=((L23TagLo)&(1<<0x6))>>(0x6)
+ lock=((L23TagLo)&(1<<0x5))>>(0x5)
+
+ output += " Tag = "+"0x%8x" %(tag)
+ output += ", Valid = "+"0x%1x" %(valid)
+ output += ", Dirty = "+"0x%1x" %(dirty)
+ output += ", Lock = "+"0x%1x \n" %(lock)
+
+
+def check_tag_locked_valid(L23TagLo):
+
+ tag=((L23TagLo>>0xF)<<0xF)
+ valid=((L23TagLo)&(1<<0x7))>>(0x7)
+ dirty=((L23TagLo)&(1<<0x6))>>(0x6)
+ lock=((L23TagLo)&(1<<0x5))>>(0x5)
+ if (valid==1) and (lock == 1):
+ return True
+ else:
+ return False
+
+def parse_range_address(start_addr, length):
+ global output
+ global l2cache_lock_fail_tag
+ index_way = 0x0
+ loop_count_way = 0x8
+
+ index_line = (start_addr>>0x6)&(0x7FF)
+ loop_count_line = (length>>(0x6))+index_line
+
+ while index_line < loop_count_line:
+
+ output += " Index "+"0x%4x" %(index_line) +": \n"
+ while index_way < loop_count_way:
+ L23TagLo = l2cache_lock_fail_tag[index_way*0x800+index_line]
+ output += " Way %d" %(index_way)+":"
+ parse_tag(L23TagLo)
+ index_way += 1
+ index_line += 1
+ index_way = 0
+
+
+def check_range_address_locked_valid(start_addr, length):
+ global output
+ global l2cache_lock_fail_tag
+ index_way = 0x0
+ loop_count_way = 0x8
+ per_address_check_result = False
+ total_result = True
+
+ index_line = (start_addr>>0x6)&(0x7FF)
+ loop_count_line = (length>>(0x6))+index_line
+ loop_index = 0
+
+ while index_line < loop_count_line:
+ checkAddress = start_addr + loop_index*64
+ tagCompare = (checkAddress >> (0x6 + 0xB))
+ while index_way < loop_count_way:
+ L23TagLo = l2cache_lock_fail_tag[index_way*0x800+index_line]
+ if (check_tag_locked_valid(L23TagLo) == True) and ((L23TagLo >> (0x6 + 0xB)) == tagCompare):
+ per_address_check_result = True
+ index_way += 1
+
+ if per_address_check_result == False:
+ output += "checkAddress = %8x : FAIL\n" %(checkAddress)
+ parse_range_address(checkAddress, 64)
+ total_result = False
+ else:
+ output += "checkAddress = %8x : PASS\n" %(checkAddress)
+ index_line += 1
+ index_way = 0
+ loop_index += 1
+ per_address_check_result = False
+ return total_result
+
+# Main Function
+l2cache_lock_fail_tag_magic = parse_global_variable("l2cache_lock_fail_tag_magic")
+if l2cache_lock_fail_tag_magic != 0x10306451:
+ output += "L2cacheTag magic number is wrong, it may be some situations below \n"
+ output += " 1) L2cacheTag not be dumped. (memory dump unfinished)\n"
+ output += " 2) Not exist any locked region, or all regions are unlocked.\n"
+else:
+ l2cache_lock_fail_tag = parse_array("l2cache_lock_fail_tag", 8*2048)
+
+ dl2cm_linker_symbol = parse_array_2dim("dl2cm_linker_symbol", 18, 6)
+
+ dl2cm_lock_label = parse_global_variable("dl2cm_lock_label")
+
+ i=0
+ summarized_result = False
+ for i in range(0,32,1):
+ if ((dl2cm_lock_label>>i) & 0x1) != 1:
+ # output += "bypass\n"
+ continue
+ output += "Checking Dynamic Locked Section #%d \n" %(i)
+ start_addr = dl2cm_linker_symbol[6*i]
+ length = dl2cm_linker_symbol[6*i+1]
+ output += "start_addr=%8X, length=%8x " %(start_addr, length) + "\n"
+ summarized_result = check_range_address_locked_valid(start_addr,length)
+ # check_range_address_unlocked()
+ output += "===== Summarized Result : %s ==========\n" %("PASS" if (summarized_result==True) else "FAIL")
+
+
+
+tcf = client.TCFThread(host, int(port))
+tcf.start()
+tcf.send(['E','UI','text','L2cacheTag','Text',output])
+tcf.close()
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/L2CacheTag_Parser/TCF.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/L2CacheTag_Parser/TCF.py
new file mode 100644
index 0000000..1c32411
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/L2CacheTag_Parser/TCF.py
@@ -0,0 +1,170 @@
+import getopt
+from multiprocessing import Queue
+import socket
+import sys
+from threading import Thread
+
+SPLITTER = '\x00'
+EOL = '\x03\x01'
+HEADER = '\x03\x03'
+LEN_EOL = len((SPLITTER + EOL))
+
+class Event():
+ def __init__(self, args):
+ b = bytearray(args).split(SPLITTER.encode('utf_8'))
+ self.servicename = b[1]
+ self.eventname = b[2]
+ self.data = b[3]
+ self.elements = b[3:]
+
+ def getServiceName(self):
+ return self.servicename.decode('utf_8')
+
+ def getEventName(self):
+ return self.eventname.decode('utf_8')
+
+ def getData(self):
+ return self.data.decode('utf_8')
+
+ def getElement(self, index):
+ if len(self.elements) == 0:
+ return ''
+ return self.elements[index]
+
+ def toString(self):
+ datastr = ''
+ for b in self.elements:
+ if not b == EOL:
+ datastr = datastr + ' ' + b.decode('utf_8')
+ return 'Event ' + self.getServiceName() + ' ' + self.getEventName() + ' ' + datastr
+
+class Result():
+ def __init__(self, args):
+ b = bytearray(args).split(SPLITTER.encode('utf_8'))
+ self.type = b[0]
+ self.token = b[1]
+ self.data = b[2]
+ self.elements = b[2:]
+
+ def getType(self):
+ return self.type.decode('utf_8')
+
+ def getToken(self):
+ return self.token.decode('utf_8')
+
+ def getData(self):
+ return self.data.decode('utf_8')
+
+ def getElement(self, index):
+ if len(self.elements) == 0:
+ return ''
+ return self.elements[index]
+
+ def toString(self):
+ datastr = ''
+ for b in self.elements:
+ if not b == EOL:
+ datastr = datastr + ' ' + b.decode('utf_8')
+ return self.getType() + ' ' + self.getToken() + ' ' + datastr
+
+class TCFThread(Thread):
+ def __init__(self, host='localhost', port='1534'):
+ Thread.__init__(self)
+ try:
+ opts, args = getopt.getopt(sys.argv[1:],"h:p:",["host=","port="])
+ for opt, arg in opts:
+ if opt in ("-h", "--host"):
+ host = arg
+ elif opt in ("-p", "--port"):
+ port = int(arg)
+ except getopt.GetoptError:
+ pass
+ self.tcf_terminator = (SPLITTER + EOL).encode('utf_8')
+ self.tcf = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+ self.tcf.connect((host, int(port)))
+ self.queue = Queue()
+ self.send(['E','Locator','Hello','["ZeroCopy"]'])
+
+ def run(self):
+ remain = None
+ while 1:
+ try:
+ data = self.tcf.recv(1024)
+ if remain == None:
+ remain = data
+ else:
+ remain = remain + data
+
+ if bytearray(data).endswith(self.tcf_terminator):
+ res, rem = getData(remain)
+ if bytearray(res).startswith('E'.encode('utf_8')):
+ self.queue.put(Event(res))
+ elif bytearray(res).startswith('R'.encode('utf_8')):
+ self.queue.put(Result(res))
+ remain = rem
+ except:
+ break
+ self.tcf.close()
+
+ def get(self):
+ if not self.queue.empty():
+ return self.queue.get()
+ else:
+ return None
+
+ def send(self, args):
+ for arg in args:
+ self.tcf.send(str(arg + SPLITTER).encode('utf_8'))
+ self.tcf.send(EOL.encode('utf_8'))
+
+ def rawsend(self, rawarg):
+ self.tcf.send(rawarg)
+
+ def close(self):
+ self.tcf.shutdown(1)
+ self.tcf.close()
+
+def getData(arg):
+ data = bytearray(arg)
+ result = None
+ remain = None
+ if data.startswith(HEADER.encode('utf_8')):
+ ind = data.index(HEADER.encode('utf_8'))+2
+ leng, cnt = getDataLength(data, ind, 0)
+ ind = ind + cnt + 1
+ result = data[ind:ind+leng-1]
+ remain = data[ind+leng-1:]
+ else:
+ ind = data.index((SPLITTER + EOL).encode('utf_8'))
+ if not ind == -1:
+ result = data[:ind]
+ remain = data[ind:]
+ else:
+ result = None
+ remain = data
+
+ if not remain == None and bytearray(remain).startswith((SPLITTER + EOL).encode('utf_8')):
+ remain = remain[LEN_EOL:]
+
+# print('result: \'' + str(result) + '\'')
+# print('remain: \'' + str(remain) + '\'')
+# sys.stdout.flush()
+ return result, remain
+
+def getDataLength(_rec, ind, count):
+ rec_bytes = bytearray(_rec);
+ leng = rec_bytes[ind]
+ mulp = 0
+ if count == 0:
+ mulp = 1
+ else:
+ mulp = 128 * count
+
+ if leng & 0x80 == 0:
+ return leng * mulp, count
+ else:
+ num, cnt = getDataLength(rec_bytes, ind + 1, count + 1)
+ return ((leng & 0x7f) * mulp) + num, cnt
+
+def doEcaspe(arg):
+ return str(arg).replace('\\', '\\\\').replace('\"', '\\\"')
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/L2CacheTag_Parser/TCF.pyc b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/L2CacheTag_Parser/TCF.pyc
new file mode 100644
index 0000000..36a6a69
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/L2CacheTag_Parser/TCF.pyc
Binary files differ
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/L2CacheTag_Parser/gdbsrc.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/L2CacheTag_Parser/gdbsrc.act
new file mode 100644
index 0000000..1c0236d
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/L2CacheTag_Parser/gdbsrc.act
@@ -0,0 +1,7 @@
+<?xml version="1.0"?>
+<!DOCTYPE Customize SYSTEM "Customize.dtd">
+<Customize>
+ <Action name="gdb source" icon="">
+ <GDBSource>print.py</GDBSource>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/L2CacheTag_Parser/kill.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/L2CacheTag_Parser/kill.act
new file mode 100644
index 0000000..bf4ef65
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/L2CacheTag_Parser/kill.act
@@ -0,0 +1,7 @@
+<?xml version="1.0"?>
+<!DOCTYPE Customize SYSTEM "Customize.dtd">
+<Customize>
+ <Toolbar name="Kill" icon="">
+ <GDB>kill</GDB>
+ </Toolbar>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/L2CacheTag_Parser/print.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/L2CacheTag_Parser/print.py
new file mode 100644
index 0000000..06572ab
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/L2CacheTag_Parser/print.py
@@ -0,0 +1 @@
+print 1+2
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/MPU_Parser/Customize.dtd b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/MPU_Parser/Customize.dtd
new file mode 100644
index 0000000..977cb81
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/MPU_Parser/Customize.dtd
@@ -0,0 +1,17 @@
+<!ELEMENT Customize (Toolbar*,MainMenu*)>
+<!ELEMENT Toolbar (GDB*,SHELL*,PYSWTBOT*,CMM*,Menu*,MenuItem*)>
+<!ELEMENT MainMenu (Menu*,MenuItem*)>
+<!ELEMENT Menu (Menu*,MenuItem*)>
+<!ELEMENT MenuItem (GDB*,SHELL*,PYSWTBOT*,CMM*)>
+<!ATTLIST Toolbar name CDATA #REQUIRED>
+<!ATTLIST Toolbar icon CDATA #REQUIRED>
+<!ATTLIST MainMenu name CDATA #REQUIRED>
+<!ATTLIST MainMenu icon CDATA #REQUIRED>
+<!ATTLIST Menu name CDATA #REQUIRED>
+<!ATTLIST Menu icon CDATA #REQUIRED>
+<!ATTLIST MenuItem name CDATA #REQUIRED>
+<!ATTLIST MenuItem icon CDATA #REQUIRED>
+<!ELEMENT GDB (#PCDATA)>
+<!ELEMENT SHELL (#PCDATA)>
+<!ELEMENT PYSWTBOT (#PCDATA)>
+<!ELEMENT CMM (#PCDATA)>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/MPU_Parser/TCF.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/MPU_Parser/TCF.py
new file mode 100644
index 0000000..1c32411
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/MPU_Parser/TCF.py
@@ -0,0 +1,170 @@
+import getopt
+from multiprocessing import Queue
+import socket
+import sys
+from threading import Thread
+
+SPLITTER = '\x00'
+EOL = '\x03\x01'
+HEADER = '\x03\x03'
+LEN_EOL = len((SPLITTER + EOL))
+
+class Event():
+ def __init__(self, args):
+ b = bytearray(args).split(SPLITTER.encode('utf_8'))
+ self.servicename = b[1]
+ self.eventname = b[2]
+ self.data = b[3]
+ self.elements = b[3:]
+
+ def getServiceName(self):
+ return self.servicename.decode('utf_8')
+
+ def getEventName(self):
+ return self.eventname.decode('utf_8')
+
+ def getData(self):
+ return self.data.decode('utf_8')
+
+ def getElement(self, index):
+ if len(self.elements) == 0:
+ return ''
+ return self.elements[index]
+
+ def toString(self):
+ datastr = ''
+ for b in self.elements:
+ if not b == EOL:
+ datastr = datastr + ' ' + b.decode('utf_8')
+ return 'Event ' + self.getServiceName() + ' ' + self.getEventName() + ' ' + datastr
+
+class Result():
+ def __init__(self, args):
+ b = bytearray(args).split(SPLITTER.encode('utf_8'))
+ self.type = b[0]
+ self.token = b[1]
+ self.data = b[2]
+ self.elements = b[2:]
+
+ def getType(self):
+ return self.type.decode('utf_8')
+
+ def getToken(self):
+ return self.token.decode('utf_8')
+
+ def getData(self):
+ return self.data.decode('utf_8')
+
+ def getElement(self, index):
+ if len(self.elements) == 0:
+ return ''
+ return self.elements[index]
+
+ def toString(self):
+ datastr = ''
+ for b in self.elements:
+ if not b == EOL:
+ datastr = datastr + ' ' + b.decode('utf_8')
+ return self.getType() + ' ' + self.getToken() + ' ' + datastr
+
+class TCFThread(Thread):
+ def __init__(self, host='localhost', port='1534'):
+ Thread.__init__(self)
+ try:
+ opts, args = getopt.getopt(sys.argv[1:],"h:p:",["host=","port="])
+ for opt, arg in opts:
+ if opt in ("-h", "--host"):
+ host = arg
+ elif opt in ("-p", "--port"):
+ port = int(arg)
+ except getopt.GetoptError:
+ pass
+ self.tcf_terminator = (SPLITTER + EOL).encode('utf_8')
+ self.tcf = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+ self.tcf.connect((host, int(port)))
+ self.queue = Queue()
+ self.send(['E','Locator','Hello','["ZeroCopy"]'])
+
+ def run(self):
+ remain = None
+ while 1:
+ try:
+ data = self.tcf.recv(1024)
+ if remain == None:
+ remain = data
+ else:
+ remain = remain + data
+
+ if bytearray(data).endswith(self.tcf_terminator):
+ res, rem = getData(remain)
+ if bytearray(res).startswith('E'.encode('utf_8')):
+ self.queue.put(Event(res))
+ elif bytearray(res).startswith('R'.encode('utf_8')):
+ self.queue.put(Result(res))
+ remain = rem
+ except:
+ break
+ self.tcf.close()
+
+ def get(self):
+ if not self.queue.empty():
+ return self.queue.get()
+ else:
+ return None
+
+ def send(self, args):
+ for arg in args:
+ self.tcf.send(str(arg + SPLITTER).encode('utf_8'))
+ self.tcf.send(EOL.encode('utf_8'))
+
+ def rawsend(self, rawarg):
+ self.tcf.send(rawarg)
+
+ def close(self):
+ self.tcf.shutdown(1)
+ self.tcf.close()
+
+def getData(arg):
+ data = bytearray(arg)
+ result = None
+ remain = None
+ if data.startswith(HEADER.encode('utf_8')):
+ ind = data.index(HEADER.encode('utf_8'))+2
+ leng, cnt = getDataLength(data, ind, 0)
+ ind = ind + cnt + 1
+ result = data[ind:ind+leng-1]
+ remain = data[ind+leng-1:]
+ else:
+ ind = data.index((SPLITTER + EOL).encode('utf_8'))
+ if not ind == -1:
+ result = data[:ind]
+ remain = data[ind:]
+ else:
+ result = None
+ remain = data
+
+ if not remain == None and bytearray(remain).startswith((SPLITTER + EOL).encode('utf_8')):
+ remain = remain[LEN_EOL:]
+
+# print('result: \'' + str(result) + '\'')
+# print('remain: \'' + str(remain) + '\'')
+# sys.stdout.flush()
+ return result, remain
+
+def getDataLength(_rec, ind, count):
+ rec_bytes = bytearray(_rec);
+ leng = rec_bytes[ind]
+ mulp = 0
+ if count == 0:
+ mulp = 1
+ else:
+ mulp = 128 * count
+
+ if leng & 0x80 == 0:
+ return leng * mulp, count
+ else:
+ num, cnt = getDataLength(rec_bytes, ind + 1, count + 1)
+ return ((leng & 0x7f) * mulp) + num, cnt
+
+def doEcaspe(arg):
+ return str(arg).replace('\\', '\\\\').replace('\"', '\\\"')
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/MPU_Parser/TCF.pyc b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/MPU_Parser/TCF.pyc
new file mode 100644
index 0000000..36a6a69
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/MPU_Parser/TCF.pyc
Binary files differ
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/MPU_Parser/gdbsrc.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/MPU_Parser/gdbsrc.act
new file mode 100644
index 0000000..1c0236d
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/MPU_Parser/gdbsrc.act
@@ -0,0 +1,7 @@
+<?xml version="1.0"?>
+<!DOCTYPE Customize SYSTEM "Customize.dtd">
+<Customize>
+ <Action name="gdb source" icon="">
+ <GDBSource>print.py</GDBSource>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/MPU_Parser/kill.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/MPU_Parser/kill.act
new file mode 100644
index 0000000..bf4ef65
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/MPU_Parser/kill.act
@@ -0,0 +1,7 @@
+<?xml version="1.0"?>
+<!DOCTYPE Customize SYSTEM "Customize.dtd">
+<Customize>
+ <Toolbar name="Kill" icon="">
+ <GDB>kill</GDB>
+ </Toolbar>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/MPU_Parser/mpu.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/MPU_Parser/mpu.act
new file mode 100644
index 0000000..0183c94
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/MPU_Parser/mpu.act
@@ -0,0 +1,6 @@
+<?xml version="1.0"?>
+<Customize>
+ <Action name="MPU">
+ <GDBSource>mpu.py</GDBSource>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/MPU_Parser/mpu.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/MPU_Parser/mpu.py
new file mode 100644
index 0000000..beef9aa
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/MPU_Parser/mpu.py
@@ -0,0 +1,225 @@
+import sys
+import time
+import os
+sys.path.append(os.path.dirname(os.path.realpath(__file__)))
+import gdb
+import struct
+from operator import itemgetter, attrgetter
+from TCF import Event, Result
+import TCF as client
+
+host = 'localhost'
+port = 1534
+
+result = gdb.execute('show env tcfport', to_string=True)
+if not result == None:
+ portstr = str(result)
+ try:
+ port = int(portstr[portstr.index('=')+2:])
+ except:
+ print 'parse fail: ' + portstr
+
+output = ''
+
+bank_size = 0x10000000
+bank_0 = 0x0
+bank_1 = 0x10000000
+bank_2 = 0x20000000
+bank_3 = 0x30000000
+bank_4 = 0x40000000
+bank_5 = 0x50000000
+bank_6 = 0x60000000
+bank_7 = 0x70000000
+bank_8 = 0x80000000
+bank_9 = 0x90000000
+bank_A = 0xA0000000
+bank_B = 0xB0000000
+bank_C = 0xC0000000
+bank_D = 0xD0000000
+bank_E = 0xE0000000
+bank_F = 0xF0000000
+
+# En[15] Size[14:10] Count[9:6] RI[5] WI[4] XI[3] CCA[2:0]
+mpu_FDC_offset = 0xc0
+mpu_ACSR_offset = 0x0
+mpu_Config_offset = 0x8
+mpu_SegmentControl_0_offset = 0x10
+mpu_SegmentControl_1_offset = 0x14
+mpu_SegmentControl_2_offset = 0x18
+mpu_SegmentControl_3_offset = 0x1c
+mpu_settings = []
+mpu_map = []
+
+class setting:
+ def __init__(self, idx, base_addr, end_addr, reg, En, Size, Count, RI, WI, XI, CCA, Protect):
+ self.idx = idx
+ self.base_addr = base_addr
+ self.end_addr = end_addr
+ self.reg = reg
+ self.En = En
+ self.Size = Size
+ self.Count = Count
+ self.RI = RI
+ self.WI = WI
+ self.XI = XI
+ self.CCA = CCA
+ self.Protect = Protect
+ def __repr__(self):
+ return repr((self.idx, self.base_addr, self.end_addr, self.reg, self.En, self.Size, self.Count, self.RI, self.WI, self.XI, self.CCA, self.Protect))
+
+class result:
+ def __init__(self, base_addr, end_addr, RI, WI, XI, CCA, Protect):
+ self.base_addr = base_addr
+ self.end_addr = end_addr
+ self.RI = RI
+ self.WI = WI
+ self.XI = XI
+ self.CCA = CCA
+ self.Protect = Protect
+ def __repr__(self):
+ return repr((self.base_addr, self.end_addr, self.RI, self.WI, self.XI, self.CCA, self.Protect))
+
+def CCA_cfg(cca):
+ return {
+ 2 : 'UC',
+ 3 : 'WB',
+ 4 : 'CWBE',
+ 5 : 'CWB',
+ 7 : 'UCA',
+ }.get(cca, ' ')
+
+def RI_cfg(ri):
+ return {
+ 0 : '-',
+ 1 : 'R',
+ }.get(ri, '-')
+
+def WI_cfg(wi):
+ return {
+ 0 : '-',
+ 1 : 'W',
+ }.get(wi, '-')
+
+def XI_cfg(xi):
+ return {
+ 0 : '-',
+ 1 : 'X',
+ }.get(xi, '-')
+
+gdb_cmd = "p/x $cdmmbase"
+cdmm_content = gdb.execute(gdb_cmd, True, to_string=True)
+cdmm_content = cdmm_content.split(" ")
+cdmmbase_str = cdmm_content[2]
+cdmmbase = int(cdmmbase_str, 16) + mpu_FDC_offset
+cdmmbase_str = "0x1fc100c0"
+gdb_cmd = "x/72x " + cdmmbase_str
+#gdb_cmd = "x/72x " + cdmmbase
+memory_content = gdb.execute(gdb_cmd, True, to_string=True)
+
+# format GDB x/x command results
+memory_content = memory_content.replace(":", "")
+memory_content = memory_content.replace("\n", "\t")
+memory_content = memory_content.split("\t")
+
+# remove redundant gdb information
+for i in range(90, 0, -5):
+ del memory_content[i]
+
+del memory_content[0]
+
+# parsing MPU_ACSR register (offset 0x0)
+mpu_ACSR = int(memory_content[mpu_ACSR_offset/4], 16)
+
+# parsing MPU_Config register (offset 0x8)
+# En[31], Excr[19], ExcW[18], ExcX[17], Exc_Reg_Match[16], Exc_Reg_Num[12:8], Num_Regions[4:0]
+mpu_Config = int(memory_content[mpu_Config_offset/4], 16)
+mpu_Config_En = (mpu_Config&0x80000000)>>31
+mpu_Config_ExcR = (mpu_Config&0x80000)>>19
+mpu_Config_ExcW = (mpu_Config&0x40000)>>18
+mpu_Config_ExcX = (mpu_Config&0x20000)>>17
+mpu_Config_Exc_Reg_Match = (mpu_Config&0x10000)>>16
+mpu_Config_Exc_Reg_Num = (mpu_Config&0x1f00)>>8
+mpu_Config_Num_Regions = (mpu_Config&0x1f) + 1 # count = ctrl + 1
+# print "MPU_Config", mpu_Config_En, mpu_Config_ExcR, mpu_Config_ExcW, mpu_Config_ExcX, mpu_Config_Exc_Reg_Match, mpu_Config_Exc_Reg_Num,mpu_Config_Num_Regions
+
+# MPU Segment Control Registers (offset 0x10 0x14 0x18 0x1c)
+# RI[29,21,13,5] WI[28,20,12,4] XI[27,19,11,3] CCA[26:24, 18:16, 10:8, 2:0]
+mpu_SegmentControl_0 = int(memory_content[mpu_SegmentControl_0_offset/4], 16)
+mpu_settings.append(setting(0, bank_0, bank_0 + bank_size * 1 - 1, (mpu_SegmentControl_0&0xFF), 1, bank_size, 1, (mpu_SegmentControl_0&0x20)>>5, (mpu_SegmentControl_0&0x10)>>4, (mpu_SegmentControl_0&0x8)>>3, (mpu_SegmentControl_0&0x7), 'SC'))
+mpu_settings.append(setting(1, bank_1, bank_1 + bank_size * 1 - 1, (mpu_SegmentControl_0&0xFF00)>>8, 1, bank_size, 1, (mpu_SegmentControl_0&0x2000)>>13, (mpu_SegmentControl_0&0x1000)>>12, (mpu_SegmentControl_0&0x800)>>11, (mpu_SegmentControl_0&0x700)>>8, 'SC'))
+mpu_settings.append(setting(2, bank_2, bank_2 + bank_size * 1 - 1, (mpu_SegmentControl_0&0xFF0000)>>16, 1, bank_size, 1, (mpu_SegmentControl_0&0x200000)>>21, (mpu_SegmentControl_0&0x100000)>>20, (mpu_SegmentControl_0&0x80000)>>19, (mpu_SegmentControl_0&0x70000)>>16, 'SC'))
+mpu_settings.append(setting(3, bank_3, bank_3 + bank_size * 1 - 1, (mpu_SegmentControl_0&0xFF000000)>>24, 1, bank_size, 1, (mpu_SegmentControl_0&0x20000000)>>29, (mpu_SegmentControl_0&0x10000000)>>28, (mpu_SegmentControl_0&0x8000000)>>27, (mpu_SegmentControl_0&0x7000000)>>24, 'SC'))
+
+mpu_SegmentControl_1 = int(memory_content[mpu_SegmentControl_1_offset/4], 16)
+mpu_settings.append(setting(4, bank_4, bank_4 + bank_size * 1 - 1, (mpu_SegmentControl_1&0xFF), 1, bank_size, 1, (mpu_SegmentControl_1&0x20)>>5, (mpu_SegmentControl_1&0x10)>>4, (mpu_SegmentControl_1&0x8)>>3, (mpu_SegmentControl_1&0x7), 'SC'))
+mpu_settings.append(setting(5, bank_5, bank_5 + bank_size * 1 - 1, (mpu_SegmentControl_1&0xFF00)>>8, 1, bank_size, 1, (mpu_SegmentControl_1&0x2000)>>13, (mpu_SegmentControl_1&0x1000)>>12, (mpu_SegmentControl_1&0x800)>>11, (mpu_SegmentControl_1&0x700)>>8, 'SC'))
+mpu_settings.append(setting(6, bank_6, bank_6 + bank_size * 1 - 1, (mpu_SegmentControl_1&0xFF0000)>>16, 1, bank_size, 1, (mpu_SegmentControl_1&0x200000)>>21, (mpu_SegmentControl_1&0x100000)>>20, (mpu_SegmentControl_1&0x80000)>>19, (mpu_SegmentControl_1&0x70000)>>16, 'SC'))
+mpu_settings.append(setting(7, bank_7, bank_7 + bank_size * 1 - 1, (mpu_SegmentControl_1&0xFF000000)>>24, 1, bank_size, 1, (mpu_SegmentControl_1&0x20000000)>>29, (mpu_SegmentControl_1&0x10000000)>>28, (mpu_SegmentControl_1&0x8000000)>>27, (mpu_SegmentControl_1&0x7000000)>>24, 'SC'))
+
+mpu_SegmentControl_2 = int(memory_content[mpu_SegmentControl_2_offset/4], 16)
+mpu_settings.append(setting(8, bank_8, bank_8 + bank_size * 1 - 1, (mpu_SegmentControl_2&0xFF), 1, bank_size, 1, (mpu_SegmentControl_2&0x20)>>5, (mpu_SegmentControl_2&0x10)>>4, (mpu_SegmentControl_2&0x8)>>3, (mpu_SegmentControl_2&0x7), 'SC'))
+mpu_settings.append(setting(9, bank_9, bank_9 + bank_size * 1 - 1, (mpu_SegmentControl_2&0xFF00)>>8, 1, bank_size, 1, (mpu_SegmentControl_2&0x2000)>>13, (mpu_SegmentControl_2&0x1000)>>12, (mpu_SegmentControl_2&0x800)>>11, (mpu_SegmentControl_2&0x700)>>8, 'SC'))
+mpu_settings.append(setting(10, bank_A, bank_A + bank_size * 1 - 1, (mpu_SegmentControl_2&0xFF0000)>>16, 1, bank_size, 1, (mpu_SegmentControl_2&0x200000)>>21, (mpu_SegmentControl_2&0x100000)>>20, (mpu_SegmentControl_2&0x80000)>>19, (mpu_SegmentControl_2&0x70000)>>16, 'SC'))
+mpu_settings.append(setting(11, bank_B, bank_B + bank_size * 1 - 1, (mpu_SegmentControl_2&0xFF000000)>>24, 1, bank_size, 1, (mpu_SegmentControl_2&0x20000000)>>29, (mpu_SegmentControl_2&0x10000000)>>28, (mpu_SegmentControl_2&0x8000000)>>27, (mpu_SegmentControl_2&0x7000000)>>24, 'SC'))
+
+mpu_SegmentControl_3 = int(memory_content[mpu_SegmentControl_3_offset/4], 16)
+mpu_settings.append(setting(12, bank_C, bank_C + bank_size * 1 - 1, (mpu_SegmentControl_3&0xFF), 1, bank_size, 1, (mpu_SegmentControl_3&0x20)>>5, (mpu_SegmentControl_3&0x10)>>4, (mpu_SegmentControl_3&0x8)>>3, (mpu_SegmentControl_3&0x7), 'SC'))
+mpu_settings.append(setting(13, bank_D, bank_D + bank_size * 1 - 1, (mpu_SegmentControl_3&0xFF00)>>8, 1, bank_size, 1, (mpu_SegmentControl_3&0x2000)>>13, (mpu_SegmentControl_3&0x1000)>>12, (mpu_SegmentControl_3&0x800)>>11, (mpu_SegmentControl_3&0x700)>>8, 'SC'))
+mpu_settings.append(setting(14, bank_E, bank_E + bank_size * 1 - 1, (mpu_SegmentControl_3&0xFF0000)>>16, 1, bank_size, 1, (mpu_SegmentControl_3&0x200000)>>21, (mpu_SegmentControl_3&0x100000)>>20, (mpu_SegmentControl_3&0x80000)>>19, (mpu_SegmentControl_3&0x70000)>>16, 'SC'))
+mpu_settings.append(setting(15, bank_F, bank_F + bank_size * 1 - 1, (mpu_SegmentControl_3&0xFF000000)>>24, 1, bank_size, 1, (mpu_SegmentControl_3&0x20000000)>>29, (mpu_SegmentControl_3&0x10000000)>>28, (mpu_SegmentControl_3&0x8000000)>>27, (mpu_SegmentControl_3&0x7000000)>>24, 'SC'))
+
+for i in range(0, len(mpu_settings), 1):
+ mpu_map.append(result(mpu_settings[i].base_addr, mpu_settings[i].end_addr, mpu_settings[i].RI, mpu_settings[i].WI, mpu_settings[i].XI, mpu_settings[i].CCA, mpu_settings[i].Protect))
+
+# parse MPU Region Base Address Register and Region Control Register
+# Base Address Register
+# Base_Addr [31:5]
+# Region Control Register
+# En[15] Size[14:10] Count[9:6] RI[5] WI[4] XI[3] CCA[2:0]
+for i in range(0, mpu_Config_Num_Regions, 1):
+ addr = int(memory_content[i*2+8], 16)
+ ctrl = int(memory_content[i*2+9], 16)
+ mpu_ctrl_Size = pow(2, ((ctrl&0x7C00)>>10))
+ mpu_ctrl_Count = (ctrl&0x3C0)>>6 + 1
+ mpu_ctrl_RI = (ctrl&0x20)>>5
+ mpu_ctrl_WI = (ctrl&0x10)>>4
+ mpu_ctrl_XI = (ctrl&0x8)>>3
+ mpu_ctrl_CCA = ctrl&0x7
+ end_addr = addr + mpu_ctrl_Size * mpu_ctrl_Count - 1
+ if ((ctrl&0x8000)>>15) == 1:
+ mpu_settings.append(setting(16+i, addr, addr + mpu_ctrl_Size * mpu_ctrl_Count - 1, ctrl, (ctrl&0x8000)>>15, mpu_ctrl_Size, mpu_ctrl_Count, mpu_ctrl_RI, mpu_ctrl_WI, mpu_ctrl_XI, mpu_ctrl_CCA, 'RC'))
+ for j in range(0, len(mpu_map), 1):
+ # shrink head part
+ if (mpu_map[j].base_addr <= addr) and (mpu_map[j].end_addr <= end_addr) and (mpu_map[j].end_addr >= addr) :
+ mpu_map[j].end_addr = addr - 1
+ # remove fully covered sub part
+ elif (mpu_map[j].base_addr >= addr) and (mpu_map[j].end_addr <= end_addr) :
+ mpu_map[j].base_addr = -1
+ mpu_map[j].end_addr = -1
+ # shrink tail part
+ elif (mpu_map[j].base_addr <= end_addr) and (mpu_map[j].end_addr >= end_addr) and (mpu_map[j].base_addr >= addr):
+ mpu_map[j].base_addr = end_addr + 1
+ # fully covered by previous region
+ elif (mpu_map[j].base_addr < addr) and (mpu_map[j].end_addr > end_addr) :
+ mpu_map.append(result(end_addr + 1, mpu_map[j].end_addr, mpu_map[j].RI, mpu_map[j].WI, mpu_map[j].XI, mpu_map[j].CCA, mpu_map[j].Protect))
+ mpu_map[j].end_addr = addr - 1
+ break
+ mpu_map.append(result(addr, end_addr, mpu_ctrl_RI, mpu_ctrl_WI, mpu_ctrl_XI, mpu_ctrl_CCA, 'RC'))
+
+mpu_map = sorted(mpu_map, key=attrgetter('base_addr'))
+
+# remove empty or illegal region, merge range with same attributes
+for i in range(len(mpu_map)-1, -1, -1):
+ if (mpu_map[i].end_addr == -1) or mpu_map[i].base_addr >= mpu_map[i].end_addr:
+ mpu_map.pop(i)
+ if (i>=1) and (mpu_map[i].RI == mpu_map[i-1].RI) and (mpu_map[i].WI == mpu_map[i-1].WI) and (mpu_map[i].XI == mpu_map[i-1].XI) and (mpu_map[i].CCA == mpu_map[i-1].CCA) and (mpu_map[i].Protect == mpu_map[i-1].Protect):
+ mpu_map[i-1].end_addr = mpu_map[i].end_addr
+ mpu_map.pop(i)
+
+for i in range(0, len(mpu_map), 1):
+ output += "%8x ~ %8x %s %s %s %s\t %s" %(mpu_map[i].base_addr, mpu_map[i].end_addr, RI_cfg(mpu_map[i].RI), WI_cfg(mpu_map[i].WI), XI_cfg(mpu_map[i].XI), CCA_cfg(mpu_map[i].CCA), mpu_map[i].Protect) + '\n'
+
+tcf = client.TCFThread(host, int(port))
+tcf.start()
+tcf.send(['E','UI','text','MPU','Text',output])
+tcf.close()
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/MPU_Parser/print.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/MPU_Parser/print.py
new file mode 100644
index 0000000..06572ab
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/MPU_Parser/print.py
@@ -0,0 +1 @@
+print 1+2
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/config/L1Bypass.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/config/L1Bypass.act
new file mode 100755
index 0000000..a3c4b52
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/config/L1Bypass.act
@@ -0,0 +1,6 @@
+<?xml version="1.0"?>
+<Customize>
+ <Action name="L1AssertBypass" icon="">
+ <GDB>p/x L1_ASSERT_BYPASS=3</GDB>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/config/MT3967_AllIn1_LoadSymbol.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/config/MT3967_AllIn1_LoadSymbol.launch
new file mode 100755
index 0000000..ae41718
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/config/MT3967_AllIn1_LoadSymbol.launch
@@ -0,0 +1,59 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="../../../bin/MT3967_SP_PCB01_MT3967_S00.elf"/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.cache.FilePath" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.LocalTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<intAttribute key="com.mediatek.ide.util.gdbPortNumber" value="3333"/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value="mem 0x00000000 0x4fffffff rw mem 0x60000000 0xffffffff rw "/>
+<stringAttribute key="com.mediatek.ide.util.ipAddress" value="localhost"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value="hb general_ex_handler hb INT_TEMP_general_ex_vector hb CTI_Triggered_ex_handler"/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.substitute_path_no_translate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="MT6295_Chip"/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.args" value="-f board/mips/mt6295_mips_chip.cfg -c "adapter_khz 10000""/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.cmds" value=""/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.widget.args" value="{"Clock_10000":"10000"}"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="attach"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
+<booleanAttribute key="org.eclipse.debug.core.capture_output" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_OUTPUT_ON" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/config/MT3967_AllIn1_LoadSymbol_BigRam.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/config/MT3967_AllIn1_LoadSymbol_BigRam.launch
new file mode 100755
index 0000000..6f8fd84
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/config/MT3967_AllIn1_LoadSymbol_BigRam.launch
@@ -0,0 +1,59 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="../../../bin/MT3967_SP_PCB01_MT3967_S00.elf"/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.cache.FilePath" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.LocalTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<intAttribute key="com.mediatek.ide.util.gdbPortNumber" value="3333"/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=" "/>
+<stringAttribute key="com.mediatek.ide.util.ipAddress" value="localhost"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.substitute_path_no_translate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="MT6295_Chip"/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.args" value="-f board/mips/mt6295_mips_chip.cfg -c "adapter_khz 10000""/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.cmds" value=""/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.widget.args" value="{"Clock_10000":"10000"}"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="attach"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
+<booleanAttribute key="org.eclipse.debug.core.capture_output" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_OUTPUT_ON" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/config/easyLoader/load_dsp.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/config/easyLoader/load_dsp.py
new file mode 100755
index 0000000..86e47fa
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/coretracer/config/easyLoader/load_dsp.py
@@ -0,0 +1,106 @@
+#from imgtec import codescape
+import sys
+import time
+import os
+import gdb
+import binascii
+import Tkinter, tkFileDialog
+
+app = None
+dsp_header = 0x0
+dsp_magic = "4d4d4d01"
+
+# load dsp bin file
+def load_dsp_bin(dsp_path):
+ global dsp_header
+ time_str = time.time()
+ print "=== Start load dsp bin ==="
+ print "Dsp bin path: " + dsp_path
+ if(os.path.exists(dsp_path) == False):
+ print "DSP bin doesn't exist: %s" %(dsp_path)
+ print "[Error] Load DSP bin failed"
+ return
+ else:
+ with open(dsp_path, "rb") as dsp_bin:
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print "No header detected, continue"
+ else:
+ dsp_header = 0x200
+ dsp_bin.seek(dsp_header, os.SEEK_SET)
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print "Header detected, skip first 512B"
+ else:
+ print "DSP header detected at neither 0x0 nor 0x200"
+ print "Please check the bin is legal!"
+ print "[Error] Load DSP bin failed"
+ return
+ gdb_cmd='thread 1'
+ gdb.execute(gdb_cmd)
+ ## a) need parsing: 0x13a0000 <dsp_bin_ro>
+ ##symbol_name='&dsp_bin_ro'
+ ##dsp_addr = gdb.parse_and_eval(symbol_name)
+ ## b) need parsing: $3 = 0x13a0000
+ ##gdb_cmd='p/x &dsp_bin_ro'
+ ##dsp_addr = gdb.execute(gdb_cmd, False, True)
+ symbol_name='dsp_bin_ro'
+ dsp_addr = gdb.parse_and_eval(symbol_name)
+ dsp_addr = str(dsp_addr.address).split(" ")
+ dsp_addr = int(dsp_addr[0], 16) - dsp_header
+ print hex(dsp_addr)
+ gdb_cmd = 'monitor mips32 fastchannel 0 1'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'set $cdmmbase=0x1fc1407'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'set *0x1fc100d4=0x02030202'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = " ".join(['restore', dsp_path, 'binary', hex(dsp_addr), hex(dsp_header)])
+ print gdb_cmd
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'set *0x1fc100d4=0x02020202'
+ gdb.execute(gdb_cmd)
+ time_end = time.time()
+ print("loading dsp is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+
+class gui_tk(Tkinter.Tk):
+ def __init__(self, parent):
+ Tkinter.Tk.__init__(self, parent)
+ elf_path = ""
+ dsp_path = ""
+ dsp_addr = ""
+ self.file_opt = options = {}
+ options['title'] = 'Choose a file'
+ self.parent = parent
+ self.initialize()
+
+ def initialize(self):
+ self.grid()
+
+ dsp_button = Tkinter.Button(self, text=u"Load DSP bin =>", command=self.dsp_OnButtonClick)
+ dsp_button.grid(column=0, row=4, sticky='W')
+
+ def dsp_OnButtonClick(self):
+ dsp_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(dsp_path) > 0:
+ print "You chose %s" % dsp_path
+ load_dsp_bin(dsp_path)
+ self.quit()
+
+ def quit(self):
+ global app
+ print "=== Close Easy Loader ==="
+ app.destroy()
+
+def load_dsp_gui():
+ print "=== Start Easy Loader ==="
+ global app
+ app = gui_tk(None)
+ app.title('Easy Loader')
+ app.mainloop()
+
+
+if __name__ == "__main__":
+ load_dsp_gui()
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/mt3967-evb.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/mt3967-evb.cmm
new file mode 100755
index 0000000..54de717
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/mt3967-evb.cmm
@@ -0,0 +1 @@
+wait AP update it
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/preloader_evb3967_64_emmc_TINY.elf b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/preloader_evb3967_64_emmc_TINY.elf
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT3967/preloader_evb3967_64_emmc_TINY.elf
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6295M/MT6295M_FPGA_Load_MD_Elf_With_DSP.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6295M/MT6295M_FPGA_Load_MD_Elf_With_DSP.cmm
new file mode 100755
index 0000000..d8f2868
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6295M/MT6295M_FPGA_Load_MD_Elf_With_DSP.cmm
@@ -0,0 +1,602 @@
+;sys.m prepare
+;LOCAL &TYPE
+LOCAL &BASE_MADDR_MDRGU
+LOCAL &BASE_MADDR_APRGU
+;IF DATA.LONG(DBG:0x41000000)==0x5BA02477 ; AP DAP
+;(
+; &TYPE="EAHB"
+; &BASE_MADDR_MDRGU=0x800F0000
+;)
+;ELSE ; DATA.LONG(DBG:0x41000000)==0x6BA02477 ; MD DAP
+;(
+; sys.m down
+; MULtiCore.DEBUGACCESSPORT 1
+; MULtiCore.AXIACCESSPORT 0
+; sys.m prepare
+; &TYPE="AXI"
+; &BASE_MADDR_MDRGU=0xA00F0000
+;)
+
+system.mode attach
+
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+; fixed md mips domain ID hw bug
+D.S 0xA0060060 %LE %LONG 0x03231111
+
+
+; do orginal disable_WDT2_MIPS.cmm
+&BASE_MADDR_MDRGU=0xA00F0000
+&BASE_MADDR_APRGU=0xC3670000
+
+;D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG (0x55000000|data.long(&BASE_MADDR_MDRGU+0x0100)&~(0x3))
+&temp=data.long(&BASE_MADDR_MDRGU+0x0100)
+&temp=&temp | 0x55000000
+&temp=&temp & ~(0x3)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG &temp
+
+
+;D.S &BASE_MADDR_APRGU+0x0100 %LE %LONG (0x55000000|data.long(&BASE_MADDR_APRGU+0x0100)&~(0x1))
+&temp=data.long(&BASE_MADDR_MDRGU+0x0100)
+&temp=&temp | 0x55000000
+&temp=&temp & ~(0x1)
+D.S &BASE_MADDR_APRGU+0x0100 %LE %LONG &temp
+
+
+
+; do orginal emi_init.cmm
+LOCAL &CHIP_VER ; 0 is for FPGA, 1 is for E1, and so on
+&CHIP_VER=0
+&BASE_ADDR_EMI=0xC3000000
+&BASE_ADDR_DRAMC=0xC3010000
+&BASE_ADDR_DDRPHY=0xC3020000
+&BASE_ADDR_MEMSYSAOREG_MISC=0xC3080000
+&BASE_ADDR_AP_CLKSW=0xC3750000
+
+; Check if initialize
+
+
+&temp=DATA.LONG(&BASE_ADDR_EMI+0060)
+&temp=&temp & 0x00000400
+IF (&temp == 0x00000400)
+(
+ ENDDO
+)
+
+;DRAM initialization
+
+GOSUB DRAM_INIT
+
+PRINT "=============================="
+PRINT "EMI Initialization Pass!"
+PRINT "=============================="
+
+D.S 0x0D800000 %LE %LONG 0x00
+D.S 0x00080000 %LE %LONG 0x00
+
+PRINT "=============================="
+PRINT "Clear Dsp Header!"
+PRINT "=============================="
+
+
+;Enalbe cache to speed loading
+register.set cdmmbase 0x1fc1407
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor adapter_khz 1100
+steal monitor mips32 fastchannel 0 1 0x6f800000
+
+
+PRINT "=============================="
+PRINT "Start to Load elf !"
+PRINT "=============================="
+
+
+steal lo
+
+PRINT "=============================="
+PRINT "Start to Load DSP !"
+PRINT "=============================="
+
+steal source ../cmm/coretracer\config\easyLoader\load_dsp.py
+
+PRINT "=============================="
+PRINT "Load DSP Done!"
+PRINT "=============================="
+
+
+
+steal monitor mips32 fastchannel 0 0 0x6f800000
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+
+PRINT "=============================="
+PRINT "Load elf Done!"
+PRINT "=============================="
+
+&nvram_region=var.address("Image$$EXTSRAM_FS_ZI$$ZI$$Base")
+
+IF (&nvram_region == 0xDEADDEAD)
+(
+ PRINT "=============================="
+ PRINT "Not find NVRAM region, bypass clear it"
+ PRINT "=============================="
+)
+ELSE
+(
+ &nvram_region_FS_addr_1=&nvram_region+0x1FE
+ &nvram_region_FS_addr_2=&nvram_region+0x3FE
+ PRINT "=============================="
+ PRINT "Clear NVRAM region address &nvram_region_FS_addr_1 and &nvram_region_FS_addr_2 to 0"
+ PRINT "=============================="
+ D.S &nvram_region_FS_addr_1 %LE %LONG 0x00
+ D.S &nvram_region_FS_addr_2 %LE %LONG 0x00
+)
+
+;thread.select 1
+
+;&tt=var.address(INT_Initialize_Phase1)
+;register.set pc &tt
+;steal flushreg
+
+;steal p/x $pc
+;&t=r(pc)
+;PRINT "=============================="
+;PRINT "Set PC to INT_Initialize_Phase1: &t"
+;PRINT "=============================="
+
+ENDDO
+
+
+; =========================================================================================
+; Sub Function: DRAM_INIT
+; Description: initialize MEMPLL, DRAMC, DDRPHY, DRAM, EMI
+; =========================================================================================
+DRAM_INIT:
+ ; =MEMSYS_PASSWORD=
+ ; Unlock MEMSYS Password
+ D.S &BASE_ADDR_MEMSYSAOREG_MISC+0x3000 %LE %LONG 0x24541689
+ ;GOSUB MEMPLL_INIT
+ GOSUB DRAMC_INIT
+ GOSUB EMI_INIT
+ ; =MEMINFRA_SI_WAY_CTL=
+ ; Enable MEMINFRA EMI Path
+ ; [9:8] M7_sysram:M7_emi
+ ; [7:6] M6_sysram:M6_emi
+ ; [5:4] M4_mdmda_sysram:M4_mddma_emi
+ ; [3:2] M4_l1sys_sysram:M4_l1sys_emi
+ ; [1:0] M3_sysram:M3_emi
+ ®_val=DATA.LONG(&BASE_ADDR_MEMSYSAOREG_MISC+0x4000)
+ ®_val=®_val|0x00000155
+ D.S &BASE_ADDR_MEMSYSAOREG_MISC+0x4000 %LE %LONG ®_val
+ ; =EMI_ADDR_OFFSET=
+ ; EMI offset on address[31:24], unit is 16MB
+ &MD3_offset=0x00
+ &MD2_offset=0x00
+ &MD1_offset=0x10
+ &ap_offset=0x00
+ &emi_offset=(&MD3_offset<<0x18)+(&MD2_offset<<0x10)+(&MD1_offset<<0x08)+(&ap_offset<<0x00)
+ D.S &BASE_ADDR_MEMSYSAOREG_MISC+0x1000 %LE %LONG &emi_offset
+ ; =MEMSYS_PASSWORD=
+ ; Lock MEMSYS Password
+ D.S &BASE_ADDR_MEMSYSAOREG_MISC+0x3000 %LE %LONG 0x00000000
+ RETURN
+
+; =========================================================================================
+; Sub Function: MEMPLL_INIT
+; =========================================================================================
+MEMPLL_INIT:
+ DATA.LOAD.ELF &emi_elf_path
+ B.D /ALL
+ B.S custom_InitDRAM /HARD
+ GO
+ WAIT !RUN() 5.s
+ IF r(PC)==custom_InitDRAM
+ (
+ PRINT "MEMPLL Initialization Pass!"
+ RETURN
+ )
+ ELSE
+ (
+ PRINT "MEMPLL Initialization Failed!"
+ ENDDO
+ )
+
+; =========================================================================================
+; Sub Function: DRAMC_INIT
+; Description: initialize DRAMC, DDRPHY, and DRAM, but this function doesn't initialize EMI
+; =========================================================================================
+DRAMC_INIT:
+ ; =ACTIM0=
+ D.S &BASE_ADDR_DRAMC+0x0000 %LE %LONG 0x44584493
+ ; =CONF1=
+ ; [18][5][3] no use in TK6291
+ ; [9:8]MTYPE, DRAM column address width, 2'b01 (9-bit) -> 2'b10 (10-bit)
+ ; TODO: [AC Timing] 0x00048683
+ D.S &BASE_ADDR_DRAMC+0x0004 %LE %LONG 0xF0008681 ; 0xF0008481
+ ; =R0DELDLY=
+ D.S &BASE_ADDR_DRAMC+0x0018 %LE %LONG 0x10101010
+ ; =R1DELDLY=
+ ; [30:24][22:16][14:8][6:0] DQS3/2/1/0 input delay
+ D.S &BASE_ADDR_DRAMC+0x001C %LE %LONG 0x12121212
+ ; =DLLCONF=
+ D.S &BASE_ADDR_DRAMC+0x0028 %LE %LONG 0x50000000
+ ; =TEST2_3=
+ ; [23] DQSICALI_NEW=0, using original dqs calibration
+ ; [7] TESTAUDPAT=0, ISI pattern can be set by TEST2_PAT0
+ D.S &BASE_ADDR_DRAMC+0x0044 %LE %LONG 0xBF080000
+ ; =TEST2_4=
+ D.S &BASE_ADDR_DRAMC+0x0048 %LE %LONG 0x1601110D
+ ; =DDR2CTL=
+ D.S &BASE_ADDR_DRAMC+0x007C %LE %LONG 0x00003201
+ ; =MISC=
+ ; [23:21]: PHYRXDSL_PIPE3~1 are pipe stage selection for RDATA and RDSEL
+ ; DATLAT_DSEL = DATLAT - 2*2 when enabling two top pipe (for TK6291)
+ D.S &BASE_ADDR_DRAMC+0x0080 %LE %LONG 0x00AC08A0
+ ; =ZQCS=
+ ; [15:8]: ZQCSAD, [7:0]: ZQCSOP
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x0084) & ~0x0000FFFF
+ ®_val=®_val|0x00000A56
+ D.S &BASE_ADDR_DRAMC+0x0084 %LE %LONG ®_val
+ ; =CLK1DELAY=
+ ; [23]: PHYPIPE3EN, [22]: PHYPIPE2EN, [21]: PHYPIPE1EN
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x008C) & ~0x00E00000
+ ®_val=®_val|0x00A00000
+ D.S &BASE_ADDR_DRAMC+0x008C %LE %LONG ®_val
+ ; =R0DQSIEN=
+ ; Gating Window for Rank0
+ D.S &BASE_ADDR_DRAMC+0x0094 %LE %LONG 0x31313131
+ ; =MCKDLY=
+ ; [23]: WODT has no load (useless)
+ ; [21]: DRAMEN has no load (useless)
+ ; [11:10] DQIENQKEND: DQ/DQS input enable window is larger than 6582. [11:10]=2'b00 => dle counter is 5'1f. =Others => dle counter is DATLAT-[11:10]+2
+ ; [4] DQIENLATEBEGIN, disable early begin, better for power saving
+ ; TODO: [20]: It is used for BST(Bus Termination), but TK6291 doesn't support the feature
+ D.S &BASE_ADDR_DRAMC+0x00D8 %LE %LONG 0x40500510
+ ; =DQSCTL1=
+ ; [27:24]: DQSINCTL, DQS input range control by M_CK
+ ; [23:12][11:0]: DQS3CTL/DQS2CTL, control by DDRPHY (useless)
+ D.S &BASE_ADDR_DRAMC+0x00E0 %LE %LONG 0x12200200
+ ; =GDDR3CTL1=
+ ; [24]: 8BKEN=1, 8-bank device enable
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x00F4) | 0x01000000
+ D.S &BASE_ADDR_DRAMC+0x00F4 %LE %LONG ®_val
+ ; [28]: PHYSYNCM=1, SYNC MODE using inverted PHY_M_CK
+ ®_val=DATA.LONG(&BASE_ADDR_DDRPHY+0x00F4) | 0x10000000
+ D.S &BASE_ADDR_DDRPHY+0x00F4 %LE %LONG ®_val
+ ; =MISCTL0=
+ ; [31]: REFP_ARB_EN2: per-bank refresh arbitration mask2
+ ; [30:28]: TXP, tXP Timing setting
+ ; [27] EMIPREEN: Enable advanced precharge function by EMI side-band signals, but TK6291 didn't support this feature.
+ ; [26] REFP_ARB_EN: per-bank refresh blocks in EMI arbitration
+ ; [25] REFA_ARB_EN: all-bank refresh blocks in EMI arbitration
+ ; [24] PBC_ARB_EN: block page-miss requests in EMI arbitration
+ ; [21]: REFA_ARB_EN2: all bank refresh arbtration mask enable option
+ D.S &BASE_ADDR_DRAMC+0x00FC %LE %LONG 0x81080000
+ ; [17]: INTLBT=0, IO internal loop back (useless for TK6291)
+ ; [16]: RXLPDDR2=0, IO voltage operating condition = {0:1.2V, 1:1.8V}
+ ®_val=DATA.LONG(&BASE_ADDR_DDRPHY+0x00FC) & ~0x00030000
+ D.S &BASE_ADDR_DDRPHY+0x00FC %LE %LONG ®_val
+ ; =OCDK=
+ ; [24]: DRVREF=1, drving change only when refresh cycle
+ ; [15]: DRDELSWEN=1, enable DQS input delay switching for different ranks
+ ; [8]: AUTOCALDRV=1, OCD calibration enable
+ ; [7:0]: AUTOKCNT, auto calibration counter
+ ; =RKCFG=
+ ; [7]: per-bank refresh for LPDDR2&3
+ ; TODO: [AC Timing] 0x004135C0
+ D.S &BASE_ADDR_DRAMC+0x0110 %LE %LONG 0x004121C0
+ ; =DQSCTL2=
+ D.S &BASE_ADDR_DRAMC+0x0118 %LE %LONG 0x00000002
+ ; =DQSGCTL=
+ ; [7:0] Old gating window course tune
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x0124) & ~0x000000FF
+ D.S &BASE_ADDR_DRAMC+0x0124 %LE %LONG ®_val
+ ; [31]: NEWDQSG_SEL, [30]:DQSGDUALP
+ ®_val=DATA.LONG(&BASE_ADDR_DDRPHY+0x0124) | 0xC0000000
+ D.S &BASE_ADDR_DDRPHY+0x0124 %LE %LONG ®_val
+ ; =CLKCTRL=
+ ; [29]: CLK_EN_1, [28]: CLK_EN_0
+ ; TODO: we should only enable one CLK for TK6291
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x0130) | 0x30000000
+ D.S &BASE_ADDR_DRAMC+0x0130 %LE %LONG ®_val
+ ; =ARBCTL0=
+ ; [7:0]: maximum pending number to block the arbitration
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x0168) & ~0x000000FF
+ ®_val=®_val|0x00000080
+ D.S &BASE_ADDR_DRAMC+0x0168 %LE %LONG ®_val
+ ; =DQSCAL0=
+ ; [31]: DQS strobe calibration enable
+ ; [30]: Update tracking gating value to 2 ranks simultaneously
+ ; [15]: Rank0 DQS strobe calibration high-limit enable
+ ; [14:8]: Rank0 DQS strobe calibration high-limit value
+ ; [7]: Rank0 DQS strobe calibration low-limit enable
+ ; [6:0]: Rank0 DQS strobe calibration low-limit value
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x01C0) & ~0xC000FFFF
+ ®_val=®_val | 0x80000000
+ D.S &BASE_ADDR_DRAMC+0x01C0 %LE %LONG ®_val
+ ; =MEMSYSPIPE_CGF_CTL=
+ ; [2]: PIPE_CFG_EN, [0]: DRAMC_CFG_EN
+ ; PIPE_CGF_ON=0 (timing issue) EMI_CGF_ON=0(Gated function is already designed in EMI) DRAMC_CGF_ON=1
+ D.S &BASE_ADDR_MEMSYSAOREG_MISC+0x5000 %LE %LONG 0x00000001
+ ; =DRAMC_PD_CTRL=
+ ; [24] REFFRERUN, using freerun clock to count refresh period
+ ; [23:16] REFCNT_FR_CLK, refresh period based on DRAMC freerun clock cycles
+ ; [15:8] TXREFCNT, tXSR
+ IF (&CHIP_VER==0)
+ (
+ D.S &BASE_ADDR_DRAMC+0x01DC %LE %LONG 0xC2002340
+ )
+ ELSE
+ (
+ D.S &BASE_ADDR_DRAMC+0x01DC %LE %LONG 0xC3002340
+ )
+ ; =LPDDR2_3=
+ ; TODO: should set to 0x10000000, not 0x3600_0000?
+ ; [31]: DRAM address decode by DRAMC
+ ; [28]: LPDDR2 enable
+ ; [27]: enable register output data by DRAMC
+ D.S &BASE_ADDR_DRAMC+0x01E0 %LE %LONG 0x36000000
+ ; [30]: Select IO O1 as output
+ ; [29&25:24&22:0]: DDR mode for pins
+ ; [26]: fast IO output enable
+ D.S &BASE_ADDR_DDRPHY+0x01E0 %LE %LONG 0x2601FFFF
+ ; =ACTIM1=
+ D.S &BASE_ADDR_DRAMC+0x01E8 %LE %LONG 0x81000510
+ ; =PERFCTL0=
+ ; [0] dual schedulers
+ D.S &BASE_ADDR_DRAMC+0x01EC %LE %LONG 0x0010CF11
+ ; TODO: AC_DERATING [0x01F0]
+ ; =RRRATE_CTL=, =MRR_CTL=
+ IF (&CHIP_VER==0) ; Or LPDDR3
+ (
+ D.S &BASE_ADDR_DRAMC+0x01F4 %LE %LONG 0x03020100
+ D.S &BASE_ADDR_DRAMC+0x01Fc %LE %LONG 0x07060504
+ )
+ ELSE
+ (
+ D.S &BASE_ADDR_DRAMC+0x01F4 %LE %LONG 0x02030100
+ D.S &BASE_ADDR_DRAMC+0x01Fc %LE %LONG 0x04060705
+ )
+ ; =AC_TIME_05T=
+ D.S &BASE_ADDR_DRAMC+0x01F8 %LE %LONG 0x04002600
+ ; =LPDDR2_4=
+ ; clock 1x phase selection
+ D.S &BASE_ADDR_DDRPHY+0x023C %LE %LONG 0x2201FFFF
+ ; =SELPH1=
+ ; TX 1x clock delay for CS1, RAS, CAS, WE, RESET, ODT, CKE, and CS
+ D.S &BASE_ADDR_DRAMC+0x0400 %LE %LONG 0x00000000
+ ; =SELPH2=
+ ; TX 1x clock delay for CKE1, DQSGATE_P1, CMD, DQSGATE, BA[2:0]
+ IF (&CHIP_VER==0)
+ (
+ D.S &BASE_ADDR_DRAMC+0x0404 %LE %LONG 0x00302000
+ )
+ ELSE
+ (
+ D.S &BASE_ADDR_DRAMC+0x0404 %LE %LONG 0x00101000
+ )
+ ; =SELPH3=
+ ; TX 1x clock delay for RA[7:0]
+ D.S &BASE_ADDR_DRAMC+0x0408 %LE %LONG 0x00000000
+ ; =SELPH4=
+ ; TX 1x clock delay for RA[15:8]
+ D.S &BASE_ADDR_DRAMC+0x040C %LE %LONG 0x00000000
+ ; =SELPH5=
+ ; TX 0.5's 2x clock delay for CKE1, DQSGATE_P1, DQSGATE, BA[2:0], CS1, RAS, CAS, WE, RESET, ODT, CKE, CS
+ IF (&CHIP_VER==0)
+ (
+ D.S &BASE_ADDR_DRAMC+0x0410 %LE %LONG 0x00955555
+ )
+ ELSE
+ (
+ D.S &BASE_ADDR_DRAMC+0x0410 %LE %LONG 0x57755555
+ )
+ ; TODO: SELPH6 [0x0414]
+ ; =SELPH6_1=
+ ; TX 1x clock delay for DQSGATE_P1 and DQSGATE of rank1
+ ; TX 0.5's 2x clock delay for DQSGATE_P1 and DQSGATE of rank1
+ D.S &BASE_ADDR_DRAMC+0x0418 %LE %LONG 0x00000228
+ ; =SELPH7=
+ ; TX 1x clock delay for DQ byte output enable[3:0] and DQ byte[3:0]
+ D.S &BASE_ADDR_DRAMC+0x041C %LE %LONG 0x11111111
+ ; =SELPH8=
+ ; TX 1x clock delay for DQM byte output enable[3:0] and DQM byte[3:0]
+ D.S &BASE_ADDR_DRAMC+0x0420 %LE %LONG 0x11111111
+ ; =SELPH9=
+ ; TX 1x clock delay for DQS byte output enable[3:0] and DQS byte[3:0]
+ D.S &BASE_ADDR_DRAMC+0x0424 %LE %LONG 0x11111111
+ ; =SELPH10=
+ ; TX 0.5's 2x clock delay for DQM output enable[3:0], DQ byte output enable[3:0], DQM[3:0], and DQ byte[3:0]
+ ; TODO: why we let output enable extra more 1.5 T not 0.5 DRAM clock?
+ D.S &BASE_ADDR_DRAMC+0x0428 %LE %LONG 0x0000FFFF
+ ; =SELPH11=
+ ; TX 0.5's 2x clock delay for DQS output enable[3:0] and DQS[3:0]
+ ; TODO: why we let output enable extra more 1.5 T not 0.5 DRAM clock?
+ D.S &BASE_ADDR_DRAMC+0x042C %LE %LONG 0x000000FF
+ ; TODO: offset 0x430~0x438, Don't we need to set clock 05x phase selection?
+ ; =SELPH12=
+ ; clock 05x phase selection for CLK, DQSGATE, DQS[3:0], and DQM[3:0]
+ ; clock 1x phase selection for DQS[3:0], DQM[3:0], CLK, and DQSGATE
+ D.S &BASE_ADDR_DDRPHY+0x0430 %LE %LONG 0x10F010F0
+ ; =SELPH13=
+ ; clock 1x phase selection for DQ[31:0]
+ D.S &BASE_ADDR_DDRPHY+0x0434 %LE %LONG 0xFFFFFFFF
+ ; =SELPH14=
+ ; clock 05x phase selection for DQ[31:0]
+ D.S &BASE_ADDR_DDRPHY+0x0438 %LE %LONG 0xFFFFFFFF
+ ; =SELPH15=
+ ; OCV (On-Chip Variation that affect by PVT). It is removed in TK6291.
+ ; OCV mode for DQSGATE, DQS[3:0], DQ[31:0], CLK, and CA
+ D.S &BASE_ADDR_DDRPHY+0x043C %LE %LONG 0x0000001F
+ ; =MEMPLL_DIVIDER=
+ ; DDRPHY reset flow for 1X clock phase sync
+ ; [5]: MEMCLKENB, SW control. It is used for MEMPLL initialization. After initialization, CLKENB is controlled by HW mode.
+ ; [4]: RG_DMSS_PWDB, ALLCLK_EN. It is used for gated MEMPLL output during initialization. (=1 after initilization)
+ ; [0]: MEMCLKENB_SEL, memory clock sync enable bar selection, selection for [5] (=1 select[5])
+ IF (&CHIP_VER!=0)
+ (
+ ®_val=DATA.LONG(&BASE_ADDR_DDRPHY+0x0640) | 0x00000031
+ D.S &BASE_ADDR_DDRPHY+0x0640 %LE %LONG ®_val
+ )
+ ; TODO: wait 500 sys_clock equal to 1.87us?
+ WAIT 2.us
+ GOSUB LPDDR2_INIT
+ IF (&CHIP_VER==0)
+ (
+ ; =CONF2=
+ D.S &BASE_ADDR_DRAMC+0x0008 %LE %LONG 0x0000631F
+ ; =DRAMC_PD_CTRL=
+ ;®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x01DC)&~0x00FF0000
+ ;®_val=®_val|0x00350000
+ ;D.S &BASE_ADDR_DRAMC+0x01DC %LE %LONG ®_val
+ )
+ ELSE
+ (
+ ; =CONF2=
+ ; [23] FREBW_FREN, tREFBW use xtal clock counter enable
+ ; [17:8] FREBW_FR, 6720ns/(XTALFR_clock)-1
+ ; [7:0] REFCNT: AC Timing Calculation is 0x3F, but ESL use 0x3B
+ ; TODO: [AC Timing] 0x0000003F
+ D.S &BASE_ADDR_DRAMC+0x0008 %LE %LONG 0x03806D3B
+ ; =DRAMC_PD_CTRL=
+ ; [23:16] REFCNT_FR_CLK, refresh period based on DRAMC freerun clock cycles
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x01DC) & ~0x00FF0000
+ ®_val=®_val | 0x00640000
+ D.S &BASE_ADDR_DRAMC+0x01DC %LE %LONG ®_val
+ )
+ RETURN
+
+; =========================================================================================
+; Sub Function: EMI_INIT
+; =========================================================================================
+EMI_INIT:
+ ; =EMI_CONA=
+ ; [27]: RANK_POS=0, {rank,row,bank,col}
+ ; [17]: DUAL_RANK_EN=0
+ ; [15:14][13:12]: ROW2ND=1,ROW=1, 14-bit row address
+ ; [7:6][5:4]: COL2ND=1,COL=1, 10-bit column address
+ ; [1]: DW32_EN=1, 32-bit data bus
+ D.S &BASE_ADDR_EMI+0x0000 %LE %LONG 0x00005052
+ ; =EMI_ARBI=
+ D.S &BASE_ADDR_EMI+0x0140 %LE %LONG 0x20406188
+ ; =EMI_ARBI_2ND=
+ D.S &BASE_ADDR_EMI+0x0144 %LE %LONG 0x20406188
+ ; =EMI_ARBD=
+ D.S &BASE_ADDR_EMI+0x0118 %LE %LONG 0x0700704C
+ ; =EMI_ARBE=
+ D.S &BASE_ADDR_EMI+0x0120 %LE %LONG 0x40407068
+ ; =EMI_ARBG=
+ D.S &BASE_ADDR_EMI+0x0130 %LE %LONG 0xFFFF7045
+ ; =EMI_ARBH=
+ D.S &BASE_ADDR_EMI+0x0138 %LE %LONG 0xA0A07047
+ ; TODO: CSR is not defined?
+ D.S &BASE_ADDR_EMI+0x0040 %LE %LONG 0x80808807
+ ; =EMI_ARBJ=
+ ; TODO: it is not defined in CSRv0.9
+ D.S &BASE_ADDR_EMI+0x0148 %LE %LONG 0x9719595E
+ ; =EMI_ARBJ_2ND=
+ ; TODO: it is not defined in CSRv0.9
+ D.S &BASE_ADDR_EMI+0x014C %LE %LONG 0x9719595E
+ ; =EMI_TEST_D=
+ D.S &BASE_ADDR_EMI+0x00F8 %LE %LONG 0x00000000
+ ; =EMI_BMEN=
+ ; TODO: why do we need to enable BUS_MON_EN for DRAM Init?
+ D.S &BASE_ADDR_EMI+0x0400 %LE %LONG 0x00FF0001
+ ; =EMI_CONB=
+ D.S &BASE_ADDR_EMI+0x0008 %LE %LONG 0x17283544
+ ; =EMI_CONC=
+ D.S &BASE_ADDR_EMI+0x0010 %LE %LONG 0x0A1A0B1A
+ ; TODO: offset 0x18 is not defined in CSR.
+ D.S &BASE_ADDR_EMI+0x0018 %LE %LONG 0x00000000
+ ; =EMI_CONE=
+ ; TODO: it is not defined in CSRv0.9
+ D.S &BASE_ADDR_EMI+0x0020 %LE %LONG 0xFFFF0848
+ ; =EMI_CONG=
+ D.S &BASE_ADDR_EMI+0x0030 %LE %LONG 0x2B2B2A38
+ ; =EMI_CONH=
+ D.S &BASE_ADDR_EMI+0x0038 %LE %LONG 0x00000000
+ ; =EMI_SLCT=
+ ; TODO: Why do we enable [17]:M1_LLAT_EN?
+ D.S &BASE_ADDR_EMI+0x0158 %LE %LONG 0xFF02FF00
+ ; =EMI_MDCT=
+ ; TODO: why don't we enable [14]:MDMCU_SBR_EN and [12]:ULTRA_SBR_EN?
+ D.S &BASE_ADDR_EMI+0x0078 %LE %LONG 0x002F0C17
+ ; TODO: it is not defined in CSR.
+ D.S &BASE_ADDR_EMI+0x015C %LE %LONG 0x80030303
+ ; =EMI_EMI_ARBK=
+ ; TODO: it only defines [23:16] in CSRv0.9
+ D.S &BASE_ADDR_EMI+0x0150 %LE %LONG 0x64F3FC79
+ ; =EMI_ARBK_2ND=
+ ; TODO: it is not defined in CSRv0.9
+ D.S &BASE_ADDR_EMI+0x0154 %LE %LONG 0x64F3FC79
+ ; =EMI_TESTC=
+ ; TODO: it only enables [16:8] in CSRv0.9
+ D.S &BASE_ADDR_EMI+0x00F0 %LE %LONG 0x38470000
+ ; =EMI_TESTB=
+ ; TODO: it didn't define [2:0] in CSRv0.9
+ D.S &BASE_ADDR_EMI+0x00E8 %LE %LONG 0x00020027
+ // Enable slave error
+ D.S &BASE_ADDR_EMI+0x01C0 %LE %LONG 0x10000000
+ D.S &BASE_ADDR_EMI+0x01C8 %LE %LONG 0x10000000
+ D.S &BASE_ADDR_EMI+0x01D0 %LE %LONG 0x10000000
+ D.S &BASE_ADDR_EMI+0x0200 %LE %LONG 0x10000000
+ D.S &BASE_ADDR_EMI+0x02C0 %LE %LONG 0x10000000
+ D.S &BASE_ADDR_EMI+0x02C8 %LE %LONG 0x10000000
+ D.S &BASE_ADDR_EMI+0x02D0 %LE %LONG 0x10000000
+ D.S &BASE_ADDR_EMI+0x0300 %LE %LONG 0x10000000
+ ; =EMI_CONM=
+ ; [10]: EMI_ENABLE=1
+ D.S &BASE_ADDR_EMI+0x0060 %LE %LONG 0x000006B8
+ ; =EMI_ARBP=
+ ; EBM_MODE enable
+ D.S &BASE_ADDR_EMI+0x0A20 %LE %LONG 0x00010000
+ RETURN
+
+; =========================================================================================
+; Sub Function: LPDDR2_INIT
+; =========================================================================================
+LPDDR2_INIT:
+ ; =PADCTL4=
+ ; [2]: CKE always on, [0]: CKE control by controller
+ ; CKE always on
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x00E4) | 0x00000005
+ D.S &BASE_ADDR_DRAMC+0x00E4 %LE %LONG ®_val
+ WAIT 200.us
+ ; LPDDR2 MRW RESET
+ GOSUB DRAMC_MRW 0x0000003F
+ WAIT 10.us
+ ; ZQ Init
+ GOSUB DRAMC_MRW 0x00FF000A
+ ; TODO: wait 1us after ZQ Initialization
+ WAIT 1.us
+ ; MRW MR1 => BL8, Sequential, Wrap, nWR=8
+ GOSUB DRAMC_MRW 0x00C30001
+ ; MRW MR2 => RL=8 and WL=4 for DDR1066
+ GOSUB DRAMC_MRW 0x00060002
+ ; MRW MR3 => 40-ohm typical
+ GOSUB DRAMC_MRW 0x00020003
+ ; =PADCTL4=
+ ; [2]: CKE always on, [0]: CKE control by controller
+ ; CKE is controlled by hardware
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x00E4) & ~0x00000004
+ D.S &BASE_ADDR_DRAMC+0x00E4 %LE %LONG ®_val
+ RETURN
+
+; =========================================================================================
+; Sub Function: DRAMC_MRW
+; Description: DRAMC Mode Register Write
+; argument:
+; @mrs mode register write value
+; =========================================================================================
+DRAMC_MRW:
+ ENTRY &mrs
+ LOCAL &spcmd
+ &spcmd=0x00000001
+ D.S &BASE_ADDR_DRAMC+0x0088 %LE %LONG &mrs
+ D.S &BASE_ADDR_DRAMC+0x01E4 %LE %LONG &spcmd
+ WAIT (DATA.LONG(&BASE_ADDR_DRAMC+0x03B8)&(&spcmd))==&spcmd
+ D.S &BASE_ADDR_DRAMC+0x01E4 %LE %LONG 0x00000000
+ WAIT (DATA.LONG(&BASE_ADDR_DRAMC+0x03B8)&(&spcmd))==0x00000000
+ RETURN
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6295M/MT6295M_NFI_Erase_Flash.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6295M/MT6295M_NFI_Erase_Flash.cmm
new file mode 100755
index 0000000..0f36463
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6295M/MT6295M_NFI_Erase_Flash.cmm
@@ -0,0 +1,224 @@
+
+system.mode attach
+
+;; Mo port configuration
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+
+;;Disable AP & MD Watch Dog
+&BASE_MADDR_MDRGU=0xA00F0000
+&BASE_MADDR_APRGU=0xC3670000
+&temp=data.long(&BASE_MADDR_MDRGU+0x0100)
+&temp=0x55000000 | &temp & (~0x3)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG &temp
+&temp=data.long(&BASE_MADDR_APRGU+0x0100)
+&temp=0x55000000 | &temp & (~0x1)
+D.S &BASE_MADDR_APRGU+0x0100 %LE %LONG &temp
+
+;;===================Below Porting from TK6293_NFI_ReadID_Prepare.cmm========================================
+; Step1:Reset NFI&Flush FIFO
+D.S 0xC141000C %LE %LONG 0x3
+wait 1.ms
+
+; Step2:Check FIFO is Flushed
+&check=data.long(0xC1410048)&(0x001F)
+IF &check!=0x0
+(
+ PRINT "Check FIFO is Flushed 01 Failed! Result: &check"
+ ENDDO
+)
+&check=data.long(0xC1410048)&(0x1F00)
+IF &check!=0x0
+(
+ PRINT "Check FIFO is Flushed 02 Failed! Result: &check"
+ ENDDO
+)
+
+; Step3:Disable BM
+;D.S &TYPE:0x9350000C %LE %LONG 0x0
+
+; Step4:Send Request for NLI Grant
+D.S 0xC141014C %LE %LONG 0x1
+WAIT 100.us
+&check=DATA.LONG(0xC141014C)&(0x0003)
+IF &check!=0x0003
+(
+ PRINT "Send Request for NLI Grant Failed! Result: &check"
+ ENDDO
+)
+
+;Step5:Set safe timing for init
+
+;Step6:Set the operating process(reset) flow of FSM for NFI
+D.S 0xC1410004 %LE %LONG 0x5000
+
+;Step7:Send Reset Command to Nand Flash
+D.S 0xC1410028 %LE %LONG 0xFF
+WAIT 800.us
+
+;Step8:Waiting Reset Done
+&check=DATA.LONG(0xC1410044)
+IF &check!=0x1200
+(
+ PRINT "Waiting Reset Done 1 Failed! Result: &check"
+ ENDDO
+)
+
+;;;Read ID Operation
+
+; Step1:Check FIFO is Flushed
+&check=DATA.LONG(0xC1410048)&(0x001F)
+IF &check!=0x0
+(
+ PRINT "Check FIFO is Flushed 1 Failed! Result: &check"
+ ENDDO
+)
+&check=DATA.LONG(0xC1410048)&(0x1F00)
+IF &check!=0x0
+(
+ PRINT "Check FIFO is Flushed 2 Failed! Result: &check"
+ ENDDO
+)
+
+;Step2:Set Single Read Operation
+D.S 0xC1410004 %LE %LONG 0x2000
+
+;Step3:Send Read ID Command to Nand Flash
+D.S 0xC1410028 %LE %LONG 0x90
+
+;Step4:Set Row Address
+D.S 0xC1410034 %LE %LONG 0x0
+
+;Step5:Set Column Address
+D.S 0xC1410030 %LE %LONG 0x0
+
+;Step6:Set Address Number of Byte
+D.S 0xC141002C %LE %LONG 0x1
+
+;Step7:Start Single Read
+D.S 0xC141000C %LE %LONG 0x10
+WAIT 800.us
+
+;Step8:Release NLI Grant
+D.S 0xC141014C %LE %LONG 0x0
+
+&check=DATA.LONG(0xC141012C)
+&check1=DATA.LONG(0xC1410130)
+PRINT "ID Info: &check, &check1"
+
+;;==============Above Porting from TK6293_NFI_ReadID_Prepare.cmm=============================================
+
+
+
+;;===================Below Porting from TK6293_NFI_Erase_Block_Prepare.cmm========================================
+
+;;;1st Erase and Read Status*******************************************
+;;;Reset Operation before 1st Erase
+; Step1:Reset NFI&Flush FIFO
+D.S 0xC141000C %LE %LONG 0x3
+
+WAIT 100.us
+
+; Step2:Check FIFO is Flushed
+&check=DATA.LONG(0xC1410048)&(0x001F)
+IF &check!=0x0
+(
+ PRINT "Check FIFO is Flushed 1 Failed! Result: &check"
+ ENDDO
+)
+&check=DATA.LONG(0xC1410048)&(0x1F00)
+IF &check!=0x0
+(
+ PRINT "Check FIFO is Flushed 2 Failed! Result: &check"
+ ENDDO
+)
+
+; Step3:Disable BM
+;D.S SD:0x9350000C %LE %LONG 0x0
+
+; Step5:Send Request for NLI Grant
+D.S 0xC141014C %LE %LONG 0x1
+WAIT 100.us
+&check=DATA.LONG(0xC141014C)&(0x0003)
+IF &check!=0x0003
+(
+ PRINT "Send Request for NLI Grant Failed! Result: &check"
+ ENDDO
+)
+
+;Step6:Set the operating process(reset) flow of FSM for NFI
+D.S 0xC1410004 %LE %LONG 0x5000
+
+;Step7:Send Reset Command to Nand Flash
+D.S 0xC1410028 %LE %LONG 0xFF
+WAIT 800.us
+
+;Step8:Waiting Reset Done
+&check=DATA.LONG(0xC1410044)
+IF &check!=0x1200
+(
+ PRINT "Waiting Reset Done 1 Failed! Result: &check"
+ ENDDO
+)
+
+;;;Erase Operation
+PRINT "reset done and start 1st Erase Operation"
+
+; Step1:Check FIFO is Flushed
+&check=DATA.LONG(0xC1410048)&(0x001F)
+IF &check!=0x0
+(
+ PRINT "Check FIFO is Flushed 1 Failed! Result: &check"
+ ENDDO
+)
+&check=DATA.LONG(0xC1410048)&(0x1F00)
+IF &check!=0x0
+(
+ PRINT "Check FIFO is Flushed 2 Failed! Result: &check"
+ ENDDO
+)
+
+;Step2:Set Erase Operation
+D.S 0xC1410004 %LE %LONG 0x4000
+
+;Step4:Send Erase Command to Nand Flash
+D.S 0xC1410028 %LE %LONG 0x60
+
+;Step5:Wait NFI Core is not in command State
+WAIT 500.us
+
+;Step6:Set Row Address,0x40 pages per block
+D.S 0xC1410034 %LE %LONG 0x00000
+
+;Step7:Set Row Address Cycle
+D.S 0xC141002C %LE %LONG 0x30
+
+;Step8:Wait NFI Core is not in address Mode
+WAIT 500.us
+
+&check=DATA.LONG(0xC1410044)&(0x0002)
+&check1=DATA.LONG(0xC1410044)
+
+;Step9:Set Erase command Confirm
+D.S 0xC1410028 %LE %LONG 0xD0
+
+;Step10:Wait NFI Erase Done
+WAIT 100000.us
+
+;Step11:Release NLI Grant
+D.S 0xC141014C %LE %LONG 0x0
+
+IF &check!=0x0
+(
+ PRINT "Check NIF Core is not in address Mode Fail! Result: &check"
+ ENDDO
+)
+
+PRINT "1st Erase Operation Done"
+
+;;==============Above Porting from TK6293_NFI_Erase_Block_Prepare.cmm=============================================
+
+ENDDO
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6295M/coretracer/config/easyLoader/load_dsp.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6295M/coretracer/config/easyLoader/load_dsp.py
new file mode 100755
index 0000000..86e47fa
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6295M/coretracer/config/easyLoader/load_dsp.py
@@ -0,0 +1,106 @@
+#from imgtec import codescape
+import sys
+import time
+import os
+import gdb
+import binascii
+import Tkinter, tkFileDialog
+
+app = None
+dsp_header = 0x0
+dsp_magic = "4d4d4d01"
+
+# load dsp bin file
+def load_dsp_bin(dsp_path):
+ global dsp_header
+ time_str = time.time()
+ print "=== Start load dsp bin ==="
+ print "Dsp bin path: " + dsp_path
+ if(os.path.exists(dsp_path) == False):
+ print "DSP bin doesn't exist: %s" %(dsp_path)
+ print "[Error] Load DSP bin failed"
+ return
+ else:
+ with open(dsp_path, "rb") as dsp_bin:
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print "No header detected, continue"
+ else:
+ dsp_header = 0x200
+ dsp_bin.seek(dsp_header, os.SEEK_SET)
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print "Header detected, skip first 512B"
+ else:
+ print "DSP header detected at neither 0x0 nor 0x200"
+ print "Please check the bin is legal!"
+ print "[Error] Load DSP bin failed"
+ return
+ gdb_cmd='thread 1'
+ gdb.execute(gdb_cmd)
+ ## a) need parsing: 0x13a0000 <dsp_bin_ro>
+ ##symbol_name='&dsp_bin_ro'
+ ##dsp_addr = gdb.parse_and_eval(symbol_name)
+ ## b) need parsing: $3 = 0x13a0000
+ ##gdb_cmd='p/x &dsp_bin_ro'
+ ##dsp_addr = gdb.execute(gdb_cmd, False, True)
+ symbol_name='dsp_bin_ro'
+ dsp_addr = gdb.parse_and_eval(symbol_name)
+ dsp_addr = str(dsp_addr.address).split(" ")
+ dsp_addr = int(dsp_addr[0], 16) - dsp_header
+ print hex(dsp_addr)
+ gdb_cmd = 'monitor mips32 fastchannel 0 1'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'set $cdmmbase=0x1fc1407'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'set *0x1fc100d4=0x02030202'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = " ".join(['restore', dsp_path, 'binary', hex(dsp_addr), hex(dsp_header)])
+ print gdb_cmd
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'set *0x1fc100d4=0x02020202'
+ gdb.execute(gdb_cmd)
+ time_end = time.time()
+ print("loading dsp is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+
+class gui_tk(Tkinter.Tk):
+ def __init__(self, parent):
+ Tkinter.Tk.__init__(self, parent)
+ elf_path = ""
+ dsp_path = ""
+ dsp_addr = ""
+ self.file_opt = options = {}
+ options['title'] = 'Choose a file'
+ self.parent = parent
+ self.initialize()
+
+ def initialize(self):
+ self.grid()
+
+ dsp_button = Tkinter.Button(self, text=u"Load DSP bin =>", command=self.dsp_OnButtonClick)
+ dsp_button.grid(column=0, row=4, sticky='W')
+
+ def dsp_OnButtonClick(self):
+ dsp_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(dsp_path) > 0:
+ print "You chose %s" % dsp_path
+ load_dsp_bin(dsp_path)
+ self.quit()
+
+ def quit(self):
+ global app
+ print "=== Close Easy Loader ==="
+ app.destroy()
+
+def load_dsp_gui():
+ print "=== Start Easy Loader ==="
+ global app
+ app = gui_tk(None)
+ app.title('Easy Loader')
+ app.mainloop()
+
+
+if __name__ == "__main__":
+ load_dsp_gui()
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6295M/fpga_emi_init.gdb b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6295M/fpga_emi_init.gdb
new file mode 100755
index 0000000..47bd80c
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6295M/fpga_emi_init.gdb
@@ -0,0 +1,572 @@
+set $CHIP_VER = 0
+set $BASE_ADDR_EMI = 0xC3000000
+set $BASE_ADDR_DRAMC = 0xC3010000
+set $BASE_ADDR_DDRPHY = 0xC3020000
+set $BASE_ADDR_MEMSYSAOREG_MISC = 0xC3080000
+set $BASE_ADDR_AP_CLKSW = 0xC3750000
+
+define Delay_f32k
+ set $tgt = *0xa00d0850 + $arg0
+ while *0xa00d0850 <= $tgt
+ end
+end
+
+define DRAM_INIT
+ echo DRAM_INIT ...\n
+ if (*($BASE_ADDR_EMI+0x0060) & 0x00000400) == 0x00000400
+ echo Warning: DRAM has be initialized, why ???\n
+ else
+ # =MEMSYS_PASSWORD=
+ # Unlock MEMSYS Password
+ set *($BASE_ADDR_MEMSYSAOREG_MISC+0x3000) = 0x24541689
+ DRAMC_INIT
+ EMI_INIT
+ MEMSYS_INIT
+ # =MEMSYS_PASSWORD=
+ # Lock MEMSYS Password
+ set *($BASE_ADDR_MEMSYSAOREG_MISC+0x3000) = 0x00000000
+ end
+end
+
+define DRAMC_INIT
+ echo DRAMC_INIT ...\n
+ # =ACTIM0=
+ set *($BASE_ADDR_DRAMC+0x0000) = 0x44584493
+ # =CONF1=
+ # [18][5][3] no use in TK6291
+ # [9:8]MTYPE, DRAM column address width, 2'b01 (9-bit) -> 2'b10 (10-bit)
+ # TODO: [AC Timing] 0x00048683 # 0xF0008481
+ set *($BASE_ADDR_DRAMC+0x0004) = 0xF0008681
+ # =R0DELDLY=
+ set *($BASE_ADDR_DRAMC+0x0018) = 0x10101010
+ # =R1DELDLY=
+ # [30:24][22:16][14:8][6:0] DQS3/2/1/0 input delay
+ set *($BASE_ADDR_DRAMC+0x001C) = 0x12121212
+ # =DLLCONF=
+ set *($BASE_ADDR_DRAMC+0x0028) = 0x50000000
+ # =TEST2_3=
+ # [23] DQSICALI_NEW=0, using original dqs calibration
+ # [7] TESTAUDPAT=0, ISI pattern can be set by TEST2_PAT0
+ set *($BASE_ADDR_DRAMC+0x0044) = 0xBF080000
+ # =TEST2_4=
+ set *($BASE_ADDR_DRAMC+0x0048) = 0x1601110D
+ # =DDR2CTL=
+ set *($BASE_ADDR_DRAMC+0x007C) = 0x00003201
+ # =MISC=
+ # [23:21]: PHYRXDSL_PIPE3~1 are pipe stage selection for RDATA and RDSEL
+ # DATLAT_DSEL = DATLAT - 2*2 when enabling two top pipe (for TK6291)
+ set *($BASE_ADDR_DRAMC+0x0080) = 0x00AC08A0
+ # =ZQCS=
+ # [15:8]: ZQCSAD, [7:0]: ZQCSOP
+ set $reg_val = *($BASE_ADDR_DRAMC+0x0084) & ~0x0000FFFF
+ set $reg_val = $reg_val | 0x00000A56
+ set *($BASE_ADDR_DRAMC+0x0084) = $reg_val
+ # =CLK1DELAY=
+ # [23]: PHYPIPE3EN, [22]: PHYPIPE2EN, [21]: PHYPIPE1EN
+ set $reg_val = *($BASE_ADDR_DRAMC+0x008C) & ~0x00E00000
+ set $reg_val = $reg_val | 0x00A00000
+ set *($BASE_ADDR_DRAMC+0x008C) = $reg_val
+ # =R0DQSIEN=
+ # Gating Window for Rank0
+ set *($BASE_ADDR_DRAMC+0x0094) = 0x31313131
+ # =MCKDLY=
+ # [23]: WODT has no load (useless)
+ # [21]: DRAMEN has no load (useless)
+ # [11:10] DQIENQKEND: DQ/DQS input enable window is larger than 6582. [11:10]=2'b00 => dle counter is 5'1f. =Others => dle counter is DATLAT-[11:10]+2
+ # [4] DQIENLATEBEGIN, disable early begin, better for power saving
+ # TODO: [20]: It is used for BST(Bus Termination), but TK6291 doesn't support the feature
+ set *($BASE_ADDR_DRAMC+0x00D8) = 0x40500510
+ # =DQSCTL1=
+ # [27:24]: DQSINCTL, DQS input range control by M_CK
+ # [23:12][11:0]: DQS3CTL/DQS2CTL, control by DDRPHY (useless)
+ set *($BASE_ADDR_DRAMC+0x00E0) = 0x12200200
+ # =GDDR3CTL1=
+ # [24]: 8BKEN=1, 8-bank device enable
+ set $reg_val = *($BASE_ADDR_DRAMC+0x00F4) | 0x01000000
+ set *($BASE_ADDR_DRAMC+0x00F4) = $reg_val
+ # [28]: PHYSYNCM=1, SYNC MODE using inverted PHY_M_CK
+ set $reg_val = *($BASE_ADDR_DDRPHY+0x00F4) | 0x10000000
+ set *($BASE_ADDR_DDRPHY+0x00F4) = $reg_val
+ # =MISCTL0=
+ # [31]: REFP_ARB_EN2: per-bank refresh arbitration mask2
+ # [30:28]: TXP, tXP Timing setting
+ # [27] EMIPREEN: Enable advanced precharge function by EMI side-band signals, but TK6291 didn't support this feature.
+ # [26] REFP_ARB_EN: per-bank refresh blocks in EMI arbitration
+ # [25] REFA_ARB_EN: all-bank refresh blocks in EMI arbitration
+ # [24] PBC_ARB_EN: block page-miss requests in EMI arbitration
+ # [21]: REFA_ARB_EN2: all bank refresh arbtration mask enable option
+ set *($BASE_ADDR_DRAMC+0x00FC) = 0x81080000
+ # [17]: INTLBT=0, IO internal loop back (useless for TK6291)
+ # [16]: RXLPDDR2=0, IO voltage operating condition = {0:1.2V, 1:1.8V}
+ set $reg_val = *($BASE_ADDR_DDRPHY+0x00FC) & ~0x00030000
+ set *($BASE_ADDR_DDRPHY+0x00FC) = $reg_val
+ # =OCDK=
+ # [24]: DRVREF=1, drving change only when refresh cycle
+ # [15]: DRDELSWEN=1, enable DQS input delay switching for different ranks
+ # [8]: AUTOCALDRV=1, OCD calibration enable
+ # [7:0]: AUTOKCNT, auto calibration counter
+ # =RKCFG=
+ # [7]: per-bank refresh for LPDDR2&3
+ # TODO: [AC Timing] 0x004135C0
+ set *($BASE_ADDR_DRAMC+0x0110) = 0x004121C0
+ # =DQSCTL2=
+ set *($BASE_ADDR_DRAMC+0x0118) = 0x00000002
+ # =DQSGCTL=
+ # [7:0] Old gating window course tune
+ set $reg_val = *($BASE_ADDR_DRAMC+0x0124) & ~0x000000FF
+ set *($BASE_ADDR_DRAMC+0x0124) = $reg_val
+ # [31]: NEWDQSG_SEL, [30]:DQSGDUALP
+ set $reg_val = *($BASE_ADDR_DDRPHY+0x0124) | 0xC0000000
+ set *($BASE_ADDR_DDRPHY+0x0124) = $reg_val
+ # =CLKCTRL=
+ # [29]: CLK_EN_1, [28]: CLK_EN_0
+ # TODO: we should only enable one CLK for TK6291
+ set $reg_val = *($BASE_ADDR_DRAMC+0x0130) | 0x30000000
+ set *($BASE_ADDR_DRAMC+0x0130) = $reg_val
+ # =ARBCTL0=
+ # [7:0]: maximum pending number to block the arbitration
+ set $reg_val = *($BASE_ADDR_DRAMC+0x0168) & ~0x000000FF
+ set $reg_val = $reg_val | 0x00000080
+ set *($BASE_ADDR_DRAMC+0x0168) = $reg_val
+ # =DQSCAL0=
+ # [31]: DQS strobe calibration enable
+ # [30]: Update tracking gating value to 2 ranks simultaneously
+ # [15]: Rank0 DQS strobe calibration high-limit enable
+ # [14:8]: Rank0 DQS strobe calibration high-limit value
+ # [7]: Rank0 DQS strobe calibration low-limit enable
+ # [6:0]: Rank0 DQS strobe calibration low-limit value
+ set $reg_val = *($BASE_ADDR_DRAMC+0x01C0) & ~0xC000FFFF
+ set $reg_val = $reg_val | 0x80000000
+ set *($BASE_ADDR_DRAMC+0x01C0) = $reg_val
+ # =MEMSYSPIPE_CGF_CTL=
+ # [2]: PIPE_CFG_EN, [0]: DRAMC_CFG_EN
+ # PIPE_CGF_ON=0 (timing issue) EMI_CGF_ON=0(Gated function is already designed in EMI) DRAMC_CGF_ON=1
+ set *($BASE_ADDR_MEMSYSAOREG_MISC+0x5000) = 0x00000001
+ # =DRAMC_PD_CTRL=
+ # [24] REFFRERUN, using freerun clock to count refresh period
+ # [23:16] REFCNT_FR_CLK, refresh period based on DRAMC freerun clock cycles
+ # [15:8] TXREFCNT, tXSR
+ if $CHIP_VER == 0
+ set *($BASE_ADDR_DRAMC+0x01DC) = 0xC2002340
+ else
+ set *($BASE_ADDR_DRAMC+0x01DC) = 0xC3002340
+ end
+ # =LPDDR2_3=
+ # TODO: should set to 0x10000000, not 0x3600_0000?
+ # [31]: DRAM address decode by DRAMC
+ # [28]: LPDDR2 enable
+ # [27]: enable register output data by DRAMC
+ set *($BASE_ADDR_DRAMC+0x01E0) = 0x36000000
+ # [30]: Select IO O1 as output
+ # [29&25:24&22:0]: DDR mode for pins
+ # [26]: fast IO output enable
+ set *($BASE_ADDR_DDRPHY+0x01E0) = 0x2601FFFF
+ # =ACTIM1=
+ set *($BASE_ADDR_DRAMC+0x01E8) = 0x81000510
+ # =PERFCTL0=
+ # [0] dual schedulers
+ set *($BASE_ADDR_DRAMC+0x01EC) = 0x0010CF11
+ # TODO: AC_DERATING [0x01F0]
+ # =RRRATE_CTL=, =MRR_CTL= # Or LPDDR3
+ if $CHIP_VER == 0
+ set *($BASE_ADDR_DRAMC+0x01F4) = 0x03020100
+ set *($BASE_ADDR_DRAMC+0x01Fc) = 0x07060504
+ else
+ set *($BASE_ADDR_DRAMC+0x01F4) = 0x02030100
+ set *($BASE_ADDR_DRAMC+0x01Fc) = 0x04060705
+ end
+ # =AC_TIME_05T=
+ set *($BASE_ADDR_DRAMC+0x01F8) = 0x04002600
+ # =LPDDR2_4=
+ # clock 1x phase selection
+ set *($BASE_ADDR_DDRPHY+0x023C) = 0x2201FFFF
+ # =SELPH1=
+ # TX 1x clock delay for CS1, RAS, CAS, WE, RESET, ODT, CKE, and CS
+ set *($BASE_ADDR_DRAMC+0x0400) = 0x00000000
+ # =SELPH2=
+ # TX 1x clock delay for CKE1, DQSGATE_P1, CMD, DQSGATE, BA[2:0]
+ if $CHIP_VER == 0
+ set *($BASE_ADDR_DRAMC+0x0404) = 0x00302000
+ else
+ set *($BASE_ADDR_DRAMC+0x0404) = 0x00101000
+ end
+ # =SELPH3=
+ # TX 1x clock delay for RA[7:0]
+ set *($BASE_ADDR_DRAMC+0x0408) = 0x00000000
+ # =SELPH4=
+ # TX 1x clock delay for RA[15:8]
+ set *($BASE_ADDR_DRAMC+0x040C) = 0x00000000
+ # =SELPH5=
+ # TX 0.5's 2x clock delay for CKE1, DQSGATE_P1, DQSGATE, BA[2:0], CS1, RAS, CAS, WE, RESET, ODT, CKE, CS
+ if $CHIP_VER == 0
+ set *($BASE_ADDR_DRAMC+0x0410) = 0x00955555
+ else
+ set *($BASE_ADDR_DRAMC+0x0410) = 0x57755555
+ end
+ # TODO: SELPH6 [0x0414]
+ # =SELPH6_1=
+ # TX 1x clock delay for DQSGATE_P1 and DQSGATE of rank1
+ # TX 0.5's 2x clock delay for DQSGATE_P1 and DQSGATE of rank1
+ set *($BASE_ADDR_DRAMC+0x0418) = 0x00000228
+ # =SELPH7=
+ # TX 1x clock delay for DQ byte output enable[3:0] and DQ byte[3:0]
+ set *($BASE_ADDR_DRAMC+0x041C) = 0x11111111
+ # =SELPH8=
+ # TX 1x clock delay for DQM byte output enable[3:0] and DQM byte[3:0]
+ set *($BASE_ADDR_DRAMC+0x0420) = 0x11111111
+ # =SELPH9=
+ # TX 1x clock delay for DQS byte output enable[3:0] and DQS byte[3:0]
+ set *($BASE_ADDR_DRAMC+0x0424) = 0x11111111
+ # =SELPH10=
+ # TX 0.5's 2x clock delay for DQM output enable[3:0], DQ byte output enable[3:0], DQM[3:0], and DQ byte[3:0]
+ # TODO: why we let output enable extra more 1.5 T not 0.5 DRAM clock?
+ set *($BASE_ADDR_DRAMC+0x0428) = 0x0000FFFF
+ # =SELPH11=
+ # TX 0.5's 2x clock delay for DQS output enable[3:0] and DQS[3:0]
+ # TODO: why we let output enable extra more 1.5 T not 0.5 DRAM clock?
+ set *($BASE_ADDR_DRAMC+0x042C) = 0x000000FF
+ # TODO: offset 0x430~0x438, Don't we need to set clock 05x phase selection?
+ # =SELPH12=
+ # clock 05x phase selection for CLK, DQSGATE, DQS[3:0], and DQM[3:0]
+ # clock 1x phase selection for DQS[3:0], DQM[3:0], CLK, and DQSGATE
+ set *($BASE_ADDR_DDRPHY+0x0430) = 0x10F010F0
+ # =SELPH13=
+ # clock 1x phase selection for DQ[31:0]
+ set *($BASE_ADDR_DDRPHY+0x0434) = 0xFFFFFFFF
+ # =SELPH14=
+ # clock 05x phase selection for DQ[31:0]
+ set *($BASE_ADDR_DDRPHY+0x0438) = 0xFFFFFFFF
+ # =SELPH15=
+ # OCV (On-Chip Variation that affect by PVT). It is removed in TK6291.
+ # OCV mode for DQSGATE, DQS[3:0], DQ[31:0], CLK, and CA
+ set *($BASE_ADDR_DDRPHY+0x043C) = 0x0000001F
+ # =MEMPLL_DIVIDER=
+ # DDRPHY reset flow for 1X clock phase sync
+ # [5]: MEMCLKENB, SW control. It is used for MEMPLL initialization. After initialization, CLKENB is controlled by HW mode.
+ # [4]: RG_DMSS_PWDB, ALLCLK_EN. It is used for gated MEMPLL output during initialization. (=1 after initilization)
+ # [0]: MEMCLKENB_SEL, memory clock sync enable bar selection, selection for [5] (=1 select[5])
+ if $CHIP_VER != 0
+ set $reg_val = *($BASE_ADDR_DDRPHY+0x0640) | 0x00000031
+ set *($BASE_ADDR_DDRPHY+0x0640) = $reg_val
+ end
+ # TODO: wait 500 sys_clock equal to 1.87us?
+ #WAIT 2.us
+ py time.sleep(0.001) #Delay_f32k 1
+ LPDDR2_INIT
+ if $CHIP_VER == 0
+ # =CONF2=
+ set *($BASE_ADDR_DRAMC+0x0008) = 0x0000631F
+ # =DRAMC_PD_CTRL=
+ #set $reg_val = *($BASE_ADDR_DRAMC+0x01DC) & ~0x00FF0000
+ #set $reg_val = $reg_val | 0x00350000
+ #set *($BASE_ADDR_DRAMC+0x01DC) = $reg_val
+ else
+ # =CONF2=
+ # [23] FREBW_FREN, tREFBW use xtal clock counter enable
+ # [17:8] FREBW_FR, 6720ns/(XTALFR_clock)-1
+ # [7:0] REFCNT: AC Timing Calculation is 0x3F, but ESL use 0x3B
+ # TODO: [AC Timing] 0x0000003F
+ set *($BASE_ADDR_DRAMC+0x0008) = 0x03806D3B
+ # =DRAMC_PD_CTRL=
+ # [23:16] REFCNT_FR_CLK, refresh period based on DRAMC freerun clock cycles
+ set $reg_val = *($BASE_ADDR_DRAMC+0x01DC) & ~0x00FF0000
+ set $reg_val = $reg_val | 0x00640000
+ set *($BASE_ADDR_DRAMC+0x01DC) = $reg_val
+ end
+end
+
+define EMI_INIT
+ echo EMI_INIT ...\n
+ # =EMI_CONA=
+ # [27]: RANK_POS=0, {rank,row,bank,col}
+ # [17]: DUAL_RANK_EN=0
+ # [15:14][13:12]: ROW2ND=1,ROW=1, 14-bit row address
+ # [7:6][5:4]: COL2ND=1,COL=1, 10-bit column address
+ # [1]: DW32_EN=1, 32-bit data bus
+ set *($BASE_ADDR_EMI+0x0000) = 0x00005052
+ # =EMI_ARBI=
+ set *($BASE_ADDR_EMI+0x0140) = 0x20406188
+ # =EMI_ARBI_2ND=
+ set *($BASE_ADDR_EMI+0x0144) = 0x20406188
+ # =EMI_ARBD=
+ set *($BASE_ADDR_EMI+0x0118) = 0x0700704C
+ # =EMI_ARBE=
+ set *($BASE_ADDR_EMI+0x0120) = 0x40407068
+ # =EMI_ARBG=
+ set *($BASE_ADDR_EMI+0x0130) = 0xFFFF7045
+ # =EMI_ARBH=
+ set *($BASE_ADDR_EMI+0x0138) = 0xA0A07047
+ # TODO: CSR is not defined?
+ set *($BASE_ADDR_EMI+0x0040) = 0x80808807
+ # =EMI_ARBJ=
+ # TODO: it is not defined in CSRv0.9
+ set *($BASE_ADDR_EMI+0x0148) = 0x9719595E
+ # =EMI_ARBJ_2ND=
+ # TODO: it is not defined in CSRv0.9
+ set *($BASE_ADDR_EMI+0x014C) = 0x9719595E
+ # =EMI_TEST_D=
+ set *($BASE_ADDR_EMI+0x00F8) = 0x00000000
+ # =EMI_BMEN=
+ # TODO: why do we need to enable BUS_MON_EN for DRAM Init?
+ set *($BASE_ADDR_EMI+0x0400) = 0x00FF0001
+ # =EMI_CONB=
+ set *($BASE_ADDR_EMI+0x0008) = 0x17283544
+ # =EMI_CONC=
+ set *($BASE_ADDR_EMI+0x0010) = 0x0A1A0B1A
+ # TODO: offset 0x18 is not defined in CSR.
+ set *($BASE_ADDR_EMI+0x0018) = 0x00000000
+ # =EMI_CONE=
+ # TODO: it is not defined in CSRv0.9
+ set *($BASE_ADDR_EMI+0x0020) = 0xFFFF0848
+ # =EMI_CONG=
+ set *($BASE_ADDR_EMI+0x0030) = 0x2B2B2A38
+ # =EMI_CONH=
+ set *($BASE_ADDR_EMI+0x0038) = 0x00000000
+ # =EMI_SLCT=
+ # TODO: Why do we enable [17]:M1_LLAT_EN?
+ set *($BASE_ADDR_EMI+0x0158) = 0xFF02FF00
+ # =EMI_MDCT=
+ # TODO: why don't we enable [14]:MDMCU_SBR_EN and [12]:ULTRA_SBR_EN?
+ set *($BASE_ADDR_EMI+0x0078) = 0x002F0C17
+ # TODO: it is not defined in CSR.
+ set *($BASE_ADDR_EMI+0x015C) = 0x80030303
+ # =EMI_EMI_ARBK=
+ # TODO: it only defines [23:16] in CSRv0.9
+ set *($BASE_ADDR_EMI+0x0150) = 0x64F3FC79
+ # =EMI_ARBK_2ND=
+ # TODO: it is not defined in CSRv0.9
+ set *($BASE_ADDR_EMI+0x0154) = 0x64F3FC79
+ # =EMI_TESTC=
+ # TODO: it only enables [16:8] in CSRv0.9
+ set *($BASE_ADDR_EMI+0x00F0) = 0x38470000
+ # =EMI_TESTB=
+ # TODO: it didn't define [2:0] in CSRv0.9
+ set *($BASE_ADDR_EMI+0x00E8) = 0x00020027
+ # Enable slave error
+ set *($BASE_ADDR_EMI+0x01C0) = 0x10000000
+ set *($BASE_ADDR_EMI+0x01C8) = 0x10000000
+ set *($BASE_ADDR_EMI+0x01D0) = 0x10000000
+ set *($BASE_ADDR_EMI+0x0200) = 0x10000000
+ set *($BASE_ADDR_EMI+0x02C0) = 0x10000000
+ set *($BASE_ADDR_EMI+0x02C8) = 0x10000000
+ set *($BASE_ADDR_EMI+0x02D0) = 0x10000000
+ set *($BASE_ADDR_EMI+0x0300) = 0x10000000
+ # =EMI_CONM=
+ # [10]: EMI_ENABLE=1
+ set *($BASE_ADDR_EMI+0x0060) = 0x000006B8
+ # =EMI_ARBP=
+ # EBM_MODE enable
+ set *($BASE_ADDR_EMI+0x0A20) = 0x00010000
+end
+
+define MEMSYS_INIT
+ echo MEMSYS_INIT ...\n
+ # =MEMINFRA_SI_WAY_CTL=
+ # Enable MEMINFRA EMI Path
+ # [9:8] M7_sysram:M7_emi
+ # [7:6] M6_sysram:M6_emi
+ # [5:4] M4_mdmda_sysram:M4_mddma_emi
+ # [3:2] M4_l1sys_sysram:M4_l1sys_emi
+ # [1:0] M3_sysram:M3_emi
+ set $reg_val = *($BASE_ADDR_MEMSYSAOREG_MISC+0x4000)
+ set $reg_val = $reg_val | 0x00000155
+ set *($BASE_ADDR_MEMSYSAOREG_MISC+0x4000) = $reg_val
+ # =EMI_ADDR_OFFSET=
+ # EMI offset on address[31:24], unit is 16MB
+ set $MD3_offset = 0x00
+ set $MD2_offset = 0x00
+ set $MD1_offset = 0x10
+ set $ap_offset = 0x00
+ set $emi_offset = ($MD3_offset<<0x18)+($MD2_offset<<0x10)+($MD1_offset<<0x08)+($ap_offset<<0x00)
+ set *($BASE_ADDR_MEMSYSAOREG_MISC+0x1000) = $emi_offset
+end
+
+define LPDDR2_INIT
+ # =PADCTL4=
+ # [2]: CKE always on, [0]: CKE control by controller
+ # CKE always on
+ set $reg_val = *($BASE_ADDR_DRAMC+0x00E4) | 0x00000005
+ set *($BASE_ADDR_DRAMC+0x00E4) = $reg_val
+ #WAIT 200.us
+ py time.sleep(0.001) #Delay_f32k 7
+ # LPDDR2 MRW RESET
+ DRAMC_MRW 0x0000003F
+ #WAIT 10.us
+ py time.sleep(0.001) #Delay_f32k 1
+ # ZQ Init
+ DRAMC_MRW 0x00FF000A
+ # TODO: wait 1us after ZQ Initialization
+ #WAIT 1.us
+ py time.sleep(0.001) #Delay_f32k 1
+ # MRW MR1 => BL8, Sequential, Wrap, nWR=8
+ DRAMC_MRW 0x00C30001
+ # MRW MR2 => RL=8 and WL=4 for DDR1066
+ DRAMC_MRW 0x00060002
+ # MRW MR3 => 40-ohm typical
+ DRAMC_MRW 0x00020003
+ # =PADCTL4=
+ # [2]: CKE always on, [0]: CKE control by controller
+ # CKE is controlled by hardware
+ set $reg_val = *($BASE_ADDR_DRAMC+0x00E4) & ~0x00000004
+ set *($BASE_ADDR_DRAMC+0x00E4) = $reg_val
+end
+
+define DRAMC_MRW
+ set $spcmd = 0x00000001
+ set *($BASE_ADDR_DRAMC+0x0088) = $arg0
+ set *($BASE_ADDR_DRAMC+0x01E4) = $spcmd
+ while (*($BASE_ADDR_DRAMC+0x03B8) & $spcmd) != $spcmd
+ end
+ set *($BASE_ADDR_DRAMC+0x01E4) = 0x00000000
+ while (*($BASE_ADDR_DRAMC+0x03B8) & $spcmd) != 0x00000000
+ end
+end
+
+define DRAM_TEST
+ # 0x0:infinite-loop# others:loop-N-times
+ set $TEST_LOOP = 0x2
+ # 0x0:config-and-start# others:bit-0:start,bit-1:pause,bit-2:resume.
+ set $TEST_CTRL = 0x0
+ # 0x0:pass# others:fail
+ set $TEST_RESULT = 0x0
+ # TRFG 0~3 offset 0x100
+ set $TRFG_BASE = 0xC3041000
+
+ if $TEST_CTRL != 0x0
+ set *(TRFG_BASE+0x000) = $TEST_CTRL
+ set *(TRFG_BASE+0x100) = $TEST_CTRL
+ set *(TRFG_BASE+0x200) = $TEST_CTRL
+ set *(TRFG_BASE+0x300) = $TEST_CTRL
+ #ENDDO
+ end
+
+ # Config and start
+ echo TRFG config and start ...\n
+ set $idx = 0x0
+ while $idx < 0x4
+ set $base = $TRFG_BASE + 0x100 * $idx
+ set $start_addr= 0x04000000 * $idx
+ set $pat_ctl = 0x58FF0017 + (($TEST_LOOP & 0xF) << 8)
+ # TRFG_STRAT_CTL, [0]:start, [1]:pause, [2]:resume
+ set *($base+0x00) = 0x00000000
+ # TRFG_INIT_PAT_MSB
+ set *($base+0x04) = 0x5A5A5A5A
+ # TRFG_INIT_PAT_LSB
+ set *($base+0x08) = 0xA5A5A5A5
+ # TRFG_START_ADDR
+ set *($base+0x0C) = $start_addr
+ # TRFG_TEST_LEN * 8 byte
+ set *($base+0x10) = 0x00800000
+ # TRFG_PAT_CTL, [11:8]:test_loop, [5:4]:pat_mode
+ set *($base+0x14) = $pat_ctl
+ # TRFG_BUS_CTL, [10:8]:domain, [3:0]:burst_len
+ set *($base+0x18) = 0x0000010F
+ # TRFG_STRAT_CTL, [0]:start, [1]:pause, [2]:resume
+ set *($base+0x00) = 0x00000001
+ set $idx++
+ end
+
+ # Wait done
+ echo Wait done
+ set $idx = 0x0
+ while $idx < 0x4
+ set $base = $TRFG_BASE + 0x100 * $idx
+ while (*($base+0x20) & 0x1) == 0x1
+ echo .\n
+ #WAIT 1.S
+ py time.sleep(1) #Delay_f32k 32000
+ end
+ if (*($base+0x20) & 0x04) == 0x0
+ set $TEST_RESULT++
+ printf "=> TRFG %d test fail:\n", $idx
+ printf "FAIL_ADDR = 0x%08x\n", *($base+0x24)
+ printf "EXP_DATA_MSB = 0x%08x\n", *($base+0x28)
+ printf "EXP_DATA_LSB = 0x%08x\n", *($base+0x2C)
+ printf "FAIL_DATA_MSB = 0x%08x\n", *($base+0x30)
+ printf "FAIL_DATA_LSB = 0x%08x\n", *($base+0x34)
+ end
+ set $idx++
+ end
+
+ if $TEST_RESULT == 0x0
+ echo => Traffic-Gen dram test pass ...^_^\n
+ else
+ echo => Traffic-Gen dram test fail ...>^<\n
+ end
+end
+
+define WDT_Disable
+ echo WDT_Disable ...\n
+ set $mdrgu = 0xA00F0000 + 0x0100
+ set $aprgu = 0xC3670000 + 0x0100
+ set *$mdrgu = 0x55000000 | (*$mdrgu & ~0x03)
+ set *$aprgu = 0x55000000 | (*$aprgu & ~0x01)
+end
+
+define MIPS_INIT
+ echo MIPS_INIT ...\n
+ set *0x1F000020 = 0x0000000F
+ set *0x1F000090 = 0xA0000000
+ set *0x1F000098 = 0xE0000002
+ set *0x1F0000A0 = 0xC0000000
+ set *0x1F0000A8 = 0xC0000002
+ # fixed md mips domain ID hw bug
+ #set *0xA0060060 = 0x03231111
+end
+
+define MIPS_enable_fast_write
+ echo MIPS_enable_fast_write ...\n
+ # to accelerate loading elf
+ # configure C0_CDMMBASE = 0x01FC1407 to enable access
+ set $cdmmbase = 0x01FC1407
+ if $cdmmbase != 0x01FC1407
+ printf "[error] cdmmbase = %#010x, not 0x01FC1407", $cdmmbase
+ end
+ # default all segments are NC, then configure VA Bank8 to WB for speed up load elf
+ set *0x1FC100D4 = 0x02030202
+ if *0x1FC100D4 != 0x02030202
+ printf "[error] 0x1FC100D4 = %#010x, not 0x02030202", *0x1FC100D4
+ end
+ # slow down for coretracer limitation
+ monitor adapter_khz 1100
+ monitor mips32 fastchannel 0 1 0x6f800000
+ #thread 1
+end
+
+define MIPS_disable_fast_write
+ echo MIPS_disable_fast_write ...\n
+ monitor mips32 fastchannel 0 0 0x6f800000
+ set *0x1FC100D4 = 0x02020202
+ if *0x1FC100D4 != 0x02020202
+ printf "[error] 0x1FC100D4 = %#010x, not 0x02020202", *0x1FC100D4
+ end
+ #set $cdmmbase = 0x01FC1007
+ #if $cdmmbase != 0x01FC1007
+ # printf "[error] cdmmbase = %#010x, not 0x01FC1007", $cdmmbase
+ #end
+end
+
+define LOAD_ELF_File
+ echo Clear DSP header ...\n
+ set *0x0E800000 = 0x00
+ set *0x00080000 = 0x00
+ echo Clear NVRAM header ...\n
+ set *0x0D8001FC = 0x00
+ MIPS_enable_fast_write
+ echo start to load elf ...\n
+ load
+ echo load elf done\n
+ MIPS_disable_fast_write
+end
+
+# entry point
+py from __future__ import division
+py import time;
+py tim_str = time.time()
+MIPS_INIT
+WDT_Disable
+DRAM_INIT
+#DRAM_TEST
+LOAD_ELF_File
+py tim_end = time.time()
+py print("Elapsed time: {:.3f} sec".format(tim_end-tim_str))
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6295M/fpga_emi_init_coreTracer.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6295M/fpga_emi_init_coreTracer.cmm
new file mode 100755
index 0000000..b8a501f
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6295M/fpga_emi_init_coreTracer.cmm
@@ -0,0 +1,584 @@
+;sys.m prepare
+;LOCAL &TYPE
+LOCAL &BASE_MADDR_MDRGU
+LOCAL &BASE_MADDR_APRGU
+;IF DATA.LONG(DBG:0x41000000)==0x5BA02477 ; AP DAP
+;(
+; &TYPE="EAHB"
+; &BASE_MADDR_MDRGU=0x800F0000
+;)
+;ELSE ; DATA.LONG(DBG:0x41000000)==0x6BA02477 ; MD DAP
+;(
+; sys.m down
+; MULtiCore.DEBUGACCESSPORT 1
+; MULtiCore.AXIACCESSPORT 0
+; sys.m prepare
+; &TYPE="AXI"
+; &BASE_MADDR_MDRGU=0xA00F0000
+;)
+
+system.mode attach
+
+PRINT "=============================="
+PRINT "EMI Initialization Start!"
+PRINT "=============================="
+
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+; fixed md mips domain ID hw bug
+;D.S 0xA0060060 %LE %LONG 0x03231111
+
+; do orginal disable_WDT2_MIPS.cmm
+&BASE_MADDR_MDRGU=0xA00F0000
+&BASE_MADDR_APRGU=0xC3670000
+
+;D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG (0x55000000|data.long(&BASE_MADDR_MDRGU+0x0100)&~(0x3))
+&temp=data.long(&BASE_MADDR_MDRGU+0x0100)
+&temp=&temp | 0x55000000
+&temp=&temp & ~(0x3)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG &temp
+
+;D.S &BASE_MADDR_APRGU+0x0100 %LE %LONG (0x55000000|data.long(&BASE_MADDR_APRGU+0x0100)&~(0x1))
+&temp=data.long(&BASE_MADDR_MDRGU+0x0100)
+&temp=&temp | 0x55000000
+&temp=&temp & ~(0x1)
+D.S &BASE_MADDR_APRGU+0x0100 %LE %LONG &temp
+
+; do orginal emi_init.cmm
+LOCAL &CHIP_VER ; 0 is for FPGA, 1 is for E1, and so on
+&CHIP_VER=0
+&BASE_ADDR_EMI=0xC3000000
+&BASE_ADDR_DRAMC=0xC3010000
+&BASE_ADDR_DDRPHY=0xC3020000
+&BASE_ADDR_MEMSYSAOREG_MISC=0xC3080000
+&BASE_ADDR_AP_CLKSW=0xC3750000
+
+; Check if initialize
+&temp=DATA.LONG(&BASE_ADDR_EMI+0x0060)
+&temp=&temp & 0x00000400
+IF (&temp == 0x00000400)
+(
+ PRINT "=============================="
+ PRINT "Warning: EMI has be initialized, why ......"
+ PRINT "=============================="
+ ;ENDDO
+)
+ELSE
+(
+ ;DRAM initialization
+ GOSUB DRAM_INIT
+ PRINT "=============================="
+ PRINT "EMI Initialization Pass!"
+ PRINT "=============================="
+)
+
+PRINT "=============================="
+PRINT "Clear Dsp Header ..."
+PRINT "=============================="
+D.S 0x0D800000 %LE %LONG 0x00
+D.S 0x00080000 %LE %LONG 0x00
+
+;Enalbe cache to speed loading
+register.set cdmmbase 0x1fc1407
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor adapter_khz 1100
+steal monitor mips32 fastchannel 0 1 0x6f800000
+
+PRINT "=============================="
+PRINT "Start to Load elf ..."
+PRINT "=============================="
+steal lo
+steal monitor mips32 fastchannel 0 0 0x6f800000
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+PRINT "=============================="
+PRINT "Load elf Done!"
+PRINT "=============================="
+
+&nvram_region=var.address("Image$$EXTSRAM_FS_ZI$$ZI$$Base")
+
+IF (&nvram_region == 0xDEADDEAD)
+(
+ PRINT "=============================="
+ PRINT "Not find NVRAM region, bypass clear it"
+ PRINT "=============================="
+)
+ELSE
+(
+ &nvram_region_FS_addr_1=&nvram_region+0x1FE
+ &nvram_region_FS_addr_2=&nvram_region+0x3FE
+ PRINT "=============================="
+ PRINT "Clear NVRAM region address &nvram_region_FS_addr_1 and &nvram_region_FS_addr_2 to 0"
+ PRINT "=============================="
+ D.S &nvram_region_FS_addr_1 %LE %LONG 0x00
+ D.S &nvram_region_FS_addr_2 %LE %LONG 0x00
+)
+
+;thread.select 1
+
+;&tt=var.address(INT_Initialize_Phase1)
+;register.set pc &tt
+;steal flushreg
+
+;steal p/x $pc
+;&t=r(pc)
+;PRINT "=============================="
+;PRINT "Set PC to INT_Initialize_Phase1: &t"
+;PRINT "=============================="
+
+ENDDO
+
+
+; =========================================================================================
+; Sub Function: DRAM_INIT
+; Description: initialize MEMPLL, DRAMC, DDRPHY, DRAM, EMI
+; =========================================================================================
+DRAM_INIT:
+ ; =MEMSYS_PASSWORD=
+ ; Unlock MEMSYS Password
+ D.S &BASE_ADDR_MEMSYSAOREG_MISC+0x3000 %LE %LONG 0x24541689
+ ;GOSUB MEMPLL_INIT
+ GOSUB DRAMC_INIT
+ GOSUB EMI_INIT
+ ; =MEMINFRA_SI_WAY_CTL=
+ ; Enable MEMINFRA EMI Path
+ ; [9:8] M7_sysram:M7_emi
+ ; [7:6] M6_sysram:M6_emi
+ ; [5:4] M4_mdmda_sysram:M4_mddma_emi
+ ; [3:2] M4_l1sys_sysram:M4_l1sys_emi
+ ; [1:0] M3_sysram:M3_emi
+ ®_val=DATA.LONG(&BASE_ADDR_MEMSYSAOREG_MISC+0x4000)
+ ®_val=®_val|0x00000155
+ D.S &BASE_ADDR_MEMSYSAOREG_MISC+0x4000 %LE %LONG ®_val
+ ; =EMI_ADDR_OFFSET=
+ ; EMI offset on address[31:24], unit is 16MB
+ &MD3_offset=0x00
+ &MD2_offset=0x00
+ &MD1_offset=0x10
+ &ap_offset=0x00
+ &emi_offset=(&MD3_offset<<0x18)+(&MD2_offset<<0x10)+(&MD1_offset<<0x08)+(&ap_offset<<0x00)
+ D.S &BASE_ADDR_MEMSYSAOREG_MISC+0x1000 %LE %LONG &emi_offset
+ ; =MEMSYS_PASSWORD=
+ ; Lock MEMSYS Password
+ D.S &BASE_ADDR_MEMSYSAOREG_MISC+0x3000 %LE %LONG 0x00000000
+ RETURN
+
+; =========================================================================================
+; Sub Function: MEMPLL_INIT
+; =========================================================================================
+MEMPLL_INIT:
+ DATA.LOAD.ELF &emi_elf_path
+ B.D /ALL
+ B.S custom_InitDRAM /HARD
+ GO
+ WAIT !RUN() 5.s
+ IF r(PC)==custom_InitDRAM
+ (
+ PRINT "MEMPLL Initialization Pass!"
+ RETURN
+ )
+ ELSE
+ (
+ PRINT "MEMPLL Initialization Failed!"
+ ENDDO
+ )
+
+; =========================================================================================
+; Sub Function: DRAMC_INIT
+; Description: initialize DRAMC, DDRPHY, and DRAM, but this function doesn't initialize EMI
+; =========================================================================================
+DRAMC_INIT:
+ ; =ACTIM0=
+ D.S &BASE_ADDR_DRAMC+0x0000 %LE %LONG 0x44584493
+ ; =CONF1=
+ ; [18][5][3] no use in TK6291
+ ; [9:8]MTYPE, DRAM column address width, 2'b01 (9-bit) -> 2'b10 (10-bit)
+ ; TODO: [AC Timing] 0x00048683
+ D.S &BASE_ADDR_DRAMC+0x0004 %LE %LONG 0xF0008681 ; 0xF0008481
+ ; =R0DELDLY=
+ D.S &BASE_ADDR_DRAMC+0x0018 %LE %LONG 0x10101010
+ ; =R1DELDLY=
+ ; [30:24][22:16][14:8][6:0] DQS3/2/1/0 input delay
+ D.S &BASE_ADDR_DRAMC+0x001C %LE %LONG 0x12121212
+ ; =DLLCONF=
+ D.S &BASE_ADDR_DRAMC+0x0028 %LE %LONG 0x50000000
+ ; =TEST2_3=
+ ; [23] DQSICALI_NEW=0, using original dqs calibration
+ ; [7] TESTAUDPAT=0, ISI pattern can be set by TEST2_PAT0
+ D.S &BASE_ADDR_DRAMC+0x0044 %LE %LONG 0xBF080000
+ ; =TEST2_4=
+ D.S &BASE_ADDR_DRAMC+0x0048 %LE %LONG 0x1601110D
+ ; =DDR2CTL=
+ D.S &BASE_ADDR_DRAMC+0x007C %LE %LONG 0x00003201
+ ; =MISC=
+ ; [23:21]: PHYRXDSL_PIPE3~1 are pipe stage selection for RDATA and RDSEL
+ ; DATLAT_DSEL = DATLAT - 2*2 when enabling two top pipe (for TK6291)
+ D.S &BASE_ADDR_DRAMC+0x0080 %LE %LONG 0x00AC08A0
+ ; =ZQCS=
+ ; [15:8]: ZQCSAD, [7:0]: ZQCSOP
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x0084) & ~0x0000FFFF
+ ®_val=®_val|0x00000A56
+ D.S &BASE_ADDR_DRAMC+0x0084 %LE %LONG ®_val
+ ; =CLK1DELAY=
+ ; [23]: PHYPIPE3EN, [22]: PHYPIPE2EN, [21]: PHYPIPE1EN
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x008C) & ~0x00E00000
+ ®_val=®_val|0x00A00000
+ D.S &BASE_ADDR_DRAMC+0x008C %LE %LONG ®_val
+ ; =R0DQSIEN=
+ ; Gating Window for Rank0
+ D.S &BASE_ADDR_DRAMC+0x0094 %LE %LONG 0x31313131
+ ; =MCKDLY=
+ ; [23]: WODT has no load (useless)
+ ; [21]: DRAMEN has no load (useless)
+ ; [11:10] DQIENQKEND: DQ/DQS input enable window is larger than 6582. [11:10]=2'b00 => dle counter is 5'1f. =Others => dle counter is DATLAT-[11:10]+2
+ ; [4] DQIENLATEBEGIN, disable early begin, better for power saving
+ ; TODO: [20]: It is used for BST(Bus Termination), but TK6291 doesn't support the feature
+ D.S &BASE_ADDR_DRAMC+0x00D8 %LE %LONG 0x40500510
+ ; =DQSCTL1=
+ ; [27:24]: DQSINCTL, DQS input range control by M_CK
+ ; [23:12][11:0]: DQS3CTL/DQS2CTL, control by DDRPHY (useless)
+ D.S &BASE_ADDR_DRAMC+0x00E0 %LE %LONG 0x12200200
+ ; =GDDR3CTL1=
+ ; [24]: 8BKEN=1, 8-bank device enable
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x00F4) | 0x01000000
+ D.S &BASE_ADDR_DRAMC+0x00F4 %LE %LONG ®_val
+ ; [28]: PHYSYNCM=1, SYNC MODE using inverted PHY_M_CK
+ ®_val=DATA.LONG(&BASE_ADDR_DDRPHY+0x00F4) | 0x10000000
+ D.S &BASE_ADDR_DDRPHY+0x00F4 %LE %LONG ®_val
+ ; =MISCTL0=
+ ; [31]: REFP_ARB_EN2: per-bank refresh arbitration mask2
+ ; [30:28]: TXP, tXP Timing setting
+ ; [27] EMIPREEN: Enable advanced precharge function by EMI side-band signals, but TK6291 didn't support this feature.
+ ; [26] REFP_ARB_EN: per-bank refresh blocks in EMI arbitration
+ ; [25] REFA_ARB_EN: all-bank refresh blocks in EMI arbitration
+ ; [24] PBC_ARB_EN: block page-miss requests in EMI arbitration
+ ; [21]: REFA_ARB_EN2: all bank refresh arbtration mask enable option
+ D.S &BASE_ADDR_DRAMC+0x00FC %LE %LONG 0x81080000
+ ; [17]: INTLBT=0, IO internal loop back (useless for TK6291)
+ ; [16]: RXLPDDR2=0, IO voltage operating condition = {0:1.2V, 1:1.8V}
+ ®_val=DATA.LONG(&BASE_ADDR_DDRPHY+0x00FC) & ~0x00030000
+ D.S &BASE_ADDR_DDRPHY+0x00FC %LE %LONG ®_val
+ ; =OCDK=
+ ; [24]: DRVREF=1, drving change only when refresh cycle
+ ; [15]: DRDELSWEN=1, enable DQS input delay switching for different ranks
+ ; [8]: AUTOCALDRV=1, OCD calibration enable
+ ; [7:0]: AUTOKCNT, auto calibration counter
+ ; =RKCFG=
+ ; [7]: per-bank refresh for LPDDR2&3
+ ; TODO: [AC Timing] 0x004135C0
+ D.S &BASE_ADDR_DRAMC+0x0110 %LE %LONG 0x004121C0
+ ; =DQSCTL2=
+ D.S &BASE_ADDR_DRAMC+0x0118 %LE %LONG 0x00000002
+ ; =DQSGCTL=
+ ; [7:0] Old gating window course tune
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x0124) & ~0x000000FF
+ D.S &BASE_ADDR_DRAMC+0x0124 %LE %LONG ®_val
+ ; [31]: NEWDQSG_SEL, [30]:DQSGDUALP
+ ®_val=DATA.LONG(&BASE_ADDR_DDRPHY+0x0124) | 0xC0000000
+ D.S &BASE_ADDR_DDRPHY+0x0124 %LE %LONG ®_val
+ ; =CLKCTRL=
+ ; [29]: CLK_EN_1, [28]: CLK_EN_0
+ ; TODO: we should only enable one CLK for TK6291
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x0130) | 0x30000000
+ D.S &BASE_ADDR_DRAMC+0x0130 %LE %LONG ®_val
+ ; =ARBCTL0=
+ ; [7:0]: maximum pending number to block the arbitration
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x0168) & ~0x000000FF
+ ®_val=®_val|0x00000080
+ D.S &BASE_ADDR_DRAMC+0x0168 %LE %LONG ®_val
+ ; =DQSCAL0=
+ ; [31]: DQS strobe calibration enable
+ ; [30]: Update tracking gating value to 2 ranks simultaneously
+ ; [15]: Rank0 DQS strobe calibration high-limit enable
+ ; [14:8]: Rank0 DQS strobe calibration high-limit value
+ ; [7]: Rank0 DQS strobe calibration low-limit enable
+ ; [6:0]: Rank0 DQS strobe calibration low-limit value
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x01C0) & ~0xC000FFFF
+ ®_val=®_val | 0x80000000
+ D.S &BASE_ADDR_DRAMC+0x01C0 %LE %LONG ®_val
+ ; =MEMSYSPIPE_CGF_CTL=
+ ; [2]: PIPE_CFG_EN, [0]: DRAMC_CFG_EN
+ ; PIPE_CGF_ON=0 (timing issue) EMI_CGF_ON=0(Gated function is already designed in EMI) DRAMC_CGF_ON=1
+ D.S &BASE_ADDR_MEMSYSAOREG_MISC+0x5000 %LE %LONG 0x00000001
+ ; =DRAMC_PD_CTRL=
+ ; [24] REFFRERUN, using freerun clock to count refresh period
+ ; [23:16] REFCNT_FR_CLK, refresh period based on DRAMC freerun clock cycles
+ ; [15:8] TXREFCNT, tXSR
+ IF (&CHIP_VER==0)
+ (
+ D.S &BASE_ADDR_DRAMC+0x01DC %LE %LONG 0xC2002340
+ )
+ ELSE
+ (
+ D.S &BASE_ADDR_DRAMC+0x01DC %LE %LONG 0xC3002340
+ )
+ ; =LPDDR2_3=
+ ; TODO: should set to 0x10000000, not 0x3600_0000?
+ ; [31]: DRAM address decode by DRAMC
+ ; [28]: LPDDR2 enable
+ ; [27]: enable register output data by DRAMC
+ D.S &BASE_ADDR_DRAMC+0x01E0 %LE %LONG 0x36000000
+ ; [30]: Select IO O1 as output
+ ; [29&25:24&22:0]: DDR mode for pins
+ ; [26]: fast IO output enable
+ D.S &BASE_ADDR_DDRPHY+0x01E0 %LE %LONG 0x2601FFFF
+ ; =ACTIM1=
+ D.S &BASE_ADDR_DRAMC+0x01E8 %LE %LONG 0x81000510
+ ; =PERFCTL0=
+ ; [0] dual schedulers
+ D.S &BASE_ADDR_DRAMC+0x01EC %LE %LONG 0x0010CF11
+ ; TODO: AC_DERATING [0x01F0]
+ ; =RRRATE_CTL=, =MRR_CTL=
+ IF (&CHIP_VER==0) ; Or LPDDR3
+ (
+ D.S &BASE_ADDR_DRAMC+0x01F4 %LE %LONG 0x03020100
+ D.S &BASE_ADDR_DRAMC+0x01Fc %LE %LONG 0x07060504
+ )
+ ELSE
+ (
+ D.S &BASE_ADDR_DRAMC+0x01F4 %LE %LONG 0x02030100
+ D.S &BASE_ADDR_DRAMC+0x01Fc %LE %LONG 0x04060705
+ )
+ ; =AC_TIME_05T=
+ D.S &BASE_ADDR_DRAMC+0x01F8 %LE %LONG 0x04002600
+ ; =LPDDR2_4=
+ ; clock 1x phase selection
+ D.S &BASE_ADDR_DDRPHY+0x023C %LE %LONG 0x2201FFFF
+ ; =SELPH1=
+ ; TX 1x clock delay for CS1, RAS, CAS, WE, RESET, ODT, CKE, and CS
+ D.S &BASE_ADDR_DRAMC+0x0400 %LE %LONG 0x00000000
+ ; =SELPH2=
+ ; TX 1x clock delay for CKE1, DQSGATE_P1, CMD, DQSGATE, BA[2:0]
+ IF (&CHIP_VER==0)
+ (
+ D.S &BASE_ADDR_DRAMC+0x0404 %LE %LONG 0x00302000
+ )
+ ELSE
+ (
+ D.S &BASE_ADDR_DRAMC+0x0404 %LE %LONG 0x00101000
+ )
+ ; =SELPH3=
+ ; TX 1x clock delay for RA[7:0]
+ D.S &BASE_ADDR_DRAMC+0x0408 %LE %LONG 0x00000000
+ ; =SELPH4=
+ ; TX 1x clock delay for RA[15:8]
+ D.S &BASE_ADDR_DRAMC+0x040C %LE %LONG 0x00000000
+ ; =SELPH5=
+ ; TX 0.5's 2x clock delay for CKE1, DQSGATE_P1, DQSGATE, BA[2:0], CS1, RAS, CAS, WE, RESET, ODT, CKE, CS
+ IF (&CHIP_VER==0)
+ (
+ D.S &BASE_ADDR_DRAMC+0x0410 %LE %LONG 0x00955555
+ )
+ ELSE
+ (
+ D.S &BASE_ADDR_DRAMC+0x0410 %LE %LONG 0x57755555
+ )
+ ; TODO: SELPH6 [0x0414]
+ ; =SELPH6_1=
+ ; TX 1x clock delay for DQSGATE_P1 and DQSGATE of rank1
+ ; TX 0.5's 2x clock delay for DQSGATE_P1 and DQSGATE of rank1
+ D.S &BASE_ADDR_DRAMC+0x0418 %LE %LONG 0x00000228
+ ; =SELPH7=
+ ; TX 1x clock delay for DQ byte output enable[3:0] and DQ byte[3:0]
+ D.S &BASE_ADDR_DRAMC+0x041C %LE %LONG 0x11111111
+ ; =SELPH8=
+ ; TX 1x clock delay for DQM byte output enable[3:0] and DQM byte[3:0]
+ D.S &BASE_ADDR_DRAMC+0x0420 %LE %LONG 0x11111111
+ ; =SELPH9=
+ ; TX 1x clock delay for DQS byte output enable[3:0] and DQS byte[3:0]
+ D.S &BASE_ADDR_DRAMC+0x0424 %LE %LONG 0x11111111
+ ; =SELPH10=
+ ; TX 0.5's 2x clock delay for DQM output enable[3:0], DQ byte output enable[3:0], DQM[3:0], and DQ byte[3:0]
+ ; TODO: why we let output enable extra more 1.5 T not 0.5 DRAM clock?
+ D.S &BASE_ADDR_DRAMC+0x0428 %LE %LONG 0x0000FFFF
+ ; =SELPH11=
+ ; TX 0.5's 2x clock delay for DQS output enable[3:0] and DQS[3:0]
+ ; TODO: why we let output enable extra more 1.5 T not 0.5 DRAM clock?
+ D.S &BASE_ADDR_DRAMC+0x042C %LE %LONG 0x000000FF
+ ; TODO: offset 0x430~0x438, Don't we need to set clock 05x phase selection?
+ ; =SELPH12=
+ ; clock 05x phase selection for CLK, DQSGATE, DQS[3:0], and DQM[3:0]
+ ; clock 1x phase selection for DQS[3:0], DQM[3:0], CLK, and DQSGATE
+ D.S &BASE_ADDR_DDRPHY+0x0430 %LE %LONG 0x10F010F0
+ ; =SELPH13=
+ ; clock 1x phase selection for DQ[31:0]
+ D.S &BASE_ADDR_DDRPHY+0x0434 %LE %LONG 0xFFFFFFFF
+ ; =SELPH14=
+ ; clock 05x phase selection for DQ[31:0]
+ D.S &BASE_ADDR_DDRPHY+0x0438 %LE %LONG 0xFFFFFFFF
+ ; =SELPH15=
+ ; OCV (On-Chip Variation that affect by PVT). It is removed in TK6291.
+ ; OCV mode for DQSGATE, DQS[3:0], DQ[31:0], CLK, and CA
+ D.S &BASE_ADDR_DDRPHY+0x043C %LE %LONG 0x0000001F
+ ; =MEMPLL_DIVIDER=
+ ; DDRPHY reset flow for 1X clock phase sync
+ ; [5]: MEMCLKENB, SW control. It is used for MEMPLL initialization. After initialization, CLKENB is controlled by HW mode.
+ ; [4]: RG_DMSS_PWDB, ALLCLK_EN. It is used for gated MEMPLL output during initialization. (=1 after initilization)
+ ; [0]: MEMCLKENB_SEL, memory clock sync enable bar selection, selection for [5] (=1 select[5])
+ IF (&CHIP_VER!=0)
+ (
+ ®_val=DATA.LONG(&BASE_ADDR_DDRPHY+0x0640) | 0x00000031
+ D.S &BASE_ADDR_DDRPHY+0x0640 %LE %LONG ®_val
+ )
+ ; TODO: wait 500 sys_clock equal to 1.87us?
+ WAIT 2.us
+ GOSUB LPDDR2_INIT
+ IF (&CHIP_VER==0)
+ (
+ ; =CONF2=
+ D.S &BASE_ADDR_DRAMC+0x0008 %LE %LONG 0x0000631F
+ ; =DRAMC_PD_CTRL=
+ ;®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x01DC)&~0x00FF0000
+ ;®_val=®_val|0x00350000
+ ;D.S &BASE_ADDR_DRAMC+0x01DC %LE %LONG ®_val
+ )
+ ELSE
+ (
+ ; =CONF2=
+ ; [23] FREBW_FREN, tREFBW use xtal clock counter enable
+ ; [17:8] FREBW_FR, 6720ns/(XTALFR_clock)-1
+ ; [7:0] REFCNT: AC Timing Calculation is 0x3F, but ESL use 0x3B
+ ; TODO: [AC Timing] 0x0000003F
+ D.S &BASE_ADDR_DRAMC+0x0008 %LE %LONG 0x03806D3B
+ ; =DRAMC_PD_CTRL=
+ ; [23:16] REFCNT_FR_CLK, refresh period based on DRAMC freerun clock cycles
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x01DC) & ~0x00FF0000
+ ®_val=®_val | 0x00640000
+ D.S &BASE_ADDR_DRAMC+0x01DC %LE %LONG ®_val
+ )
+ RETURN
+
+; =========================================================================================
+; Sub Function: EMI_INIT
+; =========================================================================================
+EMI_INIT:
+ ; =EMI_CONA=
+ ; [27]: RANK_POS=0, {rank,row,bank,col}
+ ; [17]: DUAL_RANK_EN=0
+ ; [15:14][13:12]: ROW2ND=1,ROW=1, 14-bit row address
+ ; [7:6][5:4]: COL2ND=1,COL=1, 10-bit column address
+ ; [1]: DW32_EN=1, 32-bit data bus
+ D.S &BASE_ADDR_EMI+0x0000 %LE %LONG 0x00005052
+ ; =EMI_ARBI=
+ D.S &BASE_ADDR_EMI+0x0140 %LE %LONG 0x20406188
+ ; =EMI_ARBI_2ND=
+ D.S &BASE_ADDR_EMI+0x0144 %LE %LONG 0x20406188
+ ; =EMI_ARBD=
+ D.S &BASE_ADDR_EMI+0x0118 %LE %LONG 0x0700704C
+ ; =EMI_ARBE=
+ D.S &BASE_ADDR_EMI+0x0120 %LE %LONG 0x40407068
+ ; =EMI_ARBG=
+ D.S &BASE_ADDR_EMI+0x0130 %LE %LONG 0xFFFF7045
+ ; =EMI_ARBH=
+ D.S &BASE_ADDR_EMI+0x0138 %LE %LONG 0xA0A07047
+ ; TODO: CSR is not defined?
+ D.S &BASE_ADDR_EMI+0x0040 %LE %LONG 0x80808807
+ ; =EMI_ARBJ=
+ ; TODO: it is not defined in CSRv0.9
+ D.S &BASE_ADDR_EMI+0x0148 %LE %LONG 0x9719595E
+ ; =EMI_ARBJ_2ND=
+ ; TODO: it is not defined in CSRv0.9
+ D.S &BASE_ADDR_EMI+0x014C %LE %LONG 0x9719595E
+ ; =EMI_TEST_D=
+ D.S &BASE_ADDR_EMI+0x00F8 %LE %LONG 0x00000000
+ ; =EMI_BMEN=
+ ; TODO: why do we need to enable BUS_MON_EN for DRAM Init?
+ D.S &BASE_ADDR_EMI+0x0400 %LE %LONG 0x00FF0001
+ ; =EMI_CONB=
+ D.S &BASE_ADDR_EMI+0x0008 %LE %LONG 0x17283544
+ ; =EMI_CONC=
+ D.S &BASE_ADDR_EMI+0x0010 %LE %LONG 0x0A1A0B1A
+ ; TODO: offset 0x18 is not defined in CSR.
+ D.S &BASE_ADDR_EMI+0x0018 %LE %LONG 0x00000000
+ ; =EMI_CONE=
+ ; TODO: it is not defined in CSRv0.9
+ D.S &BASE_ADDR_EMI+0x0020 %LE %LONG 0xFFFF0848
+ ; =EMI_CONG=
+ D.S &BASE_ADDR_EMI+0x0030 %LE %LONG 0x2B2B2A38
+ ; =EMI_CONH=
+ D.S &BASE_ADDR_EMI+0x0038 %LE %LONG 0x00000000
+ ; =EMI_SLCT=
+ ; TODO: Why do we enable [17]:M1_LLAT_EN?
+ D.S &BASE_ADDR_EMI+0x0158 %LE %LONG 0xFF02FF00
+ ; =EMI_MDCT=
+ ; TODO: why don't we enable [14]:MDMCU_SBR_EN and [12]:ULTRA_SBR_EN?
+ D.S &BASE_ADDR_EMI+0x0078 %LE %LONG 0x002F0C17
+ ; TODO: it is not defined in CSR.
+ D.S &BASE_ADDR_EMI+0x015C %LE %LONG 0x80030303
+ ; =EMI_EMI_ARBK=
+ ; TODO: it only defines [23:16] in CSRv0.9
+ D.S &BASE_ADDR_EMI+0x0150 %LE %LONG 0x64F3FC79
+ ; =EMI_ARBK_2ND=
+ ; TODO: it is not defined in CSRv0.9
+ D.S &BASE_ADDR_EMI+0x0154 %LE %LONG 0x64F3FC79
+ ; =EMI_TESTC=
+ ; TODO: it only enables [16:8] in CSRv0.9
+ D.S &BASE_ADDR_EMI+0x00F0 %LE %LONG 0x38470000
+ ; =EMI_TESTB=
+ ; TODO: it didn't define [2:0] in CSRv0.9
+ D.S &BASE_ADDR_EMI+0x00E8 %LE %LONG 0x00020027
+ // Enable slave error
+ D.S &BASE_ADDR_EMI+0x01C0 %LE %LONG 0x10000000
+ D.S &BASE_ADDR_EMI+0x01C8 %LE %LONG 0x10000000
+ D.S &BASE_ADDR_EMI+0x01D0 %LE %LONG 0x10000000
+ D.S &BASE_ADDR_EMI+0x0200 %LE %LONG 0x10000000
+ D.S &BASE_ADDR_EMI+0x02C0 %LE %LONG 0x10000000
+ D.S &BASE_ADDR_EMI+0x02C8 %LE %LONG 0x10000000
+ D.S &BASE_ADDR_EMI+0x02D0 %LE %LONG 0x10000000
+ D.S &BASE_ADDR_EMI+0x0300 %LE %LONG 0x10000000
+ ; =EMI_CONM=
+ ; [10]: EMI_ENABLE=1
+ D.S &BASE_ADDR_EMI+0x0060 %LE %LONG 0x000006B8
+ ; =EMI_ARBP=
+ ; EBM_MODE enable
+ D.S &BASE_ADDR_EMI+0x0A20 %LE %LONG 0x00010000
+ RETURN
+
+; =========================================================================================
+; Sub Function: LPDDR2_INIT
+; =========================================================================================
+LPDDR2_INIT:
+ ; =PADCTL4=
+ ; [2]: CKE always on, [0]: CKE control by controller
+ ; CKE always on
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x00E4) | 0x00000005
+ D.S &BASE_ADDR_DRAMC+0x00E4 %LE %LONG ®_val
+ WAIT 200.us
+ ; LPDDR2 MRW RESET
+ GOSUB DRAMC_MRW 0x0000003F
+ WAIT 10.us
+ ; ZQ Init
+ GOSUB DRAMC_MRW 0x00FF000A
+ ; TODO: wait 1us after ZQ Initialization
+ WAIT 1.us
+ ; MRW MR1 => BL8, Sequential, Wrap, nWR=8
+ GOSUB DRAMC_MRW 0x00C30001
+ ; MRW MR2 => RL=8 and WL=4 for DDR1066
+ GOSUB DRAMC_MRW 0x00060002
+ ; MRW MR3 => 40-ohm typical
+ GOSUB DRAMC_MRW 0x00020003
+ ; =PADCTL4=
+ ; [2]: CKE always on, [0]: CKE control by controller
+ ; CKE is controlled by hardware
+ ®_val=DATA.LONG(&BASE_ADDR_DRAMC+0x00E4) & ~0x00000004
+ D.S &BASE_ADDR_DRAMC+0x00E4 %LE %LONG ®_val
+ RETURN
+
+; =========================================================================================
+; Sub Function: DRAMC_MRW
+; Description: DRAMC Mode Register Write
+; argument:
+; @mrs mode register write value
+; =========================================================================================
+DRAMC_MRW:
+ ENTRY &mrs
+ LOCAL &spcmd
+ &spcmd=0x00000001
+ D.S &BASE_ADDR_DRAMC+0x0088 %LE %LONG &mrs
+ D.S &BASE_ADDR_DRAMC+0x01E4 %LE %LONG &spcmd
+ WAIT (DATA.LONG(&BASE_ADDR_DRAMC+0x03B8)&(&spcmd))==&spcmd
+ D.S &BASE_ADDR_DRAMC+0x01E4 %LE %LONG 0x00000000
+ WAIT (DATA.LONG(&BASE_ADDR_DRAMC+0x03B8)&(&spcmd))==0x00000000
+ RETURN
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/codescape_fpga_emi_init.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/codescape_fpga_emi_init.py
new file mode 100755
index 0000000..fef2f8e
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/codescape_fpga_emi_init.py
@@ -0,0 +1,1200 @@
+from imgtec import codescape
+from imgtec.console import *
+import os
+import random
+import sys
+import time
+
+dsp_bin_base = "0x0d500000"
+ramdisk_base = "0x0c500000"
+RAMDISK_SIZE = 0x1000
+CPUREG_NAME = ['zero', 'at', 't4', 't5',
+ 'a0', 'a1', 'a2', 'a3',
+ 'a4', 'a5', 'a6', 'a7',
+ 't0', 't1', 't2', 't3',
+ 's0', 's1', 's2', 's3',
+ 's4', 's5', 's6', 's7',
+ 't8', 't9', 'k0', 'k1',
+ 'gp', 'sp', 'fp', 'ra']
+
+reg_backup = []
+
+def restore_callstack(da, ex_vpe):
+ core_num = ex_vpe/3
+ vpe_num = ex_vpe%3
+ print "restore CORE"+str(core_num)+" VPE"+str(vpe_num)
+ thread = da.cores[core_num].hwthreads[vpe_num]
+ try:
+ sym_addr = thread.GetSymbol('ex_info_reg').location
+ except:
+ print "There is no exception info symbol ex_info_reg. restore abort!"
+ return
+
+ print "&ex_info_reg=",format(sym_addr)
+ target_reg_info_addr = int(sym_addr, 0) + 0x178*int(ex_vpe)
+ var_status_addr = int(sym_addr, 0) + 0x88
+ var_epc_addr = int(sym_addr, 0) + 0x88 + 0x4*2
+ tmp_addr = target_reg_info_addr
+
+ print "regs restore start .."
+ for cpu_reg in CPUREG_NAME:
+ #reg_backup = thread.ReadRegister(cpu_reg) #regs(cpu_reg)
+ reg_val = thread.memory.Read(tmp_addr)
+ time.sleep(0.1)
+ thread.WriteRegister(cpu_reg, reg_val)#regs(cpu_reg, word(tmp_addr))
+ #print cpu_reg + " : " + hex(reg_val)
+ tmp_addr += 4
+ #time.sleep(0.1)
+ thread.WriteRegister('pc', thread.memory.Read(var_epc_addr))#regs('pc', regs('epc'))
+ thread.WriteRegister('status', thread.memory.Read(var_status_addr))
+ print "regs restore done. callstack restore finish!!!"
+ print "Please open call stack region in VPE"+str(ex_vpe)
+
+def find_excep_vpe(da):
+ print "checking vpe status .."
+ thread = da.cores[0].hwthreads[0]
+ try:
+ sst_off_vpeid_addr = thread.GetSymbol('sst_offending_vpeid').location
+ #sst_off_coreid_addr = thread.GetSymbol('sst_offending_coreid').location
+ #sst_offending_vpeid
+ #sst_offending_coreid
+ #sst_offending_tcid
+ except:
+ return -1
+
+ vpe_val = thread.memory.Read(sst_off_vpeid_addr)
+ #core_val = thread.memory.Read(sst_off_coreid_addr)
+ #print "Offending vpeid = "+hex(vpe_val)
+ if vpe_val==0xffffffff: #or core_val==0xffffffff:
+ return -1
+ else:
+ return vpe_val
+
+def enable_fast_write(da):
+ # To accelerate load elf
+ # Configure C0_CDMMBASE = 0x01FC1407 to enable access
+ thread.WriteRegister('CDMMBase', 0x01FC1407)
+ # Default all segments are NC, then configure VA Bank8 to WB for speed up load elf
+ thread.memory.Write(0x1FC100D4, 0x02030202)
+ da.SetDASettingValue("Fast Monitor Address", 0x6F800000)
+ da.SetDASettingValue("Fast Writes", True)
+
+
+def disable_fast_write(da):
+ thread = da.cores[0].hwthreads[0]
+ # Restore Default all segments to NC
+ thread.memory.Write(0x1FC100D4, 0x02020202)
+ # Restore C0_CDMMBASE = 0x01FC1007
+ thread.WriteRegister('CDMMBase', 0x01FC1007)
+ da.SetDASettingValue("Fast Writes", False)
+
+
+def load_all_elf(da, thread, elf_path):
+ if(os.path.exists(elf_path) == False):
+ print "[Error] UMOLY ELF doesn't exist %s" %(elf_path)
+ return 0
+
+ print elf_path
+ time_str = time.time()
+ core_num = (thread.memory.Read(0x1F000000) & 0xFF)+1
+ print "=== Get Core Number ===: %d" %(core_num)
+ print "=== Start Loading .elf ==="
+ print "Image path: " + elf_path
+
+ for core_idx in range(core_num):
+ if(core_idx == 0):
+ # load binary only on VPE0 of 0 core
+ thread = da.cores[core_idx].hwthreads[0]
+ thread.Stop()
+ enable_fast_write(da)
+ thread.LoadProgramFile(elf_path, False, 0x83, True, "")
+ #probe('sp536')
+ #print load(elf_path,verbose=True, physical=False)
+ print "[Core%d,VPE0] Load ELF successfully" %(core_idx)
+ thread = da.cores[core_idx].hwthreads[1]
+ thread.Stop()
+ thread.LoadProgramFile(elf_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE1] Load ELF successfully" %(core_idx)
+ thread = da.cores[core_idx].hwthreads[2]
+ thread.Stop()
+ thread.LoadProgramFile(elf_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE2] Load ELF successfully" %(core_idx)
+ else:
+ thread = da.cores[core_idx].hwthreads[0]
+ thread.Stop()
+ thread.LoadProgramFile(elf_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE0] Load ELF successfully" %(core_idx)
+ thread = da.cores[core_idx].hwthreads[1]
+ thread.Stop()
+ thread.LoadProgramFile(elf_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE1] Load ELF successfully" %(core_idx)
+ thread = da.cores[core_idx].hwthreads[2]
+ thread.Stop()
+ thread.LoadProgramFile(elf_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE2] Load ELF successfully" %(core_idx)
+
+ clean_ram_disk_region(thread)
+ clean_dsp_bin_magic(thread)
+ time_end = time.time()
+ print("All loading is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+ disable_fast_write(da)
+ return 1
+
+def clean_ram_disk_region(thread):
+ global ramdisk_base
+ ram_disk_addr = 0
+ try:
+ ram_disk_addr = thread.GetSymbol('ram_disk').location
+ except:
+ ram_disk_addr = 0
+
+ if ram_disk_addr!=0:
+ print("ram_disk = %s . clean 4K .." % ram_disk_addr)
+ word(ram_disk_addr,0,RAMDISK_SIZE)
+ ramdisk_base = ram_disk_addr
+ else:
+ print "There is no ram_disk symbol in this elf!"
+
+def clean_dsp_bin_magic(thread):
+ global dsp_bin_base
+ magic_addr = 0
+ try:
+ magic_addr = thread.GetSymbol('dsp_bin_ro').location
+ except:
+ magic_addr = 0
+
+ if magic_addr!=0:
+ print("dsp_bin_addr = %s . write the addr with 0 .." % magic_addr)
+ word(magic_addr, 0)
+ dsp_bin_base = magic_addr
+ else:
+ print "There is no dsp_bin_ro symbol in this elf!"
+
+
+def load_dsp_bin(da, thread, dsp_path, dsp_addr):
+ if(os.path.exists(dsp_path) == False):
+ print "[Error] DSP BIN doesn't exist %s" %(dsp_path)
+ return
+
+ enable_fast_write(da)
+ time_str = time.time()
+ print "=== Start load dsp bin ==="
+ print "Dsp bin path: " + dsp_path
+ print "Dsp bin load address: " + dsp_addr
+
+ dsp_file = open(dsp_path, "rb")
+ dsp_hdr = dsp_file.read(4)
+ dsp_file.close()
+
+ thread = da.cores[0].hwthreads[0]
+ if dsp_hdr == b'\x4d\x4d\x4d\x01':
+ dsp_bin_size = os.path.getsize(dsp_path)
+ print "Dsp bin file size: " + str(dsp_bin_size) + " bytes"
+ print "Loading DSP bin ..."
+ thread.memory.LoadBinaryFile(dsp_path, dsp_addr, start_offset = 0, length = None)
+ else:
+ dsp_bin_size = os.path.getsize(dsp_path) - 0x200
+ print "Dsp bin file size: " + str(dsp_bin_size) + " bytes"
+ print "Loading DSP bin ..."
+ thread.memory.LoadBinaryFile(dsp_path, dsp_addr, start_offset = 0x200, length = dsp_bin_size)
+
+ time_end = time.time()
+ print("loading dsp is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+ disable_fast_write(da)
+
+
+def WDT_Disable(thread):
+ """diable WDT function
+ [in] thread, codescape thread object
+ """
+ print("WDT disable ...")
+ mdrgu = 0xA00F0000 + 0x0100
+ aprgu = 0xC0007000
+ thread.memory.Write(mdrgu, (thread.memory.Read(mdrgu) & 0xFFFFFFFC) | 0x55000000)
+ thread.memory.Write(aprgu, (thread.memory.Read(aprgu) & 0xFFFFFFFE) | 0x22000000)
+
+
+def MD_Remap(thread, adr=None):
+ """MD reamp config
+ [in] thread, codescape thread object
+ [in] adr, user specific remap address (ap infra memory map view, 32M alignment)
+ default: emi start address
+ """
+
+ inf_emi = 0x80000000 if thread.memory.Read(0xA000001C) < 0x08566094 else 0x40000000
+ print("MD_Remap(adr={:#x}) ...".format(inf_emi if adr == None else adr))
+ if adr == None:
+ inf_md = inf_emi
+ else:
+ assert (adr & 0x01FFFFFF) == 0
+ inf_md = adr
+ print("MD_Remap -> md:bank0=>ap:{:#x}, md:bank1=>ap:{:#x}, md:bank4=>ap:{:#x}".format(inf_md, inf_md+0x10000000, inf_emi))
+ # md remap bank 0
+ bnk = inf_md >> 25
+ thread.memory.Write(0xC0001300, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ thread.memory.Write(0xC0001304, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ thread.memory.Write(0xC0001308, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ thread.memory.Write(0xC000130c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+ # md remap bank 1
+ bnk = (inf_md+0x10000000) >> 25
+ thread.memory.Write(0xC0001310, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ thread.memory.Write(0xC0001314, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ thread.memory.Write(0xC0001318, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ thread.memory.Write(0xC000131c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+ # md remap bank 4
+ bnk = inf_emi >> 25
+ thread.memory.Write(0xC0001320, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ thread.memory.Write(0xC0001324, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ thread.memory.Write(0xC0001328, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ thread.memory.Write(0xC000132c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+
+
+def DRAM_INIT(thread):
+ """initialize DRAM, include emi/dramc init
+ [in] thread, codescape thread object
+ """
+
+ def reg_write(adr, val):
+ thread.memory.Write(adr, val)
+
+ print("DRAM_INIT ...")
+ tim = time.time()
+
+ # disable md to ap write secure world register protection
+ reg_bak_APC_CON = thread.memory.Read(0xC001DF00)
+ reg_bak_MAS_SEC_0 = thread.memory.Read(0xC001DB00)
+ reg_write(0xC001DF00, 0x00000000) # APC_CON[2] = DBG_MASK = 0
+ reg_write(0xC001DB00, 0x00010000) # MAS_SEC_0[16] = M16_SEC = 1
+
+ NR_RNKS=1
+ #EMI
+
+ #DRAMC0_NAO
+ #0x10234***
+ #DRAMC0
+ #0x10230***
+ #DRAMC1
+ #0x10240***
+ #DDRPHY0
+ #0x10238***
+ #DDRPHY1
+ #0x10248***
+
+ #EMI setting
+ reg_write(0xC0219000, 0x00001052) # ;0x00025052
+ reg_write(0xC0219060, 0xff000400)
+ reg_write(0xC0219020, 0x00008000)
+ reg_write(0xC0235000, 0x00001012) # ;0x00005053
+ reg_write(0xC0235010, 0x00000001)
+
+
+ #;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ reg_write(0xC0238274, 0xffffffff)
+ reg_write(0xC0248278, 0x00000000)
+ reg_write(0xC0248274, 0xffffffff)
+ reg_write(0xC023829c, 0x38030000)
+ #PLL sel
+
+ reg_write(0xC02381a0, 0x00000000)
+ reg_write(0xC02380a0, 0x00000000)
+ reg_write(0xC0238120, 0x00000000)
+ reg_write(0xC02382ac, 0x80000006)
+ reg_write(0xC02481a0, 0x00000000)
+ reg_write(0xC02480a0, 0x00000000)
+ reg_write(0xC0248120, 0x00000000)
+ reg_write(0xC02482ac, 0x80000006)
+ reg_write(0xC02382a0, 0x00000100) # ;PINMUX
+ reg_write(0xC02482a0, 0x00000100)
+ reg_write(0xC0238264, 0x00400000)
+ reg_write(0xC0238268, 0x00000040)
+ reg_write(0xC0248264, 0x00400000)
+ reg_write(0xC0248268, 0x00000040)
+ reg_write(0xC0238e18, 0x00000000)
+ reg_write(0xC0238f18, 0x01010000)
+ reg_write(0xC0239018, 0x02020000)
+ reg_write(0xC0238e68, 0x04040000)
+ reg_write(0xC0238f68, 0x05050000)
+ reg_write(0xC0239068, 0x06060000)
+ reg_write(0xC0238ec4, 0x00000c00)
+ reg_write(0xC0238fc4, 0x00000c00)
+ reg_write(0xC02393c4, 0x00000c00)
+ reg_write(0xC02394c4, 0x00000c00)
+ reg_write(0xC0238e50, 0x00000000)
+ reg_write(0xC0238f50, 0xbbbbbbbb)
+ reg_write(0xC0239050, 0xbbbbbbbb)
+ reg_write(0xC0238e54, 0x00000000)
+ reg_write(0xC0238f54, 0x0000bb00)
+ reg_write(0xC0239054, 0x0000bb00)
+ reg_write(0xC0248ea0, 0x00000000)
+ reg_write(0xC0248fa0, 0x00bbbbbb)
+ reg_write(0xC02490a0, 0x00bbbbbb)
+ reg_write(0xC0248ea4, 0x00000000)
+ reg_write(0xC0248fa4, 0x00000bbb)
+ reg_write(0xC02490a4, 0x00000bbb)
+ reg_write(0xC0248e00, 0x00000000)
+ reg_write(0xC0248f00, 0xbbbbbbbb)
+ reg_write(0xC0249000, 0xbbbbbbbb)
+ reg_write(0xC0248e04, 0x00000000)
+ reg_write(0xC0248f04, 0x0000bb00)
+ reg_write(0xC0249004, 0x0000bb00)
+ reg_write(0xC0248e50, 0x00000000)
+ reg_write(0xC0248f50, 0xbbbbbbbb)
+ reg_write(0xC0249050, 0xbbbbbbbb)
+ reg_write(0xC0248e54, 0x00000000)
+ reg_write(0xC0248f54, 0x0000bb00)
+ reg_write(0xC0249054, 0x0000bb00)
+ reg_write(0xC0238e1c, 0x00000c00)
+ reg_write(0xC0238f1c, 0x00000c00)
+ reg_write(0xC023901c, 0x00000c00)
+ reg_write(0xC0238e6c, 0x000f0f00)
+ reg_write(0xC0238f6c, 0x000f0f00)
+ reg_write(0xC023906c, 0x000f0f00)
+ reg_write(0xC0248ec4, 0x00000f0f)
+ reg_write(0xC0248fc4, 0x00000f0f)
+ reg_write(0xC02490c4, 0x00000f0f)
+ reg_write(0xC0248e1c, 0x000f0f00)
+ reg_write(0xC0248f1c, 0x000f0f00)
+ reg_write(0xC024901c, 0x000f0f00)
+ reg_write(0xC0248e6c, 0x000f0f00)
+ reg_write(0xC0248f6c, 0x000f0f00)
+ reg_write(0xC024906c, 0x000f0f00)
+ reg_write(0xC0238128, 0x00001010)
+ reg_write(0xC023812c, 0x01111010)
+ reg_write(0xC0238130, 0x010c10d0)
+ reg_write(0xC023812c, 0x03111010)
+ reg_write(0xC02381a4, 0x0000008c)
+ #TINFO="SHL ddrphy chA reset release"
+ reg_write(0xC02381b0, 0x00080010) # ;SER MODE
+ reg_write(0xC0238d04, 0x00000101)
+ reg_write(0xC0238d08, 0x00000101)
+ reg_write(0xC0239204, 0x00000101)
+ reg_write(0xC0239208, 0x00000101)
+ reg_write(0xC02380a4, 0x0000008c)
+ reg_write(0xC02380b0, 0x00080010) # ;SER MODE
+ reg_write(0xC0238c04, 0x00000101)
+ reg_write(0xC0238c08, 0x00000101)
+ reg_write(0xC0239104, 0x00000101)
+ reg_write(0xC0239108, 0x00000101)
+ reg_write(0xC02481a8, 0x00001010)
+ reg_write(0xC02481ac, 0x01111010)
+ reg_write(0xC02481b0, 0x010c10d0)
+ reg_write(0xC02481ac, 0x03111010)
+ reg_write(0xC02480a8, 0x00001010)
+ reg_write(0xC02480ac, 0x01111010)
+ reg_write(0xC02480b0, 0x010c10d0)
+ reg_write(0xC02480ac, 0x03111010)
+ reg_write(0xC0248128, 0x00001010)
+ reg_write(0xC024812c, 0x01111010)
+ reg_write(0xC0248130, 0x010c10d0)
+ reg_write(0xC024812c, 0x03111010)
+ #PLL
+
+ reg_write(0xC0238c18, 0x44000000)
+ reg_write(0xC0239118, 0x04000000)
+ reg_write(0xC0238c98, 0x44000000)
+ reg_write(0xC0239198, 0x04000000)
+ reg_write(0xC0238d18, 0x44000000)
+ reg_write(0xC0239218, 0x04000000)
+ reg_write(0xC0248c18, 0x44000000)
+ reg_write(0xC0249118, 0x04000000)
+ reg_write(0xC0248c98, 0x44000000)
+ reg_write(0xC0249198, 0x04000000)
+ reg_write(0xC0248d18, 0x44000000)
+ reg_write(0xC0249218, 0x04000000)
+ reg_write(0xC0238da0, 0x00000000)
+ reg_write(0xC02392a0, 0x00000000)
+ # DLL
+
+ reg_write(0xC0238124, 0x0000051e)
+ reg_write(0xC02481a4, 0x0000051e)
+ #TINFO="SHL ddrphy chB reset release"
+ reg_write(0xC02480a4, 0x0000051e)
+ reg_write(0xC0248124, 0x0000051e)
+ reg_write(0xC0238194, 0x00660600)
+ reg_write(0xC0238094, 0xc0660600)
+ reg_write(0xC0238114, 0xc0660600)
+ reg_write(0xC0248194, 0xc0660600)
+ reg_write(0xC0248094, 0xc0660600)
+ reg_write(0xC0248114, 0xc0660600)
+ reg_write(0xC02381b8, 0x00180101)
+ reg_write(0xC023826c, 0x00000000)
+ reg_write(0xC02481b8, 0x00180101)
+ reg_write(0xC024826c, 0x00000000)
+ reg_write(0xC0238d14, 0x00000000)
+ reg_write(0xC0239214, 0x00000000)
+ reg_write(0xC0239714, 0x00000000)
+ reg_write(0xC0239c14, 0x00000000)
+ reg_write(0xC0248d14, 0x00000000)
+ reg_write(0xC0249214, 0x00000000)
+ reg_write(0xC0249714, 0x00000000)
+ reg_write(0xC0249c14, 0x00000000)
+
+ time.sleep(0.001)
+
+ reg_write(0xC023800c, 0x006d0000)
+ reg_write(0xC0238180, 0x0000000c)
+ reg_write(0xC0238080, 0x00000009)
+ reg_write(0xC0238100, 0x00000009)
+ reg_write(0xC0248180, 0x00000009)
+ reg_write(0xC0248080, 0x00000009)
+ reg_write(0xC0248100, 0x00000009)
+
+ time.sleep(0.001)
+
+ reg_write(0xC0238000, 0x80000000)
+ reg_write(0xC0238004, 0x80000000)
+ reg_write(0xC0238004, 0x00000000)
+
+ time.sleep(0.001)
+
+ reg_write(0xC0238da4, 0x00019200)
+
+ time.sleep(0.001)
+
+ reg_write(0xC0238194, 0x00660e00)
+
+ time.sleep(0.001)
+
+ reg_write(0xC0238094, 0xc0660e00)
+ reg_write(0xC0238114, 0xc0660e00)
+ reg_write(0xC0248194, 0xc0660e00)
+ reg_write(0xC0248094, 0xc0660e00)
+ reg_write(0xC0248114, 0xc0660e00)
+ reg_write(0xC0238284, 0x0000001f)
+
+ time.sleep(0.001)
+
+ reg_write(0xC0238124, 0x0001051e)
+ reg_write(0xC02481a4, 0x0001051e)
+ reg_write(0xC02480a4, 0x0001051e)
+ reg_write(0xC0248124, 0x0001051e)
+ reg_write(0xC02382a0, 0x8100018c)
+ reg_write(0xC02482a0, 0x8100018c)
+ reg_write(0xC02381b8, 0x00040101)
+ reg_write(0xC02381b4, 0x00000000)
+ reg_write(0xC02380b4, 0x00000000)
+ reg_write(0xC0238134, 0x00000000)
+ reg_write(0xC0238c1c, 0x00200000) # ; WJ: LP3
+ reg_write(0xC02481b4, 0x00000000)
+ reg_write(0xC02480b4, 0x00000000)
+ reg_write(0xC0248134, 0x00000000)
+ reg_write(0xC0248c1c, 0x00200000) # ; WJ: LP3
+ reg_write(0xC02300dc, 0x00051008)
+ #;D.S EAXI:0x1024000dc %LE %LONG 0x00050008
+ reg_write(0xC0230000, 0x02101000) # ;[24]=LP2_EN , [25]=LP3_EN, [26]=LP4_EN
+ reg_write(0xC0230640, 0xa688049f)
+ reg_write(0xC0230660, 0x00030053)
+ reg_write(0xC023004c, 0x25712000)
+ reg_write(0xC0230680, 0x00000000)
+ reg_write(0xC0230684, 0x00000000)
+ reg_write(0xC0230688, 0x00000000)
+ reg_write(0xC023068c, 0x00000000)
+ reg_write(0xC0230690, 0x11111011)
+ reg_write(0xC0230694, 0x01101111)
+ reg_write(0xC0230698, 0x11111111)
+ reg_write(0xC023069c, 0x11111111)
+ reg_write(0xC02306a0, 0x11111111) # ;TXDLY DQS
+ reg_write(0xC02306a4, 0x66667777)
+ reg_write(0xC023082c, 0x11111111) # ;TXDLY DQ
+ reg_write(0xC0230830, 0x11111111) # ;TXDLY DQM
+ reg_write(0xC0230834, 0x66667777)
+ reg_write(0xC0230838, 0x66667777)
+ #D.S EAXI:0x1023092c %LE %LONG 0x22222222
+ #D.S EAXI:0x10230930 %LE %LONG 0x22222222
+ #D.S EAXI:0x10230934 %LE %LONG 0x66667777
+ #D.S EAXI:0x10230938 %LE %LONG 0x66667777
+ #D.S EAXI:0x10230a2c %LE %LONG 0x22222222
+ #D.S EAXI:0x10230a30 %LE %LONG 0x22222222
+ #D.S EAXI:0x10230a34 %LE %LONG 0x66667777
+ #D.S EAXI:0x10230a38 %LE %LONG 0x66667777
+ reg_write(0xC023081c, 0x00000000)
+ reg_write(0xC0230820, 0x00000000)
+ #D.S EAXI:0x1023091c %LE %LONG 0x00000000
+ #D.S EAXI:0x10230920 %LE %LONG 0x00000000
+ #D.S EAXI:0x10230a1c %LE %LONG 0x00000000
+ #D.S EAXI:0x10230a20 %LE %LONG 0x66666666
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ reg_write(0xC0230200, 0xf0100000) # ;[31]=DQSIEN MODE
+ reg_write(0xC0230048, 0x08000000)
+ reg_write(0xC0230678, 0xc0000000)
+ reg_write(0xC0230600, 0x09030b06)
+ reg_write(0xC0230604, 0x14090901)
+ reg_write(0xC0230608, 0x0c050201)
+ reg_write(0xC023060c, 0x00490019)
+ reg_write(0xC0230614, 0x01000606)
+ reg_write(0xC023061c, 0x02030408)
+ reg_write(0xC0230620, 0x02000400)
+ reg_write(0xC0230648, 0x9007320f)
+ reg_write(0xC0230644, 0x00000b0d) # ;DATLAT
+ reg_write(0xC0230000, 0x02111000) # ;[24]=LP2_EN , [25]=LP3_EN, [26]=LP4_EN
+ reg_write(0xC0230004, 0x20002000)
+ reg_write(0xC0230008, 0x81080000)
+ reg_write(0xC023000c, 0x0002cf13)
+ reg_write(0xC0230010, 0x00000080)
+ reg_write(0xC0230020, 0x00000009)
+ reg_write(0xC0230024, 0x80030000)
+ reg_write(0xC0230038, 0x80000106)
+ reg_write(0xC0230040, 0x3000000c)
+ reg_write(0xC023004c, 0x25714001)
+ reg_write(0xC0230064, 0x25b1f1cf) # ;REFRDIS=1
+ reg_write(0xC02300b0, 0x04300000)
+ reg_write(0xC0230200, 0xf0310000) # ;[31]=DQSIEN MODE
+ reg_write(0xC0230658, 0x21200001)
+ reg_write(0xC0230800, 0x00000002)
+ #D.S EAXI:0x10230900 %LE %LONG 0x00000002
+ #D.S EAXI:0x10230a00 %LE %LONG 0x00000002
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC0230824, 0x10101010) # ;GATE WINDOW unit:2T
+ reg_write(0xC0230828, 0x17171717)
+ #D.S EAXI:0x10230924 %LE %LONG 0x11111111
+ #D.S EAXI:0x10230928 %LE %LONG 0x42424242
+ #D.S EAXI:0x10230a24 %LE %LONG 0x32323232
+ #D.S EAXI:0x10230a28 %LE %LONG 0x06060606
+ #;D.S EAXI:0x10240a24 %LE %LONG 0x00000000; ;GATE WINDOW unit:2T
+ #;D.S EAXI:0x10240a28 %LE %LONG 0x53535353
+ #;D.S EAXI:0x10240b24 %LE %LONG 0x32323232
+ #;D.S EAXI:0x10240b28 %LE %LONG 0x06060606
+ #;D.S EAXI:0x10240c24 %LE %LONG 0x32323232
+ #;D.S EAXI:0x10240c28 %LE %LONG 0x06060606
+ # 33961 === over_write_setting_begin ===
+ # 33961 === over_write_setting_end ===
+ reg_write(0xC0230034, 0x00731010)
+ reg_write(0xC0230024, 0x80030050)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC023005c, 0x00003f00)
+ reg_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC0230060, 0x00000000)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC023005c, 0x00000aff)
+ reg_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC0230060, 0x00000000)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC023005c, 0x00000183)
+ reg_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC0230060, 0x00000000)
+ reg_write(0xC023005c, 0x00000206) # ;RL/WL
+ reg_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC0230060, 0x00000000)
+ reg_write(0xC0230028, 0x00000034)
+ reg_write(0xC023005c, 0x00000b03)
+ reg_write(0xC0230060, 0x00000001)
+
+ #=============================RANK1 MRW==================
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #D.S EAXI:0x1023005c %LE %LONG 0x01003f00
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000aff
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000183
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000206; ;RL/WL
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000b03
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #================== end RANK1 MRW =====================
+
+
+ reg_write(0xC0230060, 0x00000000)
+ reg_write(0xC0230024, 0x80030040)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ reg_write(0xC023005c, 0x00000400)
+
+
+
+ reg_write(0xC023064c, 0x00000005)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC023004c, 0x25774001)
+ reg_write(0xC0230034, 0x00731810)
+ reg_write(0xC0230024, 0x80030000)
+ reg_write(0xC0230004, 0x20082000)
+ reg_write(0xC0230058, 0x00000a56)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ reg_write(0xC023064c, 0x00ff0005)
+ reg_write(0xC0230064, 0x25b1f1cf) # ;REFRDIS=1
+ reg_write(0xC0230610, 0x22653055)
+ reg_write(0xC023004c, 0x45774001)
+ reg_write(0xC0230048, 0x48000000)
+ reg_write(0xC023005c, 0x80000400)
+ reg_write(0xC0230038, 0xc0000107)
+ reg_write(0xC023020c, 0x00010002)
+ reg_write(0xC0230204, 0x00014e00)
+ reg_write(0xC0230094, 0x00100000)
+ reg_write(0xC0230098, 0x00004000)
+ reg_write(0xC023009c, 0x12010480)
+ # 54377 === DE initial sequence done ===
+
+ #selftest
+ #D.S EAXI:0x1023009C %LE %LONG 0x02010080
+ #D.S EAXI:0x10230094 %LE %LONG 0x00100000
+ #D.S EAXI:0x10230098 %LE %LONG 0x00004000
+ #D.S EAXI:0x1023009C %LE %LONG 0x82010080
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ # restore md to ap write secure world register protection
+ reg_write(0xC001DB00, reg_bak_MAS_SEC_0) # MAS_SEC_0[16] = M16_SEC = 0
+ reg_write(0xC001DF00, reg_bak_APC_CON) # APC_CON[2] = DBG_MASK = 1
+
+ print("DRAM_INIT -> elapsed time: {:.3f}".format(time.time()-tim))
+
+
+def DRAM_TEST(thread):
+ """dram test
+ [in] thread, codescape thread object
+ """
+ def _dram_test_by_ice(thread):
+ """simple dram test by ice
+ [in] thread, codescape thread object
+ """
+ adr, siz, omx = 0x0, 0x1000, 0x1000
+ print("_dram_test_by_ice(adr={:#x}, siz={:#x}) ...".format(adr, siz))
+
+ # fix pattern
+ tim = time.time()
+ ptn, inc = 0x55AAAA55, 0
+ print("fix pattern test, {:#010x} ...".format(ptn))
+ idx, rem, err = adr, siz, 0
+ while rem:
+ one = omx if rem > omx else rem
+ thread.memory.Fill(idx, element_size=4, element_count=one>>2, initial_value=ptn, increment=inc)
+ idx += one
+ rem -= one
+ idx, rem = adr, siz
+ while rem:
+ one = omx if rem > omx else rem
+ if not thread.memory.Check(idx, element_size=4, element_count=one>>2, initial_value=ptn, increment=inc):
+ print("-> {:#x}~{:#x} fail ...>\"<".format(idx, idx+one-1))
+ err += 1
+ idx += one
+ rem -= one
+ print("-> elapsed {:.3f} sec, {}".format(time.time()-tim, "fail ...>\"<" if err else "pass"))
+
+ # random pattern
+ print("random pattern test")
+ tim = time.time()
+ ptn = [random.randint(0x0, 0xFFFFFFFF) for _ in range(siz>>2)]
+ idx, rem, err = adr, siz, 0
+ while rem:
+ one = omx if rem > omx else rem
+ thread.memory.Write(idx, ptn[(idx-adr)>>2:(idx-adr+one)>>2])
+ idx += one
+ rem -= one
+ idx, rem, dat = adr, siz, []
+ while rem:
+ one = omx if rem > omx else rem
+ dat.extend(thread.memory.Read(idx, count=one>>2))
+ idx += one
+ rem -= one
+ for idx in range(siz>>2):
+ if ptn[idx] != dat[idx]:
+ print("{:#010x}: {:#010x} -> {:#010x} mismatch".format(idx*4, ptn[idx], dat[idx]))
+ err += 1
+ print("-> elapsed {:.3f} sec, {}".format(time.time()-tim, "fail ...>\"<" if err else "pass"))
+
+ def _dram_test_by_trfg(thread, ctrl=0, loop=2):
+ """use traffic-gen (TRFG) *4 to test DRAM
+ [in] thread, codescape thread object
+ [in] ctrl, all-0: config and start
+ bit-0: start
+ bit-1: pause
+ bit-2: resume
+ [in] loop, test loop, 0:infinite, others:N-times
+ [out] 0:success, 1:fail
+ """
+ TRFG_BASE = 0xC0215000 # TRFG 0~3 offset 0x100
+
+ if ctrl != 0:
+ thread.memory.Write(TRFG_BASE+0x000, ctrl)
+ thread.memory.Write(TRFG_BASE+0x100, ctrl)
+ thread.memory.Write(TRFG_BASE+0x200, ctrl)
+ thread.memory.Write(TRFG_BASE+0x300, ctrl)
+ print("TRFG control done ...")
+ return 0
+
+ print("TRFG config and start ...")
+ for idx in range(4):
+ base = TRFG_BASE + 0x100 * idx
+ start_addr = 0x01000000 * idx
+ pat_ctl = 0x07FF0017 + ((loop & 0xF) << 8)
+ # TRFG_STRAT_CTL, [0]:start, [1]:pause, [2]:resume
+ thread.memory.Write(base+0x00, 0x00000000)
+ # TRFG_INIT_PAT_W3
+ thread.memory.Write(base+0x04, 0x5A5A5A5A)
+ # TRFG_INIT_PAT_W2
+ thread.memory.Write(base+0x08, 0xA5A5A5A5)
+ # TRFG_INIT_PAT_W1
+ thread.memory.Write(base+0x0C, 0x5A5A5A5A)
+ # TRFG_INIT_PAT_W0
+ thread.memory.Write(base+0x10, 0xA5A5A5A5)
+ # TRFG_START_ADDR
+ thread.memory.Write(base+0x14, start_addr)
+ # TRFG_TEST_LEN * 16 byte
+ thread.memory.Write(base+0x18, 0x00040000)
+ # TRFG_PAT_CTL, [11:8]:test_loop, [5:4]:pat_mode
+ thread.memory.Write(base+0x1C, pat_ctl)
+ # TRFG_BUS_CTL, [13:10]:domain, [3:0]:burst_len
+ thread.memory.Write(base+0x20, 0x00000003)
+ # TRFG_STRAT_CTL, [0]:start, [1]:pause, [2]:resume
+ thread.memory.Write(base+0x00, 0x00000001)
+
+ # Wait done
+ print("Wait done")
+ trfg = [None] * 4
+ while None in trfg:
+ print(".")
+ time.sleep(1)
+ for idx in range(4):
+ base = TRFG_BASE + 0x100 * idx
+ if trfg[idx] != None:
+ continue
+ if (thread.memory.Read(base+0x24) & 0x1) == 0x1:
+ continue
+ if (thread.memory.Read(base+0x24) & 0x4) == 0x0:
+ print("-> TRFG {} test fail:".format(idx))
+ print("FAIL_ADDR = {:#010x}".format(thread.memory.Read(base+0x28)))
+ print("EXP_DATA_W3~0 = " + \
+ ", ".join(["{:#010x}".format(thread.memory.Read(base+0x2C+_*4)) for _ in range(4)]))
+ print("FAIL_DATA_W3~0 = " +\
+ ", ".join(["{:#010x}".format(thread.memory.Read(base+0x3C+_*4)) for _ in range(4)]))
+ trfg[idx] = 1
+ else:
+ trfg[idx] = 0
+
+ if trfg == [0,0,0,0]:
+ print("-> TRFG dram test pass ...^_^")
+ return 0
+ else:
+ print("-> TRFG dram test fail ...>'<")
+ return 1
+
+ print("DRAM_TEST() ...")
+ if thread.memory.Read(0xA000001C) < 0x08623511:
+ _dram_test_by_ice(thread)
+ else:
+ _dram_test_by_trfg(thread)
+
+
+def Head8478120_workaround(thread):
+
+ print("Workaround for bitfile(Head8478120) bootslave bug ...")
+ thread.memory.Write(0xA0061118, 0x5500)
+ thread.memory.Write(0xA0061110, 0x9fb40000)
+ thread.memory.Write(0xA0061114, 0x1)
+
+ thread.memory.Write(0xA0061124, 0x5500)
+ thread.memory.Write(0xA006111c, 0x9fb80000)
+ thread.memory.Write(0xA0061120, 0x1)
+
+ thread.memory.Write(0xA0061130, 0x5500)
+ thread.memory.Write(0xA0061128, 0x9fbc0000)
+ thread.memory.Write(0xA006112c, 0x1)
+
+
+if __name__ == "__main__":
+ print "=== Start Initializing ==="
+ umolya_path = ""
+ dsp_path = ""
+ da = codescape.GetFirstProbe()
+ print "Get probe name = %s" %(da.name)
+ probe(da.name)
+ #reset(probe(da.name))
+ #autodetect()
+
+ #config('lazy Freeze',0)
+ #cmdall(halt)
+
+ #print "Enlarge timeout for stability..."
+ #da.SetDASettingValue("Disable MMU Checking", True)
+ #da.SetDASettingValue("apb timeout",500000)
+ #da.SetDASettingValue("Enter Debug Timeout",50000)
+ #da.SetDASettingValue("reset ack timeout",50000)
+ #da.SetDASettingValue("mdh valid retry step",100000)
+ #da.SetDASettingValue("Fast Writes", False)
+
+ thread = da.cores[0].hwthreads[0]
+ core_num = (thread.memory.Read(0x1F000000) & 0xFF)+1
+ print "Get Core Number = %d" %(core_num)
+ #thread = da.cores[0].hwthreads[0]
+ #thread.Stop()
+
+ print "Stop all cores ..."
+ for idx in reversed(range(core_num)):
+ #thread = da.cores[idx].hwthreads[0]
+ #thread.Stop()
+ da.cores[idx].StopAll(False)
+
+ #da.SetDASettingValue("Lock Monitor in Cache", False)
+
+ print "Enable CPU MO port ..."
+ thread.memory.Write(0x1F000020, 0xF)
+ thread.memory.Write(0x1F000090, 0xA0000000)
+ thread.memory.Write(0x1F000098, 0xE0000002)
+ thread.memory.Write(0x1F0000A0, 0xC0000000)
+ thread.memory.Write(0x1F0000A8, 0xC0000002)
+
+ da.SetDASettingValue("Fast Monitor Address", 0x6F800000)
+ da.SetDASettingValue("Fast Writes", False)
+ da.SetDASettingValue("Fast Reads", False)
+
+ time_str = time.time()
+ WDT_Disable(thread)
+ DRAM_INIT(thread)
+ MD_Remap(thread)
+ #Head8478120_workaround(thread)
+ #DRAM_TEST(thread)
+
+ #clear dsp header
+ #print("Clear DSP Header...")
+ #thread.memory.Write(0x0D500000, 0)
+ #thread.memory.Write(0x00080000, 0)
+
+ #print("Clear NVRAM Header...")
+ #Only for BIANCO
+ #thread.memory.Write(0x0D8001FC, 0)
+
+ time_end = time.time()
+ print("Total elapsed time: {:.3f} sec".format(time_end-time_str))
+
+ if codescape.environment == "codescape":
+
+ if codescape.is_script_region:
+ region_thread = codescape.GetRegionThread()
+ # This is a script region, set up events to wait for thread halted
+ import wx
+ class Frame(wx.Frame):
+
+ dsp_bin_addr = dsp_bin_base
+ textctrl = 0
+ restore_callstack_btn = 0
+ def __init__(self, parent, thread):
+ wx.Frame.__init__(self, parent, title="[ModemOnly]LoadBin&Symbol")
+
+ # Initialize UI
+ button_width = 80
+ border_size = 6
+
+ load_all_elf_btn = wx.Button(self, pos=(0, 0), label='Load elf', size=(button_width,-1))
+ load_all_elf_btn.Bind(wx.EVT_BUTTON, self.on_load_all_elf_button)
+
+ button_width = 100
+ border_size = 6
+ load_dsp_btn = wx.Button(self, pos=(0, 35), label='Load DSP Bin', size=(button_width,-1))
+ load_dsp_btn.Bind(wx.EVT_BUTTON, self.on_load_dsp_button)
+
+ statictext = wx.StaticText(self, pos=(110, 40), label="dsp address:")
+
+ button_width = 120
+ border_size = 6
+ Frame.restore_callstack_btn = wx.Button(self, pos=(0, 70), label='Restore CallStack', size=(button_width,-1))
+ Frame.restore_callstack_btn.Bind(wx.EVT_BUTTON, self.on_restore_callstack_button)
+ statictext2 = wx.StaticText(self, pos=(125, 75), label="// use when exception")
+ Frame.restore_callstack_btn.Disable()
+
+ Frame.textctrl = wx.TextCtrl(self,pos=(190, 37), value = self.dsp_bin_addr)
+ Frame.textctrl.Bind(wx.EVT_TEXT, self.OnTextChanged)
+
+
+ # load all elf
+ def on_load_all_elf_button(self, event):
+ #myobject = event.GetEventObject()
+ #myobject.Disable()
+ da.SetDASettingValue("Fast Reads", True)
+ global dsp_bin_base
+ fileDialog = wx.FileDialog(self)
+ fileDialog.ShowModal()
+ umolya_path = fileDialog.GetPath()
+ fileDialog.Destroy()
+ thread = da.cores[0].hwthreads[0]
+ if load_all_elf(da, thread, umolya_path)==1:
+ Frame.restore_callstack_btn.Enable()
+ Frame.dsp_bin_addr = dsp_bin_base
+ Frame.textctrl.SetValue(Frame.dsp_bin_addr)
+ da.SetDASettingValue("Fast Reads", False)
+ #config('lazy Freeze',1)
+ #myobject.Enable()
+
+ # load dsp bin
+ def on_load_dsp_button(self, event):
+ myobject = event.GetEventObject()
+ myobject.Disable()
+ da.SetDASettingValue("Fast Reads", True)
+ print "Select dsp bin...."
+ fileDialog = wx.FileDialog(self)
+ fileDialog.ShowModal()
+ dsp_path = fileDialog.GetPath()
+
+ thread = da.cores[0].hwthreads[0]
+ load_dsp_bin(da, thread, dsp_path,self.dsp_bin_addr)
+ da.SetDASettingValue("Fast Reads", False)
+ myobject.Enable()
+
+ def OnTextChanged(self, event):
+ Frame.dsp_bin_addr = event.String
+ #print "Dsp address set to " + self.dsp_bin_addr
+
+ def on_restore_callstack_button(self, event):
+ myobject = event.GetEventObject()
+ myobject.Disable()
+ da.SetDASettingValue("Fast Reads", True)
+ cmdall(halt)
+ ex_vpe = find_excep_vpe(da)
+ if ex_vpe==-1:
+ print "There is no vpe enter exception!"
+ else:
+ restore_callstack(da, ex_vpe)
+ da.SetDASettingValue("Fast Reads", False)
+ myobject.Enable()
+
+ app = wx.App()
+ frame = Frame(None, region_thread);
+ frame.Show()
+ app.MainLoop()
+ sys.exit()
+ else:
+ if (len(sys.argv) == 2):
+ umolya_path = sys.argv[1]
+ load_all_elf(da, thread, umolya_path)
+ else:
+ # WDT_Disable and DRAM_INIT done
+ sys.exit("[Reminder] Remember to load .elf")
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/APOLLO_EVB.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/APOLLO_EVB.launch
new file mode 100755
index 0000000..aa3527d
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/APOLLO_EVB.launch
@@ -0,0 +1,62 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="["SPV_memset_size_profile[0]","SPV_memset_profile_cnt","SPV_memset_lr_profile[0]"]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.ui.focus_threads" value=""/>
+<stringAttribute key="com.mediatek.ide.dsf.mvpu.dbg_file" value=""/>
+<stringAttribute key="com.mediatek.ide.dsf.mvpu.pattern_file" value=""/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value=""/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.cache.FilePath" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.cache.gdbIndexElf" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.LocalTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.debuggerIpAddress" value="localhost"/>
+<intAttribute key="com.mediatek.ide.util.debuggerPortNumber" value="3333"/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.substitute_path_no_translate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="MT6297_Chip"/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.args" value="-f board/mips/mt6297_mips_chip.cfg -c "adapter_khz 10000""/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.cmds" value=""/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.widget.args" value="{"Clock_10000":"10000"}"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="attach"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
+<booleanAttribute key="org.eclipse.debug.core.capture_output" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_OUTPUT_ON" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/SSButton.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/SSButton.act
new file mode 100755
index 0000000..12d8920
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/SSButton.act
@@ -0,0 +1,14 @@
+<Customize>
+ <Action name="LoadDSP">
+ <GDBSource>coretracer_load_dsp.py</GDBSource>
+ </Action>
+ <Action name="SWLA">
+ <GDBSource>coretracer_swla.py</GDBSource>
+ </Action>
+ <Action name="restoreCallStack">
+ <GDBSource>coretracer_restore_callstack.py</GDBSource>
+ </Action>
+ <Action name="DspExceptionInfo">
+ <GDBSource>../../../dsp_debug_info_CoreTracer.py</GDBSource>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/TCF.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/TCF.py
new file mode 100755
index 0000000..bb8c771
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/TCF.py
@@ -0,0 +1,172 @@
+import getopt
+from multiprocessing import Queue
+import socket
+import sys
+from threading import Thread
+import time
+
+SPLITTER = '\x00'
+EOL = '\x03\x01'
+HEADER = '\x03\x03'
+LEN_EOL = len((SPLITTER + EOL))
+
+class Event():
+ def __init__(self, args):
+ b = bytearray(args).split(SPLITTER.encode('utf_8'))
+ self.servicename = b[1]
+ self.eventname = b[2]
+ self.data = b[3]
+ self.elements = b[3:]
+
+ def getServiceName(self):
+ return self.servicename.decode('utf_8')
+
+ def getEventName(self):
+ return self.eventname.decode('utf_8')
+
+ def getData(self):
+ return self.data.decode('utf_8')
+
+ def getElement(self, index):
+ if len(self.elements) == 0:
+ return ''
+ return self.elements[index]
+
+ def toString(self):
+ datastr = ''
+ for b in self.elements:
+ if not b == EOL:
+ datastr = datastr + ' ' + b.decode('utf_8')
+ return 'Event ' + self.getServiceName() + ' ' + self.getEventName() + ' ' + datastr
+
+class Result():
+ def __init__(self, args):
+ b = bytearray(args).split(SPLITTER.encode('utf_8'))
+ self.type = b[0]
+ self.token = b[1]
+ self.data = b[2]
+ self.elements = b[2:]
+
+ def getType(self):
+ return self.type.decode('utf_8')
+
+ def getToken(self):
+ return self.token.decode('utf_8')
+
+ def getData(self):
+ return self.data.decode('utf_8')
+
+ def getElement(self, index):
+ if len(self.elements) == 0:
+ return ''
+ return self.elements[index]
+
+ def toString(self):
+ datastr = ''
+ for b in self.elements:
+ if not b == EOL:
+ datastr = datastr + ' ' + b.decode('utf_8')
+ return self.getType() + ' ' + self.getToken() + ' ' + datastr
+
+class TCFThread(Thread):
+ def __init__(self, host='localhost', port='1534'):
+ Thread.__init__(self)
+ try:
+ opts, args = getopt.getopt(sys.argv[1:],"h:p:",["host=","port="])
+ for opt, arg in opts:
+ if opt in ("-h", "--host"):
+ host = arg
+ elif opt in ("-p", "--port"):
+ port = int(arg)
+ except getopt.GetoptError:
+ pass
+ self.tcf_terminator = (SPLITTER + EOL).encode('utf_8')
+ self.tcf = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+ self.tcf.connect((host, int(port)))
+ self.queue = Queue()
+ self.send(['E','Locator','Hello','["ZeroCopy"]'])
+
+ def run(self):
+ remain = None
+ while 1:
+ try:
+ data = self.tcf.recv(1024)
+ if remain == None:
+ remain = data
+ else:
+ remain = remain + data
+
+ if bytearray(data).endswith(self.tcf_terminator):
+ res, rem = getData(remain)
+ if bytearray(res).startswith('E'.encode('utf_8')):
+ self.queue.put(Event(res))
+ elif bytearray(res).startswith('R'.encode('utf_8')):
+ self.queue.put(Result(res))
+ remain = rem
+ except:
+ break
+ time.sleep(0.1)
+ self.tcf.close()
+
+ def get(self):
+ if not self.queue.empty():
+ return self.queue.get()
+ else:
+ return None
+
+ def send(self, args):
+ for arg in args:
+ self.tcf.send(str(arg + SPLITTER).encode('utf_8'))
+ self.tcf.send(EOL.encode('utf_8'))
+
+ def rawsend(self, rawarg):
+ self.tcf.send(rawarg)
+
+ def close(self):
+ self.tcf.shutdown(1)
+ self.tcf.close()
+
+def getData(arg):
+ data = bytearray(arg)
+ result = None
+ remain = None
+ if data.startswith(HEADER.encode('utf_8')):
+ ind = data.index(HEADER.encode('utf_8'))+2
+ leng, cnt = getDataLength(data, ind, 0)
+ ind = ind + cnt + 1
+ result = data[ind:ind+leng-1]
+ remain = data[ind+leng-1:]
+ else:
+ ind = data.index((SPLITTER + EOL).encode('utf_8'))
+ if not ind == -1:
+ result = data[:ind]
+ remain = data[ind:]
+ else:
+ result = None
+ remain = data
+
+ if not remain == None and bytearray(remain).startswith((SPLITTER + EOL).encode('utf_8')):
+ remain = remain[LEN_EOL:]
+
+# print('result: \'' + str(result) + '\'')
+# print('remain: \'' + str(remain) + '\'')
+# sys.stdout.flush()
+ return result, remain
+
+def getDataLength(_rec, ind, count):
+ rec_bytes = bytearray(_rec);
+ leng = rec_bytes[ind]
+ mulp = 0
+ if count == 0:
+ mulp = 1
+ else:
+ mulp = 128 * count
+
+ if leng & 0x80 == 0:
+ return leng * mulp, count
+ else:
+ num, cnt = getDataLength(rec_bytes, ind + 1, count + 1)
+ return ((leng & 0x7f) * mulp) + num, cnt
+
+def doEcaspe(arg):
+ return str(arg).replace('\\', '\\\\').replace('\"', '\\\"')
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/TCF.pyc b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/TCF.pyc
new file mode 100755
index 0000000..f47f3c8
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/TCF.pyc
Binary files differ
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/coretracer_basic_init.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/coretracer_basic_init.py
new file mode 100755
index 0000000..12d261d
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/coretracer_basic_init.py
@@ -0,0 +1,213 @@
+import sys
+import time
+import os
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+
+#MD Side
+AP_REG_BASE=0xC0000000
+MD_REG_BASE=0xA0000000
+
+#AP side
+#AP_REG_BASE=0x10000000
+#MD_REG_BASE=0x20000000
+
+def switch_to_axi_mode():
+ print("Switch to AXI port ..")
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ mem_value = mem_value[12:23]
+ hex_int = int(mem_value, 16)
+ return hex_int
+
+def WDT_Disable():
+ """diable WDT function
+ [in] thread, codescape thread object
+ """
+ print("WDT disable ..")
+ mdrgu = 0xA00F0000 + 0x0100
+ aprgu = 0xC0007000
+ memory_write(mdrgu, (memory_read(mdrgu) & 0xFFFFFFFC) | 0x55000000)
+ memory_write(aprgu, (memory_read(aprgu) & 0xFFFFFFFE) | 0x22000000)
+
+def MD_SRCLKENA():
+ print("MD_SRCLKENA config ..")
+ """
+ INFRA_MISC2
+ [3:0] : mdsrc_req_0_en = 4'b0001
+ [7:4] : mdsrc_req_1_en = 4'b0010
+ """
+ infra_misc2_addr = 0x10001f0c
+ memory_write(infra_misc2_addr, (memory_read(infra_misc2_addr) & 0xFFFFFF00) | 0x21)
+
+ """
+ SRCLKEN_O1 Force RF On
+ """
+ addr1 = 0xC0006000
+ addr2 = 0xC0006008
+ memory_write(addr1, 0x0B160001) # magic key
+ memory_write(addr2, memory_read(addr2) | (1<<21) ) #set bit[21]
+
+def Config_26M_Quality():
+ print("Config 26M Quality ..")
+ addr = 0xC000C018
+ memory_write(addr, memory_read(addr) | 0x3 ) # set bit[1:0] = 2'b11
+ addr = 0xC000C00C
+ memory_write(addr, memory_read(addr) | 0x3 ) # set bit[1:0] = 2'b11
+ addr = 0xC000C000
+ memory_write(addr, memory_read(addr) | 0x3 ) # set bit[1:0] = 2'b11
+
+def MD_Remap(adr=None):
+ print("MD EMI Remap ..")
+ """MD reamp config
+ [in] thread, codescape thread object
+ [in] adr, user specific remap address (ap infra memory map view, 32M alignment)
+ default: emi start address
+ """
+
+ inf_emi = 0x40000000
+ print("MD_Remap(adr={:#x}) ...".format(inf_emi if adr == None else adr))
+ if adr == None:
+ inf_md = inf_emi
+ else:
+ assert (adr & 0x01FFFFFF) == 0
+ inf_md = adr
+ print("MD_Remap -> md:bank0=>ap:{:#x}, md:bank1=>ap:{:#x}, md:bank4=>ap:{:#x}".format(inf_md, inf_md+0x10000000, inf_emi))
+ # md remap bank 0
+ bnk = inf_md >> 25
+ memory_write(0xC0001300, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ memory_write(0xC0001304, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ memory_write(0xC0001308, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ memory_write(0xC000130c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+ # md remap bank 1
+ bnk = (inf_md+0x10000000) >> 25
+ memory_write(0xC0001310, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ memory_write(0xC0001314, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ memory_write(0xC0001318, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ memory_write(0xC000131c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+ # md remap bank 4
+ bnk = inf_emi >> 25
+ memory_write(0xC0001320, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ memory_write(0xC0001324, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ memory_write(0xC0001328, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ memory_write(0xC000132c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+
+def MO_Port_Enable():
+ print("MO port enable ..")
+ """
+ enable shaolin MO port
+ """
+ memory_write(0x1F000020, 0xF)
+ memory_write(0x1F000090, 0xA0000000)
+ memory_write(0x1F000098, 0xE0000002)
+ memory_write(0x1F0000A0, 0xC0000000)
+ memory_write(0x1F0000A8, 0xC0000002)
+
+def Switch_MDJtag_to_ShaolinDAP():
+ print("Switch MDJtag to ShaolinDAP ..")
+ """
+ switch MD JTAG to shaolinDAP (the jtag is defaultly for codescape. We want to let coretracer can use it.)
+ dbgsys addr = 0x0d101100
+ """
+ memory_write(0xA0601100, 0x3)
+ return
+
+def MD_PLL_Init():
+ print("MD PLL Init ..")
+ REGBASE_PLLMIXED = 0xA0140000
+ REGBASE_CLKSW = 0xA0150000
+
+ # default md_srclken_ack settle time = 150T 32k
+ memory_write(REGBASE_PLLMIXED+0x4, 0x02021c96)
+ # change APBPLL_SETTLE_26M to 0x2f2 => 29us
+ memory_write(REGBASE_PLLMIXED+0x20, 0x17920803)
+
+
+ memory_write(REGBASE_CLKSW+0xB8, 0x0) # Set HRAM to 800Mhz
+ memory_write(REGBASE_CLKSW+0x8c, 0x30)# Set NRPLL4_1_CK to 800Mhz
+ memory_write(REGBASE_CLKSW+0x5c, 0x11)# Set BPIPLL
+ memory_write(REGBASE_CLKSW+0x78, 0x10)# Set NRPLL1
+ memory_write(REGBASE_CLKSW+0x70, 0x21)# Set NRL2 spec to 450Mhz
+ memory_write(REGBASE_CLKSW+0x94, 0x10)# Set MCORE spec to 900MHz
+ memory_write(REGBASE_CLKSW+0x90, 0x10)# Set VCORE spec to 900MHz
+
+
+ memory_write(REGBASE_CLKSW+0xF00, 0x00D7FFFF) # NR0/1/2/4 PLL turn on
+
+ memory_write(REGBASE_PLLMIXED+0x84, memory_read(REGBASE_PLLMIXED+0x84) & 0xfffeffff) # Set FBKSEL = 0
+ memory_write(REGBASE_PLLMIXED+0x8c, memory_read(REGBASE_PLLMIXED+0x8c) & 0xfffeffff) # Set FBKSEL = 0
+
+ memory_write(REGBASE_PLLMIXED+0x58, 0x80117b13) # Fixed Fvco = 1818Mhz
+ memory_write(REGBASE_PLLMIXED+0x50, 0x8023d800) # Fvco = 3728Mhz. 3728/4 = 932Mhz
+ memory_write(REGBASE_PLLMIXED+0x48, 0x80229e00) # Fvco = 3600Mhz. 3600/4 = 900Mhz
+ memory_write(REGBASE_PLLMIXED+0x40, 0x8019f626) # Fvco = 2700Mhz. 2700/3 = 900Mhz
+
+ memory_write(REGBASE_PLLMIXED+0x98, 0x80180000) # Fvco = 2496Mhz. 2496/4 = 624Mhz
+ memory_write(REGBASE_PLLMIXED+0x9c, 0x12)
+
+ memory_write(REGBASE_PLLMIXED+0x68, 0x80133c00) # Fvco = 2000Mhz. 2000/2 = 1000Mhz
+ memory_write(REGBASE_PLLMIXED+0x70, 0x80171400) # Fvco = 2400Mhz. 2400/2 = 1000Mhz
+ memory_write(REGBASE_PLLMIXED+0x78, 0x801aec00) # Fvco = 2800Mhz. 2800/2 = 1400Mhz
+ memory_write(REGBASE_PLLMIXED+0x80, 0x80180000) # Fvco = 2496Mhz. 2496/4 = 624Mhz
+ memory_write(REGBASE_PLLMIXED+0x88, 0x800f6200) # Fvco = 1600Mhz. 1600/1 = 1600Mhz
+ memory_write(REGBASE_PLLMIXED+0x90, 0x801cd800) # Fvco = 3000Mhz. 3000/2 = 1500Mhz
+
+ memory_write(REGBASE_PLLMIXED+0x10, 0x0)
+
+ # polling untill MDMCUPLL complete freq adjustment
+ dummy_x = 0
+ while (memory_read(REGBASE_PLLMIXED+0x800) >> 14) & 0x1 == 0x1 :
+ dummy_x+=1
+
+ # wait MD bus clock ready
+ dummy_y = 0
+ while memory_read(REGBASE_CLKSW+0xcc) & 0x8000 != 0x8000 :
+ dummy_y+=1
+
+ #switch clock source to PLL
+ memory_write(REGBASE_CLKSW+0x24, memory_read(REGBASE_CLKSW+0x24) | 0x3) # switch MDMCU & MDBUS clock to PLL freq
+
+ memory_write(REGBASE_CLKSW+0x24, memory_read(REGBASE_CLKSW+0x24) | 0xfffffffc) # switch all clock to PLL freq
+ memory_write(REGBASE_CLKSW+0x28, memory_read(REGBASE_CLKSW+0x28) | 0x4)
+
+ memory_write(REGBASE_CLKSW+0x20, 0x3) # Turn off all SW clock request
+
+ memory_write(REGBASE_CLKSW+0x2c, memory_read(REGBASE_CLKSW+0x2c) | 0x1100011) # switch SDF clock to PLL freq
+
+ memory_write(REGBASE_PLLMIXED+0x314, 0xffff) # Clear PLL ADJ RDY IRQ fired by initial period adjustment
+ memory_write(REGBASE_PLLMIXED+0x318, 0xffff) # Mask all PLL ADJ RDY IRQ
+
+ memory_write(REGBASE_PLLMIXED+0xf00, 0x62970000) # Write PLL magic number
+ return
+
+if __name__ == "__main__":
+ #MO_Port_Enable()
+ switch_to_axi_mode()
+
+ #Switch_MDJtag_to_ShaolinDAP()
+
+ WDT_Disable()
+
+ #MD_SRCLKENA()
+
+ Config_26M_Quality()
+
+ #MD_Remap()
+
+ #MD_PLL_Init()
+ print "All misc config done!"
+
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/coretracer_init_emi.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/coretracer_init_emi.py
new file mode 100755
index 0000000..f44c884
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/coretracer_init_emi.py
@@ -0,0 +1,707 @@
+import sys
+import time
+import os
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+
+#MD Side
+AP_REG_BASE=0xC0000000
+MD_REG_BASE=0xA0000000
+
+#AP side
+#AP_REG_BASE=0x10000000
+#MD_REG_BASE=0x20000000
+
+def switch_to_axi_mode():
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ mem_value = mem_value[12:23]
+ hex_int = int(mem_value, 16)
+ return hex_int
+
+def DRAM_INIT():
+ print("DRAM_INIT ...")
+ tim = time.time()
+
+ # disable md to ap write secure world register protection
+ reg_bak_APC_CON = memory_read(0xC001DF00)
+ reg_bak_MAS_SEC_0 = memory_read(0xC001DB00)
+ memory_write(0xC001DF00, 0x00000000) # APC_CON[2] = DBG_MASK = 0
+ memory_write(0xC001DB00, 0x00010000) # MAS_SEC_0[16] = M16_SEC = 1
+
+ NR_RNKS=1
+ #EMI
+
+ #DRAMC0_NAO
+ #0x10234***
+ #DRAMC0
+ #0x10230***
+ #DRAMC1
+ #0x10240***
+ #DDRPHY0
+ #0x10238***
+ #DDRPHY1
+ #0x10248***
+
+ #EMI setting
+ memory_write(0xC0219000, 0x00001052) # ;0x00025052
+ memory_write(0xC0219060, 0xff000400)
+ memory_write(0xC0219020, 0x00008000)
+ memory_write(0xC0235000, 0x00001012) # ;0x00005053
+ memory_write(0xC0235010, 0x00000001)
+
+
+ #;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ memory_write(0xC0238274, 0xffffffff)
+ memory_write(0xC0248278, 0x00000000)
+ memory_write(0xC0248274, 0xffffffff)
+ memory_write(0xC023829c, 0x38030000)
+ #PLL sel
+
+ memory_write(0xC02381a0, 0x00000000)
+ memory_write(0xC02380a0, 0x00000000)
+ memory_write(0xC0238120, 0x00000000)
+ memory_write(0xC02382ac, 0x80000006)
+ memory_write(0xC02481a0, 0x00000000)
+ memory_write(0xC02480a0, 0x00000000)
+ memory_write(0xC0248120, 0x00000000)
+ memory_write(0xC02482ac, 0x80000006)
+ memory_write(0xC02382a0, 0x00000100) # ;PINMUX
+ memory_write(0xC02482a0, 0x00000100)
+ memory_write(0xC0238264, 0x00400000)
+ memory_write(0xC0238268, 0x00000040)
+ memory_write(0xC0248264, 0x00400000)
+ memory_write(0xC0248268, 0x00000040)
+ memory_write(0xC0238e18, 0x00000000)
+ memory_write(0xC0238f18, 0x01010000)
+ memory_write(0xC0239018, 0x02020000)
+ memory_write(0xC0238e68, 0x04040000)
+ memory_write(0xC0238f68, 0x05050000)
+ memory_write(0xC0239068, 0x06060000)
+ memory_write(0xC0238ec4, 0x00000c00)
+ memory_write(0xC0238fc4, 0x00000c00)
+ memory_write(0xC02393c4, 0x00000c00)
+ memory_write(0xC02394c4, 0x00000c00)
+ memory_write(0xC0238e50, 0x00000000)
+ memory_write(0xC0238f50, 0xbbbbbbbb)
+ memory_write(0xC0239050, 0xbbbbbbbb)
+ memory_write(0xC0238e54, 0x00000000)
+ memory_write(0xC0238f54, 0x0000bb00)
+ memory_write(0xC0239054, 0x0000bb00)
+ memory_write(0xC0248ea0, 0x00000000)
+ memory_write(0xC0248fa0, 0x00bbbbbb)
+ memory_write(0xC02490a0, 0x00bbbbbb)
+ memory_write(0xC0248ea4, 0x00000000)
+ memory_write(0xC0248fa4, 0x00000bbb)
+ memory_write(0xC02490a4, 0x00000bbb)
+ memory_write(0xC0248e00, 0x00000000)
+ memory_write(0xC0248f00, 0xbbbbbbbb)
+ memory_write(0xC0249000, 0xbbbbbbbb)
+ memory_write(0xC0248e04, 0x00000000)
+ memory_write(0xC0248f04, 0x0000bb00)
+ memory_write(0xC0249004, 0x0000bb00)
+ memory_write(0xC0248e50, 0x00000000)
+ memory_write(0xC0248f50, 0xbbbbbbbb)
+ memory_write(0xC0249050, 0xbbbbbbbb)
+ memory_write(0xC0248e54, 0x00000000)
+ memory_write(0xC0248f54, 0x0000bb00)
+ memory_write(0xC0249054, 0x0000bb00)
+ memory_write(0xC0238e1c, 0x00000c00)
+ memory_write(0xC0238f1c, 0x00000c00)
+ memory_write(0xC023901c, 0x00000c00)
+ memory_write(0xC0238e6c, 0x000f0f00)
+ memory_write(0xC0238f6c, 0x000f0f00)
+ memory_write(0xC023906c, 0x000f0f00)
+ memory_write(0xC0248ec4, 0x00000f0f)
+ memory_write(0xC0248fc4, 0x00000f0f)
+ memory_write(0xC02490c4, 0x00000f0f)
+ memory_write(0xC0248e1c, 0x000f0f00)
+ memory_write(0xC0248f1c, 0x000f0f00)
+ memory_write(0xC024901c, 0x000f0f00)
+ memory_write(0xC0248e6c, 0x000f0f00)
+ memory_write(0xC0248f6c, 0x000f0f00)
+ memory_write(0xC024906c, 0x000f0f00)
+ memory_write(0xC0238128, 0x00001010)
+ memory_write(0xC023812c, 0x01111010)
+ memory_write(0xC0238130, 0x010c10d0)
+ memory_write(0xC023812c, 0x03111010)
+ memory_write(0xC02381a4, 0x0000008c)
+ #TINFO="SHL ddrphy chA reset release"
+ memory_write(0xC02381b0, 0x00080010) # ;SER MODE
+ memory_write(0xC0238d04, 0x00000101)
+ memory_write(0xC0238d08, 0x00000101)
+ memory_write(0xC0239204, 0x00000101)
+ memory_write(0xC0239208, 0x00000101)
+ memory_write(0xC02380a4, 0x0000008c)
+ memory_write(0xC02380b0, 0x00080010) # ;SER MODE
+ memory_write(0xC0238c04, 0x00000101)
+ memory_write(0xC0238c08, 0x00000101)
+ memory_write(0xC0239104, 0x00000101)
+ memory_write(0xC0239108, 0x00000101)
+ memory_write(0xC02481a8, 0x00001010)
+ memory_write(0xC02481ac, 0x01111010)
+ memory_write(0xC02481b0, 0x010c10d0)
+ memory_write(0xC02481ac, 0x03111010)
+ memory_write(0xC02480a8, 0x00001010)
+ memory_write(0xC02480ac, 0x01111010)
+ memory_write(0xC02480b0, 0x010c10d0)
+ memory_write(0xC02480ac, 0x03111010)
+ memory_write(0xC0248128, 0x00001010)
+ memory_write(0xC024812c, 0x01111010)
+ memory_write(0xC0248130, 0x010c10d0)
+ memory_write(0xC024812c, 0x03111010)
+ #PLL
+
+ memory_write(0xC0238c18, 0x44000000)
+ memory_write(0xC0239118, 0x04000000)
+ memory_write(0xC0238c98, 0x44000000)
+ memory_write(0xC0239198, 0x04000000)
+ memory_write(0xC0238d18, 0x44000000)
+ memory_write(0xC0239218, 0x04000000)
+ memory_write(0xC0248c18, 0x44000000)
+ memory_write(0xC0249118, 0x04000000)
+ memory_write(0xC0248c98, 0x44000000)
+ memory_write(0xC0249198, 0x04000000)
+ memory_write(0xC0248d18, 0x44000000)
+ memory_write(0xC0249218, 0x04000000)
+ memory_write(0xC0238da0, 0x00000000)
+ memory_write(0xC02392a0, 0x00000000)
+ # DLL
+
+ memory_write(0xC0238124, 0x0000051e)
+ memory_write(0xC02481a4, 0x0000051e)
+ #TINFO="SHL ddrphy chB reset release"
+ memory_write(0xC02480a4, 0x0000051e)
+ memory_write(0xC0248124, 0x0000051e)
+ memory_write(0xC0238194, 0x00660600)
+ memory_write(0xC0238094, 0xc0660600)
+ memory_write(0xC0238114, 0xc0660600)
+ memory_write(0xC0248194, 0xc0660600)
+ memory_write(0xC0248094, 0xc0660600)
+ memory_write(0xC0248114, 0xc0660600)
+ memory_write(0xC02381b8, 0x00180101)
+ memory_write(0xC023826c, 0x00000000)
+ memory_write(0xC02481b8, 0x00180101)
+ memory_write(0xC024826c, 0x00000000)
+ memory_write(0xC0238d14, 0x00000000)
+ memory_write(0xC0239214, 0x00000000)
+ memory_write(0xC0239714, 0x00000000)
+ memory_write(0xC0239c14, 0x00000000)
+ memory_write(0xC0248d14, 0x00000000)
+ memory_write(0xC0249214, 0x00000000)
+ memory_write(0xC0249714, 0x00000000)
+ memory_write(0xC0249c14, 0x00000000)
+
+ time.sleep(0.001)
+
+ memory_write(0xC023800c, 0x006d0000)
+ memory_write(0xC0238180, 0x0000000c)
+ memory_write(0xC0238080, 0x00000009)
+ memory_write(0xC0238100, 0x00000009)
+ memory_write(0xC0248180, 0x00000009)
+ memory_write(0xC0248080, 0x00000009)
+ memory_write(0xC0248100, 0x00000009)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238000, 0x80000000)
+ memory_write(0xC0238004, 0x80000000)
+ memory_write(0xC0238004, 0x00000000)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238da4, 0x00019200)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238194, 0x00660e00)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238094, 0xc0660e00)
+ memory_write(0xC0238114, 0xc0660e00)
+ memory_write(0xC0248194, 0xc0660e00)
+ memory_write(0xC0248094, 0xc0660e00)
+ memory_write(0xC0248114, 0xc0660e00)
+ memory_write(0xC0238284, 0x0000001f)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238124, 0x0001051e)
+ memory_write(0xC02481a4, 0x0001051e)
+ memory_write(0xC02480a4, 0x0001051e)
+ memory_write(0xC0248124, 0x0001051e)
+ memory_write(0xC02382a0, 0x8100018c)
+ memory_write(0xC02482a0, 0x8100018c)
+ memory_write(0xC02381b8, 0x00040101)
+ memory_write(0xC02381b4, 0x00000000)
+ memory_write(0xC02380b4, 0x00000000)
+ memory_write(0xC0238134, 0x00000000)
+ memory_write(0xC0238c1c, 0x00200000) # ; WJ: LP3
+ memory_write(0xC02481b4, 0x00000000)
+ memory_write(0xC02480b4, 0x00000000)
+ memory_write(0xC0248134, 0x00000000)
+ memory_write(0xC0248c1c, 0x00200000) # ; WJ: LP3
+ memory_write(0xC02300dc, 0x00051008)
+ #;D.S EAXI:0x1024000dc %LE %LONG 0x00050008
+ memory_write(0xC0230000, 0x02101000) # ;[24]=LP2_EN , [25]=LP3_EN, [26]=LP4_EN
+ memory_write(0xC0230640, 0xa688049f)
+ memory_write(0xC0230660, 0x00030053)
+ memory_write(0xC023004c, 0x25712000)
+ memory_write(0xC0230680, 0x00000000)
+ memory_write(0xC0230684, 0x00000000)
+ memory_write(0xC0230688, 0x00000000)
+ memory_write(0xC023068c, 0x00000000)
+ memory_write(0xC0230690, 0x11111011)
+ memory_write(0xC0230694, 0x01101111)
+ memory_write(0xC0230698, 0x11111111)
+ memory_write(0xC023069c, 0x11111111)
+ memory_write(0xC02306a0, 0x11111111) # ;TXDLY DQS
+ memory_write(0xC02306a4, 0x66667777)
+ memory_write(0xC023082c, 0x11111111) # ;TXDLY DQ
+ memory_write(0xC0230830, 0x11111111) # ;TXDLY DQM
+ memory_write(0xC0230834, 0x66667777)
+ memory_write(0xC0230838, 0x66667777)
+ #D.S EAXI:0x1023092c %LE %LONG 0x22222222
+ #D.S EAXI:0x10230930 %LE %LONG 0x22222222
+ #D.S EAXI:0x10230934 %LE %LONG 0x66667777
+ #D.S EAXI:0x10230938 %LE %LONG 0x66667777
+ #D.S EAXI:0x10230a2c %LE %LONG 0x22222222
+ #D.S EAXI:0x10230a30 %LE %LONG 0x22222222
+ #D.S EAXI:0x10230a34 %LE %LONG 0x66667777
+ #D.S EAXI:0x10230a38 %LE %LONG 0x66667777
+ memory_write(0xC023081c, 0x00000000)
+ memory_write(0xC0230820, 0x00000000)
+ #D.S EAXI:0x1023091c %LE %LONG 0x00000000
+ #D.S EAXI:0x10230920 %LE %LONG 0x00000000
+ #D.S EAXI:0x10230a1c %LE %LONG 0x00000000
+ #D.S EAXI:0x10230a20 %LE %LONG 0x66666666
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ memory_write(0xC0230200, 0xf0100000) # ;[31]=DQSIEN MODE
+ memory_write(0xC0230048, 0x08000000)
+ memory_write(0xC0230678, 0xc0000000)
+ memory_write(0xC0230600, 0x09030b06)
+ memory_write(0xC0230604, 0x14090901)
+ memory_write(0xC0230608, 0x0c050201)
+ memory_write(0xC023060c, 0x00490019)
+ memory_write(0xC0230614, 0x01000606)
+ memory_write(0xC023061c, 0x02030408)
+ memory_write(0xC0230620, 0x02000400)
+ memory_write(0xC0230648, 0x9007320f)
+ memory_write(0xC0230644, 0x00000b0d) # ;DATLAT
+ memory_write(0xC0230000, 0x02111000) # ;[24]=LP2_EN , [25]=LP3_EN, [26]=LP4_EN
+ memory_write(0xC0230004, 0x20002000)
+ memory_write(0xC0230008, 0x81080000)
+ memory_write(0xC023000c, 0x0002cf13)
+ memory_write(0xC0230010, 0x00000080)
+ memory_write(0xC0230020, 0x00000009)
+ memory_write(0xC0230024, 0x80030000)
+ memory_write(0xC0230038, 0x80000106)
+ memory_write(0xC0230040, 0x3000000c)
+ memory_write(0xC023004c, 0x25714001)
+ memory_write(0xC0230064, 0x25b1f1cf) # ;REFRDIS=1
+ memory_write(0xC02300b0, 0x04300000)
+ memory_write(0xC0230200, 0xf0310000) # ;[31]=DQSIEN MODE
+ memory_write(0xC0230658, 0x21200001)
+ memory_write(0xC0230800, 0x00000002)
+ #D.S EAXI:0x10230900 %LE %LONG 0x00000002
+ #D.S EAXI:0x10230a00 %LE %LONG 0x00000002
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230824, 0x10101010) # ;GATE WINDOW unit:2T
+ memory_write(0xC0230828, 0x17171717)
+ #D.S EAXI:0x10230924 %LE %LONG 0x11111111
+ #D.S EAXI:0x10230928 %LE %LONG 0x42424242
+ #D.S EAXI:0x10230a24 %LE %LONG 0x32323232
+ #D.S EAXI:0x10230a28 %LE %LONG 0x06060606
+ #;D.S EAXI:0x10240a24 %LE %LONG 0x00000000; ;GATE WINDOW unit:2T
+ #;D.S EAXI:0x10240a28 %LE %LONG 0x53535353
+ #;D.S EAXI:0x10240b24 %LE %LONG 0x32323232
+ #;D.S EAXI:0x10240b28 %LE %LONG 0x06060606
+ #;D.S EAXI:0x10240c24 %LE %LONG 0x32323232
+ #;D.S EAXI:0x10240c28 %LE %LONG 0x06060606
+ # 33961 === over_write_setting_begin ===
+ # 33961 === over_write_setting_end ===
+ memory_write(0xC0230034, 0x00731010)
+ memory_write(0xC0230024, 0x80030050)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC023005c, 0x00003f00)
+ memory_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230060, 0x00000000)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC023005c, 0x00000aff)
+ memory_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230060, 0x00000000)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC023005c, 0x00000183)
+ memory_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230060, 0x00000000)
+ memory_write(0xC023005c, 0x00000206) # ;RL/WL
+ memory_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230060, 0x00000000)
+ memory_write(0xC0230028, 0x00000034)
+ memory_write(0xC023005c, 0x00000b03)
+ memory_write(0xC0230060, 0x00000001)
+
+ #=============================RANK1 MRW==================
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #D.S EAXI:0x1023005c %LE %LONG 0x01003f00
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000aff
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000183
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000206; ;RL/WL
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000b03
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #================== end RANK1 MRW =====================
+
+
+ memory_write(0xC0230060, 0x00000000)
+ memory_write(0xC0230024, 0x80030040)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ memory_write(0xC023005c, 0x00000400)
+
+
+
+ memory_write(0xC023064c, 0x00000005)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC023004c, 0x25774001)
+ memory_write(0xC0230034, 0x00731810)
+ memory_write(0xC0230024, 0x80030000)
+ memory_write(0xC0230004, 0x20082000)
+ memory_write(0xC0230058, 0x00000a56)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ memory_write(0xC023064c, 0x00ff0005)
+ memory_write(0xC0230064, 0x25b1f1cf) # ;REFRDIS=1
+ memory_write(0xC0230610, 0x22653055)
+ memory_write(0xC023004c, 0x45774001)
+ memory_write(0xC0230048, 0x48000000)
+ memory_write(0xC023005c, 0x80000400)
+ memory_write(0xC0230038, 0xc0000107)
+ memory_write(0xC023020c, 0x00010002)
+ memory_write(0xC0230204, 0x00014e00)
+ memory_write(0xC0230094, 0x00100000)
+ memory_write(0xC0230098, 0x00004000)
+ memory_write(0xC023009c, 0x12010480)
+ # 54377 === DE initial sequence done ===
+
+ #selftest
+ #D.S EAXI:0x1023009C %LE %LONG 0x02010080
+ #D.S EAXI:0x10230094 %LE %LONG 0x00100000
+ #D.S EAXI:0x10230098 %LE %LONG 0x00004000
+ #D.S EAXI:0x1023009C %LE %LONG 0x82010080
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ # restore md to ap write secure world register protection
+ memory_write(0xC001DB00, reg_bak_MAS_SEC_0) # MAS_SEC_0[16] = M16_SEC = 0
+ memory_write(0xC001DF00, reg_bak_APC_CON) # APC_CON[2] = DBG_MASK = 1
+
+ print("DRAM_INIT -> elapsed time: {:.3f}".format(time.time()-tim))
+
+def MD_Remap(adr=None):
+ """MD reamp config
+ [in] thread, codescape thread object
+ [in] adr, user specific remap address (ap infra memory map view, 32M alignment)
+ default: emi start address
+ """
+
+ inf_emi = 0x80000000 if memory_read(0xA000001C) < 0x08566094 else 0x40000000
+ print("MD_Remap(adr={:#x}) ...".format(inf_emi if adr == None else adr))
+ if adr == None:
+ inf_md = inf_emi
+ else:
+ assert (adr & 0x01FFFFFF) == 0
+ inf_md = adr
+ print("MD_Remap -> md:bank0=>ap:{:#x}, md:bank1=>ap:{:#x}, md:bank4=>ap:{:#x}".format(inf_md, inf_md+0x10000000, inf_emi))
+ # md remap bank 0
+ bnk = inf_md >> 25
+ memory_write(0xC0001300, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ memory_write(0xC0001304, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ memory_write(0xC0001308, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ memory_write(0xC000130c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+ # md remap bank 1
+ bnk = (inf_md+0x10000000) >> 25
+ memory_write(0xC0001310, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ memory_write(0xC0001314, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ memory_write(0xC0001318, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ memory_write(0xC000131c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+ # md remap bank 4
+ bnk = inf_emi >> 25
+ memory_write(0xC0001320, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ memory_write(0xC0001324, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ memory_write(0xC0001328, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ memory_write(0xC000132c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+
+def WDT_Disable():
+ """diable WDT function
+ [in] thread, codescape thread object
+ """
+ print("WDT disable ...")
+ mdrgu = 0xA00F0000 + 0x0100
+ aprgu = 0xC0007000
+ memory_write(mdrgu, (memory_read(mdrgu) & 0xFFFFFFFC) | 0x55000000)
+ memory_write(aprgu, (memory_read(aprgu) & 0xFFFFFFFE) | 0x22000000)
+
+if __name__ == "__main__":
+ switch_to_axi_mode()
+ WDT_Disable()
+ DRAM_INIT()
+ MD_Remap()
+ tEnd = time.time()
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/coretracer_load_dsp.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/coretracer_load_dsp.py
new file mode 100755
index 0000000..96ff456
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/coretracer_load_dsp.py
@@ -0,0 +1,147 @@
+#from imgtec import codescape
+import sys
+import time
+import os
+sys.path.append(os.path.dirname(os.path.realpath(__file__)))
+import gdb
+import binascii
+import Tkinter, tkFileDialog
+from TCF import Event, Result
+import TCF as client
+
+app = None
+dsp_header = 0x0
+dsp_magic = "4d4d4d01"
+
+TCF_HOST = 'localhost'
+TCF_PORT = 1534
+
+def get_tcf_port():
+ global TCF_PORT
+ gdb_cmd = 'show env tcfport'
+ res = gdb.execute(gdb_cmd, to_string=True)
+ TCF_PORT = int(res.split()[2], 0)
+ print "TCF_PORT = " + str(TCF_PORT)
+
+def switch_to_axi_mode():
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def switch_to_apb_mode():
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write off'
+ gdb.execute(gdb_cmd)
+
+def print_to_log(str):
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','log',str+'\n'])
+ tcf.close()
+
+# load dsp bin file
+def load_dsp_bin(dsp_path):
+ global dsp_header
+
+ time_str = time.time()
+ #print_to_log("=== Start to load dsp bin ===")
+ print_to_log("Dsp bin path: " + dsp_path)
+ if(os.path.exists(dsp_path) == False):
+ print_to_log( "DSP bin doesn't exist: %s" %(dsp_path))
+ print_to_log( "[Error] Load DSP bin failed")
+ return
+ else:
+ with open(dsp_path, "rb") as dsp_bin:
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print_to_log( "No header detected, continue")
+ else:
+ dsp_header = 0x200
+ dsp_bin.seek(dsp_header, os.SEEK_SET)
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print_to_log( "Header detected, skip first 512B")
+ else:
+ print_to_log( "DSP header detected at neither 0x0 nor 0x200")
+ print_to_log( "Please check the bin is legal!")
+ print_to_log( "[Error] Load DSP bin failed")
+ return
+ gdb_cmd='thread 1'
+ gdb.execute(gdb_cmd)
+ ## a) need parsing: 0x13a0000 <dsp_bin_ro>
+ ##symbol_name='&dsp_bin_ro'
+ ##dsp_addr = gdb.parse_and_eval(symbol_name)
+ ## b) need parsing: $3 = 0x13a0000
+ ##gdb_cmd='p/x &dsp_bin_ro'
+ ##dsp_addr = gdb.execute(gdb_cmd, False, True)
+ symbol_name='dsp_bin_ro'
+ dsp_addr = gdb.parse_and_eval(symbol_name)
+ dsp_addr = str(dsp_addr.address).split(" ")
+ dsp_addr = int(dsp_addr[0], 16) - dsp_header
+ #print_to_log( hex(dsp_addr) )
+ gdb_cmd = " ".join(['restore', dsp_path, 'binary', hex(dsp_addr), hex(dsp_header)])
+ #print_to_log( gdb_cmd)
+ switch_to_axi_mode()
+ print_to_log( "Load DSP bin ......................")
+ gdb.execute(gdb_cmd)
+ switch_to_apb_mode()
+ time_end = time.time()
+ print_to_log("loading dsp is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+
+class gui_tk(Tkinter.Tk):
+ def __init__(self, parent):
+ Tkinter.Tk.__init__(self, parent)
+ elf_path = ""
+ dsp_path = ""
+ dsp_addr = ""
+ self.file_opt = options = {}
+ options['title'] = 'Choose a file'
+ self.parent = parent
+ self.initialize()
+
+ def initialize(self):
+ self.grid()
+
+ dsp_button = Tkinter.Button(self, text=u"Load DSP bin =>", command=self.dsp_OnButtonClick)
+ dsp_button.grid(column=0, row=4, sticky='W')
+
+ def dsp_OnButtonClick(self):
+ dsp_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(dsp_path) > 0:
+ print_to_log( "You chose %s" % dsp_path)
+ load_dsp_bin(dsp_path)
+ self.quit()
+
+ def quit(self):
+ global app
+ print_to_log( "=== Close DSP Loader ===")
+ app.destroy()
+
+def load_dsp_gui():
+ print_to_log( "=== Start DSP Loader UI ===")
+ global app
+ app = gui_tk(None)
+ app.title('DSP Loader')
+ app.mainloop()
+
+def disable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','disable','["LoadDSP"]'])
+ tcf.close()
+
+def enable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','enable','["LoadDSP"]'])
+ tcf.close()
+
+if __name__ == "__main__":
+ get_tcf_port()
+ disable_button()
+ load_dsp_gui()
+ enable_button()
+
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/coretracer_misc.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/coretracer_misc.py
new file mode 100755
index 0000000..11b9be2
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/coretracer_misc.py
@@ -0,0 +1,70 @@
+import sys
+import time
+import os
+import gdb
+import ctypes
+
+dsp_bin_base = "0x0d500000"
+ramdisk_base = "0x0c500000"
+RAMDISK_SIZE = 0x1000
+EXCEPT_RET = 0xdeaddead
+
+def switch_to_axi_mode():
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def switch_to_apb_mode():
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write off'
+ gdb.execute(gdb_cmd)
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def get_symbol_addr(symbol_name):
+ res = -1
+ try:
+ res = gdb.parse_and_eval(symbol_name)
+ except:
+ return EXCEPT_RET
+
+ return str(res.address).split()[0]
+
+def clean_ram_disk_region():
+ global ramdisk_base
+
+ ram_disk_addr = get_symbol_addr('ram_disk')
+
+ if ram_disk_addr != EXCEPT_RET:
+ print("ram_disk = %s . clean 4K .." % ram_disk_addr)
+ switch_to_axi_mode()
+ for i in range(RAMDISK_SIZE/4):
+ memory_write(int(ram_disk_addr,0)+i*4,0)
+ switch_to_apb_mode()
+ ramdisk_base = ram_disk_addr
+ else:
+ print "There is no ram_disk symbol in this elf!"
+
+def clean_dsp_bin_magic():
+ global dsp_bin_base
+
+ magic_addr = get_symbol_addr('dsp_bin_ro')
+
+ if magic_addr != EXCEPT_RET:
+ print("dsp_bin_addr = %s . write the addr with 0 .." % magic_addr)
+ memory_write(magic_addr, 0)
+ dsp_bin_base = magic_addr
+ else:
+ print "There is no dsp_bin_ro symbol in this elf!"
+
+
+if __name__ == "__main__":
+ print "Check dsp bin magic .."
+ clean_dsp_bin_magic()
+ print "Check ramdisk 4k .."
+ clean_ram_disk_region()
+ print "=================== All process done. You can tigger cpu run or load DSP bin ==================="
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/coretracer_restore_callstack.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/coretracer_restore_callstack.py
new file mode 100755
index 0000000..ff9bcef
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/coretracer_restore_callstack.py
@@ -0,0 +1,188 @@
+import sys
+import time
+import os
+sys.path.append(os.path.dirname(os.path.realpath(__file__)))
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+import struct
+from TCF import Event, Result
+import TCF as client
+EXCEPT_RET = 0xdeaddead
+
+TCF_HOST = 'localhost'
+TCF_PORT = 1534
+
+CPU_CORE_NUM =4
+CPU_PER_CORE_VPE_NUM =3
+CPU_PER_CORE_TC_NUM =6
+
+CPUGPR_NAME = ['zero', 'at', 't4', 't5',
+ 'a0', 'a1', 'a2', 'a3',
+ 'a4', 'a5', 'a6', 'a7',
+ 't0', 't1', 't2', 't3',
+ 's0', 's1', 's2', 's3',
+ 's4', 's5', 's6', 's7',
+ 't8', 't9', 'k0', 'k1',
+ 'gp', 'sp', 'raw_fp', 'ra']
+
+OFFENDING_VPE_NONE = 0xffffffff
+
+def get_tcf_port():
+ global TCF_PORT
+ gdb_cmd = 'show env tcfport'
+ res = gdb.execute(gdb_cmd, to_string=True)
+ TCF_PORT = int(res.split()[2], 0)
+ print "TCF_PORT = " + str(TCF_PORT)
+
+def print_to_log(str):
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','log',str+'\n'])
+ tcf.close()
+
+def disable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','disable','["restoreCallStack"]'])
+ tcf.close()
+
+def enable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','enable','["restoreCallStack"]'])
+ tcf.close()
+
+def refresh_callstack_ui():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','refresh','debug'])
+ tcf.close()
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+
+ return int(mem_value.split()[2], 0)
+
+def register_read(reg):
+ gdb_cmd = 'info register '+ str(reg)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ return int(mem_value.split()[1], 0)
+
+def register_write(reg, set_value):
+ gdb_cmd = 'set $' + str(reg) + ' = ' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def get_symbol_addr(symbol_name):
+ res = -1
+ try:
+ res = gdb.parse_and_eval(symbol_name)
+ except:
+ return EXCEPT_RET
+
+ return str(res.address).split()[0]
+
+def get_variable_value(symbol_name):
+ mem_value = gdb.parse_and_eval(symbol_name)
+ return (mem_value)
+
+def find_offender():
+ print_to_log( "checking vpe status ..")
+ offending_core = OFFENDING_VPE_NONE
+ offending_vpe = OFFENDING_VPE_NONE
+ offending_tc = OFFENDING_VPE_NONE
+ try:
+ offending_core = get_variable_value('sst_offending_coreid')
+ offending_vpe = get_variable_value('sst_offending_vpeid')
+ offending_tc = get_variable_value('sst_offending_tcid')
+ except:
+ return [OFFENDING_VPE_NONE, OFFENDING_VPE_NONE, OFFENDING_VPE_NONE]
+
+ return [offending_core, offending_vpe, offending_tc]
+
+def find_thread_id(core_num, vpe_num, tc_num):
+ gdb_cmd = 'thread find Core {}/VPE {}/TC {}'.format(core_num, vpe_num, tc_num)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ print mem_value
+ return int(mem_value.split()[1], 0)
+
+def switch_thread(tid):
+ gdb_cmd = 'thread '+str(tid)
+ gdb.execute(gdb_cmd)
+
+def restore_thread_callstack(core, vpe, tc): # core0~3, vpe0~2, tc0~1
+ # switch thread
+ thread_id = find_thread_id(core, vpe, vpe*2 + tc)
+ switch_thread(thread_id)
+
+ #print_to_log( "CONT. VPE"+str(core*3+vpe) )
+ vpe_ex_tc = get_variable_value('ex_info[{}][0].tcid'.format(core*3+vpe)) # tc0~5
+
+ #print_to_log('CORE{}/vpe{}/tc{}'.format(core, vpe, tc))
+ if vpe_ex_tc%2 == tc :# offender tc will use ex_info to restore
+ #print_to_log("restore from ex_info_reg ..")
+ # restore GPR from variable ex_info_reg
+ base_addr = get_symbol_addr('ex_info[{}][0].SST_Exception_Regs.GPR'.format(core*3+vpe))
+ #print_to_log("ex_info.GPR base addr = {}".format(base_addr))
+ i=0
+ for reg_name in CPUGPR_NAME:
+ val = memory_read(int(base_addr,0) + i*4)
+ register_write(reg_name, val)
+ i+=1
+ else: # else we use interaptive_state
+ #print_to_log("restore from ex_interaptive_state ..")
+ # restore GPR from variable ex_interaptive_state
+ base_addr = get_symbol_addr('ex_interaptive_state.coreregs[{}].tcregs[{}].GPR'.format(core, tc))
+ i=0
+ for reg_name in CPUGPR_NAME:
+ val = memory_read(int(base_addr,0) + i*4)
+ register_write(reg_name, val)
+ i+=1
+
+ # restore EPC -> PC
+# epc_val = get_variable_value('ex_interaptive_state.coreregs[{}].vperegs[{}].EPC'.format(core, vpe))
+ epc_val = get_variable_value('ex_info[{}][0].SST_Exception_Regs.EPC'.format(core*3+vpe))
+ register_write("pc", epc_val)
+
+ # restore status -> status
+ status_val = get_variable_value('ex_info[{}][0].SST_Exception_Regs.status'.format(core*3+vpe))
+ register_write("status", epc_val)
+
+ return
+
+def restore_callstack(offender):
+ core_num = offender[0]
+ vpe_num = offender[1]%3 # VPE0~VPE2
+ tc_num = offender[2]%2 # TC0~TC1
+ print_to_log("============> Offender is CORE{} VPE{} TC{}".format(core_num, vpe_num, tc_num))
+
+ for core in range(CPU_CORE_NUM):
+ for vpe in range(CPU_PER_CORE_VPE_NUM):
+ print_to_log("Restore CORE{} VPE{} ..".format(core, vpe))
+ for tc in range(2):
+ #print_to_log("Restore CORE{} VPE{} TC{} ..".format(core, vpe, vpe*2 + tc))
+ restore_thread_callstack(core, vpe, tc)
+ refresh_callstack_ui()
+ print_to_log("=== restore call stack finish! ===")
+ return
+
+def main_func():
+ print_to_log("=== start to restore call stack! ===")
+ offender = find_offender()
+ if offender[0] == OFFENDING_VPE_NONE:
+ print_to_log( "This is no any exception happened. Restore abort!")
+ return
+ restore_callstack(offender)
+ return
+
+
+if __name__ == "__main__":
+ get_tcf_port()
+ disable_button()
+ main_func()
+ enable_button()
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/coretracer_swla.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/coretracer_swla.py
new file mode 100755
index 0000000..138ac69
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/coretracer_swla.py
@@ -0,0 +1,309 @@
+import sys
+import time
+import os
+sys.path.append(os.path.dirname(os.path.realpath(__file__)))
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+import struct
+from TCF import Event, Result
+import TCF as client
+
+CORE_NUM = 4
+CORE_TC_NUM = 6
+LAST_COUNT = 100
+
+EXCEPT_RET = 0xdeaddead
+
+TCF_HOST = 'localhost'
+TCF_PORT = 1534
+
+def get_tcf_port():
+ global TCF_PORT
+ gdb_cmd = 'show env tcfport'
+ res = gdb.execute(gdb_cmd, to_string=True)
+ TCF_PORT = int(res.split()[2], 0)
+ print "TCF_PORT = " + str(TCF_PORT)
+
+def print_to_log(str):
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','log',str+'\n'])
+ tcf.close()
+
+def dump_memory(start_addr, end_addr, filename):
+ gdb_cmd = 'dump binary memory '+str(filename)+' '+hex(start_addr)+' '+hex(end_addr)
+ gdb.execute(gdb_cmd)
+
+def switch_to_axi_mode():
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def switch_to_apb_mode():
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write off'
+ gdb.execute(gdb_cmd)
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ #print "[DBG] "+ mem_value
+ return int(mem_value.split()[2], 0)
+
+
+def get_symbol_addr(symbol_name):
+ res = -1
+ try:
+ res = gdb.parse_and_eval(symbol_name)
+ except:
+ return EXCEPT_RET
+
+ return str(res.address).split()[0]
+
+def get_variable_value(symbol_name):
+ mem_value = gdb.parse_and_eval(symbol_name)
+ #print "[DBG] " + str(mem_value)
+ return (mem_value)
+
+WRAP_PATTERN = 0x50415257 # WRAP
+def isBufferWrap(f, total_size, entry_size):
+ seek_offset = total_size - entry_size
+ f.seek(seek_offset)
+ raw_dword = f.read(8)
+ word1, word2 = struct.unpack('II', raw_dword)
+ if word1 == WRAP_PATTERN and word2 == WRAP_PATTERN:
+ return False
+ else:
+ print "WRAP!!"
+ return True
+
+def find_first_idx_cus(f, total_size, entry_size, next_avail_idx):
+ avail_buffer_size = total_size - entry_size
+ if next_avail_idx - LAST_COUNT >= 0:
+ return next_avail_idx - LAST_COUNT
+ else:
+ if not isBufferWrap(f, total_size, entry_size):
+ return 0
+ else:
+ return (avail_buffer_size/entry_size) + (next_avail_idx - LAST_COUNT)
+
+def parse_swla_dump(file_path, entry_size, bin_size, next_avail_idx):
+ f = open(file_path, "rb")
+ #first_idx = find_first_idx(f, bin_size, entry_size, next_avail_idx)
+ first_idx = find_first_idx_cus(f, bin_size, entry_size, next_avail_idx)
+ f.seek(first_idx*entry_size)
+
+ cnt, wrap = 0, 0
+ tmp_list = []
+ for i in range(0, CORE_TC_NUM):
+ tmp_list.append([])
+
+ while True:
+ word = f.read(entry_size)
+ tmp_hash = {}
+ context, frc, raw_coretc = struct.unpack('III', word) #################################### need to modify
+ tmp_hash['frc'], tc, core = hex(frc), raw_coretc >> 8, raw_coretc & 0xff
+
+ if context&0xf0==0xe0:
+ tmp_hash['context'] = "CUS"
+ elif context==0xAAAAAAAA:
+ #print "IRQEND!"
+ tmp_hash['context'] = "IRQEND"
+ tmp_list[tc].append(tmp_hash.copy())
+ elif context>>16==0xAAAA:
+ irq_id = int(context & 0xFFFF)
+ tmp_hash['context'] = "IRQ"+str(irq_id)
+ tmp_list[tc].append(tmp_hash.copy())
+ #print tmp_hash['context']
+ else:
+ char1, char2, char3, char4 = (context&0xff), (context>>8&0xff), (context>>16&0xff), (context>>24&0xff)
+ if char4==0:
+ if char3==0:
+ context_name = chr(char1) + chr(char2)
+ else:
+ context_name = chr(char1) + chr(char2) + chr(char3)
+ else:
+ context_name = chr(char1) + chr(char2) + chr(char3) + chr(char4)
+ tmp_hash['context'] = context_name
+ tmp_list[tc].append(tmp_hash.copy())
+
+ #print str(tc)+", "+tmp_hash['context']+", "+hex(frc)
+
+ cnt +=1
+
+ # WRAP condition
+ if f.tell()==bin_size and wrap==0 :
+ f.seek(0)
+ wrap=1
+ print "CORE"+str(file_idx)+" swla buffer WRAP"
+ #print "seek:" + hex(f.tell()) + " cnt*entry_size = "+hex(cnt*entry_size)
+
+ # check END
+ if f.tell()==next_avail_idx*entry_size:
+ #print "END! cnt="+str(cnt)
+ break
+
+ f.close()
+ return tmp_list
+
+def swla_parse(tc_lvl_list):
+ context_list = {}
+
+ irq_queue = []
+ pre_task, pre_frc = 0, 0
+ for context in tc_lvl_list:
+ context_name = context['context']
+ context_start_frc = context['frc']
+ target_context=""
+ if pre_task != 0:
+ # sys_exec case
+ if pre_task=="IRQEND" and len(irq_queue)==0:
+ target_context = "sys_exec"
+ if not target_context in context_list:
+ context_list[target_context] = []
+ context_list[target_context].append([pre_frc, context_start_frc])
+ # irqend case
+ elif pre_task=="IRQEND":
+ last_irq = irq_queue.pop()
+ target_context = last_irq
+ if not target_context in context_list:
+ context_list[target_context] = []
+ context_list[target_context].append([pre_frc, context_start_frc])
+ else:
+ if "IRQ" in context_name and context_name!="IRQEND": # irq
+ irq_queue.append(context_name)
+
+ target_context = pre_task
+ if not target_context in context_list:
+ context_list[target_context] = []
+ context_list[target_context].append([pre_frc, context_start_frc])
+ if target_context=="IRQEND":
+ print "????"
+ pre_task, pre_frc = context_name, context_start_frc
+
+ #print context_list
+ return context_list.copy()
+
+def main_func():
+ print_to_log("=== Start to parse SWLA information ===")
+ """
+ get swla buffer base address
+ """
+ res = get_symbol_addr('SysProfilerBufferAddress')
+ if res==EXCEPT_RET:
+ print_to_log( "[ERR] this elf does not support SWLA!")
+ return
+
+ swla_buffer_base_addr = int(get_symbol_addr('SysProfilerBufferAddress'), 16)
+ swla_buffer_addr_ary = []
+ for i in range(0, CORE_NUM):
+ swla_buffer_addr_ary.append(memory_read(swla_buffer_base_addr+i*4))
+
+ """
+ get swla entry size
+ """
+ swla_entry_size = get_variable_value("SA_LoggingNodeSize[0]") ##########################################
+ #print "SWLA Entry Size: "+str(swla_entry_size)+" B"
+
+ """
+ get swla next available entry index
+ """
+ swla_buffer_next_avail_index = []
+ for i in range(0, CORE_NUM):
+ swla_buffer_next_avail_index.append(get_variable_value("SA_LoggingOffset["+str(i)+"]"))
+
+ """
+ get swla buffer total size
+ """
+ tmp = get_variable_value("SA_LoggingStop[0]")
+ swla_size = int(str(tmp).split()[0], 0) - swla_buffer_addr_ary[0]
+ print_to_log( "SWLA Buffer Size: "+ hex(swla_size)+" B")
+
+ """
+ dump each core's swla raw buffer
+ """
+ swla_dump_file = []
+
+ switch_to_axi_mode() # switch to AXI mode to speed up (axi mode will not go through CPU -> MUST used in non-cache region)
+ for i in range(0, CORE_NUM):
+ print_to_log( "Dump core"+str(i)+" swla raw buffer ..")
+ s_t = time.time()
+ filename = "core"+str(i)+"_raw_swla.bin"
+ dump_memory(swla_buffer_addr_ary[i], swla_buffer_addr_ary[i]+swla_size, filename)
+ swla_dump_file.append(filename)
+ e_t = time.time()
+ print_to_log("Elapsed time: {:.3f} sec".format(e_t-s_t))
+ switch_to_apb_mode() # switch back
+
+ print "All swla raw dump finish!!"
+
+ #exit()
+ """
+ parse swla raw
+ """
+ output = open("final_swla.log", "w")
+ output.write('met-info [000] 0.0: ms_ud_timeline_header: {"resource": [{"entity-attr": ["Interrupt"], "name": "default"}], "name": "MCU Timeline"}'+"\n")
+ output.write('met-info [000] 0.0: ms_ud_timeline_description: MCU Timeline:HAS_CHILD_TRACE=Y;COPY_TO_TOP=Y'+"\n")
+
+ core_num=0
+ log_index=1
+ for file in swla_dump_file:
+ print_to_log( "Parsing "+file+" ...")
+ s_t = time.time()
+ tc_list = parse_swla_dump(file, swla_entry_size, swla_size, swla_buffer_next_avail_index[core_num])
+ #print tc_list
+ e_t = time.time()
+
+ print_to_log("Elapsed time: {:.3f} sec".format(e_t-s_t))
+ print_to_log( "start to write to final_swla ..")
+ tc_num = 0
+ for tc_content in tc_list:
+ #print tc_content
+ context_list = swla_parse(tc_content)
+ #print context_list
+ vpe_num = tc_num/2
+ for context_name, period_list in context_list.items():
+ isIRQ = "NO"
+ if "IRQ" in context_name:
+ isIRQ = "YES"
+ for period in period_list:
+ #print period
+ start_frc, end_frc = int(period[0],0)*1.0/1000000, int(period[1],0)*1.0/1000000
+ #print start_frc
+ out_str1 = "NULL-0 [000] {:.10f}: MCU Timeline: ".format(start_frc)
+ out_str2 = "'CORE{}%%VPE{}%%TC{}%%{}', 'e': [['{}']], 't': ['{:.10f}', '{:.10f}']".format(core_num, vpe_num, tc_num/2, context_name, isIRQ, start_frc, end_frc)
+ output.write(out_str1+"{'r': "+out_str2+"}\n")
+ log_index+=1
+ tc_num+=1
+
+ core_num+=1
+ #break
+ output.close()
+ print_to_log( '=== SWLA parse finish! Please use MET font-end to open final_swla.log for SWLA view ===')
+ print_to_log( '=== The output filename is "final_swla.log" in the same folder of your elf file ===')
+ return
+
+def disable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','disable','["SWLA"]'])
+ tcf.close()
+
+def enable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','enable','["SWLA"]'])
+ tcf.close()
+
+if __name__ == "__main__":
+ get_tcf_port()
+ disable_button()
+ main_func()
+ enable_button()
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/prepare_mode.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/prepare_mode.launch
new file mode 100644
index 0000000..2b67fdb
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6297/coretracer/prepare_mode.launch
@@ -0,0 +1,64 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.ui.focus_threads" value=""/>
+<stringAttribute key="com.mediatek.ide.dsf.mvpu.dbg_file" value=""/>
+<stringAttribute key="com.mediatek.ide.dsf.mvpu.pattern_file" value=""/>
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+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value=""/>
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+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="attach"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
+<booleanAttribute key="org.eclipse.debug.core.capture_output" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_OUTPUT_ON" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+<stringAttribute key="saved_expressions<seperator>Unknown<seperator>APB" value="0xa0638000,0xa0310000"/>
+<stringAttribute key="saved_expressions<seperator>Unknown<seperator>AXI" value="0xa0020000,0xa0630000,0xa0638000,0xa0291e50"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_AP2MD_enable.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_AP2MD_enable.cmm
new file mode 100755
index 0000000..bfeee00
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_AP2MD_enable.cmm
@@ -0,0 +1,29 @@
+&MEM_CLASS="AXI"
+; do AP to MD path disable
+LOCAL &BASE_ADDR_AP2MD_Dummy
+LOCAL &BASE_ADDR_INFRA_PERI2MD_PROT_EN
+LOCAL &BASE_ADDR_INFRA_MD2PERI_PROT_EN
+LOCAL &temp
+
+&BASE_ADDR_AP2MD_Dummy=0x10001370
+&BASE_ADDR_INFRA_PERI2MD_PROT_EN=0x10001220
+&BASE_ADDR_INFRA_MD2PERI_PROT_EN=0x10001250
+
+
+&temp=data.long(&MEM_CLASS:(&BASE_ADDR_INFRA_PERI2MD_PROT_EN+0x0))|0x80
+;PRINT "temp=" "&temp"
+;PRINT "BASE_ADDR_INFRA_PERI2MD_PROT_EN=" "&BASE_ADDR_INFRA_PERI2MD_PROT_EN"
+D.S &MEM_CLASS:(&BASE_ADDR_INFRA_PERI2MD_PROT_EN+0x0) %LE %LONG &temp
+
+&temp=data.long(&MEM_CLASS:(&BASE_ADDR_INFRA_MD2PERI_PROT_EN+0x0))&0xFFFFFFBF
+;PRINT "temp=" "&temp"
+;PRINT "BASE_ADDR_INFRA_MD2PERI_PROT_EN=" "&BASE_ADDR_INFRA_MD2PERI_PROT_EN"
+D.S &MEM_CLASS:(&BASE_ADDR_INFRA_MD2PERI_PROT_EN+0x0) %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&MEM_CLASS:(&BASE_ADDR_AP2MD_Dummy+0x0))|0x1
+;PRINT "temp=" "&temp"
+;PRINT "BASE_ADDR_AP2MD_Dummy=" "&BASE_ADDR_AP2MD_Dummy"
+D.S &MEM_CLASS:(&BASE_ADDR_AP2MD_Dummy+0x0) %LE %LONG &temp
+wait 1.ms
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_EVB_UART_Test.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_EVB_UART_Test.cmm
new file mode 100755
index 0000000..5ee5318
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_EVB_UART_Test.cmm
@@ -0,0 +1,33 @@
+;MT6739 MD_UART0 port test
+;You should make sure GPIO27 has connected to UART port RXD pin,GPIO28 has connected to UART port TXD pin
+
+;port: MDUART0
+;Baudrate: 115200
+;&BASE_ADDR_MDUART0=0xA0010000
+;&BASE_ADDR_MDGPIO=0xC0005000
+
+&BASE_ADDR_MDUART0=0x20010000
+&BASE_ADDR_MDGPIO=0x10005000
+
+
+D.S AXI:&BASE_ADDR_MDGPIO+0x338 %LE %LONG 0x00FF000 //Clear GPIO mode configure
+D.S AXI:&BASE_ADDR_MDGPIO+0x334 %LE %LONG 0x0066000 //Set GPIO27/28 to UART mode.
+D.S SD:&BASE_ADDR_MDUART0+0x24 %LE %LONG 0x03 //High Speed X
+D.S SD:&BASE_ADDR_MDUART0+0x28 %LE %LONG 0xE1 //Sample count
+D.S SD:&BASE_ADDR_MDUART0+0x2C %LE %LONG 0x71 //sample point
+D.S SD:&BASE_ADDR_MDUART0+0x0C %LE %LONG 0x83 //Enable Divisor latch acess bit, and set 8bit length.
+D.S SD:&BASE_ADDR_MDUART0+0x00 %LE %LONG 0x01 //sample point
+D.S SD:&BASE_ADDR_MDUART0+0x04 %LE %LONG 0x00 //sample point
+D.S SD:&BASE_ADDR_MDUART0+0x0C %LE %LONG 0x03 //Clear Divisor latch acess bit, and set 8bit length.
+
+&uart_lsr=0x0
+&uart_rxd=0x0
+PRINT "Please put char "U" from PC to EVB UART! Note: ASCII "U" remap to HEX is 0x55 "
+WHILE (&uart_lsr&0x01)!=0x01
+(
+ &uart_lsr=data.long(sd:&BASE_ADDR_MDUART0+0x14)
+)
+&uart_rxd=data.long(sd:&BASE_ADDR_MDUART0+0x0)
+PRINT "EVB UART Get data: &uart_rxd"
+D.S SD:&BASE_ADDR_MDUART0+0x00 %LE %LONG &uart_rxd //Write data to UART, please check console.
+PRINT "EVB UART will send data to PC,please check!"
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_Frequency_Meter.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_Frequency_Meter.cmm
new file mode 100755
index 0000000..c74ec9b
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_Frequency_Meter.cmm
@@ -0,0 +1,530 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; ZION MD Frequency Meter
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;;Select PLL
+LOCAL &key_in
+&key_in=0
+
+LOCAL &opt_cvd_connect
+&opt_cvd_connect="debug"
+
+;;;;;;;;;;;;;;;;;;;;;;;Below you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+LOCAL &mclass ;; Memory Class
+&mclass="axi"
+;&mclass="pm"
+
+LOCAL &clksw_base ;; MD CLKSW base address
+;&clksw_base=0xA0150000 ;; MD view APB
+;&clksw_base=0xA0096000 ;; MD view debug APB
+&clksw_base=0x20150000 ;; AP view MD system bus
+;&clksw_base=0x0D0D6000 ;; AP view MD debug sys
+
+LOCAL &pll_base ;; MD PLLMIXED base address
+;&pll_base=0xA0140000 ;; MD view APB
+;&pll_base=0xA0094000 ;; MD view debug APB
+&pll_base=0x20140000 ;; AP view MD system bus
+;&pll_base=0x0D0D4000 ;; AP view MD debug sys
+
+&fqmtr_fcksel_32k_index=0x17
+;;;;;;;;;;;;;;;;;;;;;;;Above you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LOCAL &fqmtr_winset ;; Frequency Meter Windoiw Setting (= Number of FIXED clock cycle)
+&fqmtr_winset=0x1ff
+&fqmtr_winset_for_32k=0x1E000
+
+LOCAL &fqmtr_fcksel_val ;; Frequency Meter FIXED clock selection
+&fqmtr_fcksel_val=0x1a ;; Select 26Mhz by default
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;All the PLL you could select;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+&SRC_STR_1="Reserved"
+&SRC_STR_2="Reserved"
+&SRC_STR_3="Reserved"
+&SRC_STR_4="Reserved"
+&SRC_STR_5="Reserved"
+&SRC_STR_6="Reserved"
+&SRC_STR_7="Reserved"
+&SRC_STR_8="Reserved"
+&SRC_STR_9="Reserved"
+&SRC_STR_10="TRACE_MON_clock"
+&SRC_STR_11="MDSYS_208M_clock"
+&SRC_STR_12="mdrxsys_rake_clock"
+&SRC_STR_13="mdrxsys_brp_clock"
+&SRC_STR_14="mdrxsys_vdsp_clock"
+&SRC_STR_15="mdtop_log_atb_clock"
+&SRC_STR_16="fesys_csys_clock"
+&SRC_STR_17="fesys_txsys_clock"
+&SRC_STR_18="fesys_bsi_clock"
+&SRC_STR_19="mdsys_mdcore_clock"
+&SRC_STR_20="mdsys_bus2x_nodcm_clock"
+&SRC_STR_21="mdsys_bus2x_clock"
+&SRC_STR_22="mdtop_dbg_clock"
+&SRC_STR_23="mdtop_f32k_clock"
+&SRC_STR_24="MDBPIPLL_0_DIV2_clock"
+&SRC_STR_25="MDBPIPLL_2_clock"
+&SRC_STR_26="MDBPIPLL_1_clock"
+&SRC_STR_27="MDBPIPLL_0_clock"
+&SRC_STR_28="MDTXPLL_clock"
+&SRC_STR_29="MDBRPPLL_clock"
+&SRC_STR_30="MDVDSPPLL_clock"
+&SRC_STR_31="MDMCUPLL_clock"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+DIALOG
+(&
+ HEADER "PLL Frequency Meter"
+ ICON ":chip"
+
+ POS 0. 0. 20. 1.
+ LINE "FQMTR Selection"
+ ; x y w h
+ POS 0. 1. 20. 1.
+ SEL.NONE: CHOOSEBOX "None"
+ (
+ &key_in=0x00
+ )
+;; SEL.1: CHOOSEBOX "&SRC_STR_1"
+;; (
+;; &key_in=0x1
+;; &key_str="&SRC_STR_1"
+;; )
+;; SEL.2: CHOOSEBOX "&SRC_STR_2"
+;; (
+;; &key_in=0x2
+;; &key_str="&SRC_STR_2"
+;; )
+;; SEL.3: CHOOSEBOX "&SRC_STR_3"
+;; (
+;; &key_in=0x3
+;; &key_str="&SRC_STR_3"
+;; )
+;; SEL.4: CHOOSEBOX "&SRC_STR_4"
+;; (
+;; &key_in=0x4
+;; &key_str="&SRC_STR_4"
+;; )
+;; SEL.5: CHOOSEBOX "&SRC_STR_5"
+;; (
+;; &key_in=0x5
+;; &key_str="&SRC_STR_5"
+;; )
+;; SEL.6: CHOOSEBOX "&SRC_STR_6"
+;; (
+;; &key_in=0x6
+;; &key_str="&SRC_STR_6"
+;; )
+;; SEL.7: CHOOSEBOX "&SRC_STR_7"
+;; (
+;; &key_in=0x7
+;; &key_str="&SRC_STR_7"
+;; )
+;; SEL.8: CHOOSEBOX "&SRC_STR_8"
+;; (
+;; &key_in=0x8
+;; &key_str="&SRC_STR_8"
+;; )
+;; SEL.9: CHOOSEBOX "&SRC_STR_9"
+;; (
+;; &key_in=0x9
+;; &key_str="&SRC_STR_9"
+;; )
+ SEL.10: CHOOSEBOX "&SRC_STR_10"
+ (
+ &key_in=0xA
+ &key_str="&SRC_STR_10"
+ )
+ SEL.11: CHOOSEBOX "&SRC_STR_11"
+ (
+ &key_in=0xB
+ &key_str="&SRC_STR_11"
+ )
+ SEL.12: CHOOSEBOX "&SRC_STR_12"
+ (
+ &key_in=0xC
+ &key_str="&SRC_STR_12"
+ )
+ SEL.13: CHOOSEBOX "&SRC_STR_13"
+ (
+ &key_in=0xD
+ &key_str="&SRC_STR_13"
+ )
+ SEL.14: CHOOSEBOX "&SRC_STR_14"
+ (
+ &key_in=0xE
+ &key_str="&SRC_STR_14"
+ )
+ SEL.15: CHOOSEBOX "&SRC_STR_15"
+ (
+ &key_in=0xF
+ &key_str="&SRC_STR_15"
+ )
+ SEL.16: CHOOSEBOX "&SRC_STR_16"
+ (
+ &key_in=0x10
+ &key_str="&SRC_STR_16"
+ )
+ SEL.17: CHOOSEBOX "&SRC_STR_17"
+ (
+ &key_in=0x11
+ &key_str="&SRC_STR_17"
+ )
+ SEL.18: CHOOSEBOX "&SRC_STR_18"
+ (
+ &key_in=0x12
+ &key_str="&SRC_STR_18"
+ )
+ SEL.19: CHOOSEBOX "&SRC_STR_19"
+ (
+ &key_in=0x13
+ &key_str="&SRC_STR_19"
+ )
+ SEL.20: CHOOSEBOX "&SRC_STR_20"
+ (
+ &key_in=0x14
+ &key_str="&SRC_STR_20"
+ )
+ SEL.21: CHOOSEBOX "&SRC_STR_21"
+ (
+ &key_in=0x15
+ &key_str="&SRC_STR_21"
+ )
+ SEL.22: CHOOSEBOX "&SRC_STR_22"
+ (
+ &key_in=0x16
+ &key_str="&SRC_STR_22"
+ )
+ SEL.23: CHOOSEBOX "&SRC_STR_23"
+ (
+ &key_in=0x17
+ &key_str="&SRC_STR_23"
+ )
+ SEL.24: CHOOSEBOX "&SRC_STR_24"
+ (
+ &key_in=0x18
+ &key_str="&SRC_STR_24"
+ )
+ SEL.25: CHOOSEBOX "&SRC_STR_25"
+ (
+ &key_in=0x19
+ &key_str="&SRC_STR_25"
+ )
+ SEL.26: CHOOSEBOX "&SRC_STR_26"
+ (
+ &key_in=0x1A
+ &key_str="&SRC_STR_26"
+ )
+ SEL.27: CHOOSEBOX "&SRC_STR_27"
+ (
+ &key_in=0x1B
+ &key_str="&SRC_STR_27"
+ )
+ SEL.28: CHOOSEBOX "&SRC_STR_28"
+ (
+ &key_in=0x1C
+ &key_str="&SRC_STR_28"
+ )
+ SEL.29: CHOOSEBOX "&SRC_STR_29"
+ (
+ &key_in=0x1D
+ &key_str="&SRC_STR_29"
+ )
+ SEL.30: CHOOSEBOX "&SRC_STR_30"
+ (
+ &key_in=0x1E
+ &key_str="&SRC_STR_30"
+ )
+ SEL.31: CHOOSEBOX "&SRC_STR_31"
+ (
+ &key_in=0x1F
+ &key_str="&SRC_STR_31"
+ )
+
+ POS 21. 0. 20. 1.
+ LINE "FQMTR Information"
+ INFO1: EDIT "Window Seting: &fqmtr_winset" ""
+ INFO2: EDIT "Fixed Clock: &fqmtr_fcksel_val" ""
+ INFO3: EDIT "32K measure support" ""
+
+ POSY 1. 20. 1.
+ LINE "FQMTR Result"
+ RESULT: EDIT "" ""
+
+ POSY 1. 20. 1.
+ DEFBUTTON "OK"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ IF &key_in!=0
+ (
+ GOSUB fqmtr_query &key_in &key_str 1
+ )
+ )
+
+ DEFBUTTON "LIST ALL"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ GOSUB fqmtr_list_all
+ )
+
+ DEFBUTTON "Force LIST main clk"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ GOSUB fqmtr_force_list_all
+ )
+
+ CLOSE
+ (
+ PRINT "bye~"
+ DIALOG.END
+ )
+)
+
+ ;; Disable EDIT of showing information
+ DIALOG.Disable INFO1
+ DIALOG.Disable INFO2
+ DIALOG.Disable INFO3
+ ;DIALOG.Disable RESULT
+STOP
+ENDDO
+
+;;;;;The main function to get the Frequency. &idx==> the clock you select, &str==> clock name, &info==>list more info and wait 5ms in the function
+;; &info=1 ==> for printing many PLLs at one time
+fqmtr_query:
+ENTRY &idx &str &info
+(
+ IF &info!=0
+ (
+ PRINT "&str: &idx"
+ PRINT "fqmtrsrc: 0x" FORMAT.HEX(2,&idx)
+ PRINT "opt_cvd_connect: &opt_cvd_connect"
+ )
+
+ LOCAL &unit
+ LOCAL &fqmtr_winset_26M
+ LOCAL &fqmtr_result
+ LOCAL &fqmtr_result_raw
+ LOCAL &fqmtr_result_str
+ LOCAL &safe_wait_cnt
+ LOCAL &safe_wait_cnt_max
+ LOCAL &mul_for_32k
+
+ &safe_wait_cnt=0
+
+ IF &fqmtr_fcksel_val==0x1a ;; base on 26M, unit:MHz
+ (
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &unit="Khz"
+ &fqmtr_winset_26M=&fqmtr_winset_for_32k
+ &safe_wait_cnt_max=500 ;;5000 ms = 5s ==> in real test, longer than 5s, so reduce it
+ &mul_for_32k=0x3E8
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &unit="Mhz"
+ &fqmtr_winset_26M=&fqmtr_winset
+ &safe_wait_cnt_max=32 ;;32 ms
+ &mul_for_32k=1
+ )
+ )
+ ELSE
+ (
+ &unit=""
+ )
+
+ IF "&opt_cvd_connect"=="none"
+ (
+ sys.m prepare
+ )
+ ELSE IF "&opt_cvd_connect"=="debug"
+ (
+ ; do nothing
+ )
+ ELSE IF "&opt_cvd_connect"=="ca7"
+ (
+ LOCAL &OPT_JTAG
+ LOCAL &OPT_AP_NR_CPUS
+ LOCAL &OPT_AP_COREBASE
+
+ &OPT_JTAG=0
+ &OPT_AP_NR_CPUS=2
+ &OPT_AP_COREBASE="0x80070000 0x80072000"
+ ;&OPT_AP_NR_CPUS=4
+ ;&OPT_AP_COREBASE="0x80070000 0x80072000 0x80074000 0x80076000"
+ DO CA7_connect.cmm
+ )
+ ELSE
+ (
+ IF &info!=0
+ (
+ PRINT "No explicit CVD connection, use current status"
+ )
+ )
+
+ IF &idx==0
+ (
+ ;; This is used for connect CVD only, no FQMTR test
+ RETURN
+ )
+
+ ;;div 8 and select src
+ Data.Set &mclass:(&clksw_base+0x0104) %LE %LONG 0x0 ;reset frequency meter
+ Data.Set &mclass:(&clksw_base+0x0100) %LE %LONG (0x0300)|(&idx)
+ Data.Set &mclass:(&clksw_base+0x0108) %LE %LONG &fqmtr_winset_26M
+ Data.Set &mclass:(&clksw_base+0x0104) %LE %LONG 0x1 ;enable frequency meter
+
+
+ ;; read status, to check polling done or not
+ &fqmtr_busy=DATA.LONG(&mclass:(&clksw_base+0x0104))&(1<<1)
+ WHILE &fqmtr_busy==0
+ (
+ ;PRINT ". &fqmtr_busy"
+ &fqmtr_busy=DATA.LONG(&mclass:(&clksw_base+0x0104))&(1<<1)
+ &safe_wait_cnt=&safe_wait_cnt+1
+ IF &safe_wait_cnt==&safe_wait_cnt_max
+ (
+ PRINT "[&str] Wait Fail, exit"
+ DIALOG.Set RESULT "Wait Fail(No clock), exit"
+ RETURN
+ )
+ ELSE
+ (
+;; PRINT "Waiting result. safe_wait_cnt=" "&safe_wait_cnt"
+ )
+ WAIT 1ms
+ )
+
+ ;; Calculate the result
+ &fqmtr_result_raw=DATA.LONG(&mclass:(&clksw_base+0x10c))
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*8*&mul_for_32k/&fqmtr_winset_26M
+ &fqmtr_result_dec=FORMAT.DECIMAL(0,&fqmtr_result)
+ &fqmtr_result_str=""+FORMAT.DECIMAL(0,&fqmtr_result)+" &unit"
+ IF &info==0
+ (
+ PRINT "0x" FORMAT.HEX(2,&idx) ",&fqmtr_result_dec,&unit,&str,&fqmtr_result_raw,"
+ )
+ ELSE
+ (
+ PRINT "Frequency Meter Result: &fqmtr_result_str (&fqmtr_result_raw)"
+ PRINT ""
+ )
+ DIALOG.Set RESULT "&fqmtr_result_str"
+
+ IF &info==0
+ (
+ WAIT 5ms
+ )
+
+ RETURN
+)
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+fqmtr_create_win:
+(
+ AREA.RESet
+ AREA.Create PLL_FMETER
+ AREA.Select PLL_FMETER
+ WinPOS 10.,0.,50.,35.,,, FMETER
+ AREA.view PLL_FMETER
+ AREA.Clear PLL_FMETER
+ RETURN
+)
+
+fqmtr_list_all:
+(
+ GOSUB fqmtr_create_win
+
+ ;GOSUB fqmtr_query 0x1 &SRC_STR_1 0
+ ;GOSUB fqmtr_query 0x2 &SRC_STR_2 0
+ ;GOSUB fqmtr_query 0x3 &SRC_STR_3 0
+ ;GOSUB fqmtr_query 0x4 &SRC_STR_4 0
+ ;GOSUB fqmtr_query 0x5 &SRC_STR_5 0
+ ;GOSUB fqmtr_query 0x6 &SRC_STR_6 0
+ ;GOSUB fqmtr_query 0x7 &SRC_STR_7 0
+ ;GOSUB fqmtr_query 0x8 &SRC_STR_8 0
+ ;GOSUB fqmtr_query 0x9 &SRC_STR_9 0
+ GOSUB fqmtr_query 0xA &SRC_STR_10 0
+ GOSUB fqmtr_query 0xB &SRC_STR_11 0
+ GOSUB fqmtr_query 0xC &SRC_STR_12 0
+ GOSUB fqmtr_query 0xD &SRC_STR_13 0
+ GOSUB fqmtr_query 0xE &SRC_STR_14 0
+ GOSUB fqmtr_query 0xF &SRC_STR_15 0
+ GOSUB fqmtr_query 0x10 &SRC_STR_16 0
+ GOSUB fqmtr_query 0x11 &SRC_STR_17 0
+ GOSUB fqmtr_query 0x12 &SRC_STR_18 0
+ GOSUB fqmtr_query 0x13 &SRC_STR_19 0
+ GOSUB fqmtr_query 0x14 &SRC_STR_20 0
+ GOSUB fqmtr_query 0x15 &SRC_STR_21 0
+ GOSUB fqmtr_query 0x16 &SRC_STR_22 0
+ GOSUB fqmtr_query 0x17 &SRC_STR_23 0
+ GOSUB fqmtr_query 0x18 &SRC_STR_24 0
+ GOSUB fqmtr_query 0x19 &SRC_STR_25 0
+ GOSUB fqmtr_query 0x1A &SRC_STR_26 0
+ GOSUB fqmtr_query 0x1B &SRC_STR_27 0
+ GOSUB fqmtr_query 0x1C &SRC_STR_28 0
+ GOSUB fqmtr_query 0x1D &SRC_STR_29 0
+ GOSUB fqmtr_query 0x1E &SRC_STR_30 0
+ GOSUB fqmtr_query 0x1F &SRC_STR_31 0
+ RETURN
+)
+
+fqmtr_force_list_all:
+(
+ GOSUB fqmtr_create_win
+
+ LOCAL &original_reg
+ LOCAL &original_BPIPLLCTL1_reg
+
+ &original_reg=DATA.LONG(&mclass:(&pll_base+0x10))
+ &original_BPIPLLCTL1_reg=DATA.LONG(&mclass:(&pll_base+0x64))
+
+ ; S/W force on all PLL
+ Data.Set &mclass:(&pll_base+0x10) %LE %LONG 0xFFFFFFFF
+
+ ; S/W force on BPI_1 PLL
+ Data.Set &mclass:(&pll_base+0x64) %LE %LONG &original_BPIPLLCTL1_reg|(0x80)
+
+ WAIT 1.s
+
+ ;GOSUB fqmtr_query 0x1 &SRC_STR_1 0
+ ;GOSUB fqmtr_query 0x2 &SRC_STR_2 0
+ ;GOSUB fqmtr_query 0x3 &SRC_STR_3 0
+ ;GOSUB fqmtr_query 0x4 &SRC_STR_4 0
+ ;GOSUB fqmtr_query 0x5 &SRC_STR_5 0
+ ;GOSUB fqmtr_query 0x6 &SRC_STR_6 0
+ ;GOSUB fqmtr_query 0x7 &SRC_STR_7 0
+ ;GOSUB fqmtr_query 0x8 &SRC_STR_8 0
+ ;GOSUB fqmtr_query 0x9 &SRC_STR_9 0
+ GOSUB fqmtr_query 0xA &SRC_STR_10 0
+ GOSUB fqmtr_query 0xB &SRC_STR_11 0
+ GOSUB fqmtr_query 0xC &SRC_STR_12 0
+ GOSUB fqmtr_query 0xD &SRC_STR_13 0
+ GOSUB fqmtr_query 0xE &SRC_STR_14 0
+ GOSUB fqmtr_query 0xF &SRC_STR_15 0
+ GOSUB fqmtr_query 0x10 &SRC_STR_16 0
+ GOSUB fqmtr_query 0x11 &SRC_STR_17 0
+ GOSUB fqmtr_query 0x12 &SRC_STR_18 0
+ GOSUB fqmtr_query 0x13 &SRC_STR_19 0
+ GOSUB fqmtr_query 0x14 &SRC_STR_20 0
+ GOSUB fqmtr_query 0x15 &SRC_STR_21 0
+ GOSUB fqmtr_query 0x16 &SRC_STR_22 0
+ GOSUB fqmtr_query 0x17 &SRC_STR_23 0
+ GOSUB fqmtr_query 0x18 &SRC_STR_24 0
+ GOSUB fqmtr_query 0x19 &SRC_STR_25 0
+ GOSUB fqmtr_query 0x1A &SRC_STR_26 0
+ GOSUB fqmtr_query 0x1B &SRC_STR_27 0
+ GOSUB fqmtr_query 0x1C &SRC_STR_28 0
+ GOSUB fqmtr_query 0x1D &SRC_STR_29 0
+ GOSUB fqmtr_query 0x1E &SRC_STR_30 0
+ GOSUB fqmtr_query 0x1F &SRC_STR_31 0
+
+ ; Revert to original value
+ Data.Set &mclass:(&pll_base+0x10) %LE %LONG &original_reg
+ Data.Set &mclass:(&pll_base+0x64) %LE %LONG &original_BPIPLLCTL1_reg
+
+ WAIT 1.s
+
+ RETURN
+)
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_GPIO_MDUART0.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_GPIO_MDUART0.cmm
new file mode 100755
index 0000000..d2a4e11
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_GPIO_MDUART0.cmm
@@ -0,0 +1,7 @@
+&BASE_ADDR_MDGPIO=0x10005000
+;&BASE_ADDR_MDGPIO=0xC0005000
+
+D.S AXI:&BASE_ADDR_MDGPIO+0x338 %LE %LONG 0x00FF000 //Clear GPIO mode configure
+D.S AXI:&BASE_ADDR_MDGPIO+0x334 %LE %LONG 0x0066000 //Set GPIO27/28 to UART mode.
+D.S AXI:&BASE_ADDR_MDGPIO+0x64 %LE %LONG 0x02000 //Set URXD Pull up enable
+D.S AXI:&BASE_ADDR_MDGPIO+0x48 %LE %LONG 0x02000 //Set URXD Pull down disable.
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_GPIO_SIM.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_GPIO_SIM.cmm
new file mode 100644
index 0000000..71d73de
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_GPIO_SIM.cmm
@@ -0,0 +1,7 @@
+// SIM GPIO
+d.s &MEM_CLASS:0x10005340 %long %le data.long(&MEM_CLASS:0x10005340)&(0x00000FFF)
+d.s &MEM_CLASS:0x10005340 %long %le data.long(&MEM_CLASS:0x10005340)|(0x11111000)
+
+d.s &MEM_CLASS:0x10005350 %long %le data.long(&MEM_CLASS:0x10005350)&(0xFFFFFFF0)
+d.s &MEM_CLASS:0x10005350 %long %le data.long(&MEM_CLASS:0x10005350)|(0x00000001)
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_MD2PERI_disable.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_MD2PERI_disable.cmm
new file mode 100644
index 0000000..3f7eb0d
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_MD2PERI_disable.cmm
@@ -0,0 +1,25 @@
+&MEM_CLASS="AXI"
+; do AP to MD path disable
+LOCAL &BASE_ADDR_AP2MD_Dummy
+LOCAL &BASE_ADDR_INFRA_PERI2MD_PROT_EN
+LOCAL &BASE_ADDR_INFRA_MD2PERI_PROT_EN
+LOCAL &temp
+
+&BASE_ADDR_AP2MD_Dummy=0x10001370
+&BASE_ADDR_INFRA_PERI2MD_PROT_EN=0x10001220
+&BASE_ADDR_INFRA_MD2PERI_PROT_EN=0x10001250
+
+
+&temp=data.long(&MEM_CLASS:(&BASE_ADDR_AP2MD_Dummy+0x0))&0xFFFFFFFE
+;PRINT "temp=" "&temp"
+;PRINT "BASE_ADDR_AP2MD_Dummy=" "&BASE_ADDR_AP2MD_Dummy"
+D.S &MEM_CLASS:(&BASE_ADDR_AP2MD_Dummy+0x0) %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&MEM_CLASS:(&BASE_ADDR_INFRA_MD2PERI_PROT_EN+0x0))|0x40
+;PRINT "temp=" "&temp"
+;PRINT "BASE_ADDR_INFRA_MD2PERI_PROT_EN=" "&BASE_ADDR_INFRA_MD2PERI_PROT_EN"
+D.S &MEM_CLASS:(&BASE_ADDR_INFRA_MD2PERI_PROT_EN+0x0) %LE %LONG &temp
+wait 1.ms
+
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_MD_ForceOnDebugSys.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_MD_ForceOnDebugSys.cmm
new file mode 100755
index 0000000..76a11e0
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_MD_ForceOnDebugSys.cmm
@@ -0,0 +1,10 @@
+;Core1 force on
+d.s &MEM_CLASS:0x200D0004 %long %le 0xB2002383
+;ForceOn debug sys
+d.s &MEM_CLASS:0x20150010 %long %le data.long(&MEM_CLASS:0x20150010)|(0x00080008)
+d.s &MEM_CLASS:0x200D04B0 %long %le data.long(&MEM_CLASS:0x200D04B0)|(0x00000008)
+&temp=data.long(&MEM_CLASS:0x200D0590)
+IF (&temp&0x8008)!=0x8008
+(
+ PRINT "Force on debug sys clock fail"
+)
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_MD_PLL_Init.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_MD_PLL_Init.cmm
new file mode 100755
index 0000000..2ae1f39
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_MD_PLL_Init.cmm
@@ -0,0 +1,126 @@
+; /* Step 6 config PLL setting */
+;;==============================PLL init start==================================================
+;;sys.m prepare
+&MEM_CLASS="AXI"
+
+&BASE_MADDR_APMIXEDSYS=(0x1000C000)
+&BASE_MADDR_MDTOP_PLLMIXED=(0x20140000)
+&BASE_MADDR_MDTOP_CLKSW=(0x20150000)
+
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+®_MDTOP_PLLMIXED_PLL_SW_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x14)
+®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+®_MDTOP_PLLMIXED_MDTXPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x58)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+®_MDTOP_PLLMIXED_MDPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x100)
+®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+®_MDTOP_PLLMIXED_MDPLL_CTL2=(&BASE_MADDR_MDTOP_PLLMIXED+0x108)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+
+®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0x84)
+
+&MD_PLL_MAGIC_NUM=(0x62930000)
+
+;;// initial CLKSQ_LPF
+d.s &MEM_CLASS:®_APMIXEDSYS_AP_PLL_CON0 %long %le data.long(&MEM_CLASS:®_APMIXEDSYS_AP_PLL_CON0)|0x2
+;;// 100us
+wait 1.ms
+
+;;// Default md_srclkena_ack settle time = 136T 32K
+;;//d.s &MEM_CLASS:®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E88
+
+;;//fixed 600MHz(/4), 260MHz(/7) /* Fvco = 1820M
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x80118000
+;;/ 300MHz /* Fvco = 1200M */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDTXPLL_CTL0 %long %le 0x800B8A00
+;;// 300MHz /* Fvco = 1800M */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80114E00
+;;// 450MHz /* Fvco = 1800M */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x80114E00
+;;// 600MHz /* Fvco = 1200M */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x800B8A00
+
+;;// Polling until MDMCUPLL complete frequency adjustment
+;WHILE ((data.long(&MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0
+;(
+;)
+wait 1.ms
+
+;;//In L17, MDPLL should be turn-on first manually, since first calabration requires longer time (100us).
+;;/*TINFO="MDSYS_INIT: MDPLL_208M_OUT_EN off"*/
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDPLL_CTL2 %long %le data.long(&MEM_CLASS:®_MDTOP_PLLMIXED_MDPLL_CTL2)&(~0x10000)
+
+;;/*TINFO="MDSYS_INIT: SW Force ON MDPLL"*/
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_SW_CTL0 %long %le 0x10000
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_SW_CTL0 %long %le 0x10001
+
+;;// 100us
+wait 1.ms
+
+;;/*TINFO="MDSYS_INIT: SW Force OFF MDPLL"*/
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_SW_CTL0 %long %le 0x10000
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_SW_CTL0 %long %le 0x0
+
+;;/*TINFO="MDSYS_INIT: MDPLL_208M_OUT_EN on"*/
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDPLL_CTL2 %long %le data.long(&MEM_CLASS:®_MDTOP_PLLMIXED_MDPLL_CTL2)|(0x10000)
+
+;;// 1us
+wait 1.ms
+
+;;/*TINFO="MDSYS_INIT: Disable AUTOK_EN, MDPLL settle time is 20us NOW (AUTOK_EN can only be setting when MDPLL_EN is OFF, so we add 1us to avoid signals competition)"*/
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le data.long(&MEM_CLASS:®_MDTOP_PLLMIXED_MDPLL_CTL1)&(~0x4000000)
+
+;;/*TINFO="MDSYS_INIT: Wait 1us"*/
+;;// 1us
+wait 1.ms
+
+;;/* Force TXPLL ON due to TOPSM couldn't enable this PLL by default, TXPLL would be disable after DVFS Init.
+;; other PLL ON controlled by HW" */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x100010
+
+;; /*
+;; * Wait MD bus clock ready
+;; * Once MD bus ready, other clock should be ready too
+;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+;; */
+;WHILE (data.long(&MEM_CLASS:®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000
+;(
+;)
+wait 1.ms
+
+;;// Switch MDMCU & MD BUS clock to PLL frequency
+d.s &MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL)|(0x3)
+
+;;// Switch all clock to PLL frequency
+d.s &MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL)|(0x58103FC)
+
+;;// Switch SDF clock to PLL frequency
+d.s &MEM_CLASS:®_MDTOP_CLKSW_SDF_CK_CTL %long %le data.long(&MEM_CLASS:®_MDTOP_CLKSW_SDF_CK_CTL)|(0x10)
+
+;;// Turn off all SW clock request, except ATB
+d.s &MEM_CLASS:®_MDTOP_CLKSW_CLKON_CTL %long %le data.long(&MEM_CLASS:®_MDTOP_CLKSW_CLKON_CTL)|(0x1)
+
+;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+;;// Mask all PLL ADJ RDY IRQ
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+;;// Make a record that means MD pll has been initialized.
+;;/* Note: We use "MD_PLL_MAGIC_NUM|0x1" to know PLL init in MD C code.
+;; If AP init PLL, it would be "MD_PLL_MAGIC_NUM". */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_disable_WDT.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_disable_WDT.cmm
new file mode 100755
index 0000000..521f8f6
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_disable_WDT.cmm
@@ -0,0 +1,11 @@
+;/* Step 6 Disable MD/AP WDT */
+&MEM_CLASS="AXI"
+
+;&BASE_MADDR_MDRGU=0xA00F0000
+;&BASE_MADDR_APRGU=0xC0007000
+&BASE_MADDR_MDRGU=0x200F0000
+;&BASE_MADDR_APRGU=0x10007000
+
+D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x0100 %LE %LONG (0x55000030)
+;D.S &MEM_CLASS:&BASE_MADDR_APRGU %LE %LONG 0x22000064
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_md_srclkena.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_md_srclkena.cmm
new file mode 100755
index 0000000..178fc40
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_md_srclkena.cmm
@@ -0,0 +1,33 @@
+; /* Step 4 config md_srclkena setting */
+&MEM_CLASS="AXI"
+
+; /* (1) INFRA_MISC2 */
+&BASE_INFRACFG=(0x10000000)
+; /* (2) SRCLKEN_O1 force on */
+&SPM_REG=(0x10006000)
+
+
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(&BASE_INFRACFG+0x1F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+
+
+; /* (1) INFRA_MISC2 */
+; /* [3:0] : mdsrc_req_0_en = 4'b0001 */
+d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFFF0)
+d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x1)
+
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 */
+d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFF0F)
+d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x20)
+
+; /* (2) SRCLKEN_O1 force on */
+//MMRF request
+D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x00215830 //set src clkena1 force on
+
+wait 1.ms
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_ungate_clocks.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_ungate_clocks.cmm
new file mode 100644
index 0000000..7b9b212
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/APview_MT6739_ungate_clocks.cmm
@@ -0,0 +1,9 @@
+;/* Ungate MD related clocks */
+&MEM_CLASS="AXI"
+
+&BASE_MADDR_CLK=0x10000000
+
+; Clear BIT8 and BIT9 to ungate MD1 32K and 26M
+D.S &MEM_CLASS:&BASE_MADDR_CLK %LE %LONG data.long(&MEM_CLASS:&BASE_MADDR_CLK)&(0xFFFFFCFF)
+
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/Coretracer_MT6739_Frequency_Meter.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/Coretracer_MT6739_Frequency_Meter.cmm
new file mode 100755
index 0000000..c200fee
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/Coretracer_MT6739_Frequency_Meter.cmm
@@ -0,0 +1,199 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; MT6739 MD Frequency Meter
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+
+;;;;;;;;;;;;;;;;;;;;;;;Below you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LOCAL &clksw_base ;; MD CLKSW base address
+&clksw_base=0xA0150000 ;; MD view APB
+;&clksw_base=0xA0096000 ;; MD view debug APB
+;&clksw_base=0x20150000 ;; AP view MD system bus
+;&clksw_base=0x0D0D6000 ;; AP view MD debug sys
+
+LOCAL &pll_base ;; MD PLLMIXED base address
+&pll_base=0xA0140000 ;; MD view APB
+;&pll_base=0xA0094000 ;; MD view debug APB
+;&pll_base=0x20140000 ;; AP view MD system bus
+;&pll_base=0x0D0D4000 ;; AP view MD debug sys
+
+&fqmtr_fcksel_32k_index=0x17
+
+;;;;;;;;;;;;;;;;;;;;;;;Above you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LOCAL &fqmtr_winset ;; Frequency Meter Windoiw Setting (= Number of FIXED clock cycle)
+&fqmtr_winset=0x1ff
+&fqmtr_winset_for_32k=0x1E000
+
+LOCAL &fqmtr_fcksel_val ;; Frequency Meter FIXED clock selection
+&fqmtr_fcksel_val=0x1a ;; Select 26Mhz by default
+
+&SRC_STR_10="TRACE_MON_clock"
+&SRC_STR_11="MDSYS_208M_clock"
+&SRC_STR_12="mdrxsys_rake_clock"
+&SRC_STR_13="mdrxsys_brp_clock"
+&SRC_STR_14="mdrxsys_vdsp_clock"
+&SRC_STR_15="mdtop_log_atb_clock"
+&SRC_STR_16="fesys_csys_clock"
+&SRC_STR_17="fesys_txsys_clock"
+&SRC_STR_18="fesys_bsi_clock"
+&SRC_STR_19="mdsys_mdcore_clock"
+&SRC_STR_20="mdsys_bus2x_nodcm_clock"
+&SRC_STR_21="mdsys_bus2x_clock"
+&SRC_STR_22="mdtop_dbg_clock"
+&SRC_STR_23="mdtop_f32k_clock"
+&SRC_STR_24="MDBPIPLL_0_DIV2_clock"
+&SRC_STR_25="MDBPIPLL_2_clock"
+&SRC_STR_26="MDBPIPLL_1_clock"
+&SRC_STR_27="MDBPIPLL_0_clock"
+&SRC_STR_28="MDTXPLL_clock"
+&SRC_STR_29="MDBRPPLL_clock"
+&SRC_STR_30="MDVDSPPLL_clock"
+&SRC_STR_31="MDMCUPLL_clock"
+
+LOCAL &idx
+LOCAL &str
+&idx = 0xA;
+&str = "TRACE_MON_clock"
+GOSUB fqmtr_query
+&idx = 0xB;
+&str = "MDSYS_208M_clock"
+GOSUB fqmtr_query
+&idx = 0xC;
+&str = "mdrxsys_rake_clock"
+GOSUB fqmtr_query
+&idx = 0xD;
+&str = "mdrxsys_brp_clock"
+GOSUB fqmtr_query
+&idx = 0xE;
+&str = "mdrxsys_vdsp_clock"
+GOSUB fqmtr_query
+&idx = 0xF;
+&str = "mdtop_log_atb_clock"
+GOSUB fqmtr_query
+&idx = 0x10;
+&str = "fesys_csys_clock"
+GOSUB fqmtr_query
+&idx = 0x11;
+&str = "fesys_txsys_clock"
+GOSUB fqmtr_query
+&idx = 0x12;
+&str = "fesys_bsi_clock"
+GOSUB fqmtr_query
+&idx = 0x13;
+&str = "mdsys_mdcore_clock"
+GOSUB fqmtr_query
+&idx = 0x14;
+&str = "mdsys_bus2x_nodcm_clock"
+GOSUB fqmtr_query
+&idx = 0x15;
+&str = "mdsys_bus2x_clock"
+GOSUB fqmtr_query
+&idx = 0x16;
+&str = "mdtop_dbg_clock"
+GOSUB fqmtr_query
+&idx = 0x17;
+&str = "mdtop_f32k_clock"
+GOSUB fqmtr_query
+&idx = 0x18;
+&str = "MDBPIPLL_0_DIV2_clock"
+GOSUB fqmtr_query
+&idx = 0x19;
+&str = "MDBPIPLL_2_clock"
+GOSUB fqmtr_query
+&idx = 0x1A;
+&str = "MDBPIPLL_1_clock"
+GOSUB fqmtr_query
+&idx = 0x1B;
+&str = "MDBPIPLL_0_clock"
+GOSUB fqmtr_query
+&idx = 0x1C;
+&str = "MDTXPLL_clock"
+GOSUB fqmtr_query
+&idx = 0x1D;
+&str = "MDBRPPLL_clock"
+GOSUB fqmtr_query
+&idx = 0x1E;
+&str = "MDVDSPPLL_clock"
+GOSUB fqmtr_query
+&idx = 0x1F;
+&str = "MDMCUPLL_clock"
+GOSUB fqmtr_query
+
+&idx = 0x20;
+
+;;;;;The main function to get the Frequency. &idx==> the clock you select, &str==> clock name, &info==>list more info and wait 5ms in the function
+;; &info=1 ==> for printing many PLLs at one time
+fqmtr_query:
+ LOCAL &unit
+ LOCAL &fqmtr_winset_26M
+ LOCAL &fqmtr_result
+ LOCAL &fqmtr_result_raw
+ LOCAL &safe_wait_cnt
+ LOCAL &safe_wait_cnt_max
+ LOCAL &mul_for_32k
+
+ &safe_wait_cnt=0
+ IF &idx==0x20
+ (
+ RETURN
+ )
+ ELSE
+ (
+ IF &fqmtr_fcksel_val==0x1a ;; base on 26M, unit:MHz
+ (
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &unit="Khz"
+ &fqmtr_winset_26M=&fqmtr_winset_for_32k
+ &safe_wait_cnt_max=500 ;;5000 ms = 5s ==> in real test, longer than 5s, so reduce it
+ &mul_for_32k=0x3E8
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &unit="Mhz"
+ &fqmtr_winset_26M=&fqmtr_winset
+ &safe_wait_cnt_max=32 ;;32 ms
+ &mul_for_32k=1
+ )
+ )
+
+ ;;div 8 and select src
+ Data.Set (&clksw_base+0x0104) %LE %LONG 0x0 ;reset frequency meter
+ Data.Set (&clksw_base+0x0100) %LE %LONG (0x0300)|(&idx)
+ Data.Set (&clksw_base+0x0108) %LE %LONG &fqmtr_winset_26M
+ Data.Set (&clksw_base+0x0104) %LE %LONG 0x1 ;enable frequency meter
+
+ ;; read status, to check polling done or not
+ &fqmtr_busy=DATA.LONG(&clksw_base+0x0104)&(1<<1)
+
+ WHILE &fqmtr_busy==0
+ (
+; PRINT ". &fqmtr_busy"
+ &fqmtr_busy=DATA.LONG(&clksw_base+0x0104)&(1<<1)
+ &safe_wait_cnt=&safe_wait_cnt+1
+ IF &safe_wait_cnt==&safe_wait_cnt_max
+ (
+ PRINT "[&str] Wait Fail, exit"
+ RETURN
+ )
+ ELSE
+ (
+; PRINT "Waiting result. safe_wait_cnt=" "&safe_wait_cnt"
+ )
+ WAIT 1000.us
+
+ )
+
+ ;; Calculate the result
+ &fqmtr_result_raw=DATA.LONG(&clksw_base+0x10c)
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*8*&mul_for_32k/(&fqmtr_winset_26M+3)
+ &fqmtr_result_dec=&fqmtr_result
+ &fqmtr_result_dec=FORMAT.DECIMAL( 0 , &fqmtr_result )
+
+ PRINT " &idx , &fqmtr_result_dec &unit , &str "
+
+ WAIT 1000.us
+
+ RETURN
+ )
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/MT6739_AP_Attach.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/MT6739_AP_Attach.cmm
new file mode 100755
index 0000000..ccd0067
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/MT6739_AP_Attach.cmm
@@ -0,0 +1,31 @@
+ print "[INFO][MAIN] Attach Target"
+ SYStem.Down
+
+ system.reset
+ SYSTEM.OPTION ENRESET OFF
+ SYStem.Option ResBreak OFF
+ SYStem.Option WaitReset OFF
+ SYStem.JtagClock 10.MHz
+
+ SYStem.CPU CORTEXA53;
+ ;Setting Core debug register access
+ SYStem.CONFIG CORENUMBER 1
+
+
+ SYStem.CONFIG COREBASE 0x8D410000 0x8D510000 0x8D610000 0x8D710000 0x8D810000 0x8D910000 0x8DA10000 0x8DB10000;
+ SYStem.CONFIG CTIBASE 0x8D420000 0x8D520000 0x8D620000 0x8D720000 0x8D820000 0x8D920000 0x8DA20000 0x8DB20000;
+
+ SYStem.CONFIG SWDP ON
+
+
+ SYStem.Attach
+ ON PBREAK GOSUB
+ (
+ print "[INFO][MAIN] Watchdog Disabled"
+ d.s c:0x10211000 %le %long 0x22000064
+
+ )
+ ;SETUP.IMASKHLL ON
+ ;SETUP.IMASKASM ON
+ STOP
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/MT6739_Android_scatter.txt b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/MT6739_Android_scatter.txt
new file mode 100755
index 0000000..fab2be5
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/MT6739_Android_scatter.txt
@@ -0,0 +1,239 @@
+############################################################################################################
+#
+# General Setting
+#
+############################################################################################################
+- general: MTK_PLATFORM_CFG
+ info:
+ - config_version: V1.1.2
+ platform: MT6739
+ project: evb6739_64
+ storage: EMMC
+ boot_channel: MSDC_0
+ block_size: 0x20000
+############################################################################################################
+#
+# Layout Setting
+#
+############################################################################################################
+- partition_index: SYS0
+ partition_name: preloader
+ file_name: preloader_evb6739_64_TINY.bin
+ is_download: true
+ type: SV5_BL_BIN
+ linear_start_addr: 0x0
+ physical_start_addr: 0x0
+ partition_size: 0x40000
+ region: EMMC_BOOT1_BOOT2
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: BOOTLOADERS
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS1
+ partition_name: pgpt
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x0
+ physical_start_addr: 0x0
+ partition_size: 0x800000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS2
+ partition_name: seccfg
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x800000
+ physical_start_addr: 0x800000
+ partition_size: 0x40000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS3
+ partition_name: lk
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x840000
+ physical_start_addr: 0x840000
+ partition_size: 0x60000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS4
+ partition_name: boot
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x8a0000
+ physical_start_addr: 0x8a0000
+ partition_size: 0xa00000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS5
+ partition_name: recovery
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x12a0000
+ physical_start_addr: 0x12a0000
+ partition_size: 0xa00000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS6
+ partition_name: secro
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x1ca0000
+ physical_start_addr: 0x1ca0000
+ partition_size: 0x600000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS7
+ partition_name: logo
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x22a0000
+ physical_start_addr: 0x22a0000
+ partition_size: 0x800000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS8
+ partition_name: expdb
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x2aa0000
+ physical_start_addr: 0x2aa0000
+ partition_size: 0xd60000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS9
+ partition_name: system
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x3800000
+ physical_start_addr: 0x3800000
+ partition_size: 0x2c000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS10
+ partition_name: cache
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x2f800000
+ physical_start_addr: 0x2f800000
+ partition_size: 0x8000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS11
+ partition_name: userdata
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x37800000
+ physical_start_addr: 0x37800000
+ partition_size: 0x50000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS12
+ partition_name: sgpt
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0xFFFF0004
+ physical_start_addr: 0xFFFF0004
+ partition_size: 0x80000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: false
+ is_reserved: true
+ operation_type: RESERVED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/MT6739_EVB_Load_MD_Elf.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/MT6739_EVB_Load_MD_Elf.cmm
new file mode 100755
index 0000000..19c7806
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/MT6739_EVB_Load_MD_Elf.cmm
@@ -0,0 +1,398 @@
+;sys.m prepare
+;LOCAL &TYPE
+LOCAL &BASE_MADDR_MDRGU
+LOCAL &BASE_MADDR_APRGU
+
+
+system.mode attach
+
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+
+
+
+; do orginal disable_WDT2_MIPS.cmm
+&BASE_MADDR_MDRGU=0xA00F0000
+&BASE_MADDR_APRGU=0xC3670000
+
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG (0x55000000|data.long(&BASE_MADDR_MDRGU+0x0100)&~(0x3))
+&temp=data.long(&BASE_MADDR_MDRGU+0x0100)
+&temp=&temp | 0x55000000
+&temp=&temp & ~(0x3)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG &temp
+
+
+PRINT "=============================="
+PRINT "Disable AP WDT!"
+PRINT "=============================="
+
+D.S 0xC0007000 %LE %LONG 0x22000064
+
+
+
+PRINT "=============================="
+PRINT "config md_srclkena setting"
+PRINT "=============================="
+
+; /* Step 4 config md_srclkena setting */
+
+
+; /* (1) INFRA_MISC2 */
+&BASE_INFRACFG=(0xC0000000)
+; /* (2) SRCLKEN_O1 force on */
+&SPM_REG=(0xC0006000)
+
+
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(&BASE_INFRACFG+0x1F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+
+
+; /* (1) INFRA_MISC2 */
+; /* [3:0] : mdsrc_req_0_en = 4'b0001 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFFF0)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x1)
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFFF0)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x1)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFF0F)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x20)
+
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFF0F)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x20)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+; /* (2) SRCLKEN_O1 force on */
+//MMRF request
+;D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+;D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x00215830 //set src clkena1 force on
+D.S &POWERON_CONFIG_EN %LE %LONG 0x0B160001
+D.S &SPM_POWER_ON_VAL1 %LE %LONG 0x00215830
+
+wait 1.ms
+
+
+
+PRINT "=============================="
+PRINT "config PLL setting"
+PRINT "=============================="
+
+; /* Step 5 config PLL setting */
+&BASE_MADDR_APMIXEDSYS=(0xC000C000)
+&BASE_MADDR_MDTOP_PLLMIXED=(0xA0140000)
+&BASE_MADDR_MDTOP_CLKSW=(0xA0150000)
+
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+®_MDTOP_PLLMIXED_PLL_SW_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x14)
+®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+®_MDTOP_PLLMIXED_MDTXPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x58)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+®_MDTOP_PLLMIXED_MDPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x100)
+®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+®_MDTOP_PLLMIXED_MDPLL_CTL2=(&BASE_MADDR_MDTOP_PLLMIXED+0x108)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0x84)
+
+&MD_PLL_MAGIC_NUM=(0x62930000)
+
+;;// initial CLKSQ_LPF
+&temp=data.long(AXI:®_APMIXEDSYS_AP_PLL_CON0)
+&temp=&temp|0x2
+d.s ®_APMIXEDSYS_AP_PLL_CON0 %long %le &temp
+;;// 100us
+wait 1.ms
+
+;;// Default md_srclkena_ack settle time = 136T 32K
+d.s ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E88
+
+;;//fixed 600MHz(/4), 260MHz(/7) /* Fvco = 1820M
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x80118000
+;;/ 300MHz /* Fvco = 1200M */
+d.s ®_MDTOP_PLLMIXED_MDTXPLL_CTL0 %long %le 0x800B8A00
+;;// 300MHz /* Fvco = 1800M */
+d.s ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80114E00
+;;// 450MHz /* Fvco = 1800M */
+d.s ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x80114E00
+;;// 600MHz /* Fvco = 1200M */
+d.s ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x800B8A00
+
+;;// Polling until MDMCUPLL complete frequency adjustment
+;WHILE ((data.long(®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0
+;(
+;)
+wait 1.ms
+
+;;//In L17, MDPLL should be turn-on first manually, since first calabration requires longer time (100us).
+;;/*TINFO="MDSYS_INIT: MDPLL_208M_OUT_EN off"*/
+&temp=data.long(®_MDTOP_PLLMIXED_MDPLL_CTL2)
+&temp=&temp&(~0x10000)
+d.s ®_MDTOP_PLLMIXED_MDPLL_CTL2 %long %le &temp
+
+;;/*TINFO="MDSYS_INIT: SW Force ON MDPLL"*/
+d.s ®_MDTOP_PLLMIXED_PLL_SW_CTL0 %long %le 0x10000
+d.s ®_MDTOP_PLLMIXED_PLL_SW_CTL0 %long %le 0x10001
+
+;;// 100us
+wait 1.ms
+
+;;/*TINFO="MDSYS_INIT: SW Force OFF MDPLL"*/
+d.s ®_MDTOP_PLLMIXED_PLL_SW_CTL0 %long %le 0x10000
+d.s ®_MDTOP_PLLMIXED_PLL_SW_CTL0 %long %le 0x0
+
+;;/*TINFO="MDSYS_INIT: MDPLL_208M_OUT_EN on"*/
+&temp=data.long(®_MDTOP_PLLMIXED_MDPLL_CTL2)
+&temp=&temp|(0x10000)
+d.s ®_MDTOP_PLLMIXED_MDPLL_CTL2 %long %le &temp
+
+;;// 1us
+wait 1.ms
+
+;;/*TINFO="MDSYS_INIT: Disable AUTOK_EN, MDPLL settle time is 20us NOW (AUTOK_EN can only be setting when MDPLL_EN is OFF, so we add 1us to avoid signals competition)"*/
+&temp=data.long(®_MDTOP_PLLMIXED_MDPLL_CTL1)
+&temp=&temp&(~0x4000000)
+d.s ®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le &temp
+
+;;/*TINFO="MDSYS_INIT: Wait 1us"*/
+;;// 1us
+wait 1.ms
+
+;;/* Force TXPLL ON due to TOPSM couldn't enable this PLL by default, TXPLL would be disable after DVFS Init.
+;; other PLL ON controlled by HW" */
+d.s ®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x100010
+
+;; /*
+;; * Wait MD bus clock ready
+;; * Once MD bus ready, other clock should be ready too
+;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+;; */
+;WHILE (data.long(®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000
+;(
+)
+wait 2.ms
+
+;;// Switch MDMCU & MD BUS clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x3)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch all clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x58103FC)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch SDF clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_SDF_CK_CTL)
+&temp=&temp|(0x10)
+d.s ®_MDTOP_CLKSW_SDF_CK_CTL %long %le &temp
+
+;;// Turn off all SW clock request, except ATB
+&temp=data.long(®_MDTOP_CLKSW_CLKON_CTL)
+&temp=&temp|(0x1)
+d.s ®_MDTOP_CLKSW_CLKON_CTL %long %le &temp
+
+;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+;;// Mask all PLL ADJ RDY IRQ
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+;;// Make a record that means MD pll has been initialized.
+;;/* Note: We use "MD_PLL_MAGIC_NUM|0x1" to know PLL init in MD C code.
+;; If AP init PLL, it would be "MD_PLL_MAGIC_NUM". */
+d.s ®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+
+
+PRINT "=============================="
+PRINT "Set GPIO!"
+PRINT "=============================="
+
+// Step 8: Set GPIO
+
+&BASE_ADDR_MDGPIO=0xC0005000
+;&BASE_ADDR_MDIOCFG=0xC1C10000
+
+// MD UART GPIO
+;D.S AXI:&BASE_ADDR_MDGPIO+0x338 %LE %LONG 0xFF000 //Clear GPIO mode configure
+;D.S AXI:&BASE_ADDR_MDGPIO+0x334 %LE %LONG 0x66000 //Set GPIO127/28 to UART mode.
+;D.S AXI:&BASE_ADDR_MDGPIO+0x64 %LE %LONG 0x2000 //Set URXD Pull up enable
+;D.S AXI:&BASE_ADDR_MDGPIO+0x48 %LE %LONG 0x2000 //Set URXD Pull down disable.
+
+D.S &BASE_ADDR_MDGPIO+0x338 %LE %LONG 0xFF000
+D.S &BASE_ADDR_MDGPIO+0x334 %LE %LONG 0x66000
+D.S &BASE_ADDR_MDGPIO+0x64 %LE %LONG 0x2000
+D.S &BASE_ADDR_MDGPIO+0x48 %LE %LONG 0x2000
+
+
+
+// SIM GPIO
+;d.s &MEM_CLASS:0x10005340 %long %le data.long(&MEM_CLASS:0x10005340)&(0x00000FFF)
+;d.s &MEM_CLASS:0x10005340 %long %le data.long(&MEM_CLASS:0x10005340)|(0x11111000)
+
+&temp=data.long(0x10005340)
+&temp=&temp &(0x00000FFF)
+D.S 0x10005340 %LE %LONG &temp
+
+&temp=data.long(0x10005340)
+&temp=&temp |(0x11111000)
+D.S 0x10005340 %LE %LONG &temp
+
+
+
+;d.s &MEM_CLASS:0x10005350 %long %le data.long(&MEM_CLASS:0x10005350)&(0xFFFFFFF0)
+;d.s &MEM_CLASS:0x10005350 %long %le data.long(&MEM_CLASS:0x10005350)|(0x00000001)
+
+&temp=data.long(0x10005350)
+&temp=&temp &(0xFFFFFFF0)
+D.S 0x10005350 %LE %LONG &temp
+
+&temp=data.long(0x10005350)
+&temp=&temp |(0x00000001)
+D.S 0x10005350 %LE %LONG &temp
+
+
+
+PRINT "=============================="
+PRINT "Set MD EMI Remap!"
+PRINT "=============================="
+
+
+;Step 10 set MD EMI remap address (MD view: step 9) ==>review done
+;d.s &MEM_CLASS:0xC0001300 %long %le 0x00430041
+;d.s &MEM_CLASS:0xC0001304 %long %le 0x00470045
+;d.s &MEM_CLASS:0xC0001308 %long %le 0x004b0049
+;d.s &MEM_CLASS:0xC000130c %long %le 0x004b0049
+D.S 0xC0001300 %LE %LONG 0x00430041
+D.S 0xC0001304 %LE %LONG 0x00470045
+D.S 0xC0001308 %LE %LONG 0x004b0049
+D.S 0xC000130c %LE %LONG 0x004b0049
+
+
+
+; do orginal emi_init.cmm
+LOCAL &CHIP_VER ; 0 is for FPGA, 1 is for E1, and so on
+&CHIP_VER=0
+&BASE_ADDR_EMI=0xC3000000
+&BASE_ADDR_DRAMC=0xC3010000
+&BASE_ADDR_DDRPHY=0xC3020000
+&BASE_ADDR_MEMSYSAOREG_MISC=0xC3080000
+&BASE_ADDR_AP_CLKSW=0xC3750000
+
+; Check if initialize
+
+
+&temp=DATA.LONG(&BASE_ADDR_EMI+0060)
+&temp=&temp & 0x00000400
+IF (&temp == 0x00000400)
+(
+ ENDDO
+)
+
+
+
+PRINT "=============================="
+PRINT "Set AP2MD PATH Disable!"
+PRINT "=============================="
+
+; do AP to MD path disable
+&BASE_ADDR_AP2MD_Dummy = 0xC0001370
+&BASE_ADDR_INFRA_PERI2MD_PROT_EN = 0xC0001220
+&BASE_ADDR_INFRA_MD2PERI_PROT_EN = 0xC0001250
+
+
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp & 0xFFFFFFFE
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&BASE_ADDR_INFRA_PERI2MD_PROT_EN)
+&temp = &temp | 0x80
+D.S &BASE_ADDR_INFRA_PERI2MD_PROT_EN %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&BASE_ADDR_INFRA_MD2PERI_PROT_EN)
+&temp = &temp & 0xFFFFFFBF
+D.S &BASE_ADDR_INFRA_MD2PERI_PROT_EN %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp | 0x1
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+
+
+;Enalbe cache to speed loading
+register.set cdmmbase 0x1fc1407
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor adapter_khz 2000
+steal monitor mips32 fastchannel 0 1 0x6f800000
+
+
+PRINT "=============================="
+PRINT "Start to Load elf !"
+PRINT "=============================="
+
+thread.select 1
+steal lo
+
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+PRINT "=============================="
+PRINT "Load elf Done!"
+PRINT "=============================="
+
+thread.select 1
+
+;&t=var.address(INT_Initialize_Phase1)
+;wait 20.ms
+;stop
+;steal set $pc = &INT_Initialize_Phase1
+;register.set pc &t
+
+;PRINT "=============================="
+;PRINT "Set PC to INT_Initialize_Phase1: &t"
+;PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/MT6739_EVB_Load_MD_Elf_With_DSP.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/MT6739_EVB_Load_MD_Elf_With_DSP.cmm
new file mode 100755
index 0000000..56f90de
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/MT6739_EVB_Load_MD_Elf_With_DSP.cmm
@@ -0,0 +1,400 @@
+;sys.m prepare
+;LOCAL &TYPE
+LOCAL &BASE_MADDR_MDRGU
+LOCAL &BASE_MADDR_APRGU
+
+
+system.mode attach
+
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+
+
+
+; do orginal disable_WDT2_MIPS.cmm
+&BASE_MADDR_MDRGU=0xA00F0000
+&BASE_MADDR_APRGU=0xC3670000
+
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG (0x55000000|data.long(&BASE_MADDR_MDRGU+0x0100)&~(0x3))
+&temp=data.long(&BASE_MADDR_MDRGU+0x0100)
+&temp=&temp | 0x55000000
+&temp=&temp & ~(0x3)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG &temp
+
+
+PRINT "=============================="
+PRINT "Disable AP WDT!"
+PRINT "=============================="
+
+D.S 0xC0007000 %LE %LONG 0x22000064
+
+
+
+PRINT "=============================="
+PRINT "config md_srclkena setting"
+PRINT "=============================="
+
+; /* Step 4 config md_srclkena setting */
+
+
+; /* (1) INFRA_MISC2 */
+&BASE_INFRACFG=(0xC0000000)
+; /* (2) SRCLKEN_O1 force on */
+&SPM_REG=(0xC0006000)
+
+
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(&BASE_INFRACFG+0x1F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+
+
+; /* (1) INFRA_MISC2 */
+; /* [3:0] : mdsrc_req_0_en = 4'b0001 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFFF0)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x1)
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFFF0)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x1)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFF0F)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x20)
+
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFF0F)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x20)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+; /* (2) SRCLKEN_O1 force on */
+//MMRF request
+;D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+;D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x00215830 //set src clkena1 force on
+D.S &POWERON_CONFIG_EN %LE %LONG 0x0B160001
+D.S &SPM_POWER_ON_VAL1 %LE %LONG 0x00215830
+
+wait 1.ms
+
+
+
+PRINT "=============================="
+PRINT "config PLL setting"
+PRINT "=============================="
+
+; /* Step 5 config PLL setting */
+&BASE_MADDR_APMIXEDSYS=(0xC000C000)
+&BASE_MADDR_MDTOP_PLLMIXED=(0xA0140000)
+&BASE_MADDR_MDTOP_CLKSW=(0xA0150000)
+
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+®_MDTOP_PLLMIXED_PLL_SW_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x14)
+®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+®_MDTOP_PLLMIXED_MDTXPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x58)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+®_MDTOP_PLLMIXED_MDPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x100)
+®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+®_MDTOP_PLLMIXED_MDPLL_CTL2=(&BASE_MADDR_MDTOP_PLLMIXED+0x108)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0x84)
+
+&MD_PLL_MAGIC_NUM=(0x62930000)
+
+;;// initial CLKSQ_LPF
+&temp=data.long(AXI:®_APMIXEDSYS_AP_PLL_CON0)
+&temp=&temp|0x2
+d.s ®_APMIXEDSYS_AP_PLL_CON0 %long %le &temp
+;;// 100us
+wait 1.ms
+
+;;// Default md_srclkena_ack settle time = 136T 32K
+d.s ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E88
+
+;;//fixed 600MHz(/4), 260MHz(/7) /* Fvco = 1820M
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x80118000
+;;/ 300MHz /* Fvco = 1200M */
+d.s ®_MDTOP_PLLMIXED_MDTXPLL_CTL0 %long %le 0x800B8A00
+;;// 300MHz /* Fvco = 1800M */
+d.s ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80114E00
+;;// 450MHz /* Fvco = 1800M */
+d.s ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x80114E00
+;;// 600MHz /* Fvco = 1200M */
+d.s ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x800B8A00
+
+;;// Polling until MDMCUPLL complete frequency adjustment
+;WHILE ((data.long(®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0
+;(
+;)
+wait 1.ms
+
+;;//In L17, MDPLL should be turn-on first manually, since first calabration requires longer time (100us).
+;;/*TINFO="MDSYS_INIT: MDPLL_208M_OUT_EN off"*/
+&temp=data.long(®_MDTOP_PLLMIXED_MDPLL_CTL2)
+&temp=&temp&(~0x10000)
+d.s ®_MDTOP_PLLMIXED_MDPLL_CTL2 %long %le &temp
+
+;;/*TINFO="MDSYS_INIT: SW Force ON MDPLL"*/
+d.s ®_MDTOP_PLLMIXED_PLL_SW_CTL0 %long %le 0x10000
+d.s ®_MDTOP_PLLMIXED_PLL_SW_CTL0 %long %le 0x10001
+
+;;// 100us
+wait 1.ms
+
+;;/*TINFO="MDSYS_INIT: SW Force OFF MDPLL"*/
+d.s ®_MDTOP_PLLMIXED_PLL_SW_CTL0 %long %le 0x10000
+d.s ®_MDTOP_PLLMIXED_PLL_SW_CTL0 %long %le 0x0
+
+;;/*TINFO="MDSYS_INIT: MDPLL_208M_OUT_EN on"*/
+&temp=data.long(®_MDTOP_PLLMIXED_MDPLL_CTL2)
+&temp=&temp|(0x10000)
+d.s ®_MDTOP_PLLMIXED_MDPLL_CTL2 %long %le &temp
+
+;;// 1us
+wait 1.ms
+
+;;/*TINFO="MDSYS_INIT: Disable AUTOK_EN, MDPLL settle time is 20us NOW (AUTOK_EN can only be setting when MDPLL_EN is OFF, so we add 1us to avoid signals competition)"*/
+&temp=data.long(®_MDTOP_PLLMIXED_MDPLL_CTL1)
+&temp=&temp&(~0x4000000)
+d.s ®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le &temp
+
+;;/*TINFO="MDSYS_INIT: Wait 1us"*/
+;;// 1us
+wait 1.ms
+
+;;/* Force TXPLL ON due to TOPSM couldn't enable this PLL by default, TXPLL would be disable after DVFS Init.
+;; other PLL ON controlled by HW" */
+d.s ®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x100010
+
+;; /*
+;; * Wait MD bus clock ready
+;; * Once MD bus ready, other clock should be ready too
+;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+;; */
+;WHILE (data.long(®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000
+;(
+)
+wait 2.ms
+
+;;// Switch MDMCU & MD BUS clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x3)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch all clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x58103FC)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch SDF clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_SDF_CK_CTL)
+&temp=|(0x10)
+d.s ®_MDTOP_CLKSW_SDF_CK_CTL %long %le &temp
+
+;;// Turn off all SW clock request, except ATB
+&temp=data.long(®_MDTOP_CLKSW_CLKON_CTL)
+&temp=&temp|(0x1)
+d.s ®_MDTOP_CLKSW_CLKON_CTL %long %le &temp
+
+;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+;;// Mask all PLL ADJ RDY IRQ
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+;;// Make a record that means MD pll has been initialized.
+;;/* Note: We use "MD_PLL_MAGIC_NUM|0x1" to know PLL init in MD C code.
+;; If AP init PLL, it would be "MD_PLL_MAGIC_NUM". */
+d.s ®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+
+
+PRINT "=============================="
+PRINT "Set GPIO!"
+PRINT "=============================="
+
+// Step 8: Set GPIO
+
+&BASE_ADDR_MDGPIO=0xC0005000
+;&BASE_ADDR_MDIOCFG=0xC1C10000
+
+// MD UART GPIO
+;D.S AXI:&BASE_ADDR_MDGPIO+0x338 %LE %LONG 0xFF000 //Clear GPIO mode configure
+;D.S AXI:&BASE_ADDR_MDGPIO+0x334 %LE %LONG 0x66000 //Set GPIO127/28 to UART mode.
+;D.S AXI:&BASE_ADDR_MDGPIO+0x64 %LE %LONG 0x2000 //Set URXD Pull up enable
+;D.S AXI:&BASE_ADDR_MDGPIO+0x48 %LE %LONG 0x2000 //Set URXD Pull down disable.
+
+D.S &BASE_ADDR_MDGPIO+0x338 %LE %LONG 0xFF000
+D.S &BASE_ADDR_MDGPIO+0x334 %LE %LONG 0x66000
+D.S &BASE_ADDR_MDGPIO+0x64 %LE %LONG 0x2000
+D.S &BASE_ADDR_MDGPIO+0x48 %LE %LONG 0x2000
+
+
+
+// SIM GPIO
+;d.s &MEM_CLASS:0x10005340 %long %le data.long(&MEM_CLASS:0x10005340)&(0x00000FFF)
+;d.s &MEM_CLASS:0x10005340 %long %le data.long(&MEM_CLASS:0x10005340)|(0x11111000)
+
+&temp=data.long(0x10005340)
+&temp=&temp &(0x00000FFF)
+D.S 0x10005340 %LE %LONG &temp
+
+&temp=data.long(0x10005340)
+&temp=&temp |(0x11111000)
+D.S 0x10005340 %LE %LONG &temp
+
+
+
+;d.s &MEM_CLASS:0x10005350 %long %le data.long(&MEM_CLASS:0x10005350)&(0xFFFFFFF0)
+;d.s &MEM_CLASS:0x10005350 %long %le data.long(&MEM_CLASS:0x10005350)|(0x00000001)
+
+&temp=data.long(0x10005350)
+&temp=&temp &(0xFFFFFFF0)
+D.S 0x10005350 %LE %LONG &temp
+
+&temp=data.long(0x10005350)
+&temp=&temp |(0x00000001)
+D.S 0x10005350 %LE %LONG &temp
+
+
+
+PRINT "=============================="
+PRINT "Set MD EMI Remap!"
+PRINT "=============================="
+
+
+;Step 10 set MD EMI remap address (MD view: step 9) ==>review done
+;d.s &MEM_CLASS:0xC0001300 %long %le 0x00430041
+;d.s &MEM_CLASS:0xC0001304 %long %le 0x00470045
+;d.s &MEM_CLASS:0xC0001308 %long %le 0x004b0049
+;d.s &MEM_CLASS:0xC000130c %long %le 0x004b0049
+D.S 0xC0001300 %LE %LONG 0x00430041
+D.S 0xC0001304 %LE %LONG 0x00470045
+D.S 0xC0001308 %LE %LONG 0x004b0049
+D.S 0xC000130c %LE %LONG 0x004b0049
+
+
+
+; do orginal emi_init.cmm
+LOCAL &CHIP_VER ; 0 is for FPGA, 1 is for E1, and so on
+&CHIP_VER=0
+&BASE_ADDR_EMI=0xC3000000
+&BASE_ADDR_DRAMC=0xC3010000
+&BASE_ADDR_DDRPHY=0xC3020000
+&BASE_ADDR_MEMSYSAOREG_MISC=0xC3080000
+&BASE_ADDR_AP_CLKSW=0xC3750000
+
+; Check if initialize
+
+
+&temp=DATA.LONG(&BASE_ADDR_EMI+0060)
+&temp=&temp & 0x00000400
+IF (&temp == 0x00000400)
+(
+ ENDDO
+)
+
+
+
+PRINT "=============================="
+PRINT "Set AP2MD PATH Disable!"
+PRINT "=============================="
+
+; do AP to MD path disable
+&BASE_ADDR_AP2MD_Dummy = 0xC0001370
+&BASE_ADDR_INFRA_PERI2MD_PROT_EN = 0xC0001220
+&BASE_ADDR_INFRA_MD2PERI_PROT_EN = 0xC0001250
+
+
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp & 0xFFFFFFFE
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&BASE_ADDR_INFRA_PERI2MD_PROT_EN)
+&temp = &temp | 0x80
+D.S &BASE_ADDR_INFRA_PERI2MD_PROT_EN %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&BASE_ADDR_INFRA_MD2PERI_PROT_EN)
+&temp = &temp & 0xFFFFFFBF
+D.S &BASE_ADDR_INFRA_MD2PERI_PROT_EN %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp | 0x1
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+
+
+;Enalbe cache to speed loading
+register.set cdmmbase 0x1fc1407
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor adapter_khz 2000
+steal monitor mips32 fastchannel 0 1 0x6f800000
+
+
+PRINT "=============================="
+PRINT "Start to Load elf !"
+PRINT "=============================="
+
+thread.select 1
+steal lo
+
+steal source ../cmm/coretracer\config\easyLoader\load_dsp.py
+
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+PRINT "=============================="
+PRINT "Load elf Done!"
+PRINT "=============================="
+
+thread.select 1
+
+;&t=var.address(INT_Initialize_Phase1)
+;wait 20.ms
+;stop
+;steal set $pc = &INT_Initialize_Phase1
+;register.set pc &t
+
+;PRINT "=============================="
+;PRINT "Set PC to INT_Initialize_Phase1: &t"
+;PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/MT6739_MD_Only.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/MT6739_MD_Only.cmm
new file mode 100755
index 0000000..ced1068
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/MT6739_MD_Only.cmm
@@ -0,0 +1,59 @@
+;AP pmic workaround
+&MEM_CLASS="AXI"
+sys.m prepare
+wait 1.ms
+
+; Step 1 set vcore to highest gear(0.8V)
+; [Note] CVD script do NOT need this step
+; skip
+
+; Step 2 Ungate md related clocks
+do APview_MT6739_ungate_clocks.cmm
+
+; Step 3 config MD related Buck
+; [Note] CVD script do NOT need this step
+; AP preloader should set Modem related buck
+; skip
+
+; Step 4 power on MTCMOS
+; [Note] CVD script do NOT need this step
+; do APview_MT6739_MTCMOS2.cmm
+; skip
+
+; Step 5 disable MD access register ==> check this!
+;do APview_MT6739_MD2PERI_disable.cmm
+
+; Step 6 config md_srclkena setting ==> done
+do APview_MT6739_md_srclkena.cmm
+
+; Step 7 config PLL setting ==> to be verified
+do APview_MT6739_MD_PLL_Init.cmm
+
+; Step 8 Disable MDWDT/APWDT ==> done
+do APview_MT6739_disable_WDT.cmm
+
+; Step 9 Trigger MD MCU to run (AP view)
+; [Note] Trigger MD MCU by debugger
+; skip
+
+; Step 10 enable MD to Access AP Register ==> check this!
+;do APview_MT6739_AP2MD_enable.cmm
+
+; Step 11 set GPIO (MD view: step 7)==> to be checked
+do APview_MT6739_GPIO_MDUART0.cmm
+do APview_MT6739_GPIO_SIM.cmm
+
+;Step 12 Force on Debug Sys clock (MD view: step 8) ==> done
+;do APview_MT6739_MD_ForceOnDebugSys.cmm
+
+;Step 13 set MD EMI remap address (MD view: step 9) ==> done
+d.s &MEM_CLASS:0x10001300 %long %le 0x00430041
+d.s &MEM_CLASS:0x10001304 %long %le 0x00470045
+d.s &MEM_CLASS:0x10001308 %long %le 0x004b0049
+d.s &MEM_CLASS:0x1000130c %long %le 0x004f004d
+
+; Final Step: Trigger MD MCU to run
+; skip
+
+
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/L1Bypass.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/L1Bypass.act
new file mode 100755
index 0000000..a3c4b52
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/L1Bypass.act
@@ -0,0 +1,6 @@
+<?xml version="1.0"?>
+<Customize>
+ <Action name="L1AssertBypass" icon="">
+ <GDB>p/x L1_ASSERT_BYPASS=3</GDB>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/LoadDSPBin.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/LoadDSPBin.cmm
new file mode 100755
index 0000000..263524f
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/LoadDSPBin.cmm
@@ -0,0 +1,17 @@
+system.mode attach
+
+register.set cdmmbase 0x1fc1407
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor mips32 fastchannel 0 1
+
+&temp_addr = var.address(dsp_bin_ro)
+&temp_addr = &temp_addr & 0x0FFFFFFF
+;&temp_addr = &temp_addr | 0xA0000000
+
+data.load.bin U:\MT6292\UMOLYA\DEV\UMOLYA.BIANCO.BRINGUP.DEV\mcu\build\BIANCO_FPGA\L1S_L1DISABLE\bin\DSP_BIANCO_UMOLYA_BIANCO_BRINGUP_DEV_W17_04_LTE_P3.bin &temp_addr
+;data.load.bin "D:\dsp123.bin" &temp_addr
+
+print "load dsp done!"
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+enddo
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/L1Bypass.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/L1Bypass.act
new file mode 100755
index 0000000..a3c4b52
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/L1Bypass.act
@@ -0,0 +1,6 @@
+<?xml version="1.0"?>
+<Customize>
+ <Action name="L1AssertBypass" icon="">
+ <GDB>p/x L1_ASSERT_BYPASS=3</GDB>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_AllIn1_LoadCode.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_AllIn1_LoadCode.launch
new file mode 100755
index 0000000..c4be7e6
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_AllIn1_LoadCode.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.cacheFile" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearExpression" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.LocalTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<intAttribute key="com.mediatek.ide.util.gdbPortNumber" value="3333"/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<stringAttribute key="com.mediatek.ide.util.ipAddress" value="localhost"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value="hb general_ex_handler"/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value="[CMMAUTOGEN_ROOT]"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="MT6293_Chip"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_AllIn1_LoadCode_With_DSP.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_AllIn1_LoadCode_With_DSP.launch
new file mode 100755
index 0000000..526e5a7
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_AllIn1_LoadCode_With_DSP.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.cacheFile" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearExpression" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.LocalTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<intAttribute key="com.mediatek.ide.util.gdbPortNumber" value="3333"/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<stringAttribute key="com.mediatek.ide.util.ipAddress" value="localhost"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value="hb general_ex_handler source ../cmm/coretracer/config/easyLoader/load_dsp.py"/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value="[CMMAUTOGEN_ROOT]"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="MT6293_Chip"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_AllIn1_LoadCode_non_halt.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_AllIn1_LoadCode_non_halt.launch
new file mode 100755
index 0000000..a215b4c
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_AllIn1_LoadCode_non_halt.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.cacheFile" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearExpression" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.LocalTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<intAttribute key="com.mediatek.ide.util.gdbPortNumber" value="3333"/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<stringAttribute key="com.mediatek.ide.util.ipAddress" value="localhost"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value="[CMMAUTOGEN_ROOT]"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="MT6293_Chip"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_AllIn1_LoadSymbol.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_AllIn1_LoadSymbol.launch
new file mode 100755
index 0000000..2f9190e
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_AllIn1_LoadSymbol.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
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diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_AllIn1_LoadSymbol_non_halt.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_AllIn1_LoadSymbol_non_halt.launch
new file mode 100755
index 0000000..9df1701
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_AllIn1_LoadSymbol_non_halt.launch
@@ -0,0 +1,54 @@
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diff --git "a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadCode\0501\051.launch" "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadCode\0501\051.launch"
new file mode 100755
index 0000000..085a113
--- /dev/null
+++ "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadCode\0501\051.launch"
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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diff --git "a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadCode\0502\051.launch" "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadCode\0502\051.launch"
new file mode 100755
index 0000000..05c2643
--- /dev/null
+++ "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadCode\0502\051.launch"
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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diff --git "a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadCode\0503\051.launch" "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadCode\0503\051.launch"
new file mode 100755
index 0000000..a9756e3
--- /dev/null
+++ "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadCode\0503\051.launch"
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadCode.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadCode.launch
new file mode 100755
index 0000000..4a03a4a
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadCode.launch
@@ -0,0 +1,54 @@
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diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadCode_All.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadCode_All.launch
new file mode 100755
index 0000000..8829a37
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadCode_All.launch
@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.group.launchConfigurationType">
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.name" value="MT6739_Alone_LoadCode"/>
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+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.name" value="MT6739_Alone_LoadCode(1)"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.mode" value="debug"/>
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+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.name" value="MT6739_Alone_LoadCode(3)"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadCode_All.launch.bak b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadCode_All.launch.bak
new file mode 100755
index 0000000..8829a37
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadCode_All.launch.bak
@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.group.launchConfigurationType">
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.enabled" value="true"/>
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+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.name" value="MT6739_Alone_LoadCode"/>
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+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.name" value="MT6739_Alone_LoadCode(1)"/>
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+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+</launchConfiguration>
diff --git "a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadSymbol\0501\051.launch" "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadSymbol\0501\051.launch"
new file mode 100755
index 0000000..085a113
--- /dev/null
+++ "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadSymbol\0501\051.launch"
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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diff --git "a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadSymbol\0502\051.launch" "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadSymbol\0502\051.launch"
new file mode 100755
index 0000000..05c2643
--- /dev/null
+++ "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadSymbol\0502\051.launch"
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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diff --git "a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadSymbol\0503\051.launch" "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadSymbol\0503\051.launch"
new file mode 100755
index 0000000..a9756e3
--- /dev/null
+++ "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadSymbol\0503\051.launch"
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadSymbol.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadSymbol.launch
new file mode 100755
index 0000000..813e482
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadSymbol.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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+<booleanAttribute key="com.mediatek.ide.util.cacheFile" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearExpression" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.RemoteTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<intAttribute key="com.mediatek.ide.util.gdbPortNumber" value="3666"/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<stringAttribute key="com.mediatek.ide.util.ipAddress" value="localhost"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value="hb general_ex_handler"/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value="[CMMAUTOGEN_ROOT]"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="Zion_evb_amp"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="attach"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadSymbol_All.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadSymbol_All.launch
new file mode 100755
index 0000000..6578c62
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadSymbol_All.launch
@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.group.launchConfigurationType">
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.name" value="MT6739_Alone_LoadSymbol"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.name" value="MT6739_Alone_LoadSymbol(1)"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.name" value="MT6739_Alone_LoadSymbol(2)"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.name" value="MT6739_Alone_LoadSymbol(3)"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadSymbol_All.launch.bak b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadSymbol_All.launch.bak
new file mode 100755
index 0000000..6578c62
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/MT6739_Alone_LoadSymbol_All.launch.bak
@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.group.launchConfigurationType">
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.name" value="MT6739_Alone_LoadSymbol"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.name" value="MT6739_Alone_LoadSymbol(1)"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.name" value="MT6739_Alone_LoadSymbol(2)"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.name" value="MT6739_Alone_LoadSymbol(3)"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/easyLoader/CoreTracer_easy_loader.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/easyLoader/CoreTracer_easy_loader.py
new file mode 100755
index 0000000..cc2c2fe
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/easyLoader/CoreTracer_easy_loader.py
@@ -0,0 +1,149 @@
+#from imgtec import codescape
+import sys
+import time
+import os
+import gdb
+import Tkinter, tkFileDialog
+
+#get full path of python script
+file_path = os.path.dirname(os.path.abspath(__file__))
+#append python path into system path
+sys.path.append(file_path)
+
+import load_dsp
+
+app = None
+
+# load all elf
+def load_all_elf(elf_path):
+ time_str = time.time()
+ print "=== Start Loading ELF ==="
+ print "Image path: " + elf_path
+ if(os.path.exists(elf_path) == False):
+ print "[Error] UMOLY ELF doesn't exist: %s" %(elf_path)
+ else:
+ elf_path = elf_path.replace('\\', '/')
+ gdb_cmd = 'symbol-file '+ elf_path
+ print gdb_cmd
+ gdb.execute(gdb_cmd)
+ print "Load SYMBOL successfully"
+ # Add debug point
+ gdb_cmd = 'hb general_ex_vector'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'lo '+ elf_path
+ print gdb_cmd
+ gdb.execute(gdb_cmd)
+ print "Load ELF successfully"
+ time_end = time.time()
+ print("All loading is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+# load all symbol only
+def load_all_sym(elf_path):
+ time_str = time.time()
+ print "=== Start Loading SYMBOL ==="
+ print "Image path: " + elf_path
+ if(os.path.exists(elf_path) == False):
+ print "[Error] UMOLY ELF doesn't exist: %s" %(elf_path)
+ else:
+ elf_path = elf_path.replace('\\', '/')
+ gdb_cmd = 'symbol-file '+ elf_path
+ print gdb_cmd
+ gdb.execute(gdb_cmd)
+ print "Load SYMBOL successfully"
+ # Add debug point
+ gdb_cmd = 'hb general_ex_vector'
+ gdb.execute(gdb_cmd)
+ time_end = time.time()
+ print("All loading is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+# load dsp bin file
+#def load_dsp_bin(dsp_path):
+# time_str = time.time()
+# print "=== Start load dsp bin ==="
+# print "Dsp bin path: " + dsp_path
+# if(os.path.exists(dsp_path) == False):
+# print "[Error] UMOLY DSP binary doesn't exist: %s" %(dsp_path)
+# else:
+# gdb_cmd='thread 1'
+# gdb.execute(gdb_cmd)
+# ## a) need parsing: 0x13a0000 <dsp_bin_ro>
+# ##symbol_name='&dsp_bin_ro'
+# ##dsp_addr = gdb.parse_and_eval(symbol_name)
+# ## b) need parsing: $3 = 0x13a0000
+# ##gdb_cmd='p/x &dsp_bin_ro'
+# ##dsp_addr = gdb.execute(gdb_cmd, False, True)
+# symbol_name='dsp_bin_ro'
+# dsp_addr = gdb.parse_and_eval(symbol_name)
+# dsp_addr = str(dsp_addr.address).split(" ")
+# gdb_cmd = 'restore ' + dsp_path + ' binary ' + str(dsp_addr[0])
+# print gdb_cmd
+# gdb.execute(gdb_cmd)
+# time_end = time.time()
+# print("loading dsp is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+def thread_memory_Write(mem_addr, set_value):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def thread_memory_Read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ mem_value = mem_value[12:23]
+ hex_int = int(mem_value, 16)
+ return hex_int
+
+
+class gui_tk(Tkinter.Tk):
+ def __init__(self, parent):
+ Tkinter.Tk.__init__(self, parent)
+ elf_path = ""
+ dsp_path = ""
+ dsp_addr = ""
+ self.file_opt = options = {}
+ options['title'] = 'Choose a file'
+ self.parent = parent
+ self.initialize()
+
+ def initialize(self):
+ self.grid()
+ elf_button = Tkinter.Button(self, text=u"Load elf", command=self.elf_OnButtonClick)
+ elf_button.grid(column=0, row=1, sticky='W')
+
+ sym_button = Tkinter.Button(self, text=u"Load symbol", command=self.sym_OnButtonClick)
+ sym_button.grid(column=0, row=2, sticky='W')
+
+ dsp_button = Tkinter.Button(self, text=u"Load DSP bin", command=self.dsp_OnButtonClick)
+ dsp_button.grid(column=0, row=3, sticky='W')
+
+ def elf_OnButtonClick(self):
+ elf_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(elf_path) > 0:
+ print "You chose %s" % elf_path
+ load_all_elf(elf_path)
+ self.quit()
+
+ def sym_OnButtonClick(self):
+ elf_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(elf_path) > 0:
+ print "You chose %s" % elf_path
+ load_all_sym(elf_path)
+ self.quit()
+
+ def dsp_OnButtonClick(self):
+ dsp_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(dsp_path) > 0:
+ print "You chose %s" % dsp_path
+ load_dsp.load_dsp_bin(dsp_path)
+ self.quit()
+
+ def quit(self):
+ global app
+ print "=== Close Easy Loader ==="
+ app.destroy()
+
+if __name__ == "__main__":
+ print "=== Start Easy Loader ==="
+ app = gui_tk(None)
+ app.title('Easy Loader')
+ app.mainloop()
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/easyLoader/load_dsp.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/easyLoader/load_dsp.py
new file mode 100755
index 0000000..86e47fa
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/coretracer/config/easyLoader/load_dsp.py
@@ -0,0 +1,106 @@
+#from imgtec import codescape
+import sys
+import time
+import os
+import gdb
+import binascii
+import Tkinter, tkFileDialog
+
+app = None
+dsp_header = 0x0
+dsp_magic = "4d4d4d01"
+
+# load dsp bin file
+def load_dsp_bin(dsp_path):
+ global dsp_header
+ time_str = time.time()
+ print "=== Start load dsp bin ==="
+ print "Dsp bin path: " + dsp_path
+ if(os.path.exists(dsp_path) == False):
+ print "DSP bin doesn't exist: %s" %(dsp_path)
+ print "[Error] Load DSP bin failed"
+ return
+ else:
+ with open(dsp_path, "rb") as dsp_bin:
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print "No header detected, continue"
+ else:
+ dsp_header = 0x200
+ dsp_bin.seek(dsp_header, os.SEEK_SET)
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print "Header detected, skip first 512B"
+ else:
+ print "DSP header detected at neither 0x0 nor 0x200"
+ print "Please check the bin is legal!"
+ print "[Error] Load DSP bin failed"
+ return
+ gdb_cmd='thread 1'
+ gdb.execute(gdb_cmd)
+ ## a) need parsing: 0x13a0000 <dsp_bin_ro>
+ ##symbol_name='&dsp_bin_ro'
+ ##dsp_addr = gdb.parse_and_eval(symbol_name)
+ ## b) need parsing: $3 = 0x13a0000
+ ##gdb_cmd='p/x &dsp_bin_ro'
+ ##dsp_addr = gdb.execute(gdb_cmd, False, True)
+ symbol_name='dsp_bin_ro'
+ dsp_addr = gdb.parse_and_eval(symbol_name)
+ dsp_addr = str(dsp_addr.address).split(" ")
+ dsp_addr = int(dsp_addr[0], 16) - dsp_header
+ print hex(dsp_addr)
+ gdb_cmd = 'monitor mips32 fastchannel 0 1'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'set $cdmmbase=0x1fc1407'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'set *0x1fc100d4=0x02030202'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = " ".join(['restore', dsp_path, 'binary', hex(dsp_addr), hex(dsp_header)])
+ print gdb_cmd
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'set *0x1fc100d4=0x02020202'
+ gdb.execute(gdb_cmd)
+ time_end = time.time()
+ print("loading dsp is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+
+class gui_tk(Tkinter.Tk):
+ def __init__(self, parent):
+ Tkinter.Tk.__init__(self, parent)
+ elf_path = ""
+ dsp_path = ""
+ dsp_addr = ""
+ self.file_opt = options = {}
+ options['title'] = 'Choose a file'
+ self.parent = parent
+ self.initialize()
+
+ def initialize(self):
+ self.grid()
+
+ dsp_button = Tkinter.Button(self, text=u"Load DSP bin =>", command=self.dsp_OnButtonClick)
+ dsp_button.grid(column=0, row=4, sticky='W')
+
+ def dsp_OnButtonClick(self):
+ dsp_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(dsp_path) > 0:
+ print "You chose %s" % dsp_path
+ load_dsp_bin(dsp_path)
+ self.quit()
+
+ def quit(self):
+ global app
+ print "=== Close Easy Loader ==="
+ app.destroy()
+
+def load_dsp_gui():
+ print "=== Start Easy Loader ==="
+ global app
+ app = gui_tk(None)
+ app.title('Easy Loader')
+ app.mainloop()
+
+
+if __name__ == "__main__":
+ load_dsp_gui()
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/mt6739-evb_load_timy_bootloader.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/mt6739-evb_load_timy_bootloader.cmm
new file mode 100755
index 0000000..9ff8f3c
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/mt6739-evb_load_timy_bootloader.cmm
@@ -0,0 +1,114 @@
+;*****************************************************************************
+; Copyright Statement:
+; --------------------
+; This software is protected by Copyright and the information contained
+; herein is confidential. The software may not be copied and the information
+; contained herein may not be used or disclosed except with the written
+; permission of MediaTek Inc. (C) 2011
+;
+;*****************************************************************************
+;;================================================
+;; PURPOSE: EVB Bring Up
+;; CREATE_DATE: 2016/04/01
+;; NOTE:
+;;================================================
+; Specify Core Number
+;=================================================
+
+&NR_CPUS=1
+; cluster 0 corebase: 0x8007000, 0x8007200, 0x8007400, 0x8007600
+; cluster 1 corebase: 0x8009000, 0x8009200, 0x8009400, 0x8009600
+
+;=================================================
+; Initialize CPU
+;=================================================
+&WDT_TEST=0
+if &WDT_TEST==0
+(
+ RESET
+ SYSTEM.OPTION ENRESET ON
+)
+
+SYSTEM.RESET
+SYSTEM.OPTION ENRESET ON
+SYSTEM.OPTION RESBREAK OFF
+SYSTEM.OPTION WAITRESET OFF
+
+SYSTEM.JTAGCLOCK 10.MHz;
+
+;SYSTEM.CPU CortexA7MPCore
+SYStem.CPU CORTEXA53;
+
+;R-T Memory Access
+SYSTEM.MULTICORE MEMORYACCESSPORT 0
+SYSTEM.MULTICORE DEBUGACCESSPORT 1
+
+;SYSTEM.MULTICORE COREBASE APB:0x80070000
+;Setting Core debug register access
+if &NR_CPUS==1
+(
+ SYStem.CONFIG CORENUMBER 1;
+ SYStem.CONFIG COREBASE 0x8D410000;
+ SYStem.CONFIG CTIBASE 0x8D420000;
+)
+else
+(
+ SYSTEM.CONFIG CORENUMBER 2;
+ SYSTEM.CONFIG COREBASE 0x80810000 0x80910000;
+ SYStem.CONFIG CTIBASE 0x80820000 0x80920000;
+)
+
+;=================================================
+; Attach and Stop CPU
+;=================================================
+SYStem.Up
+wait 200.us
+
+SETUP.IMASKHLL ON
+SETUP.IMASKASM ON
+
+;enable L2C 256KB
+D.S SD:0x10200000 %LE %LONG 0x00000000 ;Enable L2C share SRAM (128K)
+D.S SD:0x10200000 %LE %LONG 0x00001000 ;Enable L2C share SRAM (128K)
+
+; set_hw_breakpoint_by_def
+; setting attribute of breakpoints
+Break.Select Program OnChip
+Break.Select Hll OnChip
+Break.Select Spot OnChip
+Break.Select Read OnChip
+Break.Select Write OnChip
+
+D.S C15:0x1 0 ; Turn off MMU
+
+; disable wdt (debug purpose)
+D.S SD:0x10007000 %LE %LONG 0x22000000
+
+; Cancel BWDT timeout, otherwise it would reset in 2 second
+D.S SD:0x100070A4 %LE %LONG 0x66000001
+
+; Init DRAM
+;do MT6739_FPGA_DDR
+
+print "loading pre-loader image"
+d.load.elf ./preloader_evb6739_64_TINY.elf
+
+Y.SPATH.RESET ; reset all source path
+Y.SPATH.SRD ../../platform/mt6739/src/init
+Y.SPATH.SRD ../../platform/mt6739/src/core
+Y.SPATH.SRD ../../platform/mt6739/src/drivers
+Y.SPATH.SRD ../../platform/mt6739/src/security
+Y.SPATH.SRD ../../platform/common
+Y.SPATH.SRD ../../custom/evb6739_64
+
+
+Break.Select Program OnChip
+Break.Select Hll OnChip
+Break.Select Spot OnChip
+Break.Select Read OnChip
+Break.Select Write OnChip
+
+R.S T 0
+;winclear
+d.l
+enddo
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/preloader_evb6739_64_TINY.bin b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/preloader_evb6739_64_TINY.bin
new file mode 100755
index 0000000..25f4881
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/preloader_evb6739_64_TINY.bin
Binary files differ
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/preloader_evb6739_64_TINY.elf b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/preloader_evb6739_64_TINY.elf
new file mode 100755
index 0000000..f98f1bd
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6739/preloader_evb6739_64_TINY.elf
Binary files differ
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APView_MT6761_EVB_UART_Test.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APView_MT6761_EVB_UART_Test.cmm
new file mode 100755
index 0000000..5d2fb21
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APView_MT6761_EVB_UART_Test.cmm
@@ -0,0 +1,38 @@
+;Merlot MD_UART0 port test
+;You should make sure GPIO150 has connected to UART port RXD pin,GPIO151 has connected to UART port TXD pin
+
+;port: MDUART0
+;Baudrate: 115200
+;&BASE_ADDR_MDUART0=0xB0010000
+sys.m prepare
+&BASE_ADDR_MDUART0=0x20010000
+&BASE_ADDR_MDGPIO=0x10005000
+&BASE_ADDR_IOCFG=0x10002600
+
+D.S AXI:&BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_MDGPIO+0x420)&(0x00FFFFFF)
+D.S AXI:&BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_MDGPIO+0x420)|(0x55000000) ;set GPIO150 to MD_URXD0 mode,set GPIO151 to MD_UTXD0 mode,
+
+D.S AXI:&BASE_ADDR_IOCFG+0x60 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x60)&(0xFF7FFFFF) ;MD_URXD0 pull dowm disable
+D.S AXI:&BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)|(0x800000) ;MD_URXD0 pull up enable
+D.S AXI:&BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)&(0xFEFFFFFF) ;MD_UTXD0 pull up disable
+
+
+D.S AXI:&BASE_ADDR_MDUART0+0x24 %LE %LONG 0x03 ;High Speed X
+D.S AXI:&BASE_ADDR_MDUART0+0x28 %LE %LONG 0xE1 ;Sample count
+D.S AXI:&BASE_ADDR_MDUART0+0x2C %LE %LONG 0x71 ;sample point
+D.S AXI:&BASE_ADDR_MDUART0+0x0C %LE %LONG 0x83 ;Enable Divisor latch acess bit, and set 8bit length.
+D.S AXI:&BASE_ADDR_MDUART0+0x00 %LE %LONG 0x01 ;sample point
+D.S AXI:&BASE_ADDR_MDUART0+0x04 %LE %LONG 0x00 ;sample point
+D.S AXI:&BASE_ADDR_MDUART0+0x0C %LE %LONG 0x03 ;Clear Divisor latch acess bit, and set 8bit length.
+
+&uart_lsr=0x0
+&uart_rxd=0x0
+PRINT "Please put char "U" from PC to EVB UART! Note: ASCII "U" remap to HEX is 0x55 "
+WHILE (&uart_lsr&0x01)!=0x01
+(
+ &uart_lsr=data.long(AXI:&BASE_ADDR_MDUART0+0x14)
+)
+&uart_rxd=data.long(AXI:&BASE_ADDR_MDUART0+0x0)
+PRINT "EVB UART Get data: &uart_rxd"
+D.S AXI:&BASE_ADDR_MDUART0+0x00 %LE %LONG &uart_rxd ;Write data to UART, please check console.
+PRINT "EVB UART will send data to PC,please check!"
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APView_MT6761_GPIO_MDUART0.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APView_MT6761_GPIO_MDUART0.cmm
new file mode 100755
index 0000000..d31b29d
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APView_MT6761_GPIO_MDUART0.cmm
@@ -0,0 +1,17 @@
+;Merlot MD_UART0 port test
+;You should make sure GPIO150 has connected to UART port RXD pin,GPIO151 has connected to UART port TXD pin
+
+;port: MDUART0
+;Baudrate: 115200
+;&BASE_ADDR_MDUART0=0xB0010000
+sys.m prepare
+&BASE_ADDR_MDUART0=0x20010000
+&BASE_ADDR_MDGPIO=0x10005000
+&BASE_ADDR_IOCFG=0x10002600
+
+D.S AXI:&BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_MDGPIO+0x420)&(0x00FFFFFF)
+D.S AXI:&BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_MDGPIO+0x420)|(0x55000000) ;set GPIO150 to MD_URXD0 mode,set GPIO151 to MD_UTXD0 mode,
+
+D.S AXI:&BASE_ADDR_IOCFG+0x60 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x60)&(0xFF7FFFFF) ;MD_URXD0 pull dowm disable
+D.S AXI:&BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)|(0x800000) ;MD_URXD0 pull up enable
+D.S AXI:&BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)&(0xFEFFFFFF) ;MD_UTXD0 pull up disable
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APview_MT6761_AP2MD_enable.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APview_MT6761_AP2MD_enable.cmm
new file mode 100755
index 0000000..5a5e6e5
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APview_MT6761_AP2MD_enable.cmm
@@ -0,0 +1,31 @@
+&MEM_CLASS="AXI"
+; do AP to MD path disable
+LOCAL &BASE_ADDR_AP2MD_Dummy
+LOCAL &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN
+LOCAL &temp
+
+&BASE_ADDR_AP2MD_Dummy=0x10001370
+&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN=0x100012A0
+
+; Set peri2md_protect_en
+; Write 0x1000_12A0[7] = 1'b1.
+; MD can access AP if reg_ap2md_dummy[0] = 1'b1,
+&temp=data.long(&MEM_CLASS:(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0x0))|0x80
+;PRINT "temp=" "&temp"
+;PRINT "&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0x0"
+D.S &MEM_CLASS:(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0x0) %LE %LONG &temp
+
+; Clear md2peri_protect_en
+; Write 0x1000_12AC[6] = 1'b1.
+&temp=data.long(&MEM_CLASS:(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC))|0x40
+;PRINT "temp=" "&temp"
+;PRINT "(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC)"
+D.S &MEM_CLASS:(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC) %LE %LONG &temp
+wait 1.ms
+
+; Set reg_ap2md_dummy[0] = 1'b1
+&temp=data.long(&MEM_CLASS:(&BASE_ADDR_AP2MD_Dummy+0x0))|0x1
+;PRINT "temp=" "&temp"
+;PRINT "BASE_ADDR_AP2MD_Dummy=" "&BASE_ADDR_AP2MD_Dummy"
+D.S &MEM_CLASS:(&BASE_ADDR_AP2MD_Dummy+0x0) %LE %LONG &temp
+wait 1.ms
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APview_MT6761_Frequency_Meter.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APview_MT6761_Frequency_Meter.cmm
new file mode 100755
index 0000000..876d33c
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APview_MT6761_Frequency_Meter.cmm
@@ -0,0 +1,546 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; MERLOT MD Frequency Meter
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; do orginal APview_MT6765_disable_WDT.cmm
+LOCAL &BASE_MADDR_MDRGU
+&BASE_MADDR_MDRGU=0xA00F0000
+
+PRINT "=============================="
+PRINT "Disable AP WDT!"
+PRINT "=============================="
+
+D.S SD:0x10007000 %LE %LONG 0x22000000
+
+;;Select PLL
+LOCAL &key_in
+&key_in=0
+
+LOCAL &opt_cvd_connect
+&opt_cvd_connect="debug"
+
+;;;;;;;;;;;;;;;;;;;;;;;Below you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+LOCAL &mclass ;; Memory Class
+&mclass="axi"
+;&mclass="pm"
+
+LOCAL &clksw_base ;; MD CLKSW base address
+;&clksw_base=0xA0150000 ;; MD view APB
+;&clksw_base=0xA0096000 ;; MD view debug APB
+&clksw_base=0x20150000 ;; AP view MD system bus
+;&clksw_base=0x0D0D6000 ;; AP view MD debug sys
+
+LOCAL &pll_base ;; MD PLLMIXED base address
+;&pll_base=0xA0140000 ;; MD view APB
+;&pll_base=0xA0094000 ;; MD view debug APB
+&pll_base=0x20140000 ;; AP view MD system bus
+;&pll_base=0x0D0D4000 ;; AP view MD debug sys
+
+&fqmtr_fcksel_32k_index=0x17
+;;;;;;;;;;;;;;;;;;;;;;;Above you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LOCAL &fqmtr_winset ;; Frequency Meter Windoiw Setting (= Number of FIXED clock cycle)
+&fqmtr_winset=0x1ff
+&fqmtr_winset_for_32k=0x1E000
+
+LOCAL &fqmtr_fcksel_val ;; Frequency Meter FIXED clock selection
+&fqmtr_fcksel_val=0x1a ;; Select 26Mhz by default
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;All the PLL you could select;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+&SRC_STR_1="Reserved"
+&SRC_STR_2="Reserved"
+&SRC_STR_3="Reserved"
+&SRC_STR_4="Reserved"
+&SRC_STR_5="Reserved"
+&SRC_STR_6="Reserved"
+&SRC_STR_7="Reserved"
+&SRC_STR_8="Reserved"
+&SRC_STR_9="Reserved"
+&SRC_STR_10="TRACE_MON_clock"
+&SRC_STR_11="MDSYS_208M_clock"
+&SRC_STR_12="mdrxsys_rake_clock"
+&SRC_STR_13="mdrxsys_brp_clock"
+&SRC_STR_14="mdrxsys_vdsp_clock"
+&SRC_STR_15="mdtop_log_atb_clock"
+&SRC_STR_16="fesys_csys_clock"
+&SRC_STR_17="fesys_txsys_clock"
+&SRC_STR_18="fesys_bsi_clock"
+&SRC_STR_19="mdsys_mdcore_clock"
+&SRC_STR_20="mdsys_bus2x_nodcm_clock"
+&SRC_STR_21="mdsys_bus2x_clock"
+&SRC_STR_22="mdtop_dbg_clock"
+&SRC_STR_23="mdtop_f32k_clock"
+&SRC_STR_24="MDBPIPLL_0_DIV2_clock"
+&SRC_STR_25="MDBPIPLL_2_clock"
+&SRC_STR_26="MDBPIPLL_1_clock"
+&SRC_STR_27="MDBPIPLL_0_clock"
+&SRC_STR_28="MDTXPLL_clock"
+&SRC_STR_29="MDBRPPLL_clock"
+&SRC_STR_30="MDVDSPPLL_clock"
+&SRC_STR_31="MDMCUPLL_clock"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+DIALOG
+(&
+ HEADER "PLL Frequency Meter"
+ ICON ":chip"
+
+ POS 0. 0. 20. 1.
+ LINE "FQMTR Selection"
+ ; x y w h
+ POS 0. 1. 20. 1.
+ SEL.NONE: CHOOSEBOX "None"
+ (
+ &key_in=0x00
+ )
+;; SEL.1: CHOOSEBOX "&SRC_STR_1"
+;; (
+;; &key_in=0x1
+;; &key_str="&SRC_STR_1"
+;; )
+;; SEL.2: CHOOSEBOX "&SRC_STR_2"
+;; (
+;; &key_in=0x2
+;; &key_str="&SRC_STR_2"
+;; )
+;; SEL.3: CHOOSEBOX "&SRC_STR_3"
+;; (
+;; &key_in=0x3
+;; &key_str="&SRC_STR_3"
+;; )
+;; SEL.4: CHOOSEBOX "&SRC_STR_4"
+;; (
+;; &key_in=0x4
+;; &key_str="&SRC_STR_4"
+;; )
+;; SEL.5: CHOOSEBOX "&SRC_STR_5"
+;; (
+;; &key_in=0x5
+;; &key_str="&SRC_STR_5"
+;; )
+;; SEL.6: CHOOSEBOX "&SRC_STR_6"
+;; (
+;; &key_in=0x6
+;; &key_str="&SRC_STR_6"
+;; )
+;; SEL.7: CHOOSEBOX "&SRC_STR_7"
+;; (
+;; &key_in=0x7
+;; &key_str="&SRC_STR_7"
+;; )
+;; SEL.8: CHOOSEBOX "&SRC_STR_8"
+;; (
+;; &key_in=0x8
+;; &key_str="&SRC_STR_8"
+;; )
+;; SEL.9: CHOOSEBOX "&SRC_STR_9"
+;; (
+;; &key_in=0x9
+;; &key_str="&SRC_STR_9"
+;; )
+ SEL.10: CHOOSEBOX "&SRC_STR_10"
+ (
+ &key_in=0xA
+ &key_str="&SRC_STR_10"
+ )
+ SEL.11: CHOOSEBOX "&SRC_STR_11"
+ (
+ &key_in=0xB
+ &key_str="&SRC_STR_11"
+ )
+ SEL.12: CHOOSEBOX "&SRC_STR_12"
+ (
+ &key_in=0xC
+ &key_str="&SRC_STR_12"
+ )
+ SEL.13: CHOOSEBOX "&SRC_STR_13"
+ (
+ &key_in=0xD
+ &key_str="&SRC_STR_13"
+ )
+ SEL.14: CHOOSEBOX "&SRC_STR_14"
+ (
+ &key_in=0xE
+ &key_str="&SRC_STR_14"
+ )
+ SEL.15: CHOOSEBOX "&SRC_STR_15"
+ (
+ &key_in=0xF
+ &key_str="&SRC_STR_15"
+ )
+ SEL.16: CHOOSEBOX "&SRC_STR_16"
+ (
+ &key_in=0x10
+ &key_str="&SRC_STR_16"
+ )
+ SEL.17: CHOOSEBOX "&SRC_STR_17"
+ (
+ &key_in=0x11
+ &key_str="&SRC_STR_17"
+ )
+ SEL.18: CHOOSEBOX "&SRC_STR_18"
+ (
+ &key_in=0x12
+ &key_str="&SRC_STR_18"
+ )
+ SEL.19: CHOOSEBOX "&SRC_STR_19"
+ (
+ &key_in=0x13
+ &key_str="&SRC_STR_19"
+ )
+ SEL.20: CHOOSEBOX "&SRC_STR_20"
+ (
+ &key_in=0x14
+ &key_str="&SRC_STR_20"
+ )
+ SEL.21: CHOOSEBOX "&SRC_STR_21"
+ (
+ &key_in=0x15
+ &key_str="&SRC_STR_21"
+ )
+ SEL.22: CHOOSEBOX "&SRC_STR_22"
+ (
+ &key_in=0x16
+ &key_str="&SRC_STR_22"
+ )
+ SEL.23: CHOOSEBOX "&SRC_STR_23"
+ (
+ &key_in=0x17
+ &key_str="&SRC_STR_23"
+ )
+ SEL.24: CHOOSEBOX "&SRC_STR_24"
+ (
+ &key_in=0x18
+ &key_str="&SRC_STR_24"
+ )
+ SEL.25: CHOOSEBOX "&SRC_STR_25"
+ (
+ &key_in=0x19
+ &key_str="&SRC_STR_25"
+ )
+ SEL.26: CHOOSEBOX "&SRC_STR_26"
+ (
+ &key_in=0x1A
+ &key_str="&SRC_STR_26"
+ )
+ SEL.27: CHOOSEBOX "&SRC_STR_27"
+ (
+ &key_in=0x1B
+ &key_str="&SRC_STR_27"
+ )
+ SEL.28: CHOOSEBOX "&SRC_STR_28"
+ (
+ &key_in=0x1C
+ &key_str="&SRC_STR_28"
+ )
+ SEL.29: CHOOSEBOX "&SRC_STR_29"
+ (
+ &key_in=0x1D
+ &key_str="&SRC_STR_29"
+ )
+ SEL.30: CHOOSEBOX "&SRC_STR_30"
+ (
+ &key_in=0x1E
+ &key_str="&SRC_STR_30"
+ )
+ SEL.31: CHOOSEBOX "&SRC_STR_31"
+ (
+ &key_in=0x1F
+ &key_str="&SRC_STR_31"
+ )
+
+ POS 21. 0. 20. 1.
+ LINE "FQMTR Information"
+ INFO1: EDIT "Window Seting: &fqmtr_winset" ""
+ INFO2: EDIT "Fixed Clock: &fqmtr_fcksel_val" ""
+ INFO3: EDIT "32K measure support" ""
+
+ POSY 1. 20. 1.
+ LINE "FQMTR Result"
+ RESULT: EDIT "" ""
+
+ POSY 1. 20. 1.
+ DEFBUTTON "OK"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ IF &key_in!=0
+ (
+ GOSUB fqmtr_query &key_in &key_str 1
+ )
+ )
+
+ DEFBUTTON "LIST ALL"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ GOSUB fqmtr_list_all
+ )
+
+ DEFBUTTON "Force LIST main clk"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ GOSUB fqmtr_force_list_all
+ )
+
+ CLOSE
+ (
+ PRINT "bye~"
+ DIALOG.END
+ )
+)
+
+ ;; Disable EDIT of showing information
+ DIALOG.Disable INFO1
+ DIALOG.Disable INFO2
+ DIALOG.Disable INFO3
+ ;DIALOG.Disable RESULT
+STOP
+ENDDO
+
+;;;;;The main function to get the Frequency. &idx==> the clock you select, &str==> clock name, &info==>list more info and wait 5ms in the function
+;; &info=1 ==> for printing many PLLs at one time
+fqmtr_query:
+ENTRY &idx &str &info
+(
+ IF &info!=0
+ (
+ PRINT "&str: &idx"
+ PRINT "fqmtrsrc: 0x" FORMAT.HEX(2,&idx)
+ PRINT "opt_cvd_connect: &opt_cvd_connect"
+ )
+
+ LOCAL &unit
+ LOCAL &fqmtr_winset_26M
+ LOCAL &fqmtr_result
+ LOCAL &fqmtr_result_raw
+ LOCAL &fqmtr_result_str
+ LOCAL &safe_wait_cnt
+ LOCAL &safe_wait_cnt_max
+ LOCAL &fqmtr_busy
+
+ &safe_wait_cnt=0
+
+ IF &fqmtr_fcksel_val==0x1a ;; base on 26M, unit:MHz
+ (
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &unit="Khz"
+ &fqmtr_winset_26M=&fqmtr_winset_for_32k
+ &safe_wait_cnt_max=500 ;;5000 ms = 5s ==> in real test, longer than 5s, so reduce it
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &unit="Mhz"
+ &fqmtr_winset_26M=&fqmtr_winset
+ &safe_wait_cnt_max=32 ;;32 ms
+ )
+ )
+ ELSE
+ (
+ &unit=""
+ )
+
+ IF "&opt_cvd_connect"=="none"
+ (
+ sys.m prepare
+ )
+ ELSE IF "&opt_cvd_connect"=="debug"
+ (
+ ; do nothing
+ )
+ ELSE
+ (
+ IF &info!=0
+ (
+ PRINT "No explicit CVD connection, use current status"
+ )
+ )
+
+ IF &idx==0
+ (
+ ;; This is used for connect CVD only, no FQMTR test
+ RETURN
+ )
+
+ ;;select source to a valid clock to let reset success.
+ Data.Set &mclass:(&clksw_base+0x0100) %LE %LONG 0x13
+ Data.Set &mclass:(&clksw_base+0x0104) %LE %LONG 0x0 ;reset frequency meter
+ WAIT 1ms
+
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ ;;For accurate, don't div 8 for 32K
+ Data.Set &mclass:(&clksw_base+0x0100) %LE %LONG (&idx)
+ )
+ ELSE ;; measure PLL and other module
+ (
+ ;;div 8 and select src
+ Data.Set &mclass:(&clksw_base+0x0100) %LE %LONG (0x0300)|(&idx)
+ )
+
+ Data.Set &mclass:(&clksw_base+0x0108) %LE %LONG &fqmtr_winset_26M
+ Data.Set &mclass:(&clksw_base+0x0104) %LE %LONG 0x1 ;enable frequency meter
+
+ ;; read status, to check polling done or not
+ &fqmtr_busy=DATA.LONG(&mclass:(&clksw_base+0x0104))&(1<<1)
+ WHILE &fqmtr_busy==0
+ (
+ ;PRINT ". &fqmtr_busy"
+ &fqmtr_busy=DATA.LONG(&mclass:(&clksw_base+0x0104))&(1<<1)
+ &safe_wait_cnt=&safe_wait_cnt+1
+ IF &safe_wait_cnt==&safe_wait_cnt_max
+ (
+ PRINT "[&str] Wait Fail, exit"
+ DIALOG.Set RESULT "Wait Fail(No clock), exit"
+ RETURN
+ )
+ ELSE
+ (
+;; PRINT "Waiting result. safe_wait_cnt=" "&safe_wait_cnt"
+ )
+ WAIT 1ms
+ )
+
+ ;; Calculate the result
+ &fqmtr_result_raw=DATA.LONG(&mclass:(&clksw_base+0x10c))
+
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*(0x3E8)/(&fqmtr_winset_26M+3)
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*8/(&fqmtr_winset_26M+3)
+ )
+
+ &fqmtr_result_dec=FORMAT.DECIMAL(0,&fqmtr_result)
+ &fqmtr_result_str=""+FORMAT.DECIMAL(0,&fqmtr_result)+" &unit"
+ IF &info==0
+ (
+ PRINT "0x" FORMAT.HEX(2,&idx) ",&fqmtr_result_dec,&unit,&str,&fqmtr_result_raw,"
+ )
+ ELSE
+ (
+ PRINT "Frequency Meter Result: &fqmtr_result_str (&fqmtr_result_raw)"
+ PRINT ""
+ )
+ DIALOG.Set RESULT "&fqmtr_result_str"
+
+ IF &info==0
+ (
+ WAIT 5ms
+ )
+
+ RETURN
+)
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+fqmtr_create_win:
+(
+ AREA.RESet
+ AREA.Create PLL_FMETER
+ AREA.Select PLL_FMETER
+ WinPOS 10.,0.,50.,35.,,, FMETER
+ AREA.view PLL_FMETER
+ AREA.Clear PLL_FMETER
+ RETURN
+)
+
+fqmtr_list_all:
+(
+ GOSUB fqmtr_create_win
+
+ ;GOSUB fqmtr_query 0x1 &SRC_STR_1 0
+ ;GOSUB fqmtr_query 0x2 &SRC_STR_2 0
+ ;GOSUB fqmtr_query 0x3 &SRC_STR_3 0
+ ;GOSUB fqmtr_query 0x4 &SRC_STR_4 0
+ ;GOSUB fqmtr_query 0x5 &SRC_STR_5 0
+ ;GOSUB fqmtr_query 0x6 &SRC_STR_6 0
+ ;GOSUB fqmtr_query 0x7 &SRC_STR_7 0
+ ;GOSUB fqmtr_query 0x8 &SRC_STR_8 0
+ ;GOSUB fqmtr_query 0x9 &SRC_STR_9 0
+ GOSUB fqmtr_query 0xA &SRC_STR_10 0
+ GOSUB fqmtr_query 0xB &SRC_STR_11 0
+ GOSUB fqmtr_query 0xC &SRC_STR_12 0
+ GOSUB fqmtr_query 0xD &SRC_STR_13 0
+ GOSUB fqmtr_query 0xE &SRC_STR_14 0
+ GOSUB fqmtr_query 0xF &SRC_STR_15 0
+ GOSUB fqmtr_query 0x10 &SRC_STR_16 0
+ GOSUB fqmtr_query 0x11 &SRC_STR_17 0
+ GOSUB fqmtr_query 0x12 &SRC_STR_18 0
+ GOSUB fqmtr_query 0x13 &SRC_STR_19 0
+ GOSUB fqmtr_query 0x14 &SRC_STR_20 0
+ GOSUB fqmtr_query 0x15 &SRC_STR_21 0
+ GOSUB fqmtr_query 0x16 &SRC_STR_22 0
+ GOSUB fqmtr_query 0x17 &SRC_STR_23 0
+ GOSUB fqmtr_query 0x18 &SRC_STR_24 0
+ GOSUB fqmtr_query 0x19 &SRC_STR_25 0
+ GOSUB fqmtr_query 0x1A &SRC_STR_26 0
+ GOSUB fqmtr_query 0x1B &SRC_STR_27 0
+ GOSUB fqmtr_query 0x1C &SRC_STR_28 0
+ GOSUB fqmtr_query 0x1D &SRC_STR_29 0
+ GOSUB fqmtr_query 0x1E &SRC_STR_30 0
+ GOSUB fqmtr_query 0x1F &SRC_STR_31 0
+ RETURN
+)
+
+fqmtr_force_list_all:
+(
+ GOSUB fqmtr_create_win
+
+ LOCAL &original_reg
+ LOCAL &original_BPIPLLCTL1_reg
+
+ &original_reg=DATA.LONG(&mclass:(&pll_base+0x10))
+ &original_BPIPLLCTL1_reg=DATA.LONG(&mclass:(&pll_base+0x64))
+
+ ; S/W force on all PLL
+ Data.Set &mclass:(&pll_base+0x10) %LE %LONG 0xFFFFFFFF
+
+ ; S/W force on BPI_1 PLL
+ Data.Set &mclass:(&pll_base+0x64) %LE %LONG &original_BPIPLLCTL1_reg|(0x80)
+
+ WAIT 1.s
+
+ ;GOSUB fqmtr_query 0x1 &SRC_STR_1 0
+ ;GOSUB fqmtr_query 0x2 &SRC_STR_2 0
+ ;GOSUB fqmtr_query 0x3 &SRC_STR_3 0
+ ;GOSUB fqmtr_query 0x4 &SRC_STR_4 0
+ ;GOSUB fqmtr_query 0x5 &SRC_STR_5 0
+ ;GOSUB fqmtr_query 0x6 &SRC_STR_6 0
+ ;GOSUB fqmtr_query 0x7 &SRC_STR_7 0
+ ;GOSUB fqmtr_query 0x8 &SRC_STR_8 0
+ ;GOSUB fqmtr_query 0x9 &SRC_STR_9 0
+ GOSUB fqmtr_query 0xA &SRC_STR_10 0
+ GOSUB fqmtr_query 0xB &SRC_STR_11 0
+ GOSUB fqmtr_query 0xC &SRC_STR_12 0
+ GOSUB fqmtr_query 0xD &SRC_STR_13 0
+ GOSUB fqmtr_query 0xE &SRC_STR_14 0
+ GOSUB fqmtr_query 0xF &SRC_STR_15 0
+ GOSUB fqmtr_query 0x10 &SRC_STR_16 0
+ GOSUB fqmtr_query 0x11 &SRC_STR_17 0
+ GOSUB fqmtr_query 0x12 &SRC_STR_18 0
+ GOSUB fqmtr_query 0x13 &SRC_STR_19 0
+ GOSUB fqmtr_query 0x14 &SRC_STR_20 0
+ GOSUB fqmtr_query 0x15 &SRC_STR_21 0
+ GOSUB fqmtr_query 0x16 &SRC_STR_22 0
+ GOSUB fqmtr_query 0x17 &SRC_STR_23 0
+ GOSUB fqmtr_query 0x18 &SRC_STR_24 0
+ GOSUB fqmtr_query 0x19 &SRC_STR_25 0
+ GOSUB fqmtr_query 0x1A &SRC_STR_26 0
+ GOSUB fqmtr_query 0x1B &SRC_STR_27 0
+ GOSUB fqmtr_query 0x1C &SRC_STR_28 0
+ GOSUB fqmtr_query 0x1D &SRC_STR_29 0
+ GOSUB fqmtr_query 0x1E &SRC_STR_30 0
+ GOSUB fqmtr_query 0x1F &SRC_STR_31 0
+
+ ; Revert to original value
+ Data.Set &mclass:(&pll_base+0x10) %LE %LONG &original_reg
+ Data.Set &mclass:(&pll_base+0x64) %LE %LONG &original_BPIPLLCTL1_reg
+
+ WAIT 1.s
+
+ RETURN
+)
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APview_MT6761_GPIO_SIM.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APview_MT6761_GPIO_SIM.cmm
new file mode 100755
index 0000000..c18702b
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APview_MT6761_GPIO_SIM.cmm
@@ -0,0 +1,20 @@
+// SIM GPIO MODE
+// Clear bits
+d.s &MEM_CLASS:0x10005348 %long %le 0x77777000
+d.s &MEM_CLASS:0x10005358 %long %le 0x00000007
+// Set bits
+d.s &MEM_CLASS:0x10005344 %long %le 0x11111000
+d.s &MEM_CLASS:0x10005354 %long %le 0x00000001
+
+// SIM PUPD
+// Control PAD_SIM1_SIO PUPD pin. PUPD=0: pull up, PUPD=1: pull down.
+// Set bits
+d.s &MEM_CLASS:0x10002454 %long %le 0x00000FC0
+// Clear bits, SIO pull up
+d.s &MEM_CLASS:0x10002458 %long %le 0x00000480
+
+// SIM R1R0
+// R1R0=00:High-Z, R1R0=01:PU 45kohm;PD 75kohm,
+// R1R0=10:PU 5kohm;PD 75kohm, R1R0=11:PU 45kohm/5kohm;PD 75kohm/75kohm.
+// Set R1 bits
+d.s &MEM_CLASS:0x10002484 %long %le 0x00000FC0
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APview_MT6761_MD2PERI_disable.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APview_MT6761_MD2PERI_disable.cmm
new file mode 100755
index 0000000..ab13db2
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APview_MT6761_MD2PERI_disable.cmm
@@ -0,0 +1,29 @@
+&MEM_CLASS="AXI"
+; do AP to MD path disable
+; MD cannot access AP after running this script
+LOCAL &BASE_ADDR_AP2MD_Dummy
+LOCAL &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN
+LOCAL &temp
+
+&BASE_ADDR_AP2MD_Dummy=0x10001370
+&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN=0x100012A0
+
+; Set reg_ap2md_dummy[0] = 1'b0
+&temp=data.long(&MEM_CLASS:(&BASE_ADDR_AP2MD_Dummy+0x0))&0xFFFFFFFE
+;PRINT "temp=" "&temp"
+;PRINT "BASE_ADDR_AP2MD_Dummy=" "&BASE_ADDR_AP2MD_Dummy"
+D.S &MEM_CLASS:(&BASE_ADDR_AP2MD_Dummy+0x0) %LE %LONG &temp
+wait 1.ms
+
+; Set md2peri_protect_en = 1'b1
+; Write 0x1000_12A8[6] = 1'b1.
+&temp=data.long(&MEM_CLASS:(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0x8))|0x40
+;PRINT "temp=" "&temp"
+;PRINT "(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0x8)"
+D.S &MEM_CLASS:(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0x8) %LE %LONG &temp
+wait 1.ms
+
+; Check md2peri_protect_en setting
+;&temp=data.long(&MEM_CLASS:(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0x8))
+;PRINT "temp=" "&temp"
+;PRINT "(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0x8)"
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APview_MT6761_MD_ForceOnDebugSys.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APview_MT6761_MD_ForceOnDebugSys.cmm
new file mode 100755
index 0000000..76a11e0
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APview_MT6761_MD_ForceOnDebugSys.cmm
@@ -0,0 +1,10 @@
+;Core1 force on
+d.s &MEM_CLASS:0x200D0004 %long %le 0xB2002383
+;ForceOn debug sys
+d.s &MEM_CLASS:0x20150010 %long %le data.long(&MEM_CLASS:0x20150010)|(0x00080008)
+d.s &MEM_CLASS:0x200D04B0 %long %le data.long(&MEM_CLASS:0x200D04B0)|(0x00000008)
+&temp=data.long(&MEM_CLASS:0x200D0590)
+IF (&temp&0x8008)!=0x8008
+(
+ PRINT "Force on debug sys clock fail"
+)
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APview_MT6761_MD_PLL_Init.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APview_MT6761_MD_PLL_Init.cmm
new file mode 100755
index 0000000..bf3ddc8
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APview_MT6761_MD_PLL_Init.cmm
@@ -0,0 +1,101 @@
+; /* Step 6 config PLL setting */
+;;==============================PLL init start==================================================
+;;sys.m prepare
+&MEM_CLASS="AXI"
+
+&BASE_MADDR_APMIXEDSYS=(0x1000C000)
+&BASE_MADDR_MDTOP_PLLMIXED=(0x20140000)
+&BASE_MADDR_MDTOP_CLKSW=(0x20150000)
+
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+®_MDTOP_PLLMIXED_MDTXPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x58)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+
+®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0x84)
+
+&MD_PLL_MAGIC_NUM=(0x62930000)
+
+;;//Enables clock square1 low-pass filter for 26M quality.
+d.s &MEM_CLASS:®_APMIXEDSYS_AP_PLL_CON0 %long %le data.long(&MEM_CLASS:®_APMIXEDSYS_AP_PLL_CON0)|0x2
+;;// 100us
+wait 1.ms
+
+;;// Default md_srclkena_ack settle time = 136T 32K
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E88
+
+;;// fixed 600MHz(/4), 343MHz(/7), 267MHz(/9) /* Fvco = 2400M */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x801713B1
+;;// 300MHz /* Fvco = 2400M */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDTXPLL_CTL0 %long %le 0x80171400
+;;// 400MHz /* Fvco = 3600M */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80229E00
+;;// 672MHz /* Fvco = 3360M */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x80204E00
+;;// 864MHz /* Fvco = 3456M */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x80213C00
+
+;;// Polling until MDMCUPLL complete frequency adjustment
+;WHILE ((data.long(&MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0
+;(
+;)
+wait 1.ms
+
+;;// Default disable BPI /7 clock
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDBPIPLL_CTL1 %long %le data.long(&MEM_CLASS:®_MDTOP_PLLMIXED_MDBPIPLL_CTL1)&0xFFFFFF7F
+
+;;/*TINFO="MDSYS_INIT: Update ABB MDPLL control register default value"*/
+;; d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x4C43100
+
+;;/* Force TXPLL ON due to TOPSM couldn't enable this PLL by default, TXPLL would be disable after DVFS Init.
+;; other PLL ON controlled by HW" */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x100010
+
+;; /*
+;; * Wait MD bus clock ready
+;; * Once MD bus ready, other clock should be ready too
+;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+;; */
+;WHILE (data.long(&MEM_CLASS:®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000
+;(
+;)
+wait 1.ms
+
+;;// Switch MDMCU & MD BUS clock to PLL frequency
+d.s &MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL)|(0x3)
+
+;;// Switch all clock to PLL frequency
+d.s &MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL)|(0x58103FC)
+
+;;// Switch SDF clock to PLL frequency
+d.s &MEM_CLASS:®_MDTOP_CLKSW_SDF_CK_CTL %long %le data.long(&MEM_CLASS:®_MDTOP_CLKSW_SDF_CK_CTL)|(0x10)
+
+;;// Turn off all SW clock request, except ATB
+d.s &MEM_CLASS:®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+;;// Mask all PLL ADJ RDY IRQ
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+;;// Make a record that means MD pll has been initialized.
+;;/* Note: We use "MD_PLL_MAGIC_NUM|0x1" to know PLL init in MD C code.
+;; If AP init PLL, it would be "MD_PLL_MAGIC_NUM". */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APview_MT6761_disable_WDT.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APview_MT6761_disable_WDT.cmm
new file mode 100755
index 0000000..6ea39f8
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APview_MT6761_disable_WDT.cmm
@@ -0,0 +1,11 @@
+;/* Step 8 Disable MD WDT */
+&MEM_CLASS="AXI"
+
+;&BASE_MADDR_MDRGU=0xA00F0000
+;&BASE_MADDR_APRGU=0xC0007000
+&BASE_MADDR_MDRGU=0x200F0000
+;&BASE_MADDR_APRGU=0x10007000
+
+D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+;D.S &MEM_CLASS:&BASE_MADDR_APRGU %LE %LONG 0x22000064
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APview_MT6761_md_srclkena.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APview_MT6761_md_srclkena.cmm
new file mode 100755
index 0000000..244a27c
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/APview_MT6761_md_srclkena.cmm
@@ -0,0 +1,33 @@
+; /* Step 6 config md_srclkena setting */
+&MEM_CLASS="AXI"
+
+; /* (1) INFRA_MISC2 */
+&BASE_INFRACFG=(0x10000000)
+; /* (2) SRCLKEN_O1 force on */
+&SPM_REG=(0x10006000)
+
+
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(&BASE_INFRACFG+0x1F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+
+
+; /* (1) INFRA_MISC2 */
+; /* [3:0] : mdsrc_req_0_en = 4'b0001 */
+d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFFF0)
+d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x1)
+
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 */
+d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFF0F)
+d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x20)
+
+; /* (2) SRCLKEN_O1 force on */
+//MMRF request
+D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x00215830 //set src clkena1 force on
+
+wait 1.ms
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/CoreTracer_MT6761_Disable_WDT.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/CoreTracer_MT6761_Disable_WDT.cmm
new file mode 100755
index 0000000..8ba2bba
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/CoreTracer_MT6761_Disable_WDT.cmm
@@ -0,0 +1,34 @@
+;sys.m prepare
+;LOCAL &TYPE
+
+
+system.mode attach
+
+; configure GCR_ACCESS Register
+; CoreTracer will access MO port via CPU to do following configuration
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+
+
+
+; do orginal APview_MT6771_disable_WDT.cmm
+LOCAL &BASE_MADDR_MDRGU
+&BASE_MADDR_MDRGU=0xA00F0000
+
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG 0x55000030
+
+PRINT "=============================="
+PRINT "Done disable MD WDT!"
+PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/Coretracer_MT6761_Frequency_Meter.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/Coretracer_MT6761_Frequency_Meter.cmm
new file mode 100755
index 0000000..77db604
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/Coretracer_MT6761_Frequency_Meter.cmm
@@ -0,0 +1,220 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; MT6761 MD Frequency Meter
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+
+;;;;;;;;;;;;;;;;;;;;;;;Below you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LOCAL &clksw_base ;; MD CLKSW base address
+&clksw_base=0xA0150000 ;; MD view APB
+;&clksw_base=0xA0096000 ;; MD view debug APB
+;&clksw_base=0x20150000 ;; AP view MD system bus
+;&clksw_base=0x0D0D6000 ;; AP view MD debug sys
+
+LOCAL &pll_base ;; MD PLLMIXED base address
+&pll_base=0xA0140000 ;; MD view APB
+;&pll_base=0xA0094000 ;; MD view debug APB
+;&pll_base=0x20140000 ;; AP view MD system bus
+;&pll_base=0x0D0D4000 ;; AP view MD debug sys
+
+&fqmtr_fcksel_32k_index=0x17
+
+;;;;;;;;;;;;;;;;;;;;;;;Above you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LOCAL &fqmtr_winset ;; Frequency Meter Windoiw Setting (= Number of FIXED clock cycle)
+&fqmtr_winset=0x1ff
+&fqmtr_winset_for_32k=0x1E000
+
+LOCAL &fqmtr_fcksel_val ;; Frequency Meter FIXED clock selection
+&fqmtr_fcksel_val=0x1a ;; Select 26Mhz by default
+
+&SRC_STR_10="TRACE_MON_clock"
+&SRC_STR_11="MDSYS_208M_clock"
+&SRC_STR_12="mdrxsys_rake_clock"
+&SRC_STR_13="mdrxsys_brp_clock"
+&SRC_STR_14="mdrxsys_vdsp_clock"
+&SRC_STR_15="mdtop_log_atb_clock"
+&SRC_STR_16="fesys_csys_clock"
+&SRC_STR_17="fesys_txsys_clock"
+&SRC_STR_18="fesys_bsi_clock"
+&SRC_STR_19="mdsys_mdcore_clock"
+&SRC_STR_20="mdsys_bus2x_nodcm_clock"
+&SRC_STR_21="mdsys_bus2x_clock"
+&SRC_STR_22="mdtop_dbg_clock"
+&SRC_STR_23="mdtop_f32k_clock"
+&SRC_STR_24="MDBPIPLL_0_DIV2_clock"
+&SRC_STR_25="MDBPIPLL_2_clock"
+&SRC_STR_26="MDBPIPLL_1_clock"
+&SRC_STR_27="MDBPIPLL_0_clock"
+&SRC_STR_28="MDTXPLL_clock"
+&SRC_STR_29="MDBRPPLL_clock"
+&SRC_STR_30="MDVDSPPLL_clock"
+&SRC_STR_31="MDMCUPLL_clock"
+
+LOCAL &idx
+LOCAL &str
+&idx = 0xA;
+&str = "TRACE_MON_clock"
+GOSUB fqmtr_query
+&idx = 0xB;
+&str = "MDSYS_208M_clock"
+GOSUB fqmtr_query
+&idx = 0xC;
+&str = "mdrxsys_rake_clock"
+GOSUB fqmtr_query
+&idx = 0xD;
+&str = "mdrxsys_brp_clock"
+GOSUB fqmtr_query
+&idx = 0xE;
+&str = "mdrxsys_vdsp_clock"
+GOSUB fqmtr_query
+&idx = 0xF;
+&str = "mdtop_log_atb_clock"
+GOSUB fqmtr_query
+&idx = 0x10;
+&str = "fesys_csys_clock"
+GOSUB fqmtr_query
+&idx = 0x11;
+&str = "fesys_txsys_clock"
+GOSUB fqmtr_query
+&idx = 0x12;
+&str = "fesys_bsi_clock"
+GOSUB fqmtr_query
+&idx = 0x13;
+&str = "mdsys_mdcore_clock"
+GOSUB fqmtr_query
+&idx = 0x14;
+&str = "mdsys_bus2x_nodcm_clock"
+GOSUB fqmtr_query
+&idx = 0x15;
+&str = "mdsys_bus2x_clock"
+GOSUB fqmtr_query
+&idx = 0x16;
+&str = "mdtop_dbg_clock"
+GOSUB fqmtr_query
+&idx = 0x17;
+&str = "mdtop_f32k_clock"
+GOSUB fqmtr_query
+&idx = 0x18;
+&str = "MDBPIPLL_0_DIV2_clock"
+GOSUB fqmtr_query
+&idx = 0x19;
+&str = "MDBPIPLL_2_clock"
+GOSUB fqmtr_query
+&idx = 0x1A;
+&str = "MDBPIPLL_1_clock"
+GOSUB fqmtr_query
+&idx = 0x1B;
+&str = "MDBPIPLL_0_clock"
+GOSUB fqmtr_query
+&idx = 0x1C;
+&str = "MDTXPLL_clock"
+GOSUB fqmtr_query
+&idx = 0x1D;
+&str = "MDBRPPLL_clock"
+GOSUB fqmtr_query
+&idx = 0x1E;
+&str = "MDVDSPPLL_clock"
+GOSUB fqmtr_query
+&idx = 0x1F;
+&str = "MDMCUPLL_clock"
+GOSUB fqmtr_query
+
+&idx = 0x20;
+
+;;;;;The main function to get the Frequency. &idx==> the clock you select, &str==> clock name, &info==>list more info and wait 5ms in the function
+;; &info=1 ==> for printing many PLLs at one time
+fqmtr_query:
+ LOCAL &unit
+ LOCAL &fqmtr_winset_26M
+ LOCAL &fqmtr_result
+ LOCAL &fqmtr_result_raw
+ LOCAL &safe_wait_cnt
+ LOCAL &safe_wait_cnt_max
+ LOCAL &fqmtr_busy
+
+ &safe_wait_cnt=0
+ IF &idx==0x20
+ (
+ RETURN
+ )
+ ELSE
+ (
+ IF &fqmtr_fcksel_val==0x1a ;; base on 26M, unit:MHz
+ (
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &unit="Khz"
+ &fqmtr_winset_26M=&fqmtr_winset_for_32k
+ &safe_wait_cnt_max=500 ;;5000 ms = 5s ==> in real test, longer than 5s, so reduce it
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &unit="Mhz"
+ &fqmtr_winset_26M=&fqmtr_winset
+ &safe_wait_cnt_max=32 ;;32 ms
+ )
+ )
+
+ ;;select source to a valid clock to let reset success.
+ Data.Set (&clksw_base+0x0100) %LE %LONG 0x13
+ Data.Set (&clksw_base+0x0104) %LE %LONG 0x0 ;reset frequency meter
+ WAIT 1000.us
+
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ ;;For accurate, don't div 8 for 32K
+ Data.Set (&clksw_base+0x0100) %LE %LONG (&idx)
+ )
+ ELSE ;; measure PLL and other module
+ (
+ ;;div 8 and select src
+ Data.Set (&clksw_base+0x0100) %LE %LONG (0x0300)|(&idx)
+ )
+
+ Data.Set (&clksw_base+0x0108) %LE %LONG &fqmtr_winset_26M
+ Data.Set (&clksw_base+0x0104) %LE %LONG 0x1 ;enable frequency meter
+
+ ;; read status, to check polling done or not
+ &fqmtr_busy=DATA.LONG(&clksw_base+0x0104)&(1<<1)
+
+ WHILE &fqmtr_busy==0
+ (
+; PRINT ". &fqmtr_busy"
+ &fqmtr_busy=DATA.LONG(&clksw_base+0x0104)&(1<<1)
+ &safe_wait_cnt=&safe_wait_cnt+1
+ IF &safe_wait_cnt==&safe_wait_cnt_max
+ (
+ PRINT "[&str] Wait Fail, exit"
+ RETURN
+ )
+ ELSE
+ (
+; PRINT "Waiting result. safe_wait_cnt=" "&safe_wait_cnt"
+ )
+ WAIT 1000.us
+
+ )
+
+ ;; Calculate the result
+ &fqmtr_result_raw=DATA.LONG(&clksw_base+0x10c)
+
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*(0x3E8)/(&fqmtr_winset_26M+3)
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*8/(&fqmtr_winset_26M+3)
+ )
+
+
+ &fqmtr_result_dec=&fqmtr_result
+ &fqmtr_result_dec=FORMAT.DECIMAL( 0 , &fqmtr_result )
+
+ PRINT " &idx , &fqmtr_result_dec &unit , &str "
+
+ WAIT 1000.us
+
+ RETURN
+ )
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/Coretracer_MT6761_PMIC_Golden_Setting_Dump.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/Coretracer_MT6761_PMIC_Golden_Setting_Dump.cmm
new file mode 100755
index 0000000..439f50c
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/Coretracer_MT6761_PMIC_Golden_Setting_Dump.cmm
@@ -0,0 +1,69 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; MT6765 PMIC golden setting dump
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;; CLOCK & RESET
+PRINT "=== CLOCK & RESET ==="
+&MODULE_SW_CG_0_STA=0xC0001090
+&MODULE_SW_CG_2_STA=0xC00010AC
+&MODULE_SW_CG_3_STA=0xC00010C8
+&ULPOSC_CLK_SEL=0xC0006684
+&PMICW_CTRL=0xC05C4034
+&PMICW_CLOCK_CTRL=0xC0001108
+&CLK_CFG_7=0xC00000B0
+&INFRA_GLOBALCON_RST2_STA=0xC0001148
+
+&tmp=DATA.LONG(&MODULE_SW_CG_0_STA)
+PRINT "MODULE_SW_CG_0_STA &MODULE_SW_CG_0_STA = &tmp"
+&tmp=DATA.LONG(&MODULE_SW_CG_2_STA)
+PRINT "MODULE_SW_CG_2_STA &MODULE_SW_CG_2_STA = &tmp"
+&tmp=DATA.LONG(&MODULE_SW_CG_3_STA)
+PRINT "MODULE_SW_CG_3_STA &MODULE_SW_CG_3_STA = &tmp"
+&tmp=DATA.LONG(&ULPOSC_CLK_SEL)
+PRINT "ULPOSC_CLK_SEL &ULPOSC_CLK_SEL = &tmp"
+&tmp=DATA.LONG(&PMICW_CTRL)
+PRINT "PMICW_CTRL &PMICW_CTRL = &tmp"
+&tmp=DATA.LONG(&PMICW_CLOCK_CTRL)
+PRINT "PMICW_CLOCK_CTRL &PMICW_CLOCK_CTRL = &tmp"
+&tmp=DATA.LONG(&CLK_CFG_7)
+PRINT "CLK_CFG_7 &CLK_CFG_7 = &tmp"
+&tmp=DATA.LONG(&INFRA_GLOBALCON_RST2_STA)
+PRINT "INFRA_GLOBALCON_RST2_STA &INFRA_GLOBALCON_RST2_STA = &tmp"
+
+;; GPIO
+PRINT "=== GPIO ==="
+&GPIO_GPIO_MODE18=0xC0005420
+&IOCFG_LM_DRV_CFG1=0xC0002210
+&IOCFG_LM_PU_CFG0=0xC0002240
+&IOCFG_LM_PD_CFG0=0xC0002230
+
+&tmp=DATA.LONG(&GPIO_GPIO_MODE18)
+PRINT "GPIO_GPIO_MODE18 &GPIO_GPIO_MODE18 = &tmp"
+&tmp=DATA.LONG(&IOCFG_LM_DRV_CFG1)
+PRINT "IOCFG_LM_DRV_CFG1 &IOCFG_LM_DRV_CFG1 = &tmp"
+&tmp=DATA.LONG(&IOCFG_LM_PU_CFG0)
+PRINT "IOCFG_LM_PU_CFG0 &IOCFG_LM_PU_CFG0 = &tmp"
+&tmp=DATA.LONG(&IOCFG_LM_PD_CFG0)
+PRINT "IOCFG_LM_PD_CFG0 &IOCFG_LM_PD_CFG0 = &tmp"
+
+;; PMIC_WRAP
+PRINT "=== PMIC_WRAP ==="
+&MUX_SEL=0xC000D000
+&WRAP_EN=0xC000D004
+&HPRIO_ARB_EN=0xC000D06C
+&WACS0_EN=0xC000D08C
+&INIT_DONE0=0xC000D090
+&WACS0_RDATA=0xC000DC04
+
+&tmp=DATA.LONG(&MUX_SEL)
+PRINT "MUX_SEL &MUX_SEL = &tmp"
+&tmp=DATA.LONG(&WRAP_EN)
+PRINT "WRAP_EN &WRAP_EN = &tmp"
+&tmp=DATA.LONG(&HPRIO_ARB_EN)
+PRINT "HPRIO_ARB_EN &HPRIO_ARB_EN = &tmp"
+&tmp=DATA.LONG(&WACS0_EN)
+PRINT "WACS0_EN &WACS0_EN = &tmp"
+&tmp=DATA.LONG(&INIT_DONE0)
+PRINT "INIT_DONE0 &INIT_DONE0 = &tmp"
+&tmp=DATA.LONG(&WACS0_RDATA)
+PRINT "WACS0_RDATA &WACS0_RDATA = &tmp"
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/MT6761_EVB_Load_MD_Elf.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/MT6761_EVB_Load_MD_Elf.cmm
new file mode 100755
index 0000000..2906458
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/MT6761_EVB_Load_MD_Elf.cmm
@@ -0,0 +1,315 @@
+;sys.m prepare
+;LOCAL &TYPE
+
+system.mode attach
+
+; configure GCR_ACCESS Register
+; CoreTracer will access MO port via CPU to do following configuration
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+
+
+; do orginal APview_MT6765_disable_WDT.cmm
+LOCAL &BASE_MADDR_MDRGU
+&BASE_MADDR_MDRGU=0xA00F0000
+
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG 0x55000030
+
+
+PRINT "=============================="
+PRINT "config md_srclkena setting"
+PRINT "=============================="
+; /* Step 6 config md_srclkena setting */
+
+; /* (1) INFRA_MISC2 */
+&BASE_INFRACFG=(0xC0000000)
+; /* (2) SRCLKEN_O1 force on */
+&SPM_REG=(0xC0006000)
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(&BASE_INFRACFG+0x1F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+
+; /* (1) INFRA_MISC2 */
+; /* [3:0] : mdsrc_req_0_en = 4'b0001 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFFF0)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x1)
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFFF0)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x1)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFF0F)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x20)
+
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFF0F)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x20)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+; /* (2) SRCLKEN_O1 force on */
+; //MMRF request
+;D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+;D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x00215830 //set src clkena1 force on
+D.S &POWERON_CONFIG_EN %LE %LONG 0x0B160001
+D.S &SPM_POWER_ON_VAL1 %LE %LONG 0x00215830
+
+wait 1.ms
+
+
+
+PRINT "=============================="
+PRINT "config PLL setting"
+PRINT "=============================="
+
+; /* Step 5 config PLL setting */
+&BASE_MADDR_APMIXEDSYS=(0xC000C000)
+&BASE_MADDR_MDTOP_PLLMIXED=(0xA0140000)
+&BASE_MADDR_MDTOP_CLKSW=(0xA0150000)
+
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+®_MDTOP_PLLMIXED_MDTXPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x58)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0x84)
+
+&MD_PLL_MAGIC_NUM=(0x62930000)
+
+;;// initial CLKSQ_LPF
+&temp=data.long(AXI:®_APMIXEDSYS_AP_PLL_CON0)
+&temp=&temp|0x2
+d.s ®_APMIXEDSYS_AP_PLL_CON0 %long %le &temp
+;;// 100us
+wait 1.ms
+
+;;// Default md_srclkena_ack settle time = 136T 32K
+d.s ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E88
+
+;;// fixed 600MHz(/4), 343MHz(/7), 267MHz(/9) /* Fvco = 2400M */
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x801713B1
+;;// 300MHz /* Fvco = 2400M */
+d.s ®_MDTOP_PLLMIXED_MDTXPLL_CTL0 %long %le 0x80171400
+;;// 400MHz /* Fvco = 3600M */
+d.s ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80229E00
+;;// 672MHz /* Fvco = 3360M */
+d.s ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x80204E00
+;;// 864MHz /* Fvco = 3456M */
+d.s ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x80213C00
+
+;;// Polling until MDMCUPLL complete frequency adjustment
+;WHILE ((data.long(®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0
+;(
+;)
+wait 1.ms
+
+;;// Default disable BPI /7 clock
+&temp=data.long(®_MDTOP_PLLMIXED_MDBPIPLL_CTL1)
+&temp=&temp&(~0x80)
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL1 %long %le &temp
+
+;;/*TINFO="MDSYS_INIT: Update ABB MDPLL control register default value"*/
+;;d.s ®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x4C43100
+
+;;/* Force TXPLL ON due to TOPSM couldn't enable this PLL by default, TXPLL would be disable after DVFS Init.
+;; other PLL ON controlled by HW" */
+d.s ®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x100010
+
+;; /*
+;; * Wait MD bus clock ready
+;; * Once MD bus ready, other clock should be ready too
+;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+;; */
+;WHILE (data.long(®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000
+;(
+)
+wait 2.ms
+
+;;// Switch MDMCU & MD BUS clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x3)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch all clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x58103FC)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch SDF clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_SDF_CK_CTL)
+&temp=&temp|(0x10)
+d.s ®_MDTOP_CLKSW_SDF_CK_CTL %long %le &temp
+
+;;// Turn off all SW clock request, except ATB
+d.s ®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+;;// Mask all PLL ADJ RDY IRQ
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+;;// Make a record that means MD pll has been initialized.
+;;/* Note: We use "MD_PLL_MAGIC_NUM|0x1" to know PLL init in MD C code.
+;; If AP init PLL, it would be "MD_PLL_MAGIC_NUM". */
+d.s ®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+
+
+PRINT "=============================="
+PRINT "Set GPIO!"
+PRINT "=============================="
+;;////// Step 8: Set GPIO
+;;//// MD UART GPIO
+&BASE_ADDR_MDGPIO=0xC0005000
+&BASE_ADDR_IOCFG=0xC0002600
+D.S &BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_MDGPIO+0x420)&(0x00FFFFFF)
+D.S &BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_MDGPIO+0x420)|(0x55000000) ;//set GPIO150 to MD_URXD0 mode,set GPIO151 to MD_UTXD0 mode,
+D.S &BASE_ADDR_IOCFG+0x60 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x60)&(0xFF7FFFFF) ;//MD_URXD0 pull dowm disable
+D.S &BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)|(0x800000) ;//MD_URXD0 pull up enable
+D.S &BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)&(0xFEFFFFFF) ;//MD_UTXD0 pull up disable
+;;//// SIM GPIO
+;;// Clear bits
+d.s 0xC0005348 %long %le 0x77777000
+d.s 0xC0005358 %long %le 0x00000007
+;;// Set bits
+d.s 0xC0005344 %long %le 0x11111000
+d.s 0xC0005354 %long %le 0x00000001
+
+;;// SIM PUPD
+;;// Control PAD_SIM1_SIO PUPD pin. PUPD=0: pull up, PUPD=1: pull down.
+;;// Set bits
+d.s 0xC0002454 %long %le 0x00000FC0
+;;// Clear bits, SIO pull up
+d.s 0xC0002458 %long %le 0x00000480
+
+;;// SIM R1R0
+;;// R1R0=00:High-Z, R1R0=01:PU 45kohm;PD 75kohm,
+;;// R1R0=10:PU 5kohm;PD 75kohm, R1R0=11:PU 45kohm/5kohm;PD 75kohm/75kohm.
+;;// Set R1 bits
+d.s 0xC0002484 %long %le 0x00000FC0
+
+PRINT "=============================="
+PRINT "Set MD EMI Remap!"
+PRINT "=============================="
+
+
+;Step 10 set MD EMI remap address (MD view: step 9) ==>review done
+;d.s &MEM_CLASS:0xC0001300 %long %le 0x00430041
+;d.s &MEM_CLASS:0xC0001304 %long %le 0x00470045
+;d.s &MEM_CLASS:0xC0001308 %long %le 0x004b0049
+;d.s &MEM_CLASS:0xC000130c %long %le 0x004f004d
+D.S 0xC0001300 %LE %LONG 0x00430041
+D.S 0xC0001304 %LE %LONG 0x00470045
+D.S 0xC0001308 %LE %LONG 0x004b0049
+D.S 0xC000130c %LE %LONG 0x004f004d
+
+
+PRINT "=============================="
+PRINT "Set AP2MD PATH Disable!"
+PRINT "=============================="
+
+; do AP to MD path disable
+&BASE_ADDR_AP2MD_Dummy = 0xC0001370
+&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN=0xC00012A0
+
+
+; Set reg_ap2md_dummy[0] = 1'b0
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp & 0xFFFFFFFE
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+; Set peri2md_protect_en
+; Write 0x1000_12A0[7] = 1'b1.
+; MD can access AP if reg_ap2md_dummy[0] = 1'b1,
+&temp=data.long(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN)
+&temp = &temp | 0x80
+D.S &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN %LE %LONG &temp
+wait 1.ms
+
+; Clear md2peri_protect_en
+; Write 0x1000_12AC[6] = 1'b1.
+&temp=data.long(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC)
+&temp = &temp | 0x40
+D.S &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp | 0x1
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+;Enalbe cache to speed loading
+;By setting bank 6 segment control attribute
+register.set cdmmbase 0x1fc1407
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor adapter_khz 2000
+steal monitor mips32 fastchannel 0 1 0x6f800000
+
+
+PRINT "=============================="
+PRINT "Start to Load elf !"
+PRINT "=============================="
+
+thread.select 1
+steal lo
+
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+PRINT "=============================="
+PRINT "Load elf Done!"
+PRINT "=============================="
+
+thread.select 1
+
+;&t=var.address(INT_Initialize_Phase1)
+;wait 20.ms
+;stop
+;steal set $pc = &INT_Initialize_Phase1
+;register.set pc &t
+
+;PRINT "=============================="
+;PRINT "Set PC to INT_Initialize_Phase1: &t"
+;PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/MT6761_EVB_Load_MD_Elf_With_DSP.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/MT6761_EVB_Load_MD_Elf_With_DSP.cmm
new file mode 100755
index 0000000..be2c1ef
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/MT6761_EVB_Load_MD_Elf_With_DSP.cmm
@@ -0,0 +1,342 @@
+;sys.m prepare
+;LOCAL &TYPE
+
+
+system.mode attach
+
+; configure GCR_ACCESS Register
+; CoreTracer will access MO port via CPU to do following configuration
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+
+
+
+; do orginal APview_MT6765_disable_WDT.cmm
+LOCAL &BASE_MADDR_MDRGU
+&BASE_MADDR_MDRGU=0xA00F0000
+
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG 0x55000030
+
+
+
+PRINT "=============================="
+PRINT "config md_srclkena setting"
+PRINT "=============================="
+
+; /* Step 6 config md_srclkena setting */
+
+
+; /* (1) INFRA_MISC2 */
+&BASE_INFRACFG=(0xC0000000)
+; /* (2) SRCLKEN_O1 force on */
+&SPM_REG=(0xC0006000)
+
+
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(&BASE_INFRACFG+0x1F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+
+
+; /* (1) INFRA_MISC2 */
+; /* [3:0] : mdsrc_req_0_en = 4'b0001 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFFF0)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x1)
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFFF0)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x1)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFF0F)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x20)
+
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFF0F)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x20)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+; /* (2) SRCLKEN_O1 force on */
+; //MMRF request
+;D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+;D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x00215830 //set src clkena1 force on
+D.S &POWERON_CONFIG_EN %LE %LONG 0x0B160001
+D.S &SPM_POWER_ON_VAL1 %LE %LONG 0x00215830
+
+wait 1.ms
+
+
+
+PRINT "=============================="
+PRINT "config PLL setting"
+PRINT "=============================="
+
+; /* Step 5 config PLL setting */
+&BASE_MADDR_APMIXEDSYS=(0xC000C000)
+&BASE_MADDR_MDTOP_PLLMIXED=(0xA0140000)
+&BASE_MADDR_MDTOP_CLKSW=(0xA0150000)
+
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+®_MDTOP_PLLMIXED_MDTXPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x58)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0x84)
+
+&MD_PLL_MAGIC_NUM=(0x62930000)
+
+;;// initial CLKSQ_LPF
+&temp=data.long(AXI:®_APMIXEDSYS_AP_PLL_CON0)
+&temp=&temp|0x2
+d.s ®_APMIXEDSYS_AP_PLL_CON0 %long %le &temp
+;;// 100us
+wait 1.ms
+
+;;// Default md_srclkena_ack settle time = 136T 32K
+d.s ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E88
+
+;;// fixed 600MHz(/4), 343MHz(/7), 267MHz(/9) /* Fvco = 2400M */
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x801713B1
+;;// 300MHz /* Fvco = 2400M */
+d.s ®_MDTOP_PLLMIXED_MDTXPLL_CTL0 %long %le 0x80171400
+;;// 400MHz /* Fvco = 3600M */
+d.s ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80229E00
+;;// 672MHz /* Fvco = 3360M */
+d.s ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x80204E00
+;;// 864MHz /* Fvco = 3456M */
+d.s ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x80213C00
+
+;;// Polling until MDMCUPLL complete frequency adjustment
+;WHILE ((data.long(®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0
+;(
+;)
+wait 1.ms
+
+;;// Default disable BPI /7 clock
+&temp=data.long(®_MDTOP_PLLMIXED_MDBPIPLL_CTL1)
+&temp=&temp&(~0x80)
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL1 %long %le &temp
+
+;;/*TINFO="MDSYS_INIT: Update ABB MDPLL control register default value"*/
+;;d.s ®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x4C43100
+
+;;/* Force TXPLL ON due to TOPSM couldn't enable this PLL by default, TXPLL would be disable after DVFS Init.
+;; other PLL ON controlled by HW" */
+d.s ®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x100010
+
+;; /*
+;; * Wait MD bus clock ready
+;; * Once MD bus ready, other clock should be ready too
+;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+;; */
+;WHILE (data.long(®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000
+;(
+)
+wait 2.ms
+
+;;// Switch MDMCU & MD BUS clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x3)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch all clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x58103FC)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch SDF clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_SDF_CK_CTL)
+&temp=&temp|(0x10)
+d.s ®_MDTOP_CLKSW_SDF_CK_CTL %long %le &temp
+
+;;// Turn off all SW clock request, except ATB
+d.s ®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+;;// Mask all PLL ADJ RDY IRQ
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+;;// Make a record that means MD pll has been initialized.
+;;/* Note: We use "MD_PLL_MAGIC_NUM|0x1" to know PLL init in MD C code.
+;; If AP init PLL, it would be "MD_PLL_MAGIC_NUM". */
+d.s ®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+
+
+PRINT "=============================="
+PRINT "Set GPIO!"
+PRINT "=============================="
+;;////// Step 8: Set GPIO
+;;//// MD UART GPIO
+&BASE_ADDR_MDGPIO=0xC0005000
+&BASE_ADDR_IOCFG=0xC0002600
+D.S &BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_MDGPIO+0x420)&(0x00FFFFFF)
+D.S &BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_MDGPIO+0x420)|(0x55000000) ;//set GPIO150 to MD_URXD0 mode,set GPIO151 to MD_UTXD0 mode,
+D.S &BASE_ADDR_IOCFG+0x60 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x60)&(0xFF7FFFFF) ;//MD_URXD0 pull dowm disable
+D.S &BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)|(0x800000) ;//MD_URXD0 pull up enable
+D.S &BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)&(0xFEFFFFFF) ;//MD_UTXD0 pull up disable
+;;//// SIM GPIO
+;;// Clear bits
+d.s 0xC0005348 %long %le 0x77777000
+d.s 0xC0005358 %long %le 0x00000007
+;;// Set bits
+d.s 0xC0005344 %long %le 0x11111000
+d.s 0xC0005354 %long %le 0x00000001
+
+;;// SIM PUPD
+;;// Control PAD_SIM1_SIO PUPD pin. PUPD=0: pull up, PUPD=1: pull down.
+;;// Set bits
+d.s 0xC0002454 %long %le 0x00000FC0
+;;// Clear bits, SIO pull up
+d.s 0xC0002458 %long %le 0x00000480
+
+;;// SIM R1R0
+;;// R1R0=00:High-Z, R1R0=01:PU 45kohm;PD 75kohm,
+;;// R1R0=10:PU 5kohm;PD 75kohm, R1R0=11:PU 45kohm/5kohm;PD 75kohm/75kohm.
+;;// Set R1 bits
+d.s 0xC0002484 %long %le 0x00000FC0
+
+PRINT "=============================="
+PRINT "Set MD EMI Remap!"
+PRINT "=============================="
+
+
+;Step 10 set MD EMI remap address (MD view: step 9) ==>review done
+;d.s &MEM_CLASS:0xC0001300 %long %le 0x00430041
+;d.s &MEM_CLASS:0xC0001304 %long %le 0x00470045
+;d.s &MEM_CLASS:0xC0001308 %long %le 0x004b0049
+;d.s &MEM_CLASS:0xC000130c %long %le 0x004f004d
+D.S 0xC0001300 %LE %LONG 0x00430041
+D.S 0xC0001304 %LE %LONG 0x00470045
+D.S 0xC0001308 %LE %LONG 0x004b0049
+D.S 0xC000130c %LE %LONG 0x004f004d
+
+PRINT "=============================="
+PRINT "Set MD EMI Remap!"
+PRINT "=============================="
+
+
+;Step 10 set MD EMI remap address (MD view: step 9) ==>review done
+;d.s &MEM_CLASS:0xC0001300 %long %le 0x00430041
+;d.s &MEM_CLASS:0xC0001304 %long %le 0x00470045
+;d.s &MEM_CLASS:0xC0001308 %long %le 0x004b0049
+;d.s &MEM_CLASS:0xC000130c %long %le 0x004f004d
+D.S 0xC0001300 %LE %LONG 0x00430041
+D.S 0xC0001304 %LE %LONG 0x00470045
+D.S 0xC0001308 %LE %LONG 0x004b0049
+D.S 0xC000130c %LE %LONG 0x004f004d
+
+
+PRINT "=============================="
+PRINT "Set AP2MD PATH Disable!"
+PRINT "=============================="
+
+; do AP to MD path disable
+&BASE_ADDR_AP2MD_Dummy = 0xC0001370
+&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN=0xC00012A0
+
+
+; Set reg_ap2md_dummy[0] = 1'b0
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp & 0xFFFFFFFE
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+; Set peri2md_protect_en
+; Write 0x1000_12A0[7] = 1'b1.
+; MD can access AP if reg_ap2md_dummy[0] = 1'b1,
+&temp=data.long(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN)
+&temp = &temp | 0x80
+D.S &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN %LE %LONG &temp
+wait 1.ms
+
+; Clear md2peri_protect_en
+; Write 0x1000_12AC[6] = 1'b1.
+&temp=data.long(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC)
+&temp = &temp | 0x40
+D.S &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp | 0x1
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+
+
+;Enalbe cache to speed loading
+;By setting bank 6 segment control attribute
+register.set cdmmbase 0x1fc1407
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor adapter_khz 2000
+steal monitor mips32 fastchannel 0 1 0x6f800000
+
+
+PRINT "=============================="
+PRINT "Start to Load elf !"
+PRINT "=============================="
+
+thread.select 1
+steal lo
+
+steal source ../cmm/coretracer\config\easyLoader\load_dsp.py
+
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+PRINT "=============================="
+PRINT "Load elf Done!"
+PRINT "=============================="
+
+thread.select 1
+
+;&t=var.address(INT_Initialize_Phase1)
+;wait 20.ms
+;stop
+;steal set $pc = &INT_Initialize_Phase1
+;register.set pc &t
+
+;PRINT "=============================="
+;PRINT "Set PC to INT_Initialize_Phase1: &t"
+;PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/MT6761_EVB_Load_MD_Elf_With_SPRAM.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/MT6761_EVB_Load_MD_Elf_With_SPRAM.cmm
new file mode 100755
index 0000000..cb645f1
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/MT6761_EVB_Load_MD_Elf_With_SPRAM.cmm
@@ -0,0 +1,337 @@
+;sys.m prepare
+;LOCAL &TYPE
+
+
+system.mode attach
+
+; configure GCR_ACCESS Register
+; CoreTracer will access MO port via CPU to do following configuration
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+
+
+
+; do orginal APview_MT6765_disable_WDT.cmm
+LOCAL &BASE_MADDR_MDRGU
+&BASE_MADDR_MDRGU=0xA00F0000
+
+PRINT "=============================="
+PRINT "Disable AP WDT!"
+PRINT "=============================="
+
+D.S SD:0xc0007000 %LE %LONG 0x22000000
+
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG 0x55000030
+
+
+
+PRINT "=============================="
+PRINT "config md_srclkena setting"
+PRINT "=============================="
+
+; /* Step 6 config md_srclkena setting */
+
+
+; /* (1) INFRA_MISC2 */
+&BASE_INFRACFG=(0xC0000000)
+; /* (2) SRCLKEN_O1 force on */
+&SPM_REG=(0xC0006000)
+
+
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(&BASE_INFRACFG+0x1F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+
+
+; /* (1) INFRA_MISC2 */
+; /* [3:0] : mdsrc_req_0_en = 4'b0001 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFFF0)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x1)
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFFF0)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x1)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFF0F)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x20)
+
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFF0F)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x20)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+; /* (2) SRCLKEN_O1 force on */
+; //MMRF request
+;D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+;D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x00215830 //set src clkena1 force on
+D.S &POWERON_CONFIG_EN %LE %LONG 0x0B160001
+D.S &SPM_POWER_ON_VAL1 %LE %LONG 0x00215830
+
+wait 1.ms
+
+
+
+PRINT "=============================="
+PRINT "config PLL setting"
+PRINT "=============================="
+
+; /* Step 5 config PLL setting */
+&BASE_MADDR_APMIXEDSYS=(0xC000C000)
+&BASE_MADDR_MDTOP_PLLMIXED=(0xA0140000)
+&BASE_MADDR_MDTOP_CLKSW=(0xA0150000)
+
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+®_MDTOP_PLLMIXED_MDTXPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x58)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0x84)
+
+&MD_PLL_MAGIC_NUM=(0x62930000)
+
+;;// initial CLKSQ_LPF
+&temp=data.long(AXI:®_APMIXEDSYS_AP_PLL_CON0)
+&temp=&temp|0x2
+d.s ®_APMIXEDSYS_AP_PLL_CON0 %long %le &temp
+;;// 100us
+wait 1.ms
+
+;;// Default md_srclkena_ack settle time = 136T 32K
+d.s ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E88
+
+;;// fixed 600MHz(/4), 343MHz(/7), 267MHz(/9) /* Fvco = 2400M */
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x801713B1
+;;// 300MHz /* Fvco = 2400M */
+d.s ®_MDTOP_PLLMIXED_MDTXPLL_CTL0 %long %le 0x80171400
+;;// 400MHz /* Fvco = 3600M */
+d.s ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80229E00
+;;// 672MHz /* Fvco = 3360M */
+d.s ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x80204E00
+;;// 864MHz /* Fvco = 3456M */
+d.s ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x80213C00
+
+;;// Polling until MDMCUPLL complete frequency adjustment
+;WHILE ((data.long(®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0
+;(
+;)
+wait 1.ms
+
+;;// Default disable BPI /7 clock
+&temp=data.long(®_MDTOP_PLLMIXED_MDBPIPLL_CTL1)
+&temp=&temp&(~0x80)
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL1 %long %le &temp
+
+;;/*TINFO="MDSYS_INIT: Update ABB MDPLL control register default value"*/
+;;d.s ®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x4C43100
+
+;;/* Force TXPLL ON due to TOPSM couldn't enable this PLL by default, TXPLL would be disable after DVFS Init.
+;; other PLL ON controlled by HW" */
+d.s ®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x100010
+
+;; /*
+;; * Wait MD bus clock ready
+;; * Once MD bus ready, other clock should be ready too
+;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+;; */
+;WHILE (data.long(®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000
+;(
+)
+wait 2.ms
+
+;;// Switch MDMCU & MD BUS clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x3)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch all clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x58103FC)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch SDF clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_SDF_CK_CTL)
+&temp=&temp|(0x10)
+d.s ®_MDTOP_CLKSW_SDF_CK_CTL %long %le &temp
+
+;;// Turn off all SW clock request, except ATB
+d.s ®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+;;// Mask all PLL ADJ RDY IRQ
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+;;// Make a record that means MD pll has been initialized.
+;;/* Note: We use "MD_PLL_MAGIC_NUM|0x1" to know PLL init in MD C code.
+;; If AP init PLL, it would be "MD_PLL_MAGIC_NUM". */
+d.s ®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+
+
+PRINT "=============================="
+PRINT "Set GPIO!"
+PRINT "=============================="
+;;////// Step 8: Set GPIO
+;;//// MD UART GPIO
+&BASE_ADDR_MDGPIO=0xC0005000
+&BASE_ADDR_IOCFG=0xC0002600
+D.S &BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_MDGPIO+0x420)&(0x00FFFFFF)
+D.S &BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_MDGPIO+0x420)|(0x55000000) ;//set GPIO150 to MD_URXD0 mode,set GPIO151 to MD_UTXD0 mode,
+D.S &BASE_ADDR_IOCFG+0x60 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x60)&(0xFF7FFFFF) ;//MD_URXD0 pull dowm disable
+D.S &BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)|(0x800000) ;//MD_URXD0 pull up enable
+D.S &BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)&(0xFEFFFFFF) ;//MD_UTXD0 pull up disable
+;;//// SIM GPIO
+;;// Clear bits
+d.s 0xC0005348 %long %le 0x77777000
+d.s 0xC0005358 %long %le 0x00000007
+;;// Set bits
+d.s 0xC0005344 %long %le 0x11111000
+d.s 0xC0005354 %long %le 0x00000001
+
+;;// SIM PUPD
+;;// Control PAD_SIM1_SIO PUPD pin. PUPD=0: pull up, PUPD=1: pull down.
+;;// Set bits
+d.s 0xC0002454 %long %le 0x00000FC0
+;;// Clear bits, SIO pull up
+d.s 0xC0002458 %long %le 0x00000480
+
+;;// SIM R1R0
+;;// R1R0=00:High-Z, R1R0=01:PU 45kohm;PD 75kohm,
+;;// R1R0=10:PU 5kohm;PD 75kohm, R1R0=11:PU 45kohm/5kohm;PD 75kohm/75kohm.
+;;// Set R1 bits
+d.s 0xC0002484 %long %le 0x00000FC0
+
+PRINT "=============================="
+PRINT "Set MD EMI Remap!"
+PRINT "=============================="
+
+
+;Step 10 set MD EMI remap address (MD view: step 9) ==>review done
+;d.s &MEM_CLASS:0xC0001300 %long %le 0x00430041
+;d.s &MEM_CLASS:0xC0001304 %long %le 0x00470045
+;d.s &MEM_CLASS:0xC0001308 %long %le 0x004b0049
+;d.s &MEM_CLASS:0xC000130c %long %le 0x004b0049
+D.S 0xC0001300 %LE %LONG 0x00430041
+D.S 0xC0001304 %LE %LONG 0x00470045
+D.S 0xC0001308 %LE %LONG 0x004b0049
+D.S 0xC000130c %LE %LONG 0x004b0049
+
+
+PRINT "=============================="
+PRINT "Set AP2MD PATH Disable!"
+PRINT "=============================="
+
+; do AP to MD path disable
+&BASE_ADDR_AP2MD_Dummy = 0xC0001370
+&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN=0x100012A0
+
+
+; Set reg_ap2md_dummy[0] = 1'b0
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp & 0xFFFFFFFE
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+; Set peri2md_protect_en
+; Write 0x1000_12A0[7] = 1'b1.
+; MD can access AP if reg_ap2md_dummy[0] = 1'b1,
+&temp=data.long(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN)
+&temp = &temp | 0x80
+D.S &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN %LE %LONG &temp
+wait 1.ms
+
+; Clear md2peri_protect_en
+; Write 0x1000_12AC[6] = 1'b1.
+&temp=data.long(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC)
+&temp = &temp | 0x40
+D.S &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp | 0x1
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+
+
+;Enalbe cache to speed loading
+steal monitor adapter_khz 2000
+
+PRINT "=============================="
+PRINT "Set MD Bus Way Disable!"
+PRINT "=============================="
+
+&BASE_ADDR_MDMCU_BUS_CONFIG = 0xA0330000
+
+&temp=data.long(&BASE_ADDR_MDMCU_BUS_CONFIG)
+&temp = &temp & 0xFFFFFFFD
+D.S &BASE_ADDR_MDMCU_BUS_CONFIG %LE %LONG &temp
+wait 1.ms
+
+PRINT "=============================="
+PRINT "Start to Load elf !"
+PRINT "=============================="
+
+thread.select 1
+steal source ../cmm/coretracer/single_core_basic_load_no_emi_codetracer_SPRAM.py
+
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+PRINT "=============================="
+PRINT "Load elf Done!"
+PRINT "=============================="
+
+thread.select 1
+
+;&t=var.address(INT_Initialize_Phase1)
+;wait 20.ms
+;stop
+;steal set $pc = &INT_Initialize_Phase1
+;register.set pc &t
+
+;PRINT "=============================="
+;PRINT "Set PC to INT_Initialize_Phase1: &t"
+;PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/MT6761_MD_Only.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/MT6761_MD_Only.cmm
new file mode 100755
index 0000000..7a0c45b
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/MT6761_MD_Only.cmm
@@ -0,0 +1,52 @@
+;AP pmic workaround
+&MEM_CLASS="AXI"
+sys.m prepare
+wait 1.ms
+
+; Step 1 (AP CCCI only) Configure AP/MD shared buck through DVFSRC API
+; [Note] CVD script do NOT need this step
+; skip
+
+; Step 3 config MD related Buck
+; [Note] CVD script do NOT need this step
+; AP preloader should set Modem related buck
+; skip
+
+; Step 4 power on MTCMOS
+; [Note] CVD script do NOT need this step
+; skip
+
+; Step 5 disable MD access register
+do APview_MT6761_MD2PERI_disable.cmm
+
+; Step 6 config md_srclkena setting
+do APview_MT6761_md_srclkena.cmm
+
+; Step 7 config PLL setting
+do APview_MT6761_MD_PLL_Init.cmm
+
+; Step 8 Disable MD WDT
+do APview_MT6761_disable_WDT.cmm
+
+; Step 9 enable MD to Access AP Register
+do APview_MT6761_AP2MD_enable.cmm
+
+; Step 10 Trigger MD MCU to run (AP view)
+; [Note] Trigger MD MCU by debugger
+; skip
+
+; Step 11 set GPIO (MD view: step 7)
+do APview_MT6761_GPIO_MDUART0.cmm
+do APview_MT6761_GPIO_SIM.cmm
+
+;Step 12 Force on Debug Sys clock (MD view: step 8)
+;do APview_MT6761_MD_ForceOnDebugSys.cmm
+
+;Step 13 set MD EMI remap address (MD view: step 9)
+d.s &MEM_CLASS:0x10001300 %long %le 0x00430041
+d.s &MEM_CLASS:0x10001304 %long %le 0x00470045
+d.s &MEM_CLASS:0x10001308 %long %le 0x004b0049
+d.s &MEM_CLASS:0x1000130c %long %le 0x004f004d
+
+; Final Step: Trigger MD MCU to run
+; skip
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/coretracer/L1Bypass.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/coretracer/L1Bypass.act
new file mode 100755
index 0000000..a3c4b52
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/coretracer/L1Bypass.act
@@ -0,0 +1,6 @@
+<?xml version="1.0"?>
+<Customize>
+ <Action name="L1AssertBypass" icon="">
+ <GDB>p/x L1_ASSERT_BYPASS=3</GDB>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/coretracer/LoadDSPBin.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/coretracer/LoadDSPBin.cmm
new file mode 100755
index 0000000..08b4a8c
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/coretracer/LoadDSPBin.cmm
@@ -0,0 +1,17 @@
+system.mode attach
+
+register.set cdmmbase 0x1fc1407
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor mips32 fastchannel 0 1
+
+&temp_addr = var.address(dsp_bin_ro)
+&temp_addr = &temp_addr & 0x0FFFFFFF
+;&temp_addr = &temp_addr | 0xA0000000
+
+;data.load.bin U:\MT6292\UMOLYA\DEV\UMOLYA.BIANCO.BRINGUP.DEV\mcu\build\BIANCO_FPGA\L1S_L1DISABLE\bin\DSP_BIANCO_UMOLYA_BIANCO_BRINGUP_DEV_W17_04_LTE_P3.bin &temp_addr
+data.load.bin "D:\dsp123.bin" &temp_addr
+
+print "load dsp done!"
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+enddo
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/coretracer/config/L1Bypass.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/coretracer/config/L1Bypass.act
new file mode 100755
index 0000000..a3c4b52
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/coretracer/config/L1Bypass.act
@@ -0,0 +1,6 @@
+<?xml version="1.0"?>
+<Customize>
+ <Action name="L1AssertBypass" icon="">
+ <GDB>p/x L1_ASSERT_BYPASS=3</GDB>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/coretracer/config/MT6761_AllIn1_LoadSymbol.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/coretracer/config/MT6761_AllIn1_LoadSymbol.launch
new file mode 100755
index 0000000..9efd844
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/coretracer/config/MT6761_AllIn1_LoadSymbol.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/coretracer/config/MT6761_AllIn1_LoadSymbol_SPRAM.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/coretracer/config/MT6761_AllIn1_LoadSymbol_SPRAM.launch
new file mode 100755
index 0000000..f2b3528
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/coretracer/config/MT6761_AllIn1_LoadSymbol_SPRAM.launch
@@ -0,0 +1,61 @@
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+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="attach"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
+<booleanAttribute key="org.eclipse.debug.core.capture_output" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_OUTPUT_ON" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+<stringAttribute key="saved_expressions<seperator>Unknown" value="0xa0350000,0xa0330000,0x9ff02400,0x9f00ff80,0x9f000000,0x9f000300,0x9f200000,0xa0210800,0xa02100000,0xa0210000,0x90005b04,0xa0310000"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/coretracer/config/easyLoader/CoreTracer_easy_loader.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/coretracer/config/easyLoader/CoreTracer_easy_loader.py
new file mode 100755
index 0000000..cc2c2fe
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/coretracer/config/easyLoader/CoreTracer_easy_loader.py
@@ -0,0 +1,149 @@
+#from imgtec import codescape
+import sys
+import time
+import os
+import gdb
+import Tkinter, tkFileDialog
+
+#get full path of python script
+file_path = os.path.dirname(os.path.abspath(__file__))
+#append python path into system path
+sys.path.append(file_path)
+
+import load_dsp
+
+app = None
+
+# load all elf
+def load_all_elf(elf_path):
+ time_str = time.time()
+ print "=== Start Loading ELF ==="
+ print "Image path: " + elf_path
+ if(os.path.exists(elf_path) == False):
+ print "[Error] UMOLY ELF doesn't exist: %s" %(elf_path)
+ else:
+ elf_path = elf_path.replace('\\', '/')
+ gdb_cmd = 'symbol-file '+ elf_path
+ print gdb_cmd
+ gdb.execute(gdb_cmd)
+ print "Load SYMBOL successfully"
+ # Add debug point
+ gdb_cmd = 'hb general_ex_vector'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'lo '+ elf_path
+ print gdb_cmd
+ gdb.execute(gdb_cmd)
+ print "Load ELF successfully"
+ time_end = time.time()
+ print("All loading is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+# load all symbol only
+def load_all_sym(elf_path):
+ time_str = time.time()
+ print "=== Start Loading SYMBOL ==="
+ print "Image path: " + elf_path
+ if(os.path.exists(elf_path) == False):
+ print "[Error] UMOLY ELF doesn't exist: %s" %(elf_path)
+ else:
+ elf_path = elf_path.replace('\\', '/')
+ gdb_cmd = 'symbol-file '+ elf_path
+ print gdb_cmd
+ gdb.execute(gdb_cmd)
+ print "Load SYMBOL successfully"
+ # Add debug point
+ gdb_cmd = 'hb general_ex_vector'
+ gdb.execute(gdb_cmd)
+ time_end = time.time()
+ print("All loading is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+# load dsp bin file
+#def load_dsp_bin(dsp_path):
+# time_str = time.time()
+# print "=== Start load dsp bin ==="
+# print "Dsp bin path: " + dsp_path
+# if(os.path.exists(dsp_path) == False):
+# print "[Error] UMOLY DSP binary doesn't exist: %s" %(dsp_path)
+# else:
+# gdb_cmd='thread 1'
+# gdb.execute(gdb_cmd)
+# ## a) need parsing: 0x13a0000 <dsp_bin_ro>
+# ##symbol_name='&dsp_bin_ro'
+# ##dsp_addr = gdb.parse_and_eval(symbol_name)
+# ## b) need parsing: $3 = 0x13a0000
+# ##gdb_cmd='p/x &dsp_bin_ro'
+# ##dsp_addr = gdb.execute(gdb_cmd, False, True)
+# symbol_name='dsp_bin_ro'
+# dsp_addr = gdb.parse_and_eval(symbol_name)
+# dsp_addr = str(dsp_addr.address).split(" ")
+# gdb_cmd = 'restore ' + dsp_path + ' binary ' + str(dsp_addr[0])
+# print gdb_cmd
+# gdb.execute(gdb_cmd)
+# time_end = time.time()
+# print("loading dsp is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+def thread_memory_Write(mem_addr, set_value):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def thread_memory_Read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ mem_value = mem_value[12:23]
+ hex_int = int(mem_value, 16)
+ return hex_int
+
+
+class gui_tk(Tkinter.Tk):
+ def __init__(self, parent):
+ Tkinter.Tk.__init__(self, parent)
+ elf_path = ""
+ dsp_path = ""
+ dsp_addr = ""
+ self.file_opt = options = {}
+ options['title'] = 'Choose a file'
+ self.parent = parent
+ self.initialize()
+
+ def initialize(self):
+ self.grid()
+ elf_button = Tkinter.Button(self, text=u"Load elf", command=self.elf_OnButtonClick)
+ elf_button.grid(column=0, row=1, sticky='W')
+
+ sym_button = Tkinter.Button(self, text=u"Load symbol", command=self.sym_OnButtonClick)
+ sym_button.grid(column=0, row=2, sticky='W')
+
+ dsp_button = Tkinter.Button(self, text=u"Load DSP bin", command=self.dsp_OnButtonClick)
+ dsp_button.grid(column=0, row=3, sticky='W')
+
+ def elf_OnButtonClick(self):
+ elf_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(elf_path) > 0:
+ print "You chose %s" % elf_path
+ load_all_elf(elf_path)
+ self.quit()
+
+ def sym_OnButtonClick(self):
+ elf_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(elf_path) > 0:
+ print "You chose %s" % elf_path
+ load_all_sym(elf_path)
+ self.quit()
+
+ def dsp_OnButtonClick(self):
+ dsp_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(dsp_path) > 0:
+ print "You chose %s" % dsp_path
+ load_dsp.load_dsp_bin(dsp_path)
+ self.quit()
+
+ def quit(self):
+ global app
+ print "=== Close Easy Loader ==="
+ app.destroy()
+
+if __name__ == "__main__":
+ print "=== Start Easy Loader ==="
+ app = gui_tk(None)
+ app.title('Easy Loader')
+ app.mainloop()
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/coretracer/config/easyLoader/load_dsp.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/coretracer/config/easyLoader/load_dsp.py
new file mode 100755
index 0000000..86e47fa
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/coretracer/config/easyLoader/load_dsp.py
@@ -0,0 +1,106 @@
+#from imgtec import codescape
+import sys
+import time
+import os
+import gdb
+import binascii
+import Tkinter, tkFileDialog
+
+app = None
+dsp_header = 0x0
+dsp_magic = "4d4d4d01"
+
+# load dsp bin file
+def load_dsp_bin(dsp_path):
+ global dsp_header
+ time_str = time.time()
+ print "=== Start load dsp bin ==="
+ print "Dsp bin path: " + dsp_path
+ if(os.path.exists(dsp_path) == False):
+ print "DSP bin doesn't exist: %s" %(dsp_path)
+ print "[Error] Load DSP bin failed"
+ return
+ else:
+ with open(dsp_path, "rb") as dsp_bin:
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print "No header detected, continue"
+ else:
+ dsp_header = 0x200
+ dsp_bin.seek(dsp_header, os.SEEK_SET)
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print "Header detected, skip first 512B"
+ else:
+ print "DSP header detected at neither 0x0 nor 0x200"
+ print "Please check the bin is legal!"
+ print "[Error] Load DSP bin failed"
+ return
+ gdb_cmd='thread 1'
+ gdb.execute(gdb_cmd)
+ ## a) need parsing: 0x13a0000 <dsp_bin_ro>
+ ##symbol_name='&dsp_bin_ro'
+ ##dsp_addr = gdb.parse_and_eval(symbol_name)
+ ## b) need parsing: $3 = 0x13a0000
+ ##gdb_cmd='p/x &dsp_bin_ro'
+ ##dsp_addr = gdb.execute(gdb_cmd, False, True)
+ symbol_name='dsp_bin_ro'
+ dsp_addr = gdb.parse_and_eval(symbol_name)
+ dsp_addr = str(dsp_addr.address).split(" ")
+ dsp_addr = int(dsp_addr[0], 16) - dsp_header
+ print hex(dsp_addr)
+ gdb_cmd = 'monitor mips32 fastchannel 0 1'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'set $cdmmbase=0x1fc1407'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'set *0x1fc100d4=0x02030202'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = " ".join(['restore', dsp_path, 'binary', hex(dsp_addr), hex(dsp_header)])
+ print gdb_cmd
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'set *0x1fc100d4=0x02020202'
+ gdb.execute(gdb_cmd)
+ time_end = time.time()
+ print("loading dsp is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+
+class gui_tk(Tkinter.Tk):
+ def __init__(self, parent):
+ Tkinter.Tk.__init__(self, parent)
+ elf_path = ""
+ dsp_path = ""
+ dsp_addr = ""
+ self.file_opt = options = {}
+ options['title'] = 'Choose a file'
+ self.parent = parent
+ self.initialize()
+
+ def initialize(self):
+ self.grid()
+
+ dsp_button = Tkinter.Button(self, text=u"Load DSP bin =>", command=self.dsp_OnButtonClick)
+ dsp_button.grid(column=0, row=4, sticky='W')
+
+ def dsp_OnButtonClick(self):
+ dsp_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(dsp_path) > 0:
+ print "You chose %s" % dsp_path
+ load_dsp_bin(dsp_path)
+ self.quit()
+
+ def quit(self):
+ global app
+ print "=== Close Easy Loader ==="
+ app.destroy()
+
+def load_dsp_gui():
+ print "=== Start Easy Loader ==="
+ global app
+ app = gui_tk(None)
+ app.title('Easy Loader')
+ app.mainloop()
+
+
+if __name__ == "__main__":
+ load_dsp_gui()
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/coretracer/single_core_basic_load_no_emi_codetracer_SPRAM.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/coretracer/single_core_basic_load_no_emi_codetracer_SPRAM.py
new file mode 100755
index 0000000..f7458ff
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/coretracer/single_core_basic_load_no_emi_codetracer_SPRAM.py
@@ -0,0 +1,504 @@
+# <$ Name: Region Script $>
+
+import struct
+import re
+#import wx
+import os
+import time
+##import CSUtils
+##from imgtec import codescape
+from time import sleep
+##from CSUtils import DA
+import gdb
+import io
+import sys
+import Tkinter, tkFileDialog
+
+def get_selected_inferior():
+ """
+ Return the selected inferior in gdb.
+ """
+ # Woooh, another bug in gdb! Is there an end in sight?
+ # http://sourceware.org/bugzilla/show_bug.cgi?id=12212
+ return gdb.inferiors()[0]
+
+ selected_thread = gdb.selected_thread()
+
+ for inferior in gdb.inferiors():
+ for thread in inferior.threads():
+ if thread == selected_thread:
+ return inferior
+
+class gui_tk(Tkinter.Tk):
+ elf_path = ""
+ sym_path = ""
+ def __init__(self, parent):
+ Tkinter.Tk.__init__(self, parent)
+ self.file_opt = options = {}
+ options['title'] = 'Choose ELF and sym file'
+ self.parent = parent
+ self.initialize()
+
+ def initialize(self):
+ self.grid()
+ global elf_addr_entry
+ elf_addr_entry = Tkinter.Entry(self)
+ elf_addr_entry.grid(column=1, row=3)
+ elf_addr_entry.insert(20, "Choose ELF and sym")
+
+ elf_button = Tkinter.Button(self, text=u"Choose ELF file", command=self.elf_OnButtonClick)
+ elf_button.grid(column=0, row=4, sticky='W')
+
+ sym_button = Tkinter.Button(self, text=u"Choose sym file", command=self.sym_OnButtonClick)
+ sym_button.grid(column=2, row=4, sticky='W')
+
+ load_button = Tkinter.Button(self, text=u"Load all", command=self.load_OnButtonClick)
+ load_button.grid(column=4, row=4, sticky='W')
+
+ def elf_OnButtonClick(self):
+ self.elf_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(self.elf_path) > 0:
+ print "ELF file: %s" % self.elf_path
+
+ def sym_OnButtonClick(self):
+ self.sym_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(self.sym_path) > 0:
+ print "sym file: %s" % self.sym_path
+
+ def load_OnButtonClick(self):
+ self.load_all_elf()
+
+ def load_all_elf(self):
+ if(os.path.exists(self.elf_path) == False):
+ print "[Error] ELF doesn't exist: %s" %(self.elf_path)
+ return
+ else:
+ print "Using ELD file: %s" %(self.elf_path)
+
+ if(os.path.exists(self.sym_path) == False):
+ print "[Error] sym file doesn't exist: %s" %(self.sym_path)
+ return
+ else:
+ print "Using sym file: %s" %(self.sym_path)
+
+ regexp_spram = r'(\s*)(\d*)(\s*)(.SPRAM\d)(\s*)([a-fA-F\d]+)(\s*)([a-fA-F\d]+)(\s*)([a-fA-F\d]+)(\s*)([a-fA-F\d]+)(.*)'
+ pattern_spram = re.compile(regexp_spram)
+
+ regexp_spram_zi = r'(\s*)(\d*)(\s*)(.SPRAM\d_ZI)(\s*)([a-fA-F\d]+)(\s*)([a-fA-F\d]+)(\s*)([a-fA-F\d]+)(\s*)([a-fA-F\d]+)(.*)'
+ pattern_spram_zi= re.compile(regexp_spram_zi)
+
+ regexp_rom = r'(\s*)(\d*)(\s*)(EXTSRAM)(\s*)([a-fA-F\d]+)(\s*)([a-fA-F\d]+)(\s*)([a-fA-F\d]+)(\s*)([a-fA-F\d]+)(.*)'
+ pattern_rom = re.compile(regexp_rom)
+
+ regexp_extsram_zi = r'(\s*)(\d*)(\s*)(EXTSRAM_ZI)(\s*)([a-fA-F\d]+)(\s*)([a-fA-F\d]+)(\s*)([a-fA-F\d]+)(\s*)([a-fA-F\d]+)(.*)'
+ pattern_extsram_zi = re.compile(regexp_extsram_zi)
+
+ ispram_size = [0,0]
+ ispram_load_size = [0,0]
+ ispram_offset = [0,0]
+ ispram_addr = [0,0]
+
+ dspram_size = [0,0]
+ dspram_load_size = [0,0]
+ dspram_load_addr = [0,0]
+ dspram_offset = [0,0]
+ dspram_addr = [0,0]
+
+ dspram_zi_size = [0,0]
+ dspram_zi_addr = [0,0]
+
+ print "Finding ROM"
+ with open(self.sym_path,'r') as sym_file:
+ for line in sym_file:
+ if " EXTSRAM " in line:
+ p = pattern_rom.search(line)
+ load_size = int(p.group(6),16)
+ load_addr = int(p.group(8),16)
+ load_offset = int(p.group(12),16)
+ break
+ if load_size != 0:
+ print "ROM found at offset: 0x%x, load address: 0x%x, size %d bytes" %(load_offset, load_addr, load_size)
+ else:
+ print "ROM is empty!"
+
+ print "Finding EXTSRAM_ZI"
+ with open(self.sym_path,'r') as sym_file:
+ for line in sym_file:
+ if " EXTSRAM_ZI " in line:
+ p = pattern_extsram_zi.search(line)
+ load_zi_size = int(p.group(6),16)
+ load_zi_addr = int(p.group(8),16)
+ break
+ if load_size != 0:
+ print "EXTSRAM_ZI found, address: 0x%x, size %d bytes" %(load_zi_addr, load_zi_size)
+ else:
+ print "EXTSRAM_ZI is empty!"
+
+ print "Finding ISPRAM"
+ with open(self.sym_path,'r') as sym_file:
+ for core_idx in range(0, 2):
+ for line in sym_file:
+ if "ISPRAM0A" in line:
+ continue
+ if "ISPRAM0B" in line:
+ continue
+ if "ISPRAM0C" in line:
+ continue
+ if "ISPRAM" + str(core_idx) in line:
+ p = pattern_spram.search(line)
+ ispram_load_size[core_idx] = int(p.group(6),16)
+ ispram_offset[core_idx] = int(p.group(12),16)
+ break
+ if ispram_load_size[core_idx] != 0:
+ print "ISPRAM%d found at offset: 0x%x, size %d bytes" %(core_idx, ispram_offset[core_idx], ispram_load_size[core_idx])
+ else:
+ print "ISPRAM%d is empty" %(core_idx)
+
+ print "Finding DSPRAM"
+ with open(self.sym_path,'r') as sym_file:
+ for core_idx in range(0, 2):
+ for line in sym_file:
+ if "DSPRAM" + str(core_idx) in line:
+ p = pattern_spram.search(line)
+ dspram_load_size[core_idx] = int(p.group(6),16)
+ dspram_load_addr[core_idx] = int(p.group(8),16)
+ dspram_offset[core_idx] = int(p.group(12),16)
+ break
+ if dspram_load_size[core_idx] != 0:
+ print "DSPRAM%d found at offset: 0x%x, size %d bytes" %(core_idx, dspram_offset[core_idx], dspram_load_size[core_idx])
+ else:
+ print "DSPRAM%d is empty" %(core_idx)
+
+ print "Finding DSPRAM_ZI"
+ with open(self.sym_path,'r') as sym_file:
+ for core_idx in range(0, 2):
+ for line in sym_file:
+ if "DSPRAM" + str(core_idx) + "_ZI" in line:
+ p = pattern_spram_zi.search(line)
+ dspram_zi_size[core_idx] = int(p.group(6),16)
+ dspram_zi_addr[core_idx] = int(p.group(8),16)
+ break
+ if dspram_zi_size[core_idx] != 0:
+ print "DSPRAM%d_ZI found, address 0x%x, size %d bytes" %(core_idx, dspram_zi_addr[core_idx], dspram_zi_size[core_idx])
+ else:
+ print "DSPRAM%d_ZI is empty" %(core_idx)
+
+ gdb.execute('thread 1')
+ # load binary only on VPE0 of 0 core
+ gdb.execute('set *0x1F000020=0xF')
+ gdb.execute('set *0x1F000090=0xA0000000')
+ gdb.execute('set *0x1F000098=0xE0000002')
+ gdb.execute('set *0x1F0000A0=0xC0000000')
+ gdb.execute('set *0x1F0000A8=0xC0000002')
+ gdb.execute('set *0xA0060060=0x03231111')
+
+ # SPRAM1 L2 override to UC
+ gdb.execute('set *0x1F0000C0=0x9F200000')
+ gdb.execute('set *0x1F0000C8=0xFFE00055')
+ # L2 override to Cached
+ gdb.execute('set *0x1F0000B0=0x90000000')
+ gdb.execute('set *0x1F0000B8=0xFFE00071')
+
+ # Diable WDT
+ print("WDT disable ...")
+ mdrgu = (int((gdb.parse_and_eval('*0xA00F0100'))) & 0xFFFFFFFC) | 0x55000000
+ aprgu = (int((gdb.parse_and_eval('*0xC3670100'))) & 0xFFFFFFFE) | 0x55000000
+ gdb.execute('set *0xA00F0100=0x{0:x}'.format(mdrgu))
+ gdb.execute('set *0xC3670100=0x{0:x}'.format(aprgu))
+
+ gdb.execute('set *0x1F000060=0x1E000001')
+
+ ispram_size[0] = 180*1024
+ dspram_size[0] = 36*1024
+ ispram_size[1] = 144*1024
+ dspram_size[1] = 24*1024
+
+ gdb.execute('set *0x1E0000C0=0x{0:x}'.format(ispram_size[0]))
+ gdb.execute('set *0x1E0000C4=0x{0:x}'.format(dspram_size[0]))
+ gdb.execute('set *0x1E0000C8=0x{0:x}'.format(ispram_size[1]))
+ gdb.execute('set *0x1E0000CC=0x{0:x}'.format(dspram_size[1]))
+
+ for core_idx in range(0, 2):
+ gdb.execute('thread {0:d}'.format(core_idx + 1))
+
+ gdb.execute('monitor mips32 fastchannel 0 0')
+
+ ispram_addr[core_idx] = 0x9F000000 + (0x200000 * core_idx)
+ dspram_addr[core_idx] = 0x9F100000 + (0x200000 * core_idx)
+
+ # Enable CDMM
+ C0_CDMMBase = int(gdb.parse_and_eval('$cdmmbase'))
+ print "[Core%d] C0_CDMMBase before: 0x%x" % (core_idx, C0_CDMMBase)
+ C0_CDMMBase = C0_CDMMBase | (1 << 10)
+ gdb.execute('set $cdmmbase=0x{0:x}'.format(C0_CDMMBase))
+ C0_CDMMBase = int(gdb.parse_and_eval('$cdmmbase'))
+ print "[Core%d] C0_CDMMBase after: 0x%x" % (core_idx, C0_CDMMBase)
+
+ # Make bank9 cached
+ MPU_SEGMENT_CTRL2 = int(gdb.parse_and_eval('*0x1FC100D8'))
+ print "[Core%d] MPU_SEGMENT_CTRL2 before: 0x%x" % (core_idx, MPU_SEGMENT_CTRL2)
+ gdb.execute('set *0x1FC100D8=0x02020502')
+ MPU_SEGMENT_CTRL2 = int(gdb.parse_and_eval('*0x1FC100D8'))
+ print "[Core%d] MPU_SEGMENT_CTRL2 after: 0x%x" % (core_idx, MPU_SEGMENT_CTRL2)
+
+ # Enable Segment Ctrl
+ MPU_CONFIG = int(gdb.parse_and_eval('*0x1FC100C8')) & 0xFFFFFFFF
+ print "[Core%d] MPU_CONFIG before: 0x%x" % (core_idx, MPU_CONFIG)
+ MPU_CONFIG = MPU_CONFIG | 0x80000000
+ gdb.execute('set *0x1FC100C8=0x{0:x}'.format(MPU_CONFIG))
+ MPU_CONFIG = int(gdb.parse_and_eval('*0x1FC100C8')) & 0xFFFFFFFF
+ print "[Core%d] MPU_CONFIG after: 0x%x" % (core_idx, MPU_CONFIG)
+
+ print "zero mpu configuration"
+ address = 0x1FC100E0
+ for i in range(0,48):
+ gdb.execute('set *0x{0:x}=0'.format(address))
+ address += 4
+
+ # Configure SPRAM region MPU
+ print "start mpu configuration"
+ if core_idx == 0:
+ gdb.execute('set *0x1FC100E0=0x9F300000')
+ gdb.execute('set *0x1FC100E4=0x0000C88A')
+
+ gdb.execute('set *0x1FC100E8=0x9F200000')
+ gdb.execute('set *0x1FC100EC=0x0000C882')
+
+ gdb.execute('set *0x1FC100F0=0x9F100000')
+ gdb.execute('set *0x1FC100F4=0x0000C88A')
+
+ gdb.execute('set *0x1FC100F8=0x9F000000')
+ gdb.execute('set *0x1FC100FC=0x0000C802')
+
+ gdb.execute('set *0x1FC10100=0x90000000')
+ gdb.execute('set *0x1FC10104=0x0000C802')
+
+ gdb.execute('set *0x1FC10108=0x00000000')
+ gdb.execute('set *0x1FC1010C=0x0000D03A')
+ else:
+ gdb.execute('set *0x1FC100E0=0x9F300000')
+ gdb.execute('set *0x1FC100E4=0x0000C88A')
+
+ gdb.execute('set *0x1FC100E8=0x9F200000')
+ gdb.execute('set *0x1FC100EC=0x0000C882')
+
+ gdb.execute('set *0x1FC100F0=0x9F100000')
+ gdb.execute('set *0x1FC100F4=0x0000C88A')
+
+ gdb.execute('set *0x1FC100F8=0x9F000000')
+ gdb.execute('set *0x1FC100FC=0x0000C802')
+
+ gdb.execute('set *0x1FC10100=0x90000000')
+ gdb.execute('set *0x1FC10104=0x0000C802')
+
+ gdb.execute('set *0x1FC10108=0x00000000')
+ gdb.execute('set *0x1FC1010C=0x0000D03A')
+
+ gdb.execute('thread {0:d}'.format(core_idx + 1))
+ gdb.execute('set $status=0x0')
+ gdb.execute('set $ebase=0x9ff{0:x}0800'.format(4*core_idx))
+ #gdb.execute('set $config5=0x0')
+ C0_CAUSE = int(gdb.parse_and_eval("$cause"))
+ gdb.execute('set $cause=0x{0:x}'.format(C0_CAUSE & 0xffbfffff))
+ print "Initializind Core %d SPRAM. ISPRAM addr 0x%x, DSPRAM addr 0x%x" %(core_idx, ispram_addr[core_idx], dspram_addr[core_idx])
+
+ C0_ERRCTL = int(gdb.parse_and_eval("$errctl"))
+ gdb.execute('set $errctl=0x{0:x}'.format(C0_ERRCTL | (1 << 28)))
+
+ #Init SPRAM base addr
+ gdb.execute('set $dtaglo=0x{0:x}'.format(dspram_addr[core_idx] | (1 << 7)))
+ gdb.execute('monitor mips32 cacheop 0 0 9')
+ gdb.execute('set $itaglo=0x{0:x}'.format(ispram_addr[core_idx] | (1 << 7)))
+ gdb.execute('monitor mips32 cacheop 0 0 8')
+ #gdb.execute('handle SIGTRAP pass')
+ #gdb.execute('set $pc=0x90000000')
+ gdb.execute('set $ra=0x9ff{0:x}0000'.format(4*core_idx))
+ #return
+ gdb.execute('set $errctl=0x{0:x}'.format(C0_ERRCTL))
+ #return
+ # Load memory init code
+ if True:#load_size != 0:
+ #with io.open(self.elf_path, 'rb',0) as elf_file:
+ # elf_file.seek(load_offset, 1)
+ # gdb.selected_inferior().write_memory(load_addr, elf_file.read(load_size), load_size)
+
+
+ tmp_ispram_array = [0x8d050000,0x8d060004,0x4085e001,0x4086e801,0x000000c0,0xbd2c0000,0x0000000f,0x21080008,0x21290008,0x214afff8,0x1540fff5,0x00000000,0x03e00008,0x00000000,0xad200000,0x21290004,0x214afffc,0x1540fffc,0x00000000,0x03e00008,0x00000000,0x00000000]
+ with io.open(self.elf_path, 'rb',0) as elf_file:
+ elf_file.seek(ispram_offset[0]+0x300, 1)
+ #for i in range(0, 0x50/4):
+ # bytesFromELF = elf_file.read(4)
+ # print "Read from ELF: 0x%x", bytesFromELF.encode("hex")
+ # gdb.selected_inferior().write_memory(ispram_addr[0]+(i*0x4), bytesFromELF, 0x4)
+ # print "offset 0x%x, value: %s\n" % (i*0x4, bytesFromELF.encode("hex"))
+ gdb.selected_inferior().write_memory(ispram_addr[0]+0x300, elf_file.read(0x54), 0x54)
+ ##### try errCtrl + cacheop on ispram #####
+ #C0_ERRCTL = int(gdb.parse_and_eval("$errctl"))
+ #gdb.execute('set $errctl=0x{0:x}'.format(C0_ERRCTL | (1 << 28)))
+
+ #tmp_ispram_addr = 0x9f000300
+ #
+ #print "size(tmp_ispram_array) = %d" %(len(tmp_ispram_array))
+ #tmp_gpr_base = int(gdb.parse_and_eval("$t8"))
+ #for i in range(0, 11):
+ # print "iidatahi = 0x%x, idatalo=0x%x" %(tmp_ispram_array[2*i+1],tmp_ispram_array[2*i])
+ # gdb.execute('set $t8=0x{0:x}'.format(tmp_ispram_addr))
+ # gdb.execute('set $idatahi=0x{0:x}'.format(tmp_ispram_array[2*i+1]))
+ # gdb.execute('set $idatalo=0x{0:x}'.format(tmp_ispram_array[2*i]))
+ # gdb.execute('monitor mips32 cacheop 24 0 12')
+ # #gdb.execute('handle SIGTRAP pass')
+ # #gdb.execute('set $pc=0x90000000')
+ # gdb.execute('set $ra=0x9ff{0:x}0000'.format(4*core_idx))
+ # #return
+ # tmp_ispram_addr = tmp_ispram_addr + 0x8
+ #gdb.execute('set $errctl=0x{0:x}'.format(C0_ERRCTL))
+ ##### try errCtrl + cacheop on ispram #####
+ print "Init code Loaded"
+ #gdb.execute('set $errctl=0x{0:x}'.format(C0_ERRCTL | (1 << 28)))
+ #time.sleep(1)
+ gdb.execute('info threads')
+ gdb.execute('d')
+ if ispram_size[core_idx] != 0:
+ C0_ERRCTL = int(gdb.parse_and_eval("$errctl"))
+ gdb.execute('set $errctl=0x{0:x}'.format(C0_ERRCTL | (1 << 28)))
+ load_len = int(8 * round(ispram_load_size[core_idx]/8)) + 8
+ print "Load ISPRAM%d to 0x%x, size: %d" %(core_idx, ispram_addr[core_idx], load_len)
+ for load_round in range(0,6):
+ print "Load ISPRAM%d round %d to 0x%x"%(core_idx, load_round, ispram_addr[core_idx] + (dspram_size[core_idx] * load_round))
+ gdb.execute('set $t0=0x{0:x}'.format(dspram_addr[core_idx]))
+ #time.sleep(1)
+ gdb.execute('set $t1=0x{0:x}'.format(ispram_addr[core_idx] + (dspram_size[core_idx] * load_round)))
+ #time.sleep(1)
+ if load_len >= dspram_size[core_idx]:
+ gdb.execute('set $t2=0x{0:x}'.format(dspram_size[core_idx]))
+ time.sleep(1)
+ print "Load binary to DSPRAM"
+ with io.open(self.elf_path, 'rb',0) as elf_file:
+ elf_file.seek(ispram_offset[core_idx] + (dspram_size[core_idx] * load_round), 1)
+ print "Target:0x%x size:0x%x" % (dspram_addr[core_idx],dspram_size[core_idx])
+ gdb.execute('info threads')
+ get_selected_inferior().write_memory(dspram_addr[core_idx], elf_file.read(dspram_size[core_idx]), dspram_size[core_idx])
+ print "DSPRAM chunk loaded"
+ time.sleep(1)
+ gdb.execute('hb *0x9ff{0:x}0008 thread {1:x}'.format(4*core_idx,core_idx+1))
+ gdb.execute('set $pc=0x9ff{0:x}000c'.format(4*core_idx))
+ gdb.execute('set $gp=ispram_load_code')
+ print "Load Done"
+ gdb.execute('info b')
+ gdb.execute('p /x $pc')
+ gdb.execute('p /x $gp')
+
+ gdb.execute('c')
+ #return
+ gdb.execute('d')
+ #print "sleep done"
+ load_round = load_round + 1
+ load_len = load_len - dspram_size[core_idx]
+ elif load_len != 0:
+ gdb.execute('set $t2=0x{0:x}'.format(load_len))
+ with io.open(self.elf_path, 'rb') as elf_file:
+ elf_file.seek(ispram_offset[core_idx] + (dspram_size[core_idx] * load_round), 1)
+ print "Target:0x%x size:0x%x" % (dspram_addr[core_idx],load_len)
+ get_selected_inferior().write_memory(dspram_addr[core_idx], elf_file.read(load_len), load_len)
+ gdb.execute('set $pc=0x9ff{0:x}000c'.format(4*core_idx))
+ gdb.execute('set $gp=ispram_load_code')
+ gdb.execute('hb *0x9ff{0:x}0008 thread {1:x}'.format(4*core_idx,core_idx+1))
+ gdb.execute('c')
+
+ gdb.execute('d')
+ break
+ gdb.execute('set $errctl=0x{0:x}'.format(C0_ERRCTL))
+ print "Load ISPRAM%d done"%(core_idx)
+ else:
+ print "ISPRAM%d image is empty"%(core_idx)
+
+
+ for core_idx in range(0, 2):
+ gdb.execute('thread 1')
+ print "Loading DSPRAM%d image to: 0x%x" %(core_idx, dspram_load_addr[core_idx])
+ if dspram_load_size[core_idx] != 0:
+ with io.open(self.elf_path, 'rb') as elf_file:
+ elf_file.seek(dspram_offset[core_idx], 1)
+ get_selected_inferior().write_memory(dspram_load_addr[core_idx], elf_file.read(dspram_load_size[core_idx]), dspram_load_size[core_idx])
+ # Load DSPRAM always on core 0 to ensure L1 cache coherency
+ #gdb.execute('thread 1')
+
+ print "Initializing DSPRAM%d_ZI to: 0x%x" %(core_idx, dspram_zi_addr[core_idx])
+ if dspram_zi_size[core_idx] != 0:
+ # Do DSPRAM ZI always on core 0 to ensure L1 cache coherency
+ gdb.execute('thread 1')
+ gdb.execute('set $t1=0x{0:x}'.format(dspram_zi_addr[core_idx]))
+ gdb.execute('set $t2=0x{0:x}'.format(dspram_zi_size[core_idx]))
+ gdb.execute('set $pc=0x9ff{0:x}000c'.format(4*core_idx))
+ gdb.execute('set $gp=dspram_zi_loop')
+ gdb.execute('hb *0x9ff{0:x}0008 thread {1:x}'.format(4*core_idx,core_idx+1))
+ gdb.execute('c')
+ gdb.execute('d')
+ #time.sleep(4)
+ print "Load DSPRAM%d image done" %(core_idx)
+ #if core_idx != 0:
+ # gdb.execute('thread %d'%(core_idx + 1))
+ # gdb.execute('set $pc=0x9FF40000')
+
+
+ gdb.execute('thread 1')
+ #print "Load and lock L2 cache done"
+ gdb.execute('set *0x1FC10100=0x90000000')
+ gdb.execute('set *0x1FC10104=0x0000C805')
+
+ gdb.execute('thread 2')
+ #print "Load and lock L2 cache done"
+ gdb.execute('set *0x1FC10100=0x90000000')
+ gdb.execute('set *0x1FC10104=0x0000C805')
+
+ gdb.execute('thread 1')
+ #print "Load and lock L2 cache from 0x%x size 0x%x" %(load_zi_addr, load_zi_size)
+ #return
+ '''
+ if load_zi_size != 0:
+ print "EXTSRAM_ZI found, address: 0x%x, size %d bytes" %(load_zi_addr, load_zi_size)
+ load_zi_size = int(64 * round(load_zi_size/64))
+ print "EXTSRAM_ZI found, address: 0x%x, size %d bytes" %(load_zi_addr, load_zi_size)
+ gdb.execute('hb *0x9ff00008 thread 1')
+
+
+ while load_zi_size > 0:
+ print "WRITE 64 bytes from: 0x%x. STILL %d bytes to go" %(load_zi_addr, load_zi_size)
+ gdb.execute('info threads')
+ gdb.execute('set $t1=0x{0:x}'.format(load_zi_addr))
+ gdb.execute('set $t2=0x40')
+ gdb.execute('set $pc=0x9ff0000c')
+ gdb.execute('set $gp=l2_zi_loop')
+ load_zi_addr = load_zi_addr + 0x40
+ load_zi_size = load_zi_size - 0x40
+ gdb.execute('c')
+
+ #load_zi_size = 65536
+ #gdb.execute('info threads')
+ #gdb.execute('set $t1=0x{0:x}'.format(load_zi_addr))
+ #gdb.execute('set $t2=0x{0:x}'.format(load_zi_size))
+ #gdb.execute('set $pc=0x9ff0000c')
+ #gdb.execute('set $gp=l2_zi_loop')
+
+ #return
+ gdb.execute('c')
+ gdb.execute('d')
+ #time.sleep(60)
+
+ return
+ '''
+ gdb.execute('set $pc=INT_Vectors')
+ gdb.execute('hb *0x9f005180')
+ #gdb.execute('hb itc_init thread 2')
+ print "All loading is done"
+
+ def my_quit(self):
+ global app
+ print "=== Close Easy Loader ==="
+ app.destroy()
+
+if __name__ == "__main__":
+ app = gui_tk(None)
+ app.title("Load ELF")
+ app.mainloop()
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/mt6761-evb.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/mt6761-evb.cmm
new file mode 100755
index 0000000..91cbf95
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/mt6761-evb.cmm
@@ -0,0 +1,114 @@
+;*****************************************************************************
+; Copyright Statement:
+; --------------------
+; This software is protected by Copyright and the information contained
+; herein is confidential. The software may not be copied and the information
+; contained herein may not be used or disclosed except with the written
+; permission of MediaTek Inc. (C) 2011
+;
+;*****************************************************************************
+;;================================================
+;; PURPOSE: EVB Bring Up
+;; CREATE_DATE: 2016/04/01
+;; NOTE:
+;;================================================
+; Specify Core Number
+;=================================================
+
+&NR_CPUS=1
+; cluster 0 corebase: 0x8007000, 0x8007200, 0x8007400, 0x8007600
+; cluster 1 corebase: 0x8009000, 0x8009200, 0x8009400, 0x8009600
+
+;=================================================
+; Initialize CPU
+;=================================================
+&WDT_TEST=0
+if &WDT_TEST==0
+(
+ RESET
+ SYSTEM.OPTION ENRESET ON
+)
+
+SYSTEM.RESET
+SYSTEM.OPTION ENRESET ON
+SYSTEM.OPTION RESBREAK OFF
+SYSTEM.OPTION WAITRESET OFF
+
+SYSTEM.JTAGCLOCK 10.MHz;
+
+;SYSTEM.CPU CortexA7MPCore
+SYStem.CPU CORTEXA53;
+
+;R-T Memory Access
+SYSTEM.MULTICORE MEMORYACCESSPORT 0
+SYSTEM.MULTICORE DEBUGACCESSPORT 1
+
+;SYSTEM.MULTICORE COREBASE APB:0x80070000
+;Setting Core debug register access
+if &NR_CPUS==1
+(
+ SYStem.CONFIG CORENUMBER 1;
+ SYStem.CONFIG COREBASE 0x8D410000;
+ SYStem.CONFIG CTIBASE 0x8D420000;
+)
+else
+(
+ SYSTEM.CONFIG CORENUMBER 2;
+ SYSTEM.CONFIG COREBASE 0x80810000 0x80910000;
+ SYStem.CONFIG CTIBASE 0x80820000 0x80920000;
+)
+
+;=================================================
+; Attach and Stop CPU
+;=================================================
+SYStem.Up
+wait 200.us
+
+SETUP.IMASKHLL ON
+SETUP.IMASKASM ON
+
+;enable L2C 256KB
+D.S SD:0x102007F0 %LE %LONG 0x00010100 ;Enable L2C share SRAM (256K)
+D.S SD:0x102007F0 %LE %LONG 0x00010101 ;Enable L2C share SRAM (256K)
+
+; set_hw_breakpoint_by_def
+; setting attribute of breakpoints
+Break.Select Program OnChip
+Break.Select Hll OnChip
+Break.Select Spot OnChip
+Break.Select Read OnChip
+Break.Select Write OnChip
+
+D.S C15:0x1 0 ; Turn off MMU
+
+; for pmic power latch (RGU + 0xA4)
+d.s c:0x100070a4 %le %long 0x66000001
+
+; disable wdt (debug purpose)
+D.S SD:0x10007000 %LE %LONG 0x22000000
+
+; Init DRAM
+;do MT6765_FPGA_DDR
+
+print "loading pre-loader image"
+d.load.elf preloader_evb6761_64_emmc.elf
+
+Y.SPATH.RESET ; reset all source path
+Y.SPATH.SRD ../../platform/mt6761/src/init
+Y.SPATH.SRD ../../platform/mt6761/src/core
+Y.SPATH.SRD ../../platform/mt6761/src/drivers
+Y.SPATH.SRD ../../platform/mt6761/src/security
+Y.SPATH.SRD ../../platform/common
+Y.SPATH.SRD ../../custom/evb6761_64_emmc
+
+
+Break.Select Program OnChip
+Break.Select Hll OnChip
+Break.Select Spot OnChip
+Break.Select Read OnChip
+Break.Select Write OnChip
+
+R.S T 0
+;winclear
+d.l
+enddo
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/preloader_evb6761_64_emmc_TINY.elf b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/preloader_evb6761_64_emmc_TINY.elf
new file mode 100755
index 0000000..446612c
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6761/preloader_evb6761_64_emmc_TINY.elf
Binary files differ
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/APView_MT6763_EVB_UART_Test.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/APView_MT6763_EVB_UART_Test.cmm
new file mode 100755
index 0000000..a531715
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/APView_MT6763_EVB_UART_Test.cmm
@@ -0,0 +1,32 @@
+;MT6763 MD_UART0 port test
+;You should make sure GPIO13 has connected to UART port RXD pin,GPIO14 has connected to UART port TXD pin
+
+;port: MDUART0
+;Baudrate: 115200
+;&BASE_ADDR_MDUART0=0xA0010000
+;&BASE_ADDR_MDGPIO=0xC0005000
+
+&BASE_ADDR_MDUART0=0x20010000
+&BASE_ADDR_MDGPIO=0x10005000
+
+
+D.S SD:&BASE_ADDR_MDGPIO+0x310 %LE %LONG 0x4400000 //set GPIO 13/14 to MDUART mode
+D.S SD:&BASE_ADDR_MDUART0+0x24 %LE %LONG 0x03 //High Speed X
+D.S SD:&BASE_ADDR_MDUART0+0x28 %LE %LONG 0xE1 //Sample count
+D.S SD:&BASE_ADDR_MDUART0+0x2C %LE %LONG 0x71 //sample point
+D.S SD:&BASE_ADDR_MDUART0+0x0C %LE %LONG 0x83 //Enable Divisor latch acess bit, and set 8bit length.
+D.S SD:&BASE_ADDR_MDUART0+0x00 %LE %LONG 0x01 //sample point
+D.S SD:&BASE_ADDR_MDUART0+0x04 %LE %LONG 0x00 //sample point
+D.S SD:&BASE_ADDR_MDUART0+0x0C %LE %LONG 0x03 //Clear Divisor latch acess bit, and set 8bit length.
+
+&uart_lsr=0x0
+&uart_rxd=0x0
+PRINT "Please put char "U" from PC to EVB UART! Note: ASCII "U" remap to HEX is 0x55 "
+WHILE (&uart_lsr&0x01)!=0x01
+(
+ &uart_lsr=data.long(sd:&BASE_ADDR_MDUART0+0x14)
+)
+&uart_rxd=data.long(sd:&BASE_ADDR_MDUART0+0x0)
+PRINT "EVB UART Get data: &uart_rxd"
+D.S SD:&BASE_ADDR_MDUART0+0x00 %LE %LONG &uart_rxd //Write data to UART, please check console.
+PRINT "EVB UART will send data to PC,please check!"
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/APview_MT6763_AP2MD_enable.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/APview_MT6763_AP2MD_enable.cmm
new file mode 100755
index 0000000..c3ef9dc
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/APview_MT6763_AP2MD_enable.cmm
@@ -0,0 +1,24 @@
+&MEM_CLASS="AXI"
+; do AP to MD path disable
+LOCAL &BASE_ADDR_AP2MD_Dummy
+LOCAL &BASE_ADDR_INFRA_PERI2MD_PROT_EN
+LOCAL &BASE_ADDR_INFRA_MD2PERI_PROT_EN
+LOCAL &temp
+
+&BASE_ADDR_AP2MD_Dummy=0x10001370
+&BASE_ADDR_INFRA_PERI2MD_PROT_EN=0x10001220
+&BASE_ADDR_INFRA_MD2PERI_PROT_EN=0x10001250
+
+
+&temp=data.long(&MEM_CLASS:(&BASE_ADDR_AP2MD_Dummy+0x0))&0xFFFFFFFE
+;PRINT "temp=" "&temp"
+;PRINT "BASE_ADDR_AP2MD_Dummy=" "&BASE_ADDR_AP2MD_Dummy"
+D.S &MEM_CLASS:(&BASE_ADDR_AP2MD_Dummy+0x0) %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&MEM_CLASS:(&BASE_ADDR_INFRA_PERI2MD_PROT_EN+0x0))&0xFFFFFF7F
+;PRINT "temp=" "&temp"
+;PRINT "BASE_ADDR_INFRA_PERI2MD_PROT_EN=" "&BASE_ADDR_INFRA_PERI2MD_PROT_EN"
+D.S &MEM_CLASS:(&BASE_ADDR_INFRA_PERI2MD_PROT_EN+0x0) %LE %LONG &temp
+wait 1.ms
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/APview_MT6763_Frequency_Meter.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/APview_MT6763_Frequency_Meter.cmm
new file mode 100755
index 0000000..f19e683
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/APview_MT6763_Frequency_Meter.cmm
@@ -0,0 +1,530 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; MT6763 MD Frequency Meter
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;;Select PLL
+LOCAL &key_in
+&key_in=0
+
+LOCAL &opt_cvd_connect
+&opt_cvd_connect="debug"
+
+;;;;;;;;;;;;;;;;;;;;;;;Below you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+LOCAL &mclass ;; Memory Class
+&mclass="axi"
+;&mclass="pm"
+
+LOCAL &clksw_base ;; MD CLKSW base address
+;&clksw_base=0xA0150000 ;; MD view APB
+;&clksw_base=0xA0096000 ;; MD view debug APB
+&clksw_base=0x20150000 ;; AP view MD system bus
+;&clksw_base=0x0D0D6000 ;; AP view MD debug sys
+
+LOCAL &pll_base ;; MD PLLMIXED base address
+;&pll_base=0xA0140000 ;; MD view APB
+;&pll_base=0xA0094000 ;; MD view debug APB
+&pll_base=0x20140000 ;; AP view MD system bus
+;&pll_base=0x0D0D4000 ;; AP view MD debug sys
+
+&fqmtr_fcksel_32k_index=0x17
+;;;;;;;;;;;;;;;;;;;;;;;Above you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LOCAL &fqmtr_winset ;; Frequency Meter Windoiw Setting (= Number of FIXED clock cycle)
+&fqmtr_winset=0x1ff
+&fqmtr_winset_for_32k=0x1E000
+
+LOCAL &fqmtr_fcksel_val ;; Frequency Meter FIXED clock selection
+&fqmtr_fcksel_val=0x1a ;; Select 26Mhz by default
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;All the PLL you could select;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+&SRC_STR_1="Reserved"
+&SRC_STR_2="Reserved"
+&SRC_STR_3="Reserved"
+&SRC_STR_4="Reserved"
+&SRC_STR_5="Reserved"
+&SRC_STR_6="Reserved"
+&SRC_STR_7="Reserved"
+&SRC_STR_8="Reserved"
+&SRC_STR_9="Reserved"
+&SRC_STR_10="TRACE_MON_clock"
+&SRC_STR_11="MDSYS_208M_clock"
+&SRC_STR_12="mdrxsys_rake_clock"
+&SRC_STR_13="mdrxsys_brp_clock"
+&SRC_STR_14="mdrxsys_vdsp_clock"
+&SRC_STR_15="mdtop_log_atb_clock"
+&SRC_STR_16="fesys_csys_clock"
+&SRC_STR_17="fesys_txsys_clock"
+&SRC_STR_18="fesys_bsi_clock"
+&SRC_STR_19="mdsys_mdcore_clock"
+&SRC_STR_20="mdsys_bus2x_nodcm_clock"
+&SRC_STR_21="mdsys_bus2x_clock"
+&SRC_STR_22="mdtop_dbg_clock"
+&SRC_STR_23="mdtop_f32k_clock"
+&SRC_STR_24="MDBPIPLL_0_DIV2_clock"
+&SRC_STR_25="MDBPIPLL_2_clock"
+&SRC_STR_26="MDBPIPLL_1_clock"
+&SRC_STR_27="MDBPIPLL_0_clock"
+&SRC_STR_28="MDTXPLL_clock"
+&SRC_STR_29="MDBRPPLL_clock"
+&SRC_STR_30="MDVDSPPLL_clock"
+&SRC_STR_31="MDMCUPLL_clock"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+DIALOG
+(&
+ HEADER "PLL Frequency Meter"
+ ICON ":chip"
+
+ POS 0. 0. 20. 1.
+ LINE "FQMTR Selection"
+ ; x y w h
+ POS 0. 1. 20. 1.
+ SEL.NONE: CHOOSEBOX "None"
+ (
+ &key_in=0x00
+ )
+;; SEL.1: CHOOSEBOX "&SRC_STR_1"
+;; (
+;; &key_in=0x1
+;; &key_str="&SRC_STR_1"
+;; )
+;; SEL.2: CHOOSEBOX "&SRC_STR_2"
+;; (
+;; &key_in=0x2
+;; &key_str="&SRC_STR_2"
+;; )
+;; SEL.3: CHOOSEBOX "&SRC_STR_3"
+;; (
+;; &key_in=0x3
+;; &key_str="&SRC_STR_3"
+;; )
+;; SEL.4: CHOOSEBOX "&SRC_STR_4"
+;; (
+;; &key_in=0x4
+;; &key_str="&SRC_STR_4"
+;; )
+;; SEL.5: CHOOSEBOX "&SRC_STR_5"
+;; (
+;; &key_in=0x5
+;; &key_str="&SRC_STR_5"
+;; )
+;; SEL.6: CHOOSEBOX "&SRC_STR_6"
+;; (
+;; &key_in=0x6
+;; &key_str="&SRC_STR_6"
+;; )
+;; SEL.7: CHOOSEBOX "&SRC_STR_7"
+;; (
+;; &key_in=0x7
+;; &key_str="&SRC_STR_7"
+;; )
+;; SEL.8: CHOOSEBOX "&SRC_STR_8"
+;; (
+;; &key_in=0x8
+;; &key_str="&SRC_STR_8"
+;; )
+;; SEL.9: CHOOSEBOX "&SRC_STR_9"
+;; (
+;; &key_in=0x9
+;; &key_str="&SRC_STR_9"
+;; )
+ SEL.10: CHOOSEBOX "&SRC_STR_10"
+ (
+ &key_in=0xA
+ &key_str="&SRC_STR_10"
+ )
+ SEL.11: CHOOSEBOX "&SRC_STR_11"
+ (
+ &key_in=0xB
+ &key_str="&SRC_STR_11"
+ )
+ SEL.12: CHOOSEBOX "&SRC_STR_12"
+ (
+ &key_in=0xC
+ &key_str="&SRC_STR_12"
+ )
+ SEL.13: CHOOSEBOX "&SRC_STR_13"
+ (
+ &key_in=0xD
+ &key_str="&SRC_STR_13"
+ )
+ SEL.14: CHOOSEBOX "&SRC_STR_14"
+ (
+ &key_in=0xE
+ &key_str="&SRC_STR_14"
+ )
+ SEL.15: CHOOSEBOX "&SRC_STR_15"
+ (
+ &key_in=0xF
+ &key_str="&SRC_STR_15"
+ )
+ SEL.16: CHOOSEBOX "&SRC_STR_16"
+ (
+ &key_in=0x10
+ &key_str="&SRC_STR_16"
+ )
+ SEL.17: CHOOSEBOX "&SRC_STR_17"
+ (
+ &key_in=0x11
+ &key_str="&SRC_STR_17"
+ )
+ SEL.18: CHOOSEBOX "&SRC_STR_18"
+ (
+ &key_in=0x12
+ &key_str="&SRC_STR_18"
+ )
+ SEL.19: CHOOSEBOX "&SRC_STR_19"
+ (
+ &key_in=0x13
+ &key_str="&SRC_STR_19"
+ )
+ SEL.20: CHOOSEBOX "&SRC_STR_20"
+ (
+ &key_in=0x14
+ &key_str="&SRC_STR_20"
+ )
+ SEL.21: CHOOSEBOX "&SRC_STR_21"
+ (
+ &key_in=0x15
+ &key_str="&SRC_STR_21"
+ )
+ SEL.22: CHOOSEBOX "&SRC_STR_22"
+ (
+ &key_in=0x16
+ &key_str="&SRC_STR_22"
+ )
+ SEL.23: CHOOSEBOX "&SRC_STR_23"
+ (
+ &key_in=0x17
+ &key_str="&SRC_STR_23"
+ )
+ SEL.24: CHOOSEBOX "&SRC_STR_24"
+ (
+ &key_in=0x18
+ &key_str="&SRC_STR_24"
+ )
+ SEL.25: CHOOSEBOX "&SRC_STR_25"
+ (
+ &key_in=0x19
+ &key_str="&SRC_STR_25"
+ )
+ SEL.26: CHOOSEBOX "&SRC_STR_26"
+ (
+ &key_in=0x1A
+ &key_str="&SRC_STR_26"
+ )
+ SEL.27: CHOOSEBOX "&SRC_STR_27"
+ (
+ &key_in=0x1B
+ &key_str="&SRC_STR_27"
+ )
+ SEL.28: CHOOSEBOX "&SRC_STR_28"
+ (
+ &key_in=0x1C
+ &key_str="&SRC_STR_28"
+ )
+ SEL.29: CHOOSEBOX "&SRC_STR_29"
+ (
+ &key_in=0x1D
+ &key_str="&SRC_STR_29"
+ )
+ SEL.30: CHOOSEBOX "&SRC_STR_30"
+ (
+ &key_in=0x1E
+ &key_str="&SRC_STR_30"
+ )
+ SEL.31: CHOOSEBOX "&SRC_STR_31"
+ (
+ &key_in=0x1F
+ &key_str="&SRC_STR_31"
+ )
+
+ POS 21. 0. 20. 1.
+ LINE "FQMTR Information"
+ INFO1: EDIT "Window Seting: &fqmtr_winset" ""
+ INFO2: EDIT "Fixed Clock: &fqmtr_fcksel_val" ""
+ INFO3: EDIT "32K measure support" ""
+
+ POSY 1. 20. 1.
+ LINE "FQMTR Result"
+ RESULT: EDIT "" ""
+
+ POSY 1. 20. 1.
+ DEFBUTTON "OK"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ IF &key_in!=0
+ (
+ GOSUB fqmtr_query &key_in &key_str 1
+ )
+ )
+
+ DEFBUTTON "LIST ALL"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ GOSUB fqmtr_list_all
+ )
+
+ DEFBUTTON "Force LIST main clk"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ GOSUB fqmtr_force_list_all
+ )
+
+ CLOSE
+ (
+ PRINT "bye~"
+ DIALOG.END
+ )
+)
+
+ ;; Disable EDIT of showing information
+ DIALOG.Disable INFO1
+ DIALOG.Disable INFO2
+ DIALOG.Disable INFO3
+ ;DIALOG.Disable RESULT
+STOP
+ENDDO
+
+;;;;;The main function to get the Frequency. &idx==> the clock you select, &str==> clock name, &info==>list more info and wait 5ms in the function
+;; &info=1 ==> for printing many PLLs at one time
+fqmtr_query:
+ENTRY &idx &str &info
+(
+ IF &info!=0
+ (
+ PRINT "&str: &idx"
+ PRINT "fqmtrsrc: 0x" FORMAT.HEX(2,&idx)
+ PRINT "opt_cvd_connect: &opt_cvd_connect"
+ )
+
+ LOCAL &unit
+ LOCAL &fqmtr_winset_26M
+ LOCAL &fqmtr_result
+ LOCAL &fqmtr_result_raw
+ LOCAL &fqmtr_result_str
+ LOCAL &safe_wait_cnt
+ LOCAL &safe_wait_cnt_max
+ LOCAL &mul_for_32k
+
+ &safe_wait_cnt=0
+
+ IF &fqmtr_fcksel_val==0x1a ;; base on 26M, unit:MHz
+ (
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &unit="Khz"
+ &fqmtr_winset_26M=&fqmtr_winset_for_32k
+ &safe_wait_cnt_max=500 ;;5000 ms = 5s ==> in real test, longer than 5s, so reduce it
+ &mul_for_32k=0x3E8
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &unit="Mhz"
+ &fqmtr_winset_26M=&fqmtr_winset
+ &safe_wait_cnt_max=32 ;;32 ms
+ &mul_for_32k=1
+ )
+ )
+ ELSE
+ (
+ &unit=""
+ )
+
+ IF "&opt_cvd_connect"=="none"
+ (
+ sys.m prepare
+ )
+ ELSE IF "&opt_cvd_connect"=="debug"
+ (
+ ; do nothing
+ )
+ ELSE IF "&opt_cvd_connect"=="ca7"
+ (
+ LOCAL &OPT_JTAG
+ LOCAL &OPT_AP_NR_CPUS
+ LOCAL &OPT_AP_COREBASE
+
+ &OPT_JTAG=0
+ &OPT_AP_NR_CPUS=2
+ &OPT_AP_COREBASE="0x80070000 0x80072000"
+ ;&OPT_AP_NR_CPUS=4
+ ;&OPT_AP_COREBASE="0x80070000 0x80072000 0x80074000 0x80076000"
+ DO CA7_connect.cmm
+ )
+ ELSE
+ (
+ IF &info!=0
+ (
+ PRINT "No explicit CVD connection, use current status"
+ )
+ )
+
+ IF &idx==0
+ (
+ ;; This is used for connect CVD only, no FQMTR test
+ RETURN
+ )
+
+ ;;div 8 and select src
+ Data.Set &mclass:(&clksw_base+0x0104) %LE %LONG 0x0 ;reset frequency meter
+ Data.Set &mclass:(&clksw_base+0x0100) %LE %LONG (0x0300)|(&idx)
+ Data.Set &mclass:(&clksw_base+0x0108) %LE %LONG &fqmtr_winset_26M
+ Data.Set &mclass:(&clksw_base+0x0104) %LE %LONG 0x1 ;enable frequency meter
+
+
+ ;; read status, to check polling done or not
+ &fqmtr_busy=DATA.LONG(&mclass:(&clksw_base+0x0104))&(1<<1)
+ WHILE &fqmtr_busy==0
+ (
+ ;PRINT ". &fqmtr_busy"
+ &fqmtr_busy=DATA.LONG(&mclass:(&clksw_base+0x0104))&(1<<1)
+ &safe_wait_cnt=&safe_wait_cnt+1
+ IF &safe_wait_cnt==&safe_wait_cnt_max
+ (
+ PRINT "[&str] Wait Fail, exit"
+ DIALOG.Set RESULT "Wait Fail(No clock), exit"
+ RETURN
+ )
+ ELSE
+ (
+;; PRINT "Waiting result. safe_wait_cnt=" "&safe_wait_cnt"
+ )
+ WAIT 1ms
+ )
+
+ ;; Calculate the result
+ &fqmtr_result_raw=DATA.LONG(&mclass:(&clksw_base+0x10c))
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*8*&mul_for_32k/(&fqmtr_winset_26M+3)
+ &fqmtr_result_dec=FORMAT.DECIMAL(0,&fqmtr_result)
+ &fqmtr_result_str=""+FORMAT.DECIMAL(0,&fqmtr_result)+" &unit"
+ IF &info==0
+ (
+ PRINT "0x" FORMAT.HEX(2,&idx) ",&fqmtr_result_dec,&unit,&str,&fqmtr_result_raw,"
+ )
+ ELSE
+ (
+ PRINT "Frequency Meter Result: &fqmtr_result_str (&fqmtr_result_raw)"
+ PRINT ""
+ )
+ DIALOG.Set RESULT "&fqmtr_result_str"
+
+ IF &info==0
+ (
+ WAIT 5ms
+ )
+
+ RETURN
+)
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+fqmtr_create_win:
+(
+ AREA.RESet
+ AREA.Create PLL_FMETER
+ AREA.Select PLL_FMETER
+ WinPOS 10.,0.,50.,35.,,, FMETER
+ AREA.view PLL_FMETER
+ AREA.Clear PLL_FMETER
+ RETURN
+)
+
+fqmtr_list_all:
+(
+ GOSUB fqmtr_create_win
+
+ ;GOSUB fqmtr_query 0x1 &SRC_STR_1 0
+ ;GOSUB fqmtr_query 0x2 &SRC_STR_2 0
+ ;GOSUB fqmtr_query 0x3 &SRC_STR_3 0
+ ;GOSUB fqmtr_query 0x4 &SRC_STR_4 0
+ ;GOSUB fqmtr_query 0x5 &SRC_STR_5 0
+ ;GOSUB fqmtr_query 0x6 &SRC_STR_6 0
+ ;GOSUB fqmtr_query 0x7 &SRC_STR_7 0
+ ;GOSUB fqmtr_query 0x8 &SRC_STR_8 0
+ ;GOSUB fqmtr_query 0x9 &SRC_STR_9 0
+ GOSUB fqmtr_query 0xA &SRC_STR_10 0
+ GOSUB fqmtr_query 0xB &SRC_STR_11 0
+ GOSUB fqmtr_query 0xC &SRC_STR_12 0
+ GOSUB fqmtr_query 0xD &SRC_STR_13 0
+ GOSUB fqmtr_query 0xE &SRC_STR_14 0
+ GOSUB fqmtr_query 0xF &SRC_STR_15 0
+ GOSUB fqmtr_query 0x10 &SRC_STR_16 0
+ GOSUB fqmtr_query 0x11 &SRC_STR_17 0
+ GOSUB fqmtr_query 0x12 &SRC_STR_18 0
+ GOSUB fqmtr_query 0x13 &SRC_STR_19 0
+ GOSUB fqmtr_query 0x14 &SRC_STR_20 0
+ GOSUB fqmtr_query 0x15 &SRC_STR_21 0
+ GOSUB fqmtr_query 0x16 &SRC_STR_22 0
+ GOSUB fqmtr_query 0x17 &SRC_STR_23 0
+ GOSUB fqmtr_query 0x18 &SRC_STR_24 0
+ GOSUB fqmtr_query 0x19 &SRC_STR_25 0
+ GOSUB fqmtr_query 0x1A &SRC_STR_26 0
+ GOSUB fqmtr_query 0x1B &SRC_STR_27 0
+ GOSUB fqmtr_query 0x1C &SRC_STR_28 0
+ GOSUB fqmtr_query 0x1D &SRC_STR_29 0
+ GOSUB fqmtr_query 0x1E &SRC_STR_30 0
+ GOSUB fqmtr_query 0x1F &SRC_STR_31 0
+ RETURN
+)
+
+fqmtr_force_list_all:
+(
+ GOSUB fqmtr_create_win
+
+ LOCAL &original_reg
+ LOCAL &original_BPIPLLCTL1_reg
+
+ &original_reg=DATA.LONG(&mclass:(&pll_base+0x10))
+ &original_BPIPLLCTL1_reg=DATA.LONG(&mclass:(&pll_base+0x64))
+
+ ; S/W force on all PLL
+ Data.Set &mclass:(&pll_base+0x10) %LE %LONG 0xFFFFFFFF
+
+ ; S/W force on BPI_1 PLL
+ Data.Set &mclass:(&pll_base+0x64) %LE %LONG &original_BPIPLLCTL1_reg|(0x80)
+
+ WAIT 1.s
+
+ ;GOSUB fqmtr_query 0x1 &SRC_STR_1 0
+ ;GOSUB fqmtr_query 0x2 &SRC_STR_2 0
+ ;GOSUB fqmtr_query 0x3 &SRC_STR_3 0
+ ;GOSUB fqmtr_query 0x4 &SRC_STR_4 0
+ ;GOSUB fqmtr_query 0x5 &SRC_STR_5 0
+ ;GOSUB fqmtr_query 0x6 &SRC_STR_6 0
+ ;GOSUB fqmtr_query 0x7 &SRC_STR_7 0
+ ;GOSUB fqmtr_query 0x8 &SRC_STR_8 0
+ ;GOSUB fqmtr_query 0x9 &SRC_STR_9 0
+ GOSUB fqmtr_query 0xA &SRC_STR_10 0
+ GOSUB fqmtr_query 0xB &SRC_STR_11 0
+ GOSUB fqmtr_query 0xC &SRC_STR_12 0
+ GOSUB fqmtr_query 0xD &SRC_STR_13 0
+ GOSUB fqmtr_query 0xE &SRC_STR_14 0
+ GOSUB fqmtr_query 0xF &SRC_STR_15 0
+ GOSUB fqmtr_query 0x10 &SRC_STR_16 0
+ GOSUB fqmtr_query 0x11 &SRC_STR_17 0
+ GOSUB fqmtr_query 0x12 &SRC_STR_18 0
+ GOSUB fqmtr_query 0x13 &SRC_STR_19 0
+ GOSUB fqmtr_query 0x14 &SRC_STR_20 0
+ GOSUB fqmtr_query 0x15 &SRC_STR_21 0
+ GOSUB fqmtr_query 0x16 &SRC_STR_22 0
+ GOSUB fqmtr_query 0x17 &SRC_STR_23 0
+ GOSUB fqmtr_query 0x18 &SRC_STR_24 0
+ GOSUB fqmtr_query 0x19 &SRC_STR_25 0
+ GOSUB fqmtr_query 0x1A &SRC_STR_26 0
+ GOSUB fqmtr_query 0x1B &SRC_STR_27 0
+ GOSUB fqmtr_query 0x1C &SRC_STR_28 0
+ GOSUB fqmtr_query 0x1D &SRC_STR_29 0
+ GOSUB fqmtr_query 0x1E &SRC_STR_30 0
+ GOSUB fqmtr_query 0x1F &SRC_STR_31 0
+
+ ; Revert to original value
+ Data.Set &mclass:(&pll_base+0x10) %LE %LONG &original_reg
+ Data.Set &mclass:(&pll_base+0x64) %LE %LONG &original_BPIPLLCTL1_reg
+
+ WAIT 1.s
+
+ RETURN
+)
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/APview_MT6763_GPIO.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/APview_MT6763_GPIO.cmm
new file mode 100755
index 0000000..5fb1e14
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/APview_MT6763_GPIO.cmm
@@ -0,0 +1,19 @@
+// Step 8: Set GPIO
+
+&MEM_CLASS="AXI"
+&BASE_ADDR_MDGPIO=0x10005000
+;&BASE_ADDR_MDIOCFG=0x11C10000
+
+// MD UART GPIO
+D.S AXI:&BASE_ADDR_MDGPIO+0x318 %LE %LONG 0xFF00000 //Clear GPIO mode configure
+D.S AXI:&BASE_ADDR_MDGPIO+0x314 %LE %LONG 0x4400000 //Set GPIO13/14 to UART mode.
+D.S AXI:&BASE_ADDR_MDGPIO+0x64 %LE %LONG 0x01 //Set URXD Pull enable
+D.S AXI:&BASE_ADDR_MDGPIO+0x84 %LE %LONG 0x01 //Set URXD Pull up select.
+
+// SIM GPIO
+d.s &MEM_CLASS:0x10005340 %long %le data.long(&MEM_CLASS:0x10005340)&(0x00000FFF)
+d.s &MEM_CLASS:0x10005340 %long %le data.long(&MEM_CLASS:0x10005340)|(0x11111000)
+
+d.s &MEM_CLASS:0x10005350 %long %le data.long(&MEM_CLASS:0x10005350)&(0xFFFFFFF0)
+d.s &MEM_CLASS:0x10005350 %long %le data.long(&MEM_CLASS:0x10005350)|(0x00000001)
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/APview_MT6763_MD_ForceOnDebugSys.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/APview_MT6763_MD_ForceOnDebugSys.cmm
new file mode 100755
index 0000000..76a11e0
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/APview_MT6763_MD_ForceOnDebugSys.cmm
@@ -0,0 +1,10 @@
+;Core1 force on
+d.s &MEM_CLASS:0x200D0004 %long %le 0xB2002383
+;ForceOn debug sys
+d.s &MEM_CLASS:0x20150010 %long %le data.long(&MEM_CLASS:0x20150010)|(0x00080008)
+d.s &MEM_CLASS:0x200D04B0 %long %le data.long(&MEM_CLASS:0x200D04B0)|(0x00000008)
+&temp=data.long(&MEM_CLASS:0x200D0590)
+IF (&temp&0x8008)!=0x8008
+(
+ PRINT "Force on debug sys clock fail"
+)
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/APview_MT6763_MD_PLL_Init.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/APview_MT6763_MD_PLL_Init.cmm
new file mode 100755
index 0000000..6fc8389
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/APview_MT6763_MD_PLL_Init.cmm
@@ -0,0 +1,99 @@
+; /* Step 6 config PLL setting */
+;;==============================PLL init start==================================================
+;;sys.m prepare
+&MEM_CLASS="AXI"
+
+&BASE_MADDR_APMIXEDSYS=(0x1000C000)
+&BASE_MADDR_MDTOP_PLLMIXED=(0x20140000)
+&BASE_MADDR_MDTOP_CLKSW=(0x20150000)
+
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+®_MDTOP_PLLMIXED_MDTXPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x58)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+®_MDTOP_PLLMIXED_MDPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x100)
+®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+
+®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0x84)
+
+&MD_PLL_MAGIC_NUM=(0x62930000)
+
+;;// initial CLKSQ_LPF
+d.s &MEM_CLASS:®_APMIXEDSYS_AP_PLL_CON0 %long %le data.long(&MEM_CLASS:®_APMIXEDSYS_AP_PLL_CON0)|0x2
+;;// 100us
+wait 1.ms
+
+;;// Default md_srclkena_ack settle time = 136T 32K
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E88
+
+;;//fixed 600MHz(/4), 343MHz(/7), 267MHz(/9) /* Fvco = 2400M
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x801713B1
+;;/ 300MHz /* Fvco = 2400M */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDTXPLL_CTL0 %long %le 0x80171400
+;;// 400MHz /* Fvco = 3600M */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80229E00
+;;// 672MHz /* Fvco = 3360M */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x80204E00
+;;// 864MHz /* Fvco = 3456M */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x80213C00
+;;// 600MHz /* Fvco = 3456M */
+;d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x801713B1
+
+;;// Polling until MDMCUPLL complete frequency adjustment
+;WHILE (((data.long(&MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1))
+;(
+;)
+wait 1.ms
+
+;;// Default disable BPI /7 clock
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDBPIPLL_CTL1 %long %le data.long(&MEM_CLASS:®_MDTOP_PLLMIXED_MDBPIPLL_CTL1)&(~0x80)
+
+;;// TINFO="MDSYS_INIT: Update ABB MDPLL control register default value
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x4C43100
+
+;;// Force TXPLL ON due to TOPSM couldn't enable this PLL by default, TXPLL would be disable after DVFS Init.
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x100010
+
+;;// Wait MD bus clock ready,Once MD bus ready, other clock should be ready too
+;WHILE ((data.long(&MEM_CLASS:®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000)
+;(
+;)
+wait 2.ms
+
+;;// Switch MDMCU & MD BUS clock to PLL frequency
+d.s &MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL)|(0x3)
+
+;;// Switch all clock to PLL frequency
+d.s &MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL)|(0x58103FC)
+
+;;// Switch SDF clock to PLL frequency
+d.s &MEM_CLASS:®_MDTOP_CLKSW_SDF_CK_CTL %long %le data.long(&MEM_CLASS:®_MDTOP_CLKSW_SDF_CK_CTL)|(0x10)
+
+;;// Turn off all SW clock request, except ATB
+d.s &MEM_CLASS:®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+;;// Mask all PLL ADJ RDY IRQ
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+
+;;// Make a record that means MD pll has been initialized.
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+
+;;}
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/APview_MT6763_disable_WDT.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/APview_MT6763_disable_WDT.cmm
new file mode 100755
index 0000000..3e747f8
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/APview_MT6763_disable_WDT.cmm
@@ -0,0 +1,11 @@
+;/* Step 6 Disable MD/AP WDT */
+&MEM_CLASS="AXI"
+
+;&BASE_MADDR_MDRGU=0xA00F0000
+;&BASE_MADDR_APRGU=0xC0007000
+&BASE_MADDR_MDRGU=0x200F0000
+&BASE_MADDR_APRGU=0x10007000
+
+D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x0100 %LE %LONG (0x55000030)
+D.S &MEM_CLASS:&BASE_MADDR_APRGU %LE %LONG 0x22000064
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/APview_MT6763_md_srclkena.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/APview_MT6763_md_srclkena.cmm
new file mode 100755
index 0000000..178fc40
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/APview_MT6763_md_srclkena.cmm
@@ -0,0 +1,33 @@
+; /* Step 4 config md_srclkena setting */
+&MEM_CLASS="AXI"
+
+; /* (1) INFRA_MISC2 */
+&BASE_INFRACFG=(0x10000000)
+; /* (2) SRCLKEN_O1 force on */
+&SPM_REG=(0x10006000)
+
+
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(&BASE_INFRACFG+0x1F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+
+
+; /* (1) INFRA_MISC2 */
+; /* [3:0] : mdsrc_req_0_en = 4'b0001 */
+d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFFF0)
+d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x1)
+
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 */
+d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFF0F)
+d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x20)
+
+; /* (2) SRCLKEN_O1 force on */
+//MMRF request
+D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x00215830 //set src clkena1 force on
+
+wait 1.ms
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/Coretracer_MT6763_Frequency_Meter.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/Coretracer_MT6763_Frequency_Meter.cmm
new file mode 100755
index 0000000..2906ca7
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/Coretracer_MT6763_Frequency_Meter.cmm
@@ -0,0 +1,199 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; MT6763 MD Frequency Meter
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+
+;;;;;;;;;;;;;;;;;;;;;;;Below you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LOCAL &clksw_base ;; MD CLKSW base address
+&clksw_base=0xA0150000 ;; MD view APB
+;&clksw_base=0xA0096000 ;; MD view debug APB
+;&clksw_base=0x20150000 ;; AP view MD system bus
+;&clksw_base=0x0D0D6000 ;; AP view MD debug sys
+
+LOCAL &pll_base ;; MD PLLMIXED base address
+&pll_base=0xA0140000 ;; MD view APB
+;&pll_base=0xA0094000 ;; MD view debug APB
+;&pll_base=0x20140000 ;; AP view MD system bus
+;&pll_base=0x0D0D4000 ;; AP view MD debug sys
+
+&fqmtr_fcksel_32k_index=0x17
+
+;;;;;;;;;;;;;;;;;;;;;;;Above you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LOCAL &fqmtr_winset ;; Frequency Meter Windoiw Setting (= Number of FIXED clock cycle)
+&fqmtr_winset=0x1ff
+&fqmtr_winset_for_32k=0x1E000
+
+LOCAL &fqmtr_fcksel_val ;; Frequency Meter FIXED clock selection
+&fqmtr_fcksel_val=0x1a ;; Select 26Mhz by default
+
+&SRC_STR_10="TRACE_MON_clock"
+&SRC_STR_11="MDSYS_208M_clock"
+&SRC_STR_12="mdrxsys_rake_clock"
+&SRC_STR_13="mdrxsys_brp_clock"
+&SRC_STR_14="mdrxsys_vdsp_clock"
+&SRC_STR_15="mdtop_log_atb_clock"
+&SRC_STR_16="fesys_csys_clock"
+&SRC_STR_17="fesys_txsys_clock"
+&SRC_STR_18="fesys_bsi_clock"
+&SRC_STR_19="mdsys_mdcore_clock"
+&SRC_STR_20="mdsys_bus2x_nodcm_clock"
+&SRC_STR_21="mdsys_bus2x_clock"
+&SRC_STR_22="mdtop_dbg_clock"
+&SRC_STR_23="mdtop_f32k_clock"
+&SRC_STR_24="MDBPIPLL_0_DIV2_clock"
+&SRC_STR_25="MDBPIPLL_2_clock"
+&SRC_STR_26="MDBPIPLL_1_clock"
+&SRC_STR_27="MDBPIPLL_0_clock"
+&SRC_STR_28="MDTXPLL_clock"
+&SRC_STR_29="MDBRPPLL_clock"
+&SRC_STR_30="MDVDSPPLL_clock"
+&SRC_STR_31="MDMCUPLL_clock"
+
+LOCAL &idx
+LOCAL &str
+&idx = 0xA;
+&str = "TRACE_MON_clock"
+GOSUB fqmtr_query
+&idx = 0xB;
+&str = "MDSYS_208M_clock"
+GOSUB fqmtr_query
+&idx = 0xC;
+&str = "mdrxsys_rake_clock"
+GOSUB fqmtr_query
+&idx = 0xD;
+&str = "mdrxsys_brp_clock"
+GOSUB fqmtr_query
+&idx = 0xE;
+&str = "mdrxsys_vdsp_clock"
+GOSUB fqmtr_query
+&idx = 0xF;
+&str = "mdtop_log_atb_clock"
+GOSUB fqmtr_query
+&idx = 0x10;
+&str = "fesys_csys_clock"
+GOSUB fqmtr_query
+&idx = 0x11;
+&str = "fesys_txsys_clock"
+GOSUB fqmtr_query
+&idx = 0x12;
+&str = "fesys_bsi_clock"
+GOSUB fqmtr_query
+&idx = 0x13;
+&str = "mdsys_mdcore_clock"
+GOSUB fqmtr_query
+&idx = 0x14;
+&str = "mdsys_bus2x_nodcm_clock"
+GOSUB fqmtr_query
+&idx = 0x15;
+&str = "mdsys_bus2x_clock"
+GOSUB fqmtr_query
+&idx = 0x16;
+&str = "mdtop_dbg_clock"
+GOSUB fqmtr_query
+&idx = 0x17;
+&str = "mdtop_f32k_clock"
+GOSUB fqmtr_query
+&idx = 0x18;
+&str = "MDBPIPLL_0_DIV2_clock"
+GOSUB fqmtr_query
+&idx = 0x19;
+&str = "MDBPIPLL_2_clock"
+GOSUB fqmtr_query
+&idx = 0x1A;
+&str = "MDBPIPLL_1_clock"
+GOSUB fqmtr_query
+&idx = 0x1B;
+&str = "MDBPIPLL_0_clock"
+GOSUB fqmtr_query
+&idx = 0x1C;
+&str = "MDTXPLL_clock"
+GOSUB fqmtr_query
+&idx = 0x1D;
+&str = "MDBRPPLL_clock"
+GOSUB fqmtr_query
+&idx = 0x1E;
+&str = "MDVDSPPLL_clock"
+GOSUB fqmtr_query
+&idx = 0x1F;
+&str = "MDMCUPLL_clock"
+GOSUB fqmtr_query
+
+&idx = 0x20;
+
+;;;;;The main function to get the Frequency. &idx==> the clock you select, &str==> clock name, &info==>list more info and wait 5ms in the function
+;; &info=1 ==> for printing many PLLs at one time
+fqmtr_query:
+ LOCAL &unit
+ LOCAL &fqmtr_winset_26M
+ LOCAL &fqmtr_result
+ LOCAL &fqmtr_result_raw
+ LOCAL &safe_wait_cnt
+ LOCAL &safe_wait_cnt_max
+ LOCAL &mul_for_32k
+
+ &safe_wait_cnt=0
+ IF &idx==0x20
+ (
+ RETURN
+ )
+ ELSE
+ (
+ IF &fqmtr_fcksel_val==0x1a ;; base on 26M, unit:MHz
+ (
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &unit="Khz"
+ &fqmtr_winset_26M=&fqmtr_winset_for_32k
+ &safe_wait_cnt_max=500 ;;5000 ms = 5s ==> in real test, longer than 5s, so reduce it
+ &mul_for_32k=0x3E8
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &unit="Mhz"
+ &fqmtr_winset_26M=&fqmtr_winset
+ &safe_wait_cnt_max=32 ;;32 ms
+ &mul_for_32k=1
+ )
+ )
+
+ ;;div 8 and select src
+ Data.Set (&clksw_base+0x0104) %LE %LONG 0x0 ;reset frequency meter
+ Data.Set (&clksw_base+0x0100) %LE %LONG (0x0300)|(&idx)
+ Data.Set (&clksw_base+0x0108) %LE %LONG &fqmtr_winset_26M
+ Data.Set (&clksw_base+0x0104) %LE %LONG 0x1 ;enable frequency meter
+
+ ;; read status, to check polling done or not
+ &fqmtr_busy=DATA.LONG(&clksw_base+0x0104)&(1<<1)
+
+ WHILE &fqmtr_busy==0
+ (
+; PRINT ". &fqmtr_busy"
+ &fqmtr_busy=DATA.LONG(&clksw_base+0x0104)&(1<<1)
+ &safe_wait_cnt=&safe_wait_cnt+1
+ IF &safe_wait_cnt==&safe_wait_cnt_max
+ (
+ PRINT "[&str] Wait Fail, exit"
+ RETURN
+ )
+ ELSE
+ (
+; PRINT "Waiting result. safe_wait_cnt=" "&safe_wait_cnt"
+ )
+ WAIT 1000.us
+
+ )
+
+ ;; Calculate the result
+ &fqmtr_result_raw=DATA.LONG(&clksw_base+0x10c)
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*8*&mul_for_32k/(&fqmtr_winset_26M+3)
+ &fqmtr_result_dec=&fqmtr_result
+ &fqmtr_result_dec=FORMAT.DECIMAL( 0 , &fqmtr_result )
+
+ PRINT " &idx , &fqmtr_result_dec &unit , &str "
+
+ WAIT 1000.us
+
+ RETURN
+ )
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/MT6763_AP_Attach.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/MT6763_AP_Attach.cmm
new file mode 100755
index 0000000..ccd0067
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/MT6763_AP_Attach.cmm
@@ -0,0 +1,31 @@
+ print "[INFO][MAIN] Attach Target"
+ SYStem.Down
+
+ system.reset
+ SYSTEM.OPTION ENRESET OFF
+ SYStem.Option ResBreak OFF
+ SYStem.Option WaitReset OFF
+ SYStem.JtagClock 10.MHz
+
+ SYStem.CPU CORTEXA53;
+ ;Setting Core debug register access
+ SYStem.CONFIG CORENUMBER 1
+
+
+ SYStem.CONFIG COREBASE 0x8D410000 0x8D510000 0x8D610000 0x8D710000 0x8D810000 0x8D910000 0x8DA10000 0x8DB10000;
+ SYStem.CONFIG CTIBASE 0x8D420000 0x8D520000 0x8D620000 0x8D720000 0x8D820000 0x8D920000 0x8DA20000 0x8DB20000;
+
+ SYStem.CONFIG SWDP ON
+
+
+ SYStem.Attach
+ ON PBREAK GOSUB
+ (
+ print "[INFO][MAIN] Watchdog Disabled"
+ d.s c:0x10211000 %le %long 0x22000064
+
+ )
+ ;SETUP.IMASKHLL ON
+ ;SETUP.IMASKASM ON
+ STOP
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/MT6763_Android_scatter.txt b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/MT6763_Android_scatter.txt
new file mode 100755
index 0000000..51223e6
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/MT6763_Android_scatter.txt
@@ -0,0 +1,562 @@
+############################################################################################################
+#
+# General Setting
+#
+############################################################################################################
+- general: MTK_PLATFORM_CFG
+ info:
+ - config_version: V1.1.2
+ platform: MT6763
+ project: evb6763_64_ufs
+ storage: UFS
+ boot_channel: UFSHCI_0
+ block_size: 0x80000
+############################################################################################################
+#
+# Layout Setting
+#
+############################################################################################################
+- partition_index: SYS0
+ partition_name: preloader
+ file_name: preloader_evb6763_64_ufs_TINY.bin
+ is_download: true
+ type: SV5_BL_BIN
+ linear_start_addr: 0x0
+ physical_start_addr: 0x0
+ partition_size: 0x40000
+ region: UFS_LU0_LU1
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: BOOTLOADERS
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS1
+ partition_name: pgpt
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x0
+ physical_start_addr: 0x0
+ partition_size: 0x8000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS2
+ partition_name: boot_para
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x8000
+ physical_start_addr: 0x8000
+ partition_size: 0x100000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS3
+ partition_name: recovery
+ file_name: recovery.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x108000
+ physical_start_addr: 0x108000
+ partition_size: 0x1800000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS4
+ partition_name: para
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x1908000
+ physical_start_addr: 0x1908000
+ partition_size: 0x80000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS5
+ partition_name: expdb
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x1988000
+ physical_start_addr: 0x1988000
+ partition_size: 0x1400000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS6
+ partition_name: frp
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x2d88000
+ physical_start_addr: 0x2d88000
+ partition_size: 0x100000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS7
+ partition_name: nvcfg
+ file_name: NONE
+ is_download: false
+ type: EXT4_IMG
+ linear_start_addr: 0x2e88000
+ physical_start_addr: 0x2e88000
+ partition_size: 0x6400000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: PROTECTED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS8
+ partition_name: nvdata
+ file_name: NONE
+ is_download: false
+ type: EXT4_IMG
+ linear_start_addr: 0x9288000
+ physical_start_addr: 0x9288000
+ partition_size: 0x4000000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS9
+ partition_name: metadata
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0xd288000
+ physical_start_addr: 0xd288000
+ partition_size: 0x2000000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS10
+ partition_name: protect1
+ file_name: NONE
+ is_download: false
+ type: EXT4_IMG
+ linear_start_addr: 0xf288000
+ physical_start_addr: 0xf288000
+ partition_size: 0x800000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: PROTECTED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS11
+ partition_name: protect2
+ file_name: NONE
+ is_download: false
+ type: EXT4_IMG
+ linear_start_addr: 0xfa88000
+ physical_start_addr: 0xfa88000
+ partition_size: 0xd78000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: PROTECTED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS12
+ partition_name: seccfg
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x10800000
+ physical_start_addr: 0x10800000
+ partition_size: 0x800000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS13
+ partition_name: sec1
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x11000000
+ physical_start_addr: 0x11000000
+ partition_size: 0x200000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS14
+ partition_name: proinfo
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x11200000
+ physical_start_addr: 0x11200000
+ partition_size: 0x300000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: PROTECTED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS15
+ partition_name: md1img
+ file_name: md1rom.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x11500000
+ physical_start_addr: 0x11500000
+ partition_size: 0x4000000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS16
+ partition_name: md1dsp
+ file_name: md1dsp.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x15500000
+ physical_start_addr: 0x15500000
+ partition_size: 0x400000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS17
+ partition_name: md1arm7
+ file_name: md1arm7.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x15900000
+ physical_start_addr: 0x15900000
+ partition_size: 0x300000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS18
+ partition_name: md3img
+ file_name: md3rom.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x15c00000
+ physical_start_addr: 0x15c00000
+ partition_size: 0x500000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS19
+ partition_name: spmfw
+ file_name: spmfw.bin
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x16100000
+ physical_start_addr: 0x16100000
+ partition_size: 0x100000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS20
+ partition_name: nvram
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x16200000
+ physical_start_addr: 0x16200000
+ partition_size: 0x4000000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: BINREGION
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS21
+ partition_name: lk
+ file_name: lk.bin
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x1a200000
+ physical_start_addr: 0x1a200000
+ partition_size: 0x100000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: true
+ reserve: 0x00
+
+- partition_index: SYS22
+ partition_name: lk2
+ file_name: lk.bin
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x1a300000
+ physical_start_addr: 0x1a300000
+ partition_size: 0x100000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS23
+ partition_name: boot
+ file_name: boot.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x1a400000
+ physical_start_addr: 0x1a400000
+ partition_size: 0x1800000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS24
+ partition_name: logo
+ file_name: logo.bin
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x1bc00000
+ physical_start_addr: 0x1bc00000
+ partition_size: 0x800000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: false
+ empty_boot_needed: true
+ reserve: 0x00
+
+- partition_index: SYS25
+ partition_name: tee1
+ file_name: trustzone.bin
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x1c400000
+ physical_start_addr: 0x1c400000
+ partition_size: 0x500000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: true
+ reserve: 0x00
+
+- partition_index: SYS26
+ partition_name: tee2
+ file_name: trustzone.bin
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x1c900000
+ physical_start_addr: 0x1c900000
+ partition_size: 0x700000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS27
+ partition_name: system
+ file_name: system.img
+ is_download: true
+ type: EXT4_IMG
+ linear_start_addr: 0x1d000000
+ physical_start_addr: 0x1d000000
+ partition_size: 0xc0000000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS28
+ partition_name: cache
+ file_name: cache.img
+ is_download: true
+ type: EXT4_IMG
+ linear_start_addr: 0xdd000000
+ physical_start_addr: 0xdd000000
+ partition_size: 0x1b000000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS29
+ partition_name: userdata
+ file_name: userdata.img
+ is_download: true
+ type: EXT4_IMG
+ linear_start_addr: 0xf8000000
+ physical_start_addr: 0xf8000000
+ partition_size: 0xc0000000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS30
+ partition_name: flashinfo
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0xFFFF0020
+ physical_start_addr: 0xFFFF0020
+ partition_size: 0x1000000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: false
+ is_reserved: true
+ operation_type: RESERVED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS31
+ partition_name: sgpt
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0xFFFF0000
+ physical_start_addr: 0xFFFF0000
+ partition_size: 0x8000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: false
+ is_reserved: true
+ operation_type: RESERVED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/MT6763_EVB_ETT.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/MT6763_EVB_ETT.cmm
new file mode 100755
index 0000000..eb2a4a0
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/MT6763_EVB_ETT.cmm
@@ -0,0 +1,130 @@
+;*****************************************************************************
+; Copyright Statement:
+; --------------------
+; This software is protected by Copyright and the information contained
+; herein is confidential. The software may not be copied and the information
+; contained herein may not be used or disclosed except with the written
+; permission of MediaTek Inc. (C) 2011
+;
+;*****************************************************************************
+;;================================================
+;; PURPOSE: EVB Bring Up
+;; CREATE_DATE: 2016/04/01
+;; NOTE:
+;;================================================
+; Specify Core Number
+;=================================================
+
+&NR_CPUS=1
+; cluster 0 corebase: 0x8007000, 0x8007200, 0x8007400, 0x8007600
+; cluster 1 corebase: 0x8009000, 0x8009200, 0x8009400, 0x8009600
+
+;=================================================
+; Initialize CPU
+;=================================================
+&WDT_TEST=0
+if &WDT_TEST==0
+(
+ RESET
+ SYSTEM.OPTION ENRESET ON
+)
+
+SYSTEM.RESET
+SYSTEM.OPTION ENRESET ON
+SYSTEM.OPTION RESBREAK OFF
+SYSTEM.OPTION WAITRESET OFF
+
+SYSTEM.JTAGCLOCK 10.MHz;
+
+;SYSTEM.CPU CortexA7MPCore
+SYStem.CPU CORTEXA53;
+
+;R-T Memory Access
+SYSTEM.MULTICORE MEMORYACCESSPORT 0
+SYSTEM.MULTICORE DEBUGACCESSPORT 1
+
+;SYSTEM.MULTICORE COREBASE APB:0x80070000
+;Setting Core debug register access
+if &NR_CPUS==1
+(
+ SYStem.CONFIG CORENUMBER 1;
+ SYStem.CONFIG COREBASE 0x8D410000;
+ SYStem.CONFIG CTIBASE 0x8D420000;
+)
+else
+(
+ SYSTEM.CONFIG CORENUMBER 2;
+ SYSTEM.CONFIG COREBASE 0x80810000 0x80910000;
+ SYStem.CONFIG CTIBASE 0x80820000 0x80920000;
+)
+
+;=================================================
+; Attach and Stop CPU
+;=================================================
+SYStem.Up
+wait 200.us
+
+SETUP.IMASKHLL ON
+SETUP.IMASKASM ON
+
+;Disable acinactm
+;d.s c:0x1020002c %le %long 0x8
+;d.s c:0x1020022c %le %long 0x8
+
+
+
+;D.S SD:0x00000000 %LE %LONG 0xEAFFFFFE
+;D.S SD:0x10006000 %LE %LONG 0x0b160001
+;D.S SD:0x100062A0 %LE %LONG 0x7C
+;D.S SD:0x100062B0 %LE %LONG 0x7C
+
+
+;enable L2C 256KB
+D.S SD:0x102007F0 %LE %LONG 0x00010100 ;Enable L2C share SRAM (256K)
+D.S SD:0x102007F0 %LE %LONG 0x00010101 ;Enable L2C share SRAM (256K)
+
+
+
+
+; MSDC FPGA DTB: Card power(GPIO3), MSDC Bus 3.3V(GPIO2), MSDC Bus 1.8V(GPIO1) control
+; Set GPIO direction
+;D.S SD:0x10001E88 %LE %LONG 0xFF00
+; Set GPIO output value
+;D.S SD:0x10001E84 %LE %LONG 0x5500
+
+; set_hw_breakpoint_by_def
+; setting attribute of breakpoints
+Break.Select Program OnChip
+Break.Select Hll OnChip
+Break.Select Spot OnChip
+Break.Select Read OnChip
+Break.Select Write OnChip
+
+D.S C15:0x1 0 ; Turn off MMU
+
+; disable wdt (debug purpose)
+D.S SD:0x10007000 %LE %LONG 0x22000000
+
+; board init
+print "loading pre-loader image"
+d.load.elf ../../../../../../../../out/target/product/evb99v2_64_ufs/obj/PRELOADER_OBJ/bin/preloader_evb99v2_64_ufs.elf /long
+
+Y.SPATH.RESET ; reset all source path
+Y.SPATH.SRD ../../platform/mt6799/src/init
+Y.SPATH.SRD ../../platform/mt6799/src/core
+Y.SPATH.SRD ../../platform/mt6799/src/drivers
+Y.SPATH.SRD ../../platform/mt6799/src/security
+Y.SPATH.SRD ../../custom/evb99v2_64_ufs
+Y.SPATH.SRD ../../platform/common
+
+
+Break.Select Program OnChip
+Break.Select Hll OnChip
+Break.Select Spot OnChip
+Break.Select Read OnChip
+Break.Select Write OnChip
+
+R.S T 0
+;winclear
+d.l
+enddo
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/MT6763_EVB_LoadTinyPreloader.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/MT6763_EVB_LoadTinyPreloader.cmm
new file mode 100755
index 0000000..736b927
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/MT6763_EVB_LoadTinyPreloader.cmm
@@ -0,0 +1,113 @@
+;*****************************************************************************
+; Copyright Statement:
+; --------------------
+; This software is protected by Copyright and the information contained
+; herein is confidential. The software may not be copied and the information
+; contained herein may not be used or disclosed except with the written
+; permission of MediaTek Inc. (C) 2011
+;
+;*****************************************************************************
+;;================================================
+;; PURPOSE: EVB Bring Up
+;; CREATE_DATE: 2016/04/01
+;; NOTE:
+;;================================================
+; Specify Core Number
+;=================================================
+
+&NR_CPUS=1
+; cluster 0 corebase: 0x8007000, 0x8007200, 0x8007400, 0x8007600
+; cluster 1 corebase: 0x8009000, 0x8009200, 0x8009400, 0x8009600
+
+;=================================================
+; Initialize CPU
+;=================================================
+&WDT_TEST=0
+if &WDT_TEST==0
+(
+ RESET
+ SYSTEM.OPTION ENRESET ON
+)
+
+SYSTEM.RESET
+SYSTEM.OPTION ENRESET ON
+SYSTEM.OPTION RESBREAK OFF
+SYSTEM.OPTION WAITRESET OFF
+
+SYSTEM.JTAGCLOCK 10.MHz;
+
+;SYSTEM.CPU CortexA7MPCore
+SYStem.CPU CORTEXA53;
+
+;R-T Memory Access
+SYSTEM.MULTICORE MEMORYACCESSPORT 0
+SYSTEM.MULTICORE DEBUGACCESSPORT 1
+
+;SYSTEM.MULTICORE COREBASE APB:0x80070000
+;Setting Core debug register access
+if &NR_CPUS==1
+(
+ SYStem.CONFIG CORENUMBER 1;
+ SYStem.CONFIG COREBASE 0x8D410000;
+ SYStem.CONFIG CTIBASE 0x8D420000;
+)
+else
+(
+ SYSTEM.CONFIG CORENUMBER 2;
+ SYSTEM.CONFIG COREBASE 0x80810000 0x80910000;
+ SYStem.CONFIG CTIBASE 0x80820000 0x80920000;
+)
+
+;=================================================
+; Attach and Stop CPU
+;=================================================
+SYStem.CONFIG SWDP ON
+
+SYStem.Up
+wait 200.us
+
+SETUP.IMASKHLL ON
+SETUP.IMASKASM ON
+
+;enable L2C 256KB
+D.S SD:0x0C5307F0 %LE %LONG 0x00000100 ;Enable L2C share SRAM (256K)
+D.S SD:0x0C5307F0 %LE %LONG 0x00000101 ;Enable L2C share SRAM (256K)
+
+; set_hw_breakpoint_by_def
+; setting attribute of breakpoints
+Break.Select Program OnChip
+Break.Select Hll OnChip
+Break.Select Spot OnChip
+Break.Select Read OnChip
+Break.Select Write OnChip
+
+D.S C15:0x1 0 ; Turn off MMU
+
+; disable wdt (debug purpose)
+D.S SD:0x10007000 %LE %LONG 0x22000000
+
+; Init DRAM
+;do MT6763_FPGA_DDR
+
+print "loading pre-loader image"
+d.load.elf ./preloader_evb6763_64_ufs_TINY.elf
+
+Y.SPATH.RESET ; reset all source path
+Y.SPATH.SRD ../../platform/mt6763/src/init
+Y.SPATH.SRD ../../platform/mt6763/src/core
+Y.SPATH.SRD ../../platform/mt6763/src/drivers
+Y.SPATH.SRD ../../platform/mt6763/src/security
+Y.SPATH.SRD ../../platform/common
+Y.SPATH.SRD ../../custom/evb6763_64_ufs
+
+
+Break.Select Program OnChip
+Break.Select Hll OnChip
+Break.Select Spot OnChip
+Break.Select Read OnChip
+Break.Select Write OnChip
+
+R.S T 0
+;winclear
+d.l
+enddo
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/MT6763_EVB_Load_MD_Elf.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/MT6763_EVB_Load_MD_Elf.cmm
new file mode 100755
index 0000000..1aae914
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/MT6763_EVB_Load_MD_Elf.cmm
@@ -0,0 +1,365 @@
+;sys.m prepare
+;LOCAL &TYPE
+LOCAL &BASE_MADDR_MDRGU
+LOCAL &BASE_MADDR_APRGU
+
+
+system.mode attach
+
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+
+
+
+; do orginal disable_WDT2_MIPS.cmm
+&BASE_MADDR_MDRGU=0xA00F0000
+&BASE_MADDR_APRGU=0xC3670000
+
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG (0x55000000|data.long(&BASE_MADDR_MDRGU+0x0100)&~(0x3))
+&temp=data.long(&BASE_MADDR_MDRGU+0x0100)
+&temp=&temp | 0x55000000
+&temp=&temp & ~(0x3)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG &temp
+
+
+PRINT "=============================="
+PRINT "Disable AP WDT!"
+PRINT "=============================="
+
+D.S 0xC0007000 %LE %LONG 0x22000064
+
+
+
+PRINT "=============================="
+PRINT "config md_srclkena setting"
+PRINT "=============================="
+
+; /* Step 4 config md_srclkena setting */
+
+
+; /* (1) INFRA_MISC2 */
+&BASE_INFRACFG=(0xC0000000)
+; /* (2) SRCLKEN_O1 force on */
+&SPM_REG=(0xC0006000)
+
+
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(&BASE_INFRACFG+0x1F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+
+
+; /* (1) INFRA_MISC2 */
+; /* [3:0] : mdsrc_req_0_en = 4'b0001 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFFF0)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x1)
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFFF0)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x1)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFF0F)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x20)
+
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFF0F)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x20)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+; /* (2) SRCLKEN_O1 force on */
+//MMRF request
+;D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+;D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x00215830 //set src clkena1 force on
+D.S &POWERON_CONFIG_EN %LE %LONG 0x0B160001
+D.S &SPM_POWER_ON_VAL1 %LE %LONG 0x00215830
+
+wait 1.ms
+
+
+
+PRINT "=============================="
+PRINT "config PLL setting"
+PRINT "=============================="
+
+; /* Step 5 config PLL setting */
+&BASE_MADDR_APMIXEDSYS=(0xC000C000)
+&BASE_MADDR_MDTOP_PLLMIXED=(0xA0140000)
+&BASE_MADDR_MDTOP_CLKSW=(0xA0150000)
+
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+®_MDTOP_PLLMIXED_MDTXPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x58)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+®_MDTOP_PLLMIXED_MDPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x100)
+®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0x84)
+
+&MD_PLL_MAGIC_NUM=(0x62930000)
+
+;;// initial CLKSQ_LPF
+&temp=data.long(AXI:®_APMIXEDSYS_AP_PLL_CON0)
+&temp=&temp|0x2
+d.s ®_APMIXEDSYS_AP_PLL_CON0 %long %le &temp
+;;// 100us
+wait 1.ms
+
+;;// Default md_srclkena_ack settle time = 136T 32K
+d.s ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E88
+
+;;//fixed 600MHz(/4), 343MHz(/7), 267MHz(/9) /* Fvco = 2400M
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x801713B1
+;;/ 300MHz /* Fvco = 2400M */
+d.s ®_MDTOP_PLLMIXED_MDTXPLL_CTL0 %long %le 0x80171400
+;;// 400MHz /* Fvco = 3600M */
+d.s ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80229E00
+;;// 672MHz /* Fvco = 3360M */
+d.s ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x80204E00
+;;// 864MHz /* Fvco = 3456M */
+d.s ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x80213C00
+;;// 600MHz /* Fvco = 3456M */
+;d.s ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x801713B1
+
+;;// Polling until MDMCUPLL complete frequency adjustment
+;WHILE (((data.long(AXI:®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1))
+;(
+;)
+wait 1.ms
+
+;;// Default disable BPI /7 clock
+&temp=data.long(®_MDTOP_PLLMIXED_MDBPIPLL_CTL1)
+&temp=&temp&(~0x80)
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL1 %long %le &temp
+
+;;// TINFO="MDSYS_INIT: Update ABB MDPLL control register default value
+d.s ®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x4C43100
+
+;;// Force TXPLL ON due to TOPSM couldn't enable this PLL by default, TXPLL would be disable after DVFS Init.
+d.s ®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x100010
+
+;;// Wait MD bus clock ready,Once MD bus ready, other clock should be ready too
+;WHILE ((data.long(AXI:®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000)
+;(
+;)
+wait 2.ms
+
+;;// Switch MDMCU & MD BUS clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x3)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch all clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x58103FC)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch SDF clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_SDF_CK_CTL)
+&temp=&temp|(0x10)
+d.s ®_MDTOP_CLKSW_SDF_CK_CTL %long %le &temp
+
+;;// Turn off all SW clock request, except ATB
+d.s ®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+;;// Mask all PLL ADJ RDY IRQ
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+
+;;// Make a record that means MD pll has been initialized.
+d.s ®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+
+
+
+PRINT "=============================="
+PRINT "Set GPIO!"
+PRINT "=============================="
+
+// Step 8: Set GPIO
+
+&BASE_ADDR_MDGPIO=0xC0005000
+;&BASE_ADDR_MDIOCFG=0xC1C10000
+
+// MD UART GPIO
+;D.S AXI:&BASE_ADDR_MDGPIO+0x318 %LE %LONG 0xFF00000 //Clear GPIO mode configure
+;D.S AXI:&BASE_ADDR_MDGPIO+0x314 %LE %LONG 0x4400000 //Set GPIO13/14 to UART mode.
+;D.S AXI:&BASE_ADDR_MDGPIO+0x64 %LE %LONG 0x01 //Set URXD Pull enable
+;D.S AXI:&BASE_ADDR_MDGPIO+0x84 %LE %LONG 0x01 //Set URXD Pull up select.
+
+D.S &BASE_ADDR_MDGPIO+0x318 %LE %LONG 0xFF00000
+D.S &BASE_ADDR_MDGPIO+0x314 %LE %LONG 0x4400000
+D.S &BASE_ADDR_MDGPIO+0x64 %LE %LONG 0x01
+D.S &BASE_ADDR_MDGPIO+0x84 %LE %LONG 0x01
+
+
+
+// SIM GPIO
+;d.s &MEM_CLASS:0x10005340 %long %le data.long(&MEM_CLASS:0x10005340)&(0x00000FFF)
+;d.s &MEM_CLASS:0x10005340 %long %le data.long(&MEM_CLASS:0x10005340)|(0x11111000)
+
+&temp=data.long(0x10005340)
+&temp=&temp &(0x00000FFF)
+D.S 0x10005340 %LE %LONG &temp
+
+&temp=data.long(0x10005340)
+&temp=&temp |(0x11111000)
+D.S 0x10005340 %LE %LONG &temp
+
+
+
+;d.s &MEM_CLASS:0x10005350 %long %le data.long(&MEM_CLASS:0x10005350)&(0xFFFFFFF0)
+;d.s &MEM_CLASS:0x10005350 %long %le data.long(&MEM_CLASS:0x10005350)|(0x00000001)
+
+&temp=data.long(0x10005350)
+&temp=&temp &(0xFFFFFFF0)
+D.S 0x10005350 %LE %LONG &temp
+
+&temp=data.long(0x10005350)
+&temp=&temp |(0x00000001)
+D.S 0x10005350 %LE %LONG &temp
+
+
+
+PRINT "=============================="
+PRINT "Set MD EMI Remap!"
+PRINT "=============================="
+
+
+;Step 10 set MD EMI remap address (MD view: step 9) ==>review done
+;d.s &MEM_CLASS:0xC0001300 %long %le 0x00430041
+;d.s &MEM_CLASS:0xC0001304 %long %le 0x00470045
+;d.s &MEM_CLASS:0xC0001308 %long %le 0x004b0049
+;d.s &MEM_CLASS:0xC000130c %long %le 0x004b0049
+D.S 0xC0001300 %LE %LONG 0x00430041
+D.S 0xC0001304 %LE %LONG 0x00470045
+D.S 0xC0001308 %LE %LONG 0x004b0049
+D.S 0xC000130c %LE %LONG 0x004b0049
+
+
+
+; do orginal emi_init.cmm
+LOCAL &CHIP_VER ; 0 is for FPGA, 1 is for E1, and so on
+&CHIP_VER=0
+&BASE_ADDR_EMI=0xC3000000
+&BASE_ADDR_DRAMC=0xC3010000
+&BASE_ADDR_DDRPHY=0xC3020000
+&BASE_ADDR_MEMSYSAOREG_MISC=0xC3080000
+&BASE_ADDR_AP_CLKSW=0xC3750000
+
+; Check if initialize
+
+
+&temp=DATA.LONG(&BASE_ADDR_EMI+0060)
+&temp=&temp & 0x00000400
+IF (&temp == 0x00000400)
+(
+ ENDDO
+)
+
+
+
+PRINT "=============================="
+PRINT "Set AP2MD PATH Disable!"
+PRINT "=============================="
+
+; do AP to MD path disable
+&BASE_ADDR_AP2MD_Dummy = 0xC0001370
+&BASE_ADDR_INFRA_PERI2MD_PROT_EN = 0xC0001220
+&BASE_ADDR_INFRA_MD2PERI_PROT_EN = 0xC0001250
+
+
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp & 0xFFFFFFFE
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&BASE_ADDR_INFRA_PERI2MD_PROT_EN)
+&temp = &temp | 0x80
+D.S &BASE_ADDR_INFRA_PERI2MD_PROT_EN %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&BASE_ADDR_INFRA_MD2PERI_PROT_EN)
+&temp = &temp & 0xFFFFFFBF
+D.S &BASE_ADDR_INFRA_MD2PERI_PROT_EN %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp | 0x1
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+
+
+;Enalbe cache to speed loading
+register.set cdmmbase 0x1fc1407
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor adapter_khz 2000
+steal monitor mips32 fastchannel 0 1 0x6f800000
+
+
+PRINT "=============================="
+PRINT "Start to Load elf !"
+PRINT "=============================="
+
+thread.select 1
+steal lo
+
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+PRINT "=============================="
+PRINT "Load elf Done!"
+PRINT "=============================="
+
+thread.select 1
+
+;&t=var.address(INT_Initialize_Phase1)
+;wait 20.ms
+;stop
+;steal set $pc = &INT_Initialize_Phase1
+;register.set pc &t
+
+;PRINT "=============================="
+;PRINT "Set PC to INT_Initialize_Phase1: &t"
+;PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/MT6763_EVB_Load_MD_Elf_With_DSP.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/MT6763_EVB_Load_MD_Elf_With_DSP.cmm
new file mode 100755
index 0000000..271ff14
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/MT6763_EVB_Load_MD_Elf_With_DSP.cmm
@@ -0,0 +1,366 @@
+;sys.m prepare
+;LOCAL &TYPE
+LOCAL &BASE_MADDR_MDRGU
+LOCAL &BASE_MADDR_APRGU
+
+
+system.mode attach
+
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+
+
+
+; do orginal disable_WDT2_MIPS.cmm
+&BASE_MADDR_MDRGU=0xA00F0000
+&BASE_MADDR_APRGU=0xC3670000
+
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG (0x55000000|data.long(&BASE_MADDR_MDRGU+0x0100)&~(0x3))
+&temp=data.long(&BASE_MADDR_MDRGU+0x0100)
+&temp=&temp | 0x55000000
+&temp=&temp & ~(0x3)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG &temp
+
+
+PRINT "=============================="
+PRINT "Disable AP WDT!"
+PRINT "=============================="
+
+D.S 0xC0007000 %LE %LONG 0x22000064
+
+
+
+PRINT "=============================="
+PRINT "config md_srclkena setting"
+PRINT "=============================="
+
+; /* Step 4 config md_srclkena setting */
+
+
+; /* (1) INFRA_MISC2 */
+&BASE_INFRACFG=(0xC0000000)
+; /* (2) SRCLKEN_O1 force on */
+&SPM_REG=(0xC0006000)
+
+
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(&BASE_INFRACFG+0x1F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+
+
+; /* (1) INFRA_MISC2 */
+; /* [3:0] : mdsrc_req_0_en = 4'b0001 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFFF0)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x1)
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFFF0)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x1)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFF0F)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x20)
+
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFF0F)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x20)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+; /* (2) SRCLKEN_O1 force on */
+//MMRF request
+;D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+;D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x00215830 //set src clkena1 force on
+D.S &POWERON_CONFIG_EN %LE %LONG 0x0B160001
+D.S &SPM_POWER_ON_VAL1 %LE %LONG 0x00215830
+
+wait 1.ms
+
+
+
+PRINT "=============================="
+PRINT "config PLL setting"
+PRINT "=============================="
+
+; /* Step 5 config PLL setting */
+&BASE_MADDR_APMIXEDSYS=(0xC000C000)
+&BASE_MADDR_MDTOP_PLLMIXED=(0xA0140000)
+&BASE_MADDR_MDTOP_CLKSW=(0xA0150000)
+
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+®_MDTOP_PLLMIXED_MDTXPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x58)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+®_MDTOP_PLLMIXED_MDPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x100)
+®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0x84)
+
+&MD_PLL_MAGIC_NUM=(0x62930000)
+
+;;// initial CLKSQ_LPF
+&temp=data.long(AXI:®_APMIXEDSYS_AP_PLL_CON0)
+&temp=&temp|0x2
+d.s ®_APMIXEDSYS_AP_PLL_CON0 %long %le &temp
+;;// 100us
+wait 1.ms
+
+;;// Default md_srclkena_ack settle time = 136T 32K
+d.s ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E88
+
+;;//fixed 600MHz(/4), 343MHz(/7), 267MHz(/9) /* Fvco = 2400M
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x801713B1
+;;/ 300MHz /* Fvco = 2400M */
+d.s ®_MDTOP_PLLMIXED_MDTXPLL_CTL0 %long %le 0x80171400
+;;// 400MHz /* Fvco = 3600M */
+d.s ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80229E00
+;;// 672MHz /* Fvco = 3360M */
+d.s ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x80204E00
+;;// 864MHz /* Fvco = 3456M */
+d.s ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x80213C00
+;;// 600MHz /* Fvco = 3456M */
+;d.s ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x801713B1
+
+;;// Polling until MDMCUPLL complete frequency adjustment
+;WHILE (((data.long(AXI:®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1))
+;(
+;)
+wait 1.ms
+
+;;// Default disable BPI /7 clock
+&temp=data.long(®_MDTOP_PLLMIXED_MDBPIPLL_CTL1)
+&temp=&temp&(~0x80)
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL1 %long %le &temp
+
+;;// TINFO="MDSYS_INIT: Update ABB MDPLL control register default value
+d.s ®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x4C43100
+
+;;// Force TXPLL ON due to TOPSM couldn't enable this PLL by default, TXPLL would be disable after DVFS Init.
+d.s ®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x100010
+
+;;// Wait MD bus clock ready,Once MD bus ready, other clock should be ready too
+;WHILE ((data.long(AXI:®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000)
+;(
+;)
+wait 2.ms
+
+;;// Switch MDMCU & MD BUS clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x3)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch all clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x58103FC)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch SDF clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_SDF_CK_CTL)
+&temp=&temp|(0x10)
+d.s ®_MDTOP_CLKSW_SDF_CK_CTL %long %le &temp
+
+;;// Turn off all SW clock request, except ATB
+d.s ®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+;;// Mask all PLL ADJ RDY IRQ
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+
+;;// Make a record that means MD pll has been initialized.
+d.s ®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+
+
+
+PRINT "=============================="
+PRINT "Set GPIO!"
+PRINT "=============================="
+
+// Step 8: Set GPIO
+
+&BASE_ADDR_MDGPIO=0xC0005000
+;&BASE_ADDR_MDIOCFG=0xC1C10000
+
+// MD UART GPIO
+;D.S AXI:&BASE_ADDR_MDGPIO+0x318 %LE %LONG 0xFF00000 //Clear GPIO mode configure
+;D.S AXI:&BASE_ADDR_MDGPIO+0x314 %LE %LONG 0x4400000 //Set GPIO13/14 to UART mode.
+;D.S AXI:&BASE_ADDR_MDGPIO+0x64 %LE %LONG 0x01 //Set URXD Pull enable
+;D.S AXI:&BASE_ADDR_MDGPIO+0x84 %LE %LONG 0x01 //Set URXD Pull up select.
+
+D.S &BASE_ADDR_MDGPIO+0x318 %LE %LONG 0xFF00000
+D.S &BASE_ADDR_MDGPIO+0x314 %LE %LONG 0x4400000
+D.S &BASE_ADDR_MDGPIO+0x64 %LE %LONG 0x01
+D.S &BASE_ADDR_MDGPIO+0x84 %LE %LONG 0x01
+
+
+
+// SIM GPIO
+;d.s &MEM_CLASS:0x10005340 %long %le data.long(&MEM_CLASS:0x10005340)&(0x00000FFF)
+;d.s &MEM_CLASS:0x10005340 %long %le data.long(&MEM_CLASS:0x10005340)|(0x11111000)
+
+&temp=data.long(0x10005340)
+&temp=&temp &(0x00000FFF)
+D.S 0x10005340 %LE %LONG &temp
+
+&temp=data.long(0x10005340)
+&temp=&temp |(0x11111000)
+D.S 0x10005340 %LE %LONG &temp
+
+
+
+;d.s &MEM_CLASS:0x10005350 %long %le data.long(&MEM_CLASS:0x10005350)&(0xFFFFFFF0)
+;d.s &MEM_CLASS:0x10005350 %long %le data.long(&MEM_CLASS:0x10005350)|(0x00000001)
+
+&temp=data.long(0x10005350)
+&temp=&temp &(0xFFFFFFF0)
+D.S 0x10005350 %LE %LONG &temp
+
+&temp=data.long(0x10005350)
+&temp=&temp |(0x00000001)
+D.S 0x10005350 %LE %LONG &temp
+
+
+
+PRINT "=============================="
+PRINT "Set MD EMI Remap!"
+PRINT "=============================="
+
+
+;Step 10 set MD EMI remap address (MD view: step 9) ==>review done
+;d.s &MEM_CLASS:0xC0001300 %long %le 0x00430041
+;d.s &MEM_CLASS:0xC0001304 %long %le 0x00470045
+;d.s &MEM_CLASS:0xC0001308 %long %le 0x004b0049
+;d.s &MEM_CLASS:0xC000130c %long %le 0x004b0049
+D.S 0xC0001300 %LE %LONG 0x00430041
+D.S 0xC0001304 %LE %LONG 0x00470045
+D.S 0xC0001308 %LE %LONG 0x004b0049
+D.S 0xC000130c %LE %LONG 0x004b0049
+
+
+
+; do orginal emi_init.cmm
+LOCAL &CHIP_VER ; 0 is for FPGA, 1 is for E1, and so on
+&CHIP_VER=0
+&BASE_ADDR_EMI=0xC3000000
+&BASE_ADDR_DRAMC=0xC3010000
+&BASE_ADDR_DDRPHY=0xC3020000
+&BASE_ADDR_MEMSYSAOREG_MISC=0xC3080000
+&BASE_ADDR_AP_CLKSW=0xC3750000
+
+; Check if initialize
+
+
+&temp=DATA.LONG(&BASE_ADDR_EMI+0060)
+&temp=&temp & 0x00000400
+IF (&temp == 0x00000400)
+(
+ ENDDO
+)
+
+
+PRINT "=============================="
+PRINT "Set AP2MD PATH Disable!"
+PRINT "=============================="
+
+; do AP to MD path disable
+&BASE_ADDR_AP2MD_Dummy = 0xC0001370
+&BASE_ADDR_INFRA_PERI2MD_PROT_EN = 0xC0001220
+&BASE_ADDR_INFRA_MD2PERI_PROT_EN = 0xC0001250
+
+
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp & 0xFFFFFFFE
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&BASE_ADDR_INFRA_PERI2MD_PROT_EN)
+&temp = &temp | 0x80
+D.S &BASE_ADDR_INFRA_PERI2MD_PROT_EN %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&BASE_ADDR_INFRA_MD2PERI_PROT_EN)
+&temp = &temp & 0xFFFFFFBF
+D.S &BASE_ADDR_INFRA_MD2PERI_PROT_EN %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp | 0x1
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+
+
+;Enalbe cache to speed loading
+register.set cdmmbase 0x1fc1407
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor adapter_khz 2000
+steal monitor mips32 fastchannel 0 1 0x6f800000
+
+
+PRINT "=============================="
+PRINT "Start to Load elf !"
+PRINT "=============================="
+
+thread.select 1
+steal lo
+
+steal source ../cmm/coretracer\config\easyLoader\load_dsp.py
+
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+PRINT "=============================="
+PRINT "Load elf Done!"
+PRINT "=============================="
+
+thread.select 1
+
+;&t=var.address(INT_Initialize_Phase1)
+;wait 20.ms
+;stop
+;steal set $pc = &INT_Initialize_Phase1
+;register.set pc &t
+
+;PRINT "=============================="
+;PRINT "Set PC to INT_Initialize_Phase1: &t"
+;PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/MT6763_EVB_UART_Test.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/MT6763_EVB_UART_Test.cmm
new file mode 100755
index 0000000..7eb0795
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/MT6763_EVB_UART_Test.cmm
@@ -0,0 +1,32 @@
+;MT6763 MD_UART0 port test
+;You should make sure GPIO13 has connected to UART port RXD pin,GPIO14 has connected to UART port TXD pin
+
+;port: MDUART0
+;Baudrate: 115200
+&BASE_ADDR_MDUART0=0xA0010000
+&BASE_ADDR_MDGPIO=0xC0005000
+
+;&BASE_ADDR_MDUART0=0x20010000
+;&BASE_ADDR_MDGPIO=0x10005000
+
+
+D.S SD:&BASE_ADDR_MDGPIO+0x310 %LE %LONG 0x4400000 //set GPIO 13/14 to MDUART mode
+D.S SD:&BASE_ADDR_MDUART0+0x24 %LE %LONG 0x03 //High Speed X
+D.S SD:&BASE_ADDR_MDUART0+0x28 %LE %LONG 0xE1 //Sample count
+D.S SD:&BASE_ADDR_MDUART0+0x2C %LE %LONG 0x71 //sample point
+D.S SD:&BASE_ADDR_MDUART0+0x0C %LE %LONG 0x83 //Enable Divisor latch acess bit, and set 8bit length.
+D.S SD:&BASE_ADDR_MDUART0+0x00 %LE %LONG 0x01 //sample point
+D.S SD:&BASE_ADDR_MDUART0+0x04 %LE %LONG 0x00 //sample point
+D.S SD:&BASE_ADDR_MDUART0+0x0C %LE %LONG 0x03 //Clear Divisor latch acess bit, and set 8bit length.
+
+&uart_lsr=0x0
+&uart_rxd=0x0
+PRINT "Please put char "U" from PC to EVB UART! Note: ASCII "U" remap to HEX is 0x55 "
+WHILE (&uart_lsr&0x01)!=0x01
+(
+ &uart_lsr=data.long(sd:&BASE_ADDR_MDUART0+0x14)
+)
+&uart_rxd=data.long(sd:&BASE_ADDR_MDUART0+0x0)
+PRINT "EVB UART Get data: &uart_rxd"
+D.S SD:&BASE_ADDR_MDUART0+0x00 %LE %LONG &uart_rxd //Write data to UART, please check console.
+PRINT "EVB UART will send data to PC,please check!"
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/MT6763_MD_Only.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/MT6763_MD_Only.cmm
new file mode 100755
index 0000000..665264c
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/MT6763_MD_Only.cmm
@@ -0,0 +1,46 @@
+;AP pmic workaround
+&MEM_CLASS="AXI"
+sys.m prepare
+wait 1.ms
+
+; Step 1 set vcore to highest gear(0.8V)
+; [Note] CVD script do NOT need this step
+; skip
+
+; Step 2 config MD related Buck
+; AP preloader should set Modem related buck
+; Check with preloader/PMIC owner if not set
+; skip
+
+; Step 3 power on MTCMOS
+; do APview_MT6763_MTCMOS2.cmm
+; skip ==> cancelled since default on
+
+; Step 4 config md_srclkena setting ==> review done
+do APview_MT6763_md_srclkena.cmm
+
+; Step 5 config PLL setting ==> review done
+do APview_MT6763_MD_PLL_Init.cmm
+
+; Step 6 Disable MDWDT/APWDT ==> review done
+do APview_MT6763_disable_WDT.cmm
+
+; Step 7 Trigger MD MCU to run (AP view)
+; skip
+
+; Step 8 set GPIO (MD view: step 7)==> review done
+do APview_MT6763_GPIO.cmm
+
+;Step 9 Force on Debug Sys clock (MD view: step 8) ==> review done
+;do APview_MT6763_MD_ForceOnDebugSys.cmm
+
+;Step 10 set MD EMI remap address (MD view: step 9) ==>review done
+d.s &MEM_CLASS:0x10001300 %long %le 0x00430041
+d.s &MEM_CLASS:0x10001304 %long %le 0x00470045
+d.s &MEM_CLASS:0x10001308 %long %le 0x004b0049
+d.s &MEM_CLASS:0x1000130c %long %le 0x004f004d
+
+; Final Step: Trigger MD MCU to run
+; skip
+
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/L1Bypass.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/L1Bypass.act
new file mode 100755
index 0000000..a3c4b52
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/L1Bypass.act
@@ -0,0 +1,6 @@
+<?xml version="1.0"?>
+<Customize>
+ <Action name="L1AssertBypass" icon="">
+ <GDB>p/x L1_ASSERT_BYPASS=3</GDB>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/LoadDSPBin.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/LoadDSPBin.cmm
new file mode 100755
index 0000000..263524f
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/LoadDSPBin.cmm
@@ -0,0 +1,17 @@
+system.mode attach
+
+register.set cdmmbase 0x1fc1407
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor mips32 fastchannel 0 1
+
+&temp_addr = var.address(dsp_bin_ro)
+&temp_addr = &temp_addr & 0x0FFFFFFF
+;&temp_addr = &temp_addr | 0xA0000000
+
+data.load.bin U:\MT6292\UMOLYA\DEV\UMOLYA.BIANCO.BRINGUP.DEV\mcu\build\BIANCO_FPGA\L1S_L1DISABLE\bin\DSP_BIANCO_UMOLYA_BIANCO_BRINGUP_DEV_W17_04_LTE_P3.bin &temp_addr
+;data.load.bin "D:\dsp123.bin" &temp_addr
+
+print "load dsp done!"
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+enddo
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/L1Bypass.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/L1Bypass.act
new file mode 100755
index 0000000..a3c4b52
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/L1Bypass.act
@@ -0,0 +1,6 @@
+<?xml version="1.0"?>
+<Customize>
+ <Action name="L1AssertBypass" icon="">
+ <GDB>p/x L1_ASSERT_BYPASS=3</GDB>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_AllIn1_LoadCode.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_AllIn1_LoadCode.launch
new file mode 100755
index 0000000..1ed1ed7
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_AllIn1_LoadCode.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.cacheFile" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearExpression" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.LocalTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<intAttribute key="com.mediatek.ide.util.gdbPortNumber" value="3333"/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<stringAttribute key="com.mediatek.ide.util.ipAddress" value="localhost"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value="hb general_ex_handler"/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value="[CMMAUTOGEN_ROOT]"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="Bianco_evb"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_AllIn1_LoadCode_With_DSP.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_AllIn1_LoadCode_With_DSP.launch
new file mode 100755
index 0000000..034bc41
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_AllIn1_LoadCode_With_DSP.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.cacheFile" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearExpression" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.LocalTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<intAttribute key="com.mediatek.ide.util.gdbPortNumber" value="3333"/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<stringAttribute key="com.mediatek.ide.util.ipAddress" value="localhost"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value="hb general_ex_handler source ../cmm/coretracer/config/easyLoader/load_dsp.py"/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value="[CMMAUTOGEN_ROOT]"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="Bianco_evb"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_AllIn1_LoadCode_non_halt.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_AllIn1_LoadCode_non_halt.launch
new file mode 100755
index 0000000..1705989
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_AllIn1_LoadCode_non_halt.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.cacheFile" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearExpression" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.LocalTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<intAttribute key="com.mediatek.ide.util.gdbPortNumber" value="3333"/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<stringAttribute key="com.mediatek.ide.util.ipAddress" value="localhost"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value="[CMMAUTOGEN_ROOT]"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="Bianco_evb_non-halt"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
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diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_AllIn1_LoadSymbol.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_AllIn1_LoadSymbol.launch
new file mode 100755
index 0000000..bffd051
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_AllIn1_LoadSymbol.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
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diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_AllIn1_LoadSymbol_non_halt.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_AllIn1_LoadSymbol_non_halt.launch
new file mode 100755
index 0000000..149e65f
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_AllIn1_LoadSymbol_non_halt.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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diff --git "a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadCode\0501\051.launch" "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadCode\0501\051.launch"
new file mode 100755
index 0000000..9b7f6b9
--- /dev/null
+++ "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadCode\0501\051.launch"
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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diff --git "a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadCode\0502\051.launch" "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadCode\0502\051.launch"
new file mode 100755
index 0000000..ab8f269
--- /dev/null
+++ "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadCode\0502\051.launch"
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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diff --git "a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadCode\0503\051.launch" "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadCode\0503\051.launch"
new file mode 100755
index 0000000..78ab89a
--- /dev/null
+++ "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadCode\0503\051.launch"
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadCode.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadCode.launch
new file mode 100755
index 0000000..d895610
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadCode.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
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+<booleanAttribute key="com.mediatek.ide.util.cacheFile" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
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+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<intAttribute key="com.mediatek.ide.util.gdbPortNumber" value="3666"/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
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+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<stringAttribute key="com.mediatek.ide.util.ipAddress" value="localhost"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="true"/>
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+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
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+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value="hb general_ex_handler"/>
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+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadCode_All.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadCode_All.launch
new file mode 100755
index 0000000..d2c04d7
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadCode_All.launch
@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.group.launchConfigurationType">
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.name" value="MT6763_Alone_LoadCode"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.name" value="MT6763_Alone_LoadCode(1)"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.name" value="MT6763_Alone_LoadCode(2)"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.name" value="MT6763_Alone_LoadCode(3)"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadCode_All.launch.bak b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadCode_All.launch.bak
new file mode 100755
index 0000000..50aea16
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadCode_All.launch.bak
@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.group.launchConfigurationType">
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.name" value="BIANCO_Alone_LoadCode"/>
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+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.name" value="BIANCO_Alone_LoadCode(1)"/>
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+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.name" value="BIANCO_Alone_LoadCode(2)"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.enabled" value="true"/>
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+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.name" value="BIANCO_Alone_LoadCode(3)"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+</launchConfiguration>
diff --git "a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadSymbol\0501\051.launch" "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadSymbol\0501\051.launch"
new file mode 100755
index 0000000..9b7f6b9
--- /dev/null
+++ "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadSymbol\0501\051.launch"
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
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+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
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diff --git "a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadSymbol\0502\051.launch" "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadSymbol\0502\051.launch"
new file mode 100755
index 0000000..ab8f269
--- /dev/null
+++ "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadSymbol\0502\051.launch"
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
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+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="attach"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
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+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git "a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadSymbol\0503\051.launch" "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadSymbol\0503\051.launch"
new file mode 100755
index 0000000..78ab89a
--- /dev/null
+++ "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadSymbol\0503\051.launch"
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
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+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="attach"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadSymbol.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadSymbol.launch
new file mode 100755
index 0000000..7116e8c
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadSymbol.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.cacheFile" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearExpression" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.RemoteTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<intAttribute key="com.mediatek.ide.util.gdbPortNumber" value="3666"/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<stringAttribute key="com.mediatek.ide.util.ipAddress" value="localhost"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value="hb general_ex_handler"/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value="[CMMAUTOGEN_ROOT]"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="Bianco_evb_amp"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="attach"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadSymbol_All.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadSymbol_All.launch
new file mode 100755
index 0000000..3f9be8b
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadSymbol_All.launch
@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.group.launchConfigurationType">
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.name" value="MT6763_Alone_LoadSymbol"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.name" value="MT6763_Alone_LoadSymbol(1)"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.name" value="MT6763_Alone_LoadSymbol(2)"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.name" value="MT6763_Alone_LoadSymbol(3)"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadSymbol_All.launch.bak b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadSymbol_All.launch.bak
new file mode 100755
index 0000000..947d068
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/MT6763_Alone_LoadSymbol_All.launch.bak
@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.group.launchConfigurationType">
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.name" value="BIANCO_Alone_LoadSymbol"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.name" value="BIANCO_Alone_LoadSymbol(1)"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.name" value="BIANCO_Alone_LoadSymbol(2)"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.name" value="BIANCO_Alone_LoadSymbol(3)"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/easyLoader/CoreTracer_easy_loader.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/easyLoader/CoreTracer_easy_loader.py
new file mode 100755
index 0000000..cc2c2fe
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/easyLoader/CoreTracer_easy_loader.py
@@ -0,0 +1,149 @@
+#from imgtec import codescape
+import sys
+import time
+import os
+import gdb
+import Tkinter, tkFileDialog
+
+#get full path of python script
+file_path = os.path.dirname(os.path.abspath(__file__))
+#append python path into system path
+sys.path.append(file_path)
+
+import load_dsp
+
+app = None
+
+# load all elf
+def load_all_elf(elf_path):
+ time_str = time.time()
+ print "=== Start Loading ELF ==="
+ print "Image path: " + elf_path
+ if(os.path.exists(elf_path) == False):
+ print "[Error] UMOLY ELF doesn't exist: %s" %(elf_path)
+ else:
+ elf_path = elf_path.replace('\\', '/')
+ gdb_cmd = 'symbol-file '+ elf_path
+ print gdb_cmd
+ gdb.execute(gdb_cmd)
+ print "Load SYMBOL successfully"
+ # Add debug point
+ gdb_cmd = 'hb general_ex_vector'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'lo '+ elf_path
+ print gdb_cmd
+ gdb.execute(gdb_cmd)
+ print "Load ELF successfully"
+ time_end = time.time()
+ print("All loading is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+# load all symbol only
+def load_all_sym(elf_path):
+ time_str = time.time()
+ print "=== Start Loading SYMBOL ==="
+ print "Image path: " + elf_path
+ if(os.path.exists(elf_path) == False):
+ print "[Error] UMOLY ELF doesn't exist: %s" %(elf_path)
+ else:
+ elf_path = elf_path.replace('\\', '/')
+ gdb_cmd = 'symbol-file '+ elf_path
+ print gdb_cmd
+ gdb.execute(gdb_cmd)
+ print "Load SYMBOL successfully"
+ # Add debug point
+ gdb_cmd = 'hb general_ex_vector'
+ gdb.execute(gdb_cmd)
+ time_end = time.time()
+ print("All loading is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+# load dsp bin file
+#def load_dsp_bin(dsp_path):
+# time_str = time.time()
+# print "=== Start load dsp bin ==="
+# print "Dsp bin path: " + dsp_path
+# if(os.path.exists(dsp_path) == False):
+# print "[Error] UMOLY DSP binary doesn't exist: %s" %(dsp_path)
+# else:
+# gdb_cmd='thread 1'
+# gdb.execute(gdb_cmd)
+# ## a) need parsing: 0x13a0000 <dsp_bin_ro>
+# ##symbol_name='&dsp_bin_ro'
+# ##dsp_addr = gdb.parse_and_eval(symbol_name)
+# ## b) need parsing: $3 = 0x13a0000
+# ##gdb_cmd='p/x &dsp_bin_ro'
+# ##dsp_addr = gdb.execute(gdb_cmd, False, True)
+# symbol_name='dsp_bin_ro'
+# dsp_addr = gdb.parse_and_eval(symbol_name)
+# dsp_addr = str(dsp_addr.address).split(" ")
+# gdb_cmd = 'restore ' + dsp_path + ' binary ' + str(dsp_addr[0])
+# print gdb_cmd
+# gdb.execute(gdb_cmd)
+# time_end = time.time()
+# print("loading dsp is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+def thread_memory_Write(mem_addr, set_value):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def thread_memory_Read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ mem_value = mem_value[12:23]
+ hex_int = int(mem_value, 16)
+ return hex_int
+
+
+class gui_tk(Tkinter.Tk):
+ def __init__(self, parent):
+ Tkinter.Tk.__init__(self, parent)
+ elf_path = ""
+ dsp_path = ""
+ dsp_addr = ""
+ self.file_opt = options = {}
+ options['title'] = 'Choose a file'
+ self.parent = parent
+ self.initialize()
+
+ def initialize(self):
+ self.grid()
+ elf_button = Tkinter.Button(self, text=u"Load elf", command=self.elf_OnButtonClick)
+ elf_button.grid(column=0, row=1, sticky='W')
+
+ sym_button = Tkinter.Button(self, text=u"Load symbol", command=self.sym_OnButtonClick)
+ sym_button.grid(column=0, row=2, sticky='W')
+
+ dsp_button = Tkinter.Button(self, text=u"Load DSP bin", command=self.dsp_OnButtonClick)
+ dsp_button.grid(column=0, row=3, sticky='W')
+
+ def elf_OnButtonClick(self):
+ elf_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(elf_path) > 0:
+ print "You chose %s" % elf_path
+ load_all_elf(elf_path)
+ self.quit()
+
+ def sym_OnButtonClick(self):
+ elf_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(elf_path) > 0:
+ print "You chose %s" % elf_path
+ load_all_sym(elf_path)
+ self.quit()
+
+ def dsp_OnButtonClick(self):
+ dsp_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(dsp_path) > 0:
+ print "You chose %s" % dsp_path
+ load_dsp.load_dsp_bin(dsp_path)
+ self.quit()
+
+ def quit(self):
+ global app
+ print "=== Close Easy Loader ==="
+ app.destroy()
+
+if __name__ == "__main__":
+ print "=== Start Easy Loader ==="
+ app = gui_tk(None)
+ app.title('Easy Loader')
+ app.mainloop()
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/easyLoader/load_dsp.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/easyLoader/load_dsp.py
new file mode 100755
index 0000000..86e47fa
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/coretracer/config/easyLoader/load_dsp.py
@@ -0,0 +1,106 @@
+#from imgtec import codescape
+import sys
+import time
+import os
+import gdb
+import binascii
+import Tkinter, tkFileDialog
+
+app = None
+dsp_header = 0x0
+dsp_magic = "4d4d4d01"
+
+# load dsp bin file
+def load_dsp_bin(dsp_path):
+ global dsp_header
+ time_str = time.time()
+ print "=== Start load dsp bin ==="
+ print "Dsp bin path: " + dsp_path
+ if(os.path.exists(dsp_path) == False):
+ print "DSP bin doesn't exist: %s" %(dsp_path)
+ print "[Error] Load DSP bin failed"
+ return
+ else:
+ with open(dsp_path, "rb") as dsp_bin:
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print "No header detected, continue"
+ else:
+ dsp_header = 0x200
+ dsp_bin.seek(dsp_header, os.SEEK_SET)
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print "Header detected, skip first 512B"
+ else:
+ print "DSP header detected at neither 0x0 nor 0x200"
+ print "Please check the bin is legal!"
+ print "[Error] Load DSP bin failed"
+ return
+ gdb_cmd='thread 1'
+ gdb.execute(gdb_cmd)
+ ## a) need parsing: 0x13a0000 <dsp_bin_ro>
+ ##symbol_name='&dsp_bin_ro'
+ ##dsp_addr = gdb.parse_and_eval(symbol_name)
+ ## b) need parsing: $3 = 0x13a0000
+ ##gdb_cmd='p/x &dsp_bin_ro'
+ ##dsp_addr = gdb.execute(gdb_cmd, False, True)
+ symbol_name='dsp_bin_ro'
+ dsp_addr = gdb.parse_and_eval(symbol_name)
+ dsp_addr = str(dsp_addr.address).split(" ")
+ dsp_addr = int(dsp_addr[0], 16) - dsp_header
+ print hex(dsp_addr)
+ gdb_cmd = 'monitor mips32 fastchannel 0 1'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'set $cdmmbase=0x1fc1407'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'set *0x1fc100d4=0x02030202'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = " ".join(['restore', dsp_path, 'binary', hex(dsp_addr), hex(dsp_header)])
+ print gdb_cmd
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'set *0x1fc100d4=0x02020202'
+ gdb.execute(gdb_cmd)
+ time_end = time.time()
+ print("loading dsp is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+
+class gui_tk(Tkinter.Tk):
+ def __init__(self, parent):
+ Tkinter.Tk.__init__(self, parent)
+ elf_path = ""
+ dsp_path = ""
+ dsp_addr = ""
+ self.file_opt = options = {}
+ options['title'] = 'Choose a file'
+ self.parent = parent
+ self.initialize()
+
+ def initialize(self):
+ self.grid()
+
+ dsp_button = Tkinter.Button(self, text=u"Load DSP bin =>", command=self.dsp_OnButtonClick)
+ dsp_button.grid(column=0, row=4, sticky='W')
+
+ def dsp_OnButtonClick(self):
+ dsp_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(dsp_path) > 0:
+ print "You chose %s" % dsp_path
+ load_dsp_bin(dsp_path)
+ self.quit()
+
+ def quit(self):
+ global app
+ print "=== Close Easy Loader ==="
+ app.destroy()
+
+def load_dsp_gui():
+ print "=== Start Easy Loader ==="
+ global app
+ app = gui_tk(None)
+ app.title('Easy Loader')
+ app.mainloop()
+
+
+if __name__ == "__main__":
+ load_dsp_gui()
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/preloader_evb6763_64_ufs_TINY.bin b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/preloader_evb6763_64_ufs_TINY.bin
new file mode 100755
index 0000000..eea49c8
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/preloader_evb6763_64_ufs_TINY.bin
Binary files differ
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/preloader_evb6763_64_ufs_TINY.elf b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/preloader_evb6763_64_ufs_TINY.elf
new file mode 100755
index 0000000..76b0192
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6763/preloader_evb6763_64_ufs_TINY.elf
Binary files differ
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APView_MT6765_EVB_UART_Test.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APView_MT6765_EVB_UART_Test.cmm
new file mode 100644
index 0000000..a98a771
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APView_MT6765_EVB_UART_Test.cmm
@@ -0,0 +1,38 @@
+;Cervino MD_UART0 port test
+;You should make sure GPIO150 has connected to UART port RXD pin,GPIO151 has connected to UART port TXD pin
+
+;port: MDUART0
+;Baudrate: 115200
+;&BASE_ADDR_MDUART0=0xB0010000
+sys.m prepare
+&BASE_ADDR_MDUART0=0x20010000
+&BASE_ADDR_MDGPIO=0x10005000
+&BASE_ADDR_IOCFG=0x10002600
+
+D.S AXI:&BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x420)&(0x00FFFFFF)
+D.S AXI:&BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x420)|(0x55000000) //set GPIO150 to MD_URXD0 mode,set GPIO151 to MD_UTXD0 mode,
+
+D.S AXI:&BASE_ADDR_IOCFG+0x60 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x60)&(0xFF7FFFFF) //MD_URXD0 pull dowm disable
+D.S AXI:&BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)|(0x800000) //MD_URXD0 pull up enable
+D.S AXI:&BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)&(0xFEFFFFFF) //MD_UTXD0 pull up disable
+
+
+D.S AXI:&BASE_ADDR_MDUART0+0x24 %LE %LONG 0x03 //High Speed X
+D.S AXI:&BASE_ADDR_MDUART0+0x28 %LE %LONG 0xE1 //Sample count
+D.S AXI:&BASE_ADDR_MDUART0+0x2C %LE %LONG 0x71 //sample point
+D.S AXI:&BASE_ADDR_MDUART0+0x0C %LE %LONG 0x83 //Enable Divisor latch acess bit, and set 8bit length.
+D.S AXI:&BASE_ADDR_MDUART0+0x00 %LE %LONG 0x01 //sample point
+D.S AXI:&BASE_ADDR_MDUART0+0x04 %LE %LONG 0x00 //sample point
+D.S AXI:&BASE_ADDR_MDUART0+0x0C %LE %LONG 0x03 //Clear Divisor latch acess bit, and set 8bit length.
+
+&uart_lsr=0x0
+&uart_rxd=0x0
+PRINT "Please put char "U" from PC to EVB UART! Note: ASCII "U" remap to HEX is 0x55 "
+WHILE (&uart_lsr&0x01)!=0x01
+(
+ &uart_lsr=data.long(AXI:&BASE_ADDR_MDUART0+0x14)
+)
+&uart_rxd=data.long(AXI:&BASE_ADDR_MDUART0+0x0)
+PRINT "EVB UART Get data: &uart_rxd"
+D.S AXI:&BASE_ADDR_MDUART0+0x00 %LE %LONG &uart_rxd //Write data to UART, please check console.
+PRINT "EVB UART will send data to PC,please check!"
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_AP2MD_enable.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_AP2MD_enable.cmm
new file mode 100644
index 0000000..5a5e6e5
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_AP2MD_enable.cmm
@@ -0,0 +1,31 @@
+&MEM_CLASS="AXI"
+; do AP to MD path disable
+LOCAL &BASE_ADDR_AP2MD_Dummy
+LOCAL &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN
+LOCAL &temp
+
+&BASE_ADDR_AP2MD_Dummy=0x10001370
+&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN=0x100012A0
+
+; Set peri2md_protect_en
+; Write 0x1000_12A0[7] = 1'b1.
+; MD can access AP if reg_ap2md_dummy[0] = 1'b1,
+&temp=data.long(&MEM_CLASS:(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0x0))|0x80
+;PRINT "temp=" "&temp"
+;PRINT "&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0x0"
+D.S &MEM_CLASS:(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0x0) %LE %LONG &temp
+
+; Clear md2peri_protect_en
+; Write 0x1000_12AC[6] = 1'b1.
+&temp=data.long(&MEM_CLASS:(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC))|0x40
+;PRINT "temp=" "&temp"
+;PRINT "(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC)"
+D.S &MEM_CLASS:(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC) %LE %LONG &temp
+wait 1.ms
+
+; Set reg_ap2md_dummy[0] = 1'b1
+&temp=data.long(&MEM_CLASS:(&BASE_ADDR_AP2MD_Dummy+0x0))|0x1
+;PRINT "temp=" "&temp"
+;PRINT "BASE_ADDR_AP2MD_Dummy=" "&BASE_ADDR_AP2MD_Dummy"
+D.S &MEM_CLASS:(&BASE_ADDR_AP2MD_Dummy+0x0) %LE %LONG &temp
+wait 1.ms
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_Frequency_Meter.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_Frequency_Meter.cmm
new file mode 100644
index 0000000..3a080ac
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_Frequency_Meter.cmm
@@ -0,0 +1,535 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; SYLVIA MD Frequency Meter
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;;Select PLL
+LOCAL &key_in
+&key_in=0
+
+LOCAL &opt_cvd_connect
+&opt_cvd_connect="debug"
+
+;;;;;;;;;;;;;;;;;;;;;;;Below you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+LOCAL &mclass ;; Memory Class
+&mclass="axi"
+;&mclass="pm"
+
+LOCAL &clksw_base ;; MD CLKSW base address
+;&clksw_base=0xA0150000 ;; MD view APB
+;&clksw_base=0xA0096000 ;; MD view debug APB
+&clksw_base=0x20150000 ;; AP view MD system bus
+;&clksw_base=0x0D0D6000 ;; AP view MD debug sys
+
+LOCAL &pll_base ;; MD PLLMIXED base address
+;&pll_base=0xA0140000 ;; MD view APB
+;&pll_base=0xA0094000 ;; MD view debug APB
+&pll_base=0x20140000 ;; AP view MD system bus
+;&pll_base=0x0D0D4000 ;; AP view MD debug sys
+
+&fqmtr_fcksel_32k_index=0x17
+;;;;;;;;;;;;;;;;;;;;;;;Above you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LOCAL &fqmtr_winset ;; Frequency Meter Windoiw Setting (= Number of FIXED clock cycle)
+&fqmtr_winset=0x1ff
+&fqmtr_winset_for_32k=0x1E000
+
+LOCAL &fqmtr_fcksel_val ;; Frequency Meter FIXED clock selection
+&fqmtr_fcksel_val=0x1a ;; Select 26Mhz by default
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;All the PLL you could select;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+&SRC_STR_1="Reserved"
+&SRC_STR_2="Reserved"
+&SRC_STR_3="Reserved"
+&SRC_STR_4="Reserved"
+&SRC_STR_5="Reserved"
+&SRC_STR_6="Reserved"
+&SRC_STR_7="Reserved"
+&SRC_STR_8="Reserved"
+&SRC_STR_9="Reserved"
+&SRC_STR_10="TRACE_MON_clock"
+&SRC_STR_11="MDSYS_208M_clock"
+&SRC_STR_12="mdrxsys_rake_clock"
+&SRC_STR_13="mdrxsys_brp_clock"
+&SRC_STR_14="mdrxsys_vdsp_clock"
+&SRC_STR_15="mdtop_log_atb_clock"
+&SRC_STR_16="fesys_csys_clock"
+&SRC_STR_17="fesys_txsys_clock"
+&SRC_STR_18="fesys_bsi_clock"
+&SRC_STR_19="mdsys_mdcore_clock"
+&SRC_STR_20="mdsys_bus2x_nodcm_clock"
+&SRC_STR_21="mdsys_bus2x_clock"
+&SRC_STR_22="mdtop_dbg_clock"
+&SRC_STR_23="mdtop_f32k_clock"
+&SRC_STR_24="MDBPIPLL_0_DIV2_clock"
+&SRC_STR_25="MDBPIPLL_2_clock"
+&SRC_STR_26="MDBPIPLL_1_clock"
+&SRC_STR_27="MDBPIPLL_0_clock"
+&SRC_STR_28="MDTXPLL_clock"
+&SRC_STR_29="MDBRPPLL_clock"
+&SRC_STR_30="MDVDSPPLL_clock"
+&SRC_STR_31="MDMCUPLL_clock"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+DIALOG
+(&
+ HEADER "PLL Frequency Meter"
+ ICON ":chip"
+
+ POS 0. 0. 20. 1.
+ LINE "FQMTR Selection"
+ ; x y w h
+ POS 0. 1. 20. 1.
+ SEL.NONE: CHOOSEBOX "None"
+ (
+ &key_in=0x00
+ )
+;; SEL.1: CHOOSEBOX "&SRC_STR_1"
+;; (
+;; &key_in=0x1
+;; &key_str="&SRC_STR_1"
+;; )
+;; SEL.2: CHOOSEBOX "&SRC_STR_2"
+;; (
+;; &key_in=0x2
+;; &key_str="&SRC_STR_2"
+;; )
+;; SEL.3: CHOOSEBOX "&SRC_STR_3"
+;; (
+;; &key_in=0x3
+;; &key_str="&SRC_STR_3"
+;; )
+;; SEL.4: CHOOSEBOX "&SRC_STR_4"
+;; (
+;; &key_in=0x4
+;; &key_str="&SRC_STR_4"
+;; )
+;; SEL.5: CHOOSEBOX "&SRC_STR_5"
+;; (
+;; &key_in=0x5
+;; &key_str="&SRC_STR_5"
+;; )
+;; SEL.6: CHOOSEBOX "&SRC_STR_6"
+;; (
+;; &key_in=0x6
+;; &key_str="&SRC_STR_6"
+;; )
+;; SEL.7: CHOOSEBOX "&SRC_STR_7"
+;; (
+;; &key_in=0x7
+;; &key_str="&SRC_STR_7"
+;; )
+;; SEL.8: CHOOSEBOX "&SRC_STR_8"
+;; (
+;; &key_in=0x8
+;; &key_str="&SRC_STR_8"
+;; )
+;; SEL.9: CHOOSEBOX "&SRC_STR_9"
+;; (
+;; &key_in=0x9
+;; &key_str="&SRC_STR_9"
+;; )
+ SEL.10: CHOOSEBOX "&SRC_STR_10"
+ (
+ &key_in=0xA
+ &key_str="&SRC_STR_10"
+ )
+ SEL.11: CHOOSEBOX "&SRC_STR_11"
+ (
+ &key_in=0xB
+ &key_str="&SRC_STR_11"
+ )
+ SEL.12: CHOOSEBOX "&SRC_STR_12"
+ (
+ &key_in=0xC
+ &key_str="&SRC_STR_12"
+ )
+ SEL.13: CHOOSEBOX "&SRC_STR_13"
+ (
+ &key_in=0xD
+ &key_str="&SRC_STR_13"
+ )
+ SEL.14: CHOOSEBOX "&SRC_STR_14"
+ (
+ &key_in=0xE
+ &key_str="&SRC_STR_14"
+ )
+ SEL.15: CHOOSEBOX "&SRC_STR_15"
+ (
+ &key_in=0xF
+ &key_str="&SRC_STR_15"
+ )
+ SEL.16: CHOOSEBOX "&SRC_STR_16"
+ (
+ &key_in=0x10
+ &key_str="&SRC_STR_16"
+ )
+ SEL.17: CHOOSEBOX "&SRC_STR_17"
+ (
+ &key_in=0x11
+ &key_str="&SRC_STR_17"
+ )
+ SEL.18: CHOOSEBOX "&SRC_STR_18"
+ (
+ &key_in=0x12
+ &key_str="&SRC_STR_18"
+ )
+ SEL.19: CHOOSEBOX "&SRC_STR_19"
+ (
+ &key_in=0x13
+ &key_str="&SRC_STR_19"
+ )
+ SEL.20: CHOOSEBOX "&SRC_STR_20"
+ (
+ &key_in=0x14
+ &key_str="&SRC_STR_20"
+ )
+ SEL.21: CHOOSEBOX "&SRC_STR_21"
+ (
+ &key_in=0x15
+ &key_str="&SRC_STR_21"
+ )
+ SEL.22: CHOOSEBOX "&SRC_STR_22"
+ (
+ &key_in=0x16
+ &key_str="&SRC_STR_22"
+ )
+ SEL.23: CHOOSEBOX "&SRC_STR_23"
+ (
+ &key_in=0x17
+ &key_str="&SRC_STR_23"
+ )
+ SEL.24: CHOOSEBOX "&SRC_STR_24"
+ (
+ &key_in=0x18
+ &key_str="&SRC_STR_24"
+ )
+ SEL.25: CHOOSEBOX "&SRC_STR_25"
+ (
+ &key_in=0x19
+ &key_str="&SRC_STR_25"
+ )
+ SEL.26: CHOOSEBOX "&SRC_STR_26"
+ (
+ &key_in=0x1A
+ &key_str="&SRC_STR_26"
+ )
+ SEL.27: CHOOSEBOX "&SRC_STR_27"
+ (
+ &key_in=0x1B
+ &key_str="&SRC_STR_27"
+ )
+ SEL.28: CHOOSEBOX "&SRC_STR_28"
+ (
+ &key_in=0x1C
+ &key_str="&SRC_STR_28"
+ )
+ SEL.29: CHOOSEBOX "&SRC_STR_29"
+ (
+ &key_in=0x1D
+ &key_str="&SRC_STR_29"
+ )
+ SEL.30: CHOOSEBOX "&SRC_STR_30"
+ (
+ &key_in=0x1E
+ &key_str="&SRC_STR_30"
+ )
+ SEL.31: CHOOSEBOX "&SRC_STR_31"
+ (
+ &key_in=0x1F
+ &key_str="&SRC_STR_31"
+ )
+
+ POS 21. 0. 20. 1.
+ LINE "FQMTR Information"
+ INFO1: EDIT "Window Seting: &fqmtr_winset" ""
+ INFO2: EDIT "Fixed Clock: &fqmtr_fcksel_val" ""
+ INFO3: EDIT "32K measure support" ""
+
+ POSY 1. 20. 1.
+ LINE "FQMTR Result"
+ RESULT: EDIT "" ""
+
+ POSY 1. 20. 1.
+ DEFBUTTON "OK"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ IF &key_in!=0
+ (
+ GOSUB fqmtr_query &key_in &key_str 1
+ )
+ )
+
+ DEFBUTTON "LIST ALL"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ GOSUB fqmtr_list_all
+ )
+
+ DEFBUTTON "Force LIST main clk"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ GOSUB fqmtr_force_list_all
+ )
+
+ CLOSE
+ (
+ PRINT "bye~"
+ DIALOG.END
+ )
+)
+
+ ;; Disable EDIT of showing information
+ DIALOG.Disable INFO1
+ DIALOG.Disable INFO2
+ DIALOG.Disable INFO3
+ ;DIALOG.Disable RESULT
+STOP
+ENDDO
+
+;;;;;The main function to get the Frequency. &idx==> the clock you select, &str==> clock name, &info==>list more info and wait 5ms in the function
+;; &info=1 ==> for printing many PLLs at one time
+fqmtr_query:
+ENTRY &idx &str &info
+(
+ IF &info!=0
+ (
+ PRINT "&str: &idx"
+ PRINT "fqmtrsrc: 0x" FORMAT.HEX(2,&idx)
+ PRINT "opt_cvd_connect: &opt_cvd_connect"
+ )
+
+ LOCAL &unit
+ LOCAL &fqmtr_winset_26M
+ LOCAL &fqmtr_result
+ LOCAL &fqmtr_result_raw
+ LOCAL &fqmtr_result_str
+ LOCAL &safe_wait_cnt
+ LOCAL &safe_wait_cnt_max
+
+ &safe_wait_cnt=0
+
+ IF &fqmtr_fcksel_val==0x1a ;; base on 26M, unit:MHz
+ (
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &unit="Khz"
+ &fqmtr_winset_26M=&fqmtr_winset_for_32k
+ &safe_wait_cnt_max=500 ;;5000 ms = 5s ==> in real test, longer than 5s, so reduce it
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &unit="Mhz"
+ &fqmtr_winset_26M=&fqmtr_winset
+ &safe_wait_cnt_max=32 ;;32 ms
+ )
+ )
+ ELSE
+ (
+ &unit=""
+ )
+
+ IF "&opt_cvd_connect"=="none"
+ (
+ sys.m prepare
+ )
+ ELSE IF "&opt_cvd_connect"=="debug"
+ (
+ ; do nothing
+ )
+ ELSE
+ (
+ IF &info!=0
+ (
+ PRINT "No explicit CVD connection, use current status"
+ )
+ )
+
+ IF &idx==0
+ (
+ ;; This is used for connect CVD only, no FQMTR test
+ RETURN
+ )
+
+ ;;select source to a valid clock to let reset success.
+ Data.Set &mclass:(&clksw_base+0x0100) %LE %LONG 0x13
+ Data.Set &mclass:(&clksw_base+0x0104) %LE %LONG 0x0 ;reset frequency meter
+ WAIT 1ms
+
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ ;;For accurate, don't div 8 for 32K
+ Data.Set &mclass:(&clksw_base+0x0100) %LE %LONG (&idx)
+ )
+ ELSE ;; measure PLL and other module
+ (
+ ;;div 8 and select src
+ Data.Set &mclass:(&clksw_base+0x0100) %LE %LONG (0x0300)|(&idx)
+ )
+
+ Data.Set &mclass:(&clksw_base+0x0108) %LE %LONG &fqmtr_winset_26M
+ Data.Set &mclass:(&clksw_base+0x0104) %LE %LONG 0x1 ;enable frequency meter
+
+ ;; read status, to check polling done or not
+ &fqmtr_busy=DATA.LONG(&mclass:(&clksw_base+0x0104))&(1<<1)
+ WHILE &fqmtr_busy==0
+ (
+ ;PRINT ". &fqmtr_busy"
+ &fqmtr_busy=DATA.LONG(&mclass:(&clksw_base+0x0104))&(1<<1)
+ &safe_wait_cnt=&safe_wait_cnt+1
+ IF &safe_wait_cnt==&safe_wait_cnt_max
+ (
+ PRINT "[&str] Wait Fail, exit"
+ DIALOG.Set RESULT "Wait Fail(No clock), exit"
+ RETURN
+ )
+ ELSE
+ (
+;; PRINT "Waiting result. safe_wait_cnt=" "&safe_wait_cnt"
+ )
+ WAIT 1ms
+ )
+
+ ;; Calculate the result
+ &fqmtr_result_raw=DATA.LONG(&mclass:(&clksw_base+0x10c))
+
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*(0x3E8)/(&fqmtr_winset_26M+3)
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*8/(&fqmtr_winset_26M+3)
+ )
+
+ &fqmtr_result_dec=FORMAT.DECIMAL(0,&fqmtr_result)
+ &fqmtr_result_str=""+FORMAT.DECIMAL(0,&fqmtr_result)+" &unit"
+ IF &info==0
+ (
+ PRINT "0x" FORMAT.HEX(2,&idx) ",&fqmtr_result_dec,&unit,&str,&fqmtr_result_raw,"
+ )
+ ELSE
+ (
+ PRINT "Frequency Meter Result: &fqmtr_result_str (&fqmtr_result_raw)"
+ PRINT ""
+ )
+ DIALOG.Set RESULT "&fqmtr_result_str"
+
+ IF &info==0
+ (
+ WAIT 5ms
+ )
+
+ RETURN
+)
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+fqmtr_create_win:
+(
+ AREA.RESet
+ AREA.Create PLL_FMETER
+ AREA.Select PLL_FMETER
+ WinPOS 10.,0.,50.,35.,,, FMETER
+ AREA.view PLL_FMETER
+ AREA.Clear PLL_FMETER
+ RETURN
+)
+
+fqmtr_list_all:
+(
+ GOSUB fqmtr_create_win
+
+ ;GOSUB fqmtr_query 0x1 &SRC_STR_1 0
+ ;GOSUB fqmtr_query 0x2 &SRC_STR_2 0
+ ;GOSUB fqmtr_query 0x3 &SRC_STR_3 0
+ ;GOSUB fqmtr_query 0x4 &SRC_STR_4 0
+ ;GOSUB fqmtr_query 0x5 &SRC_STR_5 0
+ ;GOSUB fqmtr_query 0x6 &SRC_STR_6 0
+ ;GOSUB fqmtr_query 0x7 &SRC_STR_7 0
+ ;GOSUB fqmtr_query 0x8 &SRC_STR_8 0
+ ;GOSUB fqmtr_query 0x9 &SRC_STR_9 0
+ GOSUB fqmtr_query 0xA &SRC_STR_10 0
+ GOSUB fqmtr_query 0xB &SRC_STR_11 0
+ GOSUB fqmtr_query 0xC &SRC_STR_12 0
+ GOSUB fqmtr_query 0xD &SRC_STR_13 0
+ GOSUB fqmtr_query 0xE &SRC_STR_14 0
+ GOSUB fqmtr_query 0xF &SRC_STR_15 0
+ GOSUB fqmtr_query 0x10 &SRC_STR_16 0
+ GOSUB fqmtr_query 0x11 &SRC_STR_17 0
+ GOSUB fqmtr_query 0x12 &SRC_STR_18 0
+ GOSUB fqmtr_query 0x13 &SRC_STR_19 0
+ GOSUB fqmtr_query 0x14 &SRC_STR_20 0
+ GOSUB fqmtr_query 0x15 &SRC_STR_21 0
+ GOSUB fqmtr_query 0x16 &SRC_STR_22 0
+ GOSUB fqmtr_query 0x17 &SRC_STR_23 0
+ GOSUB fqmtr_query 0x18 &SRC_STR_24 0
+ GOSUB fqmtr_query 0x19 &SRC_STR_25 0
+ GOSUB fqmtr_query 0x1A &SRC_STR_26 0
+ GOSUB fqmtr_query 0x1B &SRC_STR_27 0
+ GOSUB fqmtr_query 0x1C &SRC_STR_28 0
+ GOSUB fqmtr_query 0x1D &SRC_STR_29 0
+ GOSUB fqmtr_query 0x1E &SRC_STR_30 0
+ GOSUB fqmtr_query 0x1F &SRC_STR_31 0
+ RETURN
+)
+
+fqmtr_force_list_all:
+(
+ GOSUB fqmtr_create_win
+
+ LOCAL &original_reg
+ LOCAL &original_BPIPLLCTL1_reg
+
+ &original_reg=DATA.LONG(&mclass:(&pll_base+0x10))
+ &original_BPIPLLCTL1_reg=DATA.LONG(&mclass:(&pll_base+0x64))
+
+ ; S/W force on all PLL
+ Data.Set &mclass:(&pll_base+0x10) %LE %LONG 0xFFFFFFFF
+
+ ; S/W force on BPI_1 PLL
+ Data.Set &mclass:(&pll_base+0x64) %LE %LONG &original_BPIPLLCTL1_reg|(0x80)
+
+ WAIT 1.s
+
+ ;GOSUB fqmtr_query 0x1 &SRC_STR_1 0
+ ;GOSUB fqmtr_query 0x2 &SRC_STR_2 0
+ ;GOSUB fqmtr_query 0x3 &SRC_STR_3 0
+ ;GOSUB fqmtr_query 0x4 &SRC_STR_4 0
+ ;GOSUB fqmtr_query 0x5 &SRC_STR_5 0
+ ;GOSUB fqmtr_query 0x6 &SRC_STR_6 0
+ ;GOSUB fqmtr_query 0x7 &SRC_STR_7 0
+ ;GOSUB fqmtr_query 0x8 &SRC_STR_8 0
+ ;GOSUB fqmtr_query 0x9 &SRC_STR_9 0
+ GOSUB fqmtr_query 0xA &SRC_STR_10 0
+ GOSUB fqmtr_query 0xB &SRC_STR_11 0
+ GOSUB fqmtr_query 0xC &SRC_STR_12 0
+ GOSUB fqmtr_query 0xD &SRC_STR_13 0
+ GOSUB fqmtr_query 0xE &SRC_STR_14 0
+ GOSUB fqmtr_query 0xF &SRC_STR_15 0
+ GOSUB fqmtr_query 0x10 &SRC_STR_16 0
+ GOSUB fqmtr_query 0x11 &SRC_STR_17 0
+ GOSUB fqmtr_query 0x12 &SRC_STR_18 0
+ GOSUB fqmtr_query 0x13 &SRC_STR_19 0
+ GOSUB fqmtr_query 0x14 &SRC_STR_20 0
+ GOSUB fqmtr_query 0x15 &SRC_STR_21 0
+ GOSUB fqmtr_query 0x16 &SRC_STR_22 0
+ GOSUB fqmtr_query 0x17 &SRC_STR_23 0
+ GOSUB fqmtr_query 0x18 &SRC_STR_24 0
+ GOSUB fqmtr_query 0x19 &SRC_STR_25 0
+ GOSUB fqmtr_query 0x1A &SRC_STR_26 0
+ GOSUB fqmtr_query 0x1B &SRC_STR_27 0
+ GOSUB fqmtr_query 0x1C &SRC_STR_28 0
+ GOSUB fqmtr_query 0x1D &SRC_STR_29 0
+ GOSUB fqmtr_query 0x1E &SRC_STR_30 0
+ GOSUB fqmtr_query 0x1F &SRC_STR_31 0
+
+ ; Revert to original value
+ Data.Set &mclass:(&pll_base+0x10) %LE %LONG &original_reg
+ Data.Set &mclass:(&pll_base+0x64) %LE %LONG &original_BPIPLLCTL1_reg
+
+ WAIT 1.s
+
+ RETURN
+)
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_GPIO_MDUART0.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_GPIO_MDUART0.cmm
new file mode 100644
index 0000000..1dd5521
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_GPIO_MDUART0.cmm
@@ -0,0 +1,17 @@
+;Cervino MD_UART0 port test
+;You should make sure GPIO150 has connected to UART port RXD pin,GPIO151 has connected to UART port TXD pin
+
+;port: MDUART0
+;Baudrate: 115200
+;&BASE_ADDR_MDUART0=0xB0010000
+sys.m prepare
+&BASE_ADDR_MDUART0=0x20010000
+&BASE_ADDR_MDGPIO=0x10005000
+&BASE_ADDR_IOCFG=0x10002600
+
+D.S AXI:&BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_MDGPIO+0x420)&(0x00FFFFFF)
+D.S AXI:&BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_MDGPIO+0x420)|(0x55000000) ;//set GPIO150 to MD_URXD0 mode,set GPIO151 to MD_UTXD0 mode,
+
+D.S AXI:&BASE_ADDR_IOCFG+0x60 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x60)&(0xFF7FFFFF) ;//MD_URXD0 pull dowm disable
+D.S AXI:&BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)|(0x800000) ;//MD_URXD0 pull up enable
+D.S AXI:&BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)&(0xFEFFFFFF) ;//MD_UTXD0 pull up disable
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_GPIO_SIM.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_GPIO_SIM.cmm
new file mode 100644
index 0000000..c18702b
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_GPIO_SIM.cmm
@@ -0,0 +1,20 @@
+// SIM GPIO MODE
+// Clear bits
+d.s &MEM_CLASS:0x10005348 %long %le 0x77777000
+d.s &MEM_CLASS:0x10005358 %long %le 0x00000007
+// Set bits
+d.s &MEM_CLASS:0x10005344 %long %le 0x11111000
+d.s &MEM_CLASS:0x10005354 %long %le 0x00000001
+
+// SIM PUPD
+// Control PAD_SIM1_SIO PUPD pin. PUPD=0: pull up, PUPD=1: pull down.
+// Set bits
+d.s &MEM_CLASS:0x10002454 %long %le 0x00000FC0
+// Clear bits, SIO pull up
+d.s &MEM_CLASS:0x10002458 %long %le 0x00000480
+
+// SIM R1R0
+// R1R0=00:High-Z, R1R0=01:PU 45kohm;PD 75kohm,
+// R1R0=10:PU 5kohm;PD 75kohm, R1R0=11:PU 45kohm/5kohm;PD 75kohm/75kohm.
+// Set R1 bits
+d.s &MEM_CLASS:0x10002484 %long %le 0x00000FC0
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_MD2PERI_disable.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_MD2PERI_disable.cmm
new file mode 100644
index 0000000..2354a68
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_MD2PERI_disable.cmm
@@ -0,0 +1,24 @@
+&MEM_CLASS="AXI"
+; do AP to MD path disable
+; MD cannot access AP after running this script
+LOCAL &BASE_ADDR_AP2MD_Dummy
+LOCAL &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN
+LOCAL &temp
+
+&BASE_ADDR_AP2MD_Dummy=0x10001370
+&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN=0x100012A0
+
+; Set reg_ap2md_dummy[0] = 1'b0
+&temp=data.long(&MEM_CLASS:(&BASE_ADDR_AP2MD_Dummy+0x0))&0xFFFFFFFE
+;PRINT "temp=" "&temp"
+;PRINT "BASE_ADDR_AP2MD_Dummy=" "&BASE_ADDR_AP2MD_Dummy"
+D.S &MEM_CLASS:(&BASE_ADDR_AP2MD_Dummy+0x0) %LE %LONG &temp
+wait 1.ms
+
+; Set md2peri_protect_en = 1'b1
+; Write 0x1000_12A8[6] = 1'b1.
+&temp=data.long(&MEM_CLASS:(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0x8))|0x40
+;PRINT "temp=" "&temp"
+;PRINT "(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0x8)"
+D.S &MEM_CLASS:(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0x8) %LE %LONG &temp
+wait 1.ms
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_MD_ForceOnDebugSys.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_MD_ForceOnDebugSys.cmm
new file mode 100644
index 0000000..76a11e0
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_MD_ForceOnDebugSys.cmm
@@ -0,0 +1,10 @@
+;Core1 force on
+d.s &MEM_CLASS:0x200D0004 %long %le 0xB2002383
+;ForceOn debug sys
+d.s &MEM_CLASS:0x20150010 %long %le data.long(&MEM_CLASS:0x20150010)|(0x00080008)
+d.s &MEM_CLASS:0x200D04B0 %long %le data.long(&MEM_CLASS:0x200D04B0)|(0x00000008)
+&temp=data.long(&MEM_CLASS:0x200D0590)
+IF (&temp&0x8008)!=0x8008
+(
+ PRINT "Force on debug sys clock fail"
+)
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_MD_PLL_Init.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_MD_PLL_Init.cmm
new file mode 100644
index 0000000..878bac3
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_MD_PLL_Init.cmm
@@ -0,0 +1,101 @@
+; /* Step 6 config PLL setting */
+;;==============================PLL init start==================================================
+;;sys.m prepare
+&MEM_CLASS="AXI"
+
+&BASE_MADDR_APMIXEDSYS=(0x1000C000)
+&BASE_MADDR_MDTOP_PLLMIXED=(0x20140000)
+&BASE_MADDR_MDTOP_CLKSW=(0x20150000)
+
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+®_MDTOP_PLLMIXED_MDTXPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x58)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+
+®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0x84)
+
+&MD_PLL_MAGIC_NUM=(0x62930000)
+
+;;//Enables clock square1 low-pass filter for 26M quality.
+d.s &MEM_CLASS:®_APMIXEDSYS_AP_PLL_CON0 %long %le data.long(&MEM_CLASS:®_APMIXEDSYS_AP_PLL_CON0)|0x2
+;;// 100us
+wait 1.ms
+
+;;// Default md_srclkena_ack settle time = 136T 32K
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E88
+
+;;// fixed 600MHz(/4), 343MHz(/7), 267MHz(/9) /* Fvco = 2400M */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x801713B1
+;;// 300MHz /* Fvco = 2400M */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDTXPLL_CTL0 %long %le 0x80171400
+;;// 400MHz /* Fvco = 3600M */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80229E00
+;;// 672MHz /* Fvco = 3360M */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x80204E00
+;;// 864MHz /* Fvco = 3456M */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x80213C00
+
+;;// Polling until MDMCUPLL complete frequency adjustment
+;WHILE ((data.long(&MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0
+;(
+;)
+wait 1.ms
+
+;;// Default disable BPI /7 clock
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDBPIPLL_CTL1 %long %le data.long(&MEM_CLASS:®_MDTOP_PLLMIXED_MDBPIPLL_CTL1)&0xFFFFFF7F
+
+;;/*TINFO="MDSYS_INIT: Update ABB MDPLL control register default value"*/
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x4C43100
+
+;;/* Force TXPLL ON due to TOPSM couldn't enable this PLL by default, TXPLL would be disable after DVFS Init.
+;; other PLL ON controlled by HW" */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x100010
+
+;; /*
+;; * Wait MD bus clock ready
+;; * Once MD bus ready, other clock should be ready too
+;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+;; */
+;WHILE (data.long(&MEM_CLASS:®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000
+;(
+;)
+wait 1.ms
+
+;;// Switch MDMCU & MD BUS clock to PLL frequency
+d.s &MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL)|(0x3)
+
+;;// Switch all clock to PLL frequency
+d.s &MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL)|(0x58103FC)
+
+;;// Switch SDF clock to PLL frequency
+d.s &MEM_CLASS:®_MDTOP_CLKSW_SDF_CK_CTL %long %le data.long(&MEM_CLASS:®_MDTOP_CLKSW_SDF_CK_CTL)|(0x10)
+
+;;// Turn off all SW clock request, except ATB
+d.s &MEM_CLASS:®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+;;// Mask all PLL ADJ RDY IRQ
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+;;// Make a record that means MD pll has been initialized.
+;;/* Note: We use "MD_PLL_MAGIC_NUM|0x1" to know PLL init in MD C code.
+;; If AP init PLL, it would be "MD_PLL_MAGIC_NUM". */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_disable_WDT.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_disable_WDT.cmm
new file mode 100644
index 0000000..6ea39f8
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_disable_WDT.cmm
@@ -0,0 +1,11 @@
+;/* Step 8 Disable MD WDT */
+&MEM_CLASS="AXI"
+
+;&BASE_MADDR_MDRGU=0xA00F0000
+;&BASE_MADDR_APRGU=0xC0007000
+&BASE_MADDR_MDRGU=0x200F0000
+;&BASE_MADDR_APRGU=0x10007000
+
+D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+;D.S &MEM_CLASS:&BASE_MADDR_APRGU %LE %LONG 0x22000064
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_md_srclkena.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_md_srclkena.cmm
new file mode 100644
index 0000000..244a27c
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/APview_MT6765_md_srclkena.cmm
@@ -0,0 +1,33 @@
+; /* Step 6 config md_srclkena setting */
+&MEM_CLASS="AXI"
+
+; /* (1) INFRA_MISC2 */
+&BASE_INFRACFG=(0x10000000)
+; /* (2) SRCLKEN_O1 force on */
+&SPM_REG=(0x10006000)
+
+
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(&BASE_INFRACFG+0x1F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+
+
+; /* (1) INFRA_MISC2 */
+; /* [3:0] : mdsrc_req_0_en = 4'b0001 */
+d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFFF0)
+d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x1)
+
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 */
+d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFF0F)
+d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x20)
+
+; /* (2) SRCLKEN_O1 force on */
+//MMRF request
+D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x00215830 //set src clkena1 force on
+
+wait 1.ms
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/CoreTracer_MT6765_Disable_WDT.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/CoreTracer_MT6765_Disable_WDT.cmm
new file mode 100644
index 0000000..8ba2bba
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/CoreTracer_MT6765_Disable_WDT.cmm
@@ -0,0 +1,34 @@
+;sys.m prepare
+;LOCAL &TYPE
+
+
+system.mode attach
+
+; configure GCR_ACCESS Register
+; CoreTracer will access MO port via CPU to do following configuration
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+
+
+
+; do orginal APview_MT6771_disable_WDT.cmm
+LOCAL &BASE_MADDR_MDRGU
+&BASE_MADDR_MDRGU=0xA00F0000
+
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG 0x55000030
+
+PRINT "=============================="
+PRINT "Done disable MD WDT!"
+PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/Coretracer_MT6765_Frequency_Meter.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/Coretracer_MT6765_Frequency_Meter.cmm
new file mode 100644
index 0000000..1c41fbc
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/Coretracer_MT6765_Frequency_Meter.cmm
@@ -0,0 +1,219 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; MT6771 MD Frequency Meter
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+
+;;;;;;;;;;;;;;;;;;;;;;;Below you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LOCAL &clksw_base ;; MD CLKSW base address
+&clksw_base=0xA0150000 ;; MD view APB
+;&clksw_base=0xA0096000 ;; MD view debug APB
+;&clksw_base=0x20150000 ;; AP view MD system bus
+;&clksw_base=0x0D0D6000 ;; AP view MD debug sys
+
+LOCAL &pll_base ;; MD PLLMIXED base address
+&pll_base=0xA0140000 ;; MD view APB
+;&pll_base=0xA0094000 ;; MD view debug APB
+;&pll_base=0x20140000 ;; AP view MD system bus
+;&pll_base=0x0D0D4000 ;; AP view MD debug sys
+
+&fqmtr_fcksel_32k_index=0x17
+
+;;;;;;;;;;;;;;;;;;;;;;;Above you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LOCAL &fqmtr_winset ;; Frequency Meter Windoiw Setting (= Number of FIXED clock cycle)
+&fqmtr_winset=0x1ff
+&fqmtr_winset_for_32k=0x1E000
+
+LOCAL &fqmtr_fcksel_val ;; Frequency Meter FIXED clock selection
+&fqmtr_fcksel_val=0x1a ;; Select 26Mhz by default
+
+&SRC_STR_10="TRACE_MON_clock"
+&SRC_STR_11="MDSYS_208M_clock"
+&SRC_STR_12="mdrxsys_rake_clock"
+&SRC_STR_13="mdrxsys_brp_clock"
+&SRC_STR_14="mdrxsys_vdsp_clock"
+&SRC_STR_15="mdtop_log_atb_clock"
+&SRC_STR_16="fesys_csys_clock"
+&SRC_STR_17="fesys_txsys_clock"
+&SRC_STR_18="fesys_bsi_clock"
+&SRC_STR_19="mdsys_mdcore_clock"
+&SRC_STR_20="mdsys_bus2x_nodcm_clock"
+&SRC_STR_21="mdsys_bus2x_clock"
+&SRC_STR_22="mdtop_dbg_clock"
+&SRC_STR_23="mdtop_f32k_clock"
+&SRC_STR_24="MDBPIPLL_0_DIV2_clock"
+&SRC_STR_25="MDBPIPLL_2_clock"
+&SRC_STR_26="MDBPIPLL_1_clock"
+&SRC_STR_27="MDBPIPLL_0_clock"
+&SRC_STR_28="MDTXPLL_clock"
+&SRC_STR_29="MDBRPPLL_clock"
+&SRC_STR_30="MDVDSPPLL_clock"
+&SRC_STR_31="MDMCUPLL_clock"
+
+LOCAL &idx
+LOCAL &str
+&idx = 0xA;
+&str = "TRACE_MON_clock"
+GOSUB fqmtr_query
+&idx = 0xB;
+&str = "MDSYS_208M_clock"
+GOSUB fqmtr_query
+&idx = 0xC;
+&str = "mdrxsys_rake_clock"
+GOSUB fqmtr_query
+&idx = 0xD;
+&str = "mdrxsys_brp_clock"
+GOSUB fqmtr_query
+&idx = 0xE;
+&str = "mdrxsys_vdsp_clock"
+GOSUB fqmtr_query
+&idx = 0xF;
+&str = "mdtop_log_atb_clock"
+GOSUB fqmtr_query
+&idx = 0x10;
+&str = "fesys_csys_clock"
+GOSUB fqmtr_query
+&idx = 0x11;
+&str = "fesys_txsys_clock"
+GOSUB fqmtr_query
+&idx = 0x12;
+&str = "fesys_bsi_clock"
+GOSUB fqmtr_query
+&idx = 0x13;
+&str = "mdsys_mdcore_clock"
+GOSUB fqmtr_query
+&idx = 0x14;
+&str = "mdsys_bus2x_nodcm_clock"
+GOSUB fqmtr_query
+&idx = 0x15;
+&str = "mdsys_bus2x_clock"
+GOSUB fqmtr_query
+&idx = 0x16;
+&str = "mdtop_dbg_clock"
+GOSUB fqmtr_query
+&idx = 0x17;
+&str = "mdtop_f32k_clock"
+GOSUB fqmtr_query
+&idx = 0x18;
+&str = "MDBPIPLL_0_DIV2_clock"
+GOSUB fqmtr_query
+&idx = 0x19;
+&str = "MDBPIPLL_2_clock"
+GOSUB fqmtr_query
+&idx = 0x1A;
+&str = "MDBPIPLL_1_clock"
+GOSUB fqmtr_query
+&idx = 0x1B;
+&str = "MDBPIPLL_0_clock"
+GOSUB fqmtr_query
+&idx = 0x1C;
+&str = "MDTXPLL_clock"
+GOSUB fqmtr_query
+&idx = 0x1D;
+&str = "MDBRPPLL_clock"
+GOSUB fqmtr_query
+&idx = 0x1E;
+&str = "MDVDSPPLL_clock"
+GOSUB fqmtr_query
+&idx = 0x1F;
+&str = "MDMCUPLL_clock"
+GOSUB fqmtr_query
+
+&idx = 0x20;
+
+;;;;;The main function to get the Frequency. &idx==> the clock you select, &str==> clock name, &info==>list more info and wait 5ms in the function
+;; &info=1 ==> for printing many PLLs at one time
+fqmtr_query:
+ LOCAL &unit
+ LOCAL &fqmtr_winset_26M
+ LOCAL &fqmtr_result
+ LOCAL &fqmtr_result_raw
+ LOCAL &safe_wait_cnt
+ LOCAL &safe_wait_cnt_max
+
+ &safe_wait_cnt=0
+ IF &idx==0x20
+ (
+ RETURN
+ )
+ ELSE
+ (
+ IF &fqmtr_fcksel_val==0x1a ;; base on 26M, unit:MHz
+ (
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &unit="Khz"
+ &fqmtr_winset_26M=&fqmtr_winset_for_32k
+ &safe_wait_cnt_max=500 ;;5000 ms = 5s ==> in real test, longer than 5s, so reduce it
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &unit="Mhz"
+ &fqmtr_winset_26M=&fqmtr_winset
+ &safe_wait_cnt_max=32 ;;32 ms
+ )
+ )
+
+ ;;select source to a valid clock to let reset success.
+ Data.Set (&clksw_base+0x0100) %LE %LONG 0x13
+ Data.Set (&clksw_base+0x0104) %LE %LONG 0x0 ;reset frequency meter
+ WAIT 1000.us
+
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ ;;For accurate, don't div 8 for 32K
+ Data.Set (&clksw_base+0x0100) %LE %LONG (&idx)
+ )
+ ELSE ;; measure PLL and other module
+ (
+ ;;div 8 and select src
+ Data.Set (&clksw_base+0x0100) %LE %LONG (0x0300)|(&idx)
+ )
+
+ Data.Set (&clksw_base+0x0108) %LE %LONG &fqmtr_winset_26M
+ Data.Set (&clksw_base+0x0104) %LE %LONG 0x1 ;enable frequency meter
+
+ ;; read status, to check polling done or not
+ &fqmtr_busy=DATA.LONG(&clksw_base+0x0104)&(1<<1)
+
+ WHILE &fqmtr_busy==0
+ (
+; PRINT ". &fqmtr_busy"
+ &fqmtr_busy=DATA.LONG(&clksw_base+0x0104)&(1<<1)
+ &safe_wait_cnt=&safe_wait_cnt+1
+ IF &safe_wait_cnt==&safe_wait_cnt_max
+ (
+ PRINT "[&str] Wait Fail, exit"
+ RETURN
+ )
+ ELSE
+ (
+; PRINT "Waiting result. safe_wait_cnt=" "&safe_wait_cnt"
+ )
+ WAIT 1000.us
+
+ )
+
+ ;; Calculate the result
+ &fqmtr_result_raw=DATA.LONG(&clksw_base+0x10c)
+
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*(0x3E8)/(&fqmtr_winset_26M+3)
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*8/(&fqmtr_winset_26M+3)
+ )
+
+
+ &fqmtr_result_dec=&fqmtr_result
+ &fqmtr_result_dec=FORMAT.DECIMAL( 0 , &fqmtr_result )
+
+ PRINT " &idx , &fqmtr_result_dec &unit , &str "
+
+ WAIT 1000.us
+
+ RETURN
+ )
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/MT6765_EVB_Load_MD_Elf.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/MT6765_EVB_Load_MD_Elf.cmm
new file mode 100644
index 0000000..b74fb3f
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/MT6765_EVB_Load_MD_Elf.cmm
@@ -0,0 +1,315 @@
+;sys.m prepare
+;LOCAL &TYPE
+
+system.mode attach
+
+; configure GCR_ACCESS Register
+; CoreTracer will access MO port via CPU to do following configuration
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+
+
+; do orginal APview_MT6765_disable_WDT.cmm
+LOCAL &BASE_MADDR_MDRGU
+&BASE_MADDR_MDRGU=0xA00F0000
+
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG 0x55000030
+
+
+PRINT "=============================="
+PRINT "config md_srclkena setting"
+PRINT "=============================="
+; /* Step 6 config md_srclkena setting */
+
+; /* (1) INFRA_MISC2 */
+&BASE_INFRACFG=(0xC0000000)
+; /* (2) SRCLKEN_O1 force on */
+&SPM_REG=(0xC0006000)
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(&BASE_INFRACFG+0x1F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+
+; /* (1) INFRA_MISC2 */
+; /* [3:0] : mdsrc_req_0_en = 4'b0001 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFFF0)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x1)
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFFF0)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x1)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFF0F)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x20)
+
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFF0F)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x20)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+; /* (2) SRCLKEN_O1 force on */
+; //MMRF request
+;D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+;D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x00215830 //set src clkena1 force on
+D.S &POWERON_CONFIG_EN %LE %LONG 0x0B160001
+D.S &SPM_POWER_ON_VAL1 %LE %LONG 0x00215830
+
+wait 1.ms
+
+
+
+PRINT "=============================="
+PRINT "config PLL setting"
+PRINT "=============================="
+
+; /* Step 5 config PLL setting */
+&BASE_MADDR_APMIXEDSYS=(0xC000C000)
+&BASE_MADDR_MDTOP_PLLMIXED=(0xA0140000)
+&BASE_MADDR_MDTOP_CLKSW=(0xA0150000)
+
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+®_MDTOP_PLLMIXED_MDTXPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x58)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0x84)
+
+&MD_PLL_MAGIC_NUM=(0x62930000)
+
+;;// initial CLKSQ_LPF
+&temp=data.long(AXI:®_APMIXEDSYS_AP_PLL_CON0)
+&temp=&temp|0x2
+d.s ®_APMIXEDSYS_AP_PLL_CON0 %long %le &temp
+;;// 100us
+wait 1.ms
+
+;;// Default md_srclkena_ack settle time = 136T 32K
+d.s ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E88
+
+;;// fixed 600MHz(/4), 343MHz(/7), 267MHz(/9) /* Fvco = 2400M */
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x801713B1
+;;// 300MHz /* Fvco = 2400M */
+d.s ®_MDTOP_PLLMIXED_MDTXPLL_CTL0 %long %le 0x80171400
+;;// 400MHz /* Fvco = 3600M */
+d.s ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80229E00
+;;// 672MHz /* Fvco = 3360M */
+d.s ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x80204E00
+;;// 864MHz /* Fvco = 3456M */
+d.s ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x80213C00
+
+;;// Polling until MDMCUPLL complete frequency adjustment
+;WHILE ((data.long(®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0
+;(
+;)
+wait 1.ms
+
+;;// Default disable BPI /7 clock
+&temp=data.long(®_MDTOP_PLLMIXED_MDBPIPLL_CTL1)
+&temp=&temp&(~0x80)
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL1 %long %le &temp
+
+;;/*TINFO="MDSYS_INIT: Update ABB MDPLL control register default value"*/
+d.s ®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x4C43100
+
+;;/* Force TXPLL ON due to TOPSM couldn't enable this PLL by default, TXPLL would be disable after DVFS Init.
+;; other PLL ON controlled by HW" */
+d.s ®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x100010
+
+;; /*
+;; * Wait MD bus clock ready
+;; * Once MD bus ready, other clock should be ready too
+;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+;; */
+;WHILE (data.long(®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000
+;(
+)
+wait 2.ms
+
+;;// Switch MDMCU & MD BUS clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x3)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch all clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x58103FC)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch SDF clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_SDF_CK_CTL)
+&temp=&temp|(0x10)
+d.s ®_MDTOP_CLKSW_SDF_CK_CTL %long %le &temp
+
+;;// Turn off all SW clock request, except ATB
+d.s ®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+;;// Mask all PLL ADJ RDY IRQ
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+;;// Make a record that means MD pll has been initialized.
+;;/* Note: We use "MD_PLL_MAGIC_NUM|0x1" to know PLL init in MD C code.
+;; If AP init PLL, it would be "MD_PLL_MAGIC_NUM". */
+d.s ®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+
+
+PRINT "=============================="
+PRINT "Set GPIO!"
+PRINT "=============================="
+;;////// Step 8: Set GPIO
+;;//// MD UART GPIO
+&BASE_ADDR_MDGPIO=0xC0005000
+&BASE_ADDR_IOCFG=0xC0002600
+D.S &BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_MDGPIO+0x420)&(0x00FFFFFF)
+D.S &BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_MDGPIO+0x420)|(0x55000000) ;//set GPIO150 to MD_URXD0 mode,set GPIO151 to MD_UTXD0 mode,
+D.S &BASE_ADDR_IOCFG+0x60 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x60)&(0xFF7FFFFF) ;//MD_URXD0 pull dowm disable
+D.S &BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)|(0x800000) ;//MD_URXD0 pull up enable
+D.S &BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)&(0xFEFFFFFF) ;//MD_UTXD0 pull up disable
+;;//// SIM GPIO
+;;// Clear bits
+d.s 0xC0005348 %long %le 0x77777000
+d.s 0xC0005358 %long %le 0x00000007
+;;// Set bits
+d.s 0xC0005344 %long %le 0x11111000
+d.s 0xC0005354 %long %le 0x00000001
+
+;;// SIM PUPD
+;;// Control PAD_SIM1_SIO PUPD pin. PUPD=0: pull up, PUPD=1: pull down.
+;;// Set bits
+d.s 0xC0002454 %long %le 0x00000FC0
+;;// Clear bits, SIO pull up
+d.s 0xC0002458 %long %le 0x00000480
+
+;;// SIM R1R0
+;;// R1R0=00:High-Z, R1R0=01:PU 45kohm;PD 75kohm,
+;;// R1R0=10:PU 5kohm;PD 75kohm, R1R0=11:PU 45kohm/5kohm;PD 75kohm/75kohm.
+;;// Set R1 bits
+d.s 0xC0002484 %long %le 0x00000FC0
+
+PRINT "=============================="
+PRINT "Set MD EMI Remap!"
+PRINT "=============================="
+
+
+;Step 10 set MD EMI remap address (MD view: step 9) ==>review done
+;d.s &MEM_CLASS:0xC0001300 %long %le 0x00430041
+;d.s &MEM_CLASS:0xC0001304 %long %le 0x00470045
+;d.s &MEM_CLASS:0xC0001308 %long %le 0x004b0049
+;d.s &MEM_CLASS:0xC000130c %long %le 0x004f004d
+D.S 0xC0001300 %LE %LONG 0x00430041
+D.S 0xC0001304 %LE %LONG 0x00470045
+D.S 0xC0001308 %LE %LONG 0x004b0049
+D.S 0xC000130c %LE %LONG 0x004f004d
+
+
+PRINT "=============================="
+PRINT "Set AP2MD PATH Disable!"
+PRINT "=============================="
+
+; do AP to MD path disable
+&BASE_ADDR_AP2MD_Dummy = 0xC0001370
+&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN=0xC00012A0
+
+
+; Set reg_ap2md_dummy[0] = 1'b0
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp & 0xFFFFFFFE
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+; Set peri2md_protect_en
+; Write 0x1000_12A0[7] = 1'b1.
+; MD can access AP if reg_ap2md_dummy[0] = 1'b1,
+&temp=data.long(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN)
+&temp = &temp | 0x80
+D.S &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN %LE %LONG &temp
+wait 1.ms
+
+; Clear md2peri_protect_en
+; Write 0x1000_12AC[6] = 1'b1.
+&temp=data.long(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC)
+&temp = &temp | 0x40
+D.S &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp | 0x1
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+;Enalbe cache to speed loading
+;By setting bank 6 segment control attribute
+register.set cdmmbase 0x1fc1407
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor adapter_khz 2000
+steal monitor mips32 fastchannel 0 1 0x6f800000
+
+
+PRINT "=============================="
+PRINT "Start to Load elf !"
+PRINT "=============================="
+
+thread.select 1
+steal lo
+
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+PRINT "=============================="
+PRINT "Load elf Done!"
+PRINT "=============================="
+
+thread.select 1
+
+;&t=var.address(INT_Initialize_Phase1)
+;wait 20.ms
+;stop
+;steal set $pc = &INT_Initialize_Phase1
+;register.set pc &t
+
+;PRINT "=============================="
+;PRINT "Set PC to INT_Initialize_Phase1: &t"
+;PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/MT6765_EVB_Load_MD_Elf.cmm.bak b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/MT6765_EVB_Load_MD_Elf.cmm.bak
new file mode 100644
index 0000000..ee50d88
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/MT6765_EVB_Load_MD_Elf.cmm.bak
@@ -0,0 +1,315 @@
+;sys.m prepare
+;LOCAL &TYPE
+
+system.mode attach
+
+; configure GCR_ACCESS Register
+; CoreTracer will access MO port via CPU to do following configuration
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+
+
+; do orginal APview_MT6765_disable_WDT.cmm
+LOCAL &BASE_MADDR_MDRGU
+&BASE_MADDR_MDRGU=0xA00F0000
+
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG 0x55000030
+
+
+PRINT "=============================="
+PRINT "config md_srclkena setting"
+PRINT "=============================="
+; /* Step 6 config md_srclkena setting */
+
+; /* (1) INFRA_MISC2 */
+&BASE_INFRACFG=(0xC0000000)
+; /* (2) SRCLKEN_O1 force on */
+&SPM_REG=(0xC0006000)
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(&BASE_INFRACFG+0x1F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+
+; /* (1) INFRA_MISC2 */
+; /* [3:0] : mdsrc_req_0_en = 4'b0001 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFFF0)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x1)
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFFF0)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x1)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFF0F)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x20)
+
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFF0F)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x20)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+; /* (2) SRCLKEN_O1 force on */
+; //MMRF request
+;D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+;D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x00215830 //set src clkena1 force on
+D.S &POWERON_CONFIG_EN %LE %LONG 0x0B160001
+D.S &SPM_POWER_ON_VAL1 %LE %LONG 0x00215830
+
+wait 1.ms
+
+
+
+PRINT "=============================="
+PRINT "config PLL setting"
+PRINT "=============================="
+
+; /* Step 5 config PLL setting */
+&BASE_MADDR_APMIXEDSYS=(0xC000C000)
+&BASE_MADDR_MDTOP_PLLMIXED=(0xA0140000)
+&BASE_MADDR_MDTOP_CLKSW=(0xA0150000)
+
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+®_MDTOP_PLLMIXED_MDTXPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x58)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0x84)
+
+&MD_PLL_MAGIC_NUM=(0x62930000)
+
+;;// initial CLKSQ_LPF
+&temp=data.long(AXI:®_APMIXEDSYS_AP_PLL_CON0)
+&temp=&temp|0x2
+d.s ®_APMIXEDSYS_AP_PLL_CON0 %long %le &temp
+;;// 100us
+wait 1.ms
+
+;;// Default md_srclkena_ack settle time = 136T 32K
+d.s ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E88
+
+;;// fixed 600MHz(/4), 343MHz(/7), 267MHz(/9) /* Fvco = 2400M */
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x801713B1
+;;// 300MHz /* Fvco = 2400M */
+d.s ®_MDTOP_PLLMIXED_MDTXPLL_CTL0 %long %le 0x80171400
+;;// 400MHz /* Fvco = 3600M */
+d.s ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80229E00
+;;// 672MHz /* Fvco = 3360M */
+d.s ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x80204E00
+;;// 864MHz /* Fvco = 3456M */
+d.s ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x80213C00
+
+;;// Polling until MDMCUPLL complete frequency adjustment
+;WHILE ((data.long(®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0
+;(
+;)
+wait 1.ms
+
+;;// Default disable BPI /7 clock
+&temp=data.long(®_MDTOP_PLLMIXED_MDBPIPLL_CTL1)
+&temp=&temp&(~0x80)
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL1 %long %le &temp
+
+;;/*TINFO="MDSYS_INIT: Update ABB MDPLL control register default value"*/
+d.s ®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x4C43100
+
+;;/* Force TXPLL ON due to TOPSM couldn't enable this PLL by default, TXPLL would be disable after DVFS Init.
+;; other PLL ON controlled by HW" */
+d.s ®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x100010
+
+;; /*
+;; * Wait MD bus clock ready
+;; * Once MD bus ready, other clock should be ready too
+;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+;; */
+;WHILE (data.long(®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000
+;(
+)
+wait 2.ms
+
+;;// Switch MDMCU & MD BUS clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x3)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch all clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x58103FC)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch SDF clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_SDF_CK_CTL)
+&temp=&temp|(0x10)
+d.s ®_MDTOP_CLKSW_SDF_CK_CTL %long %le &temp
+
+;;// Turn off all SW clock request, except ATB
+d.s ®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+;;// Mask all PLL ADJ RDY IRQ
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+;;// Make a record that means MD pll has been initialized.
+;;/* Note: We use "MD_PLL_MAGIC_NUM|0x1" to know PLL init in MD C code.
+;; If AP init PLL, it would be "MD_PLL_MAGIC_NUM". */
+d.s ®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+
+
+PRINT "=============================="
+PRINT "Set GPIO!"
+PRINT "=============================="
+;;////// Step 8: Set GPIO
+;;//// MD UART GPIO
+&BASE_ADDR_MDGPIO=0xC0005000
+&BASE_ADDR_IOCFG=0xC0002600
+D.S AXI:&BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x420)&(0x00FFFFFF)
+D.S AXI:&BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x420)|(0x55000000) //set GPIO150 to MD_URXD0 mode,set GPIO151 to MD_UTXD0 mode,
+D.S AXI:&BASE_ADDR_IOCFG+0x60 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x60)&(0xFF7FFFFF) //MD_URXD0 pull dowm disable
+D.S AXI:&BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)|(0x800000) //MD_URXD0 pull up enable
+D.S AXI:&BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)&(0xFEFFFFFF) //MD_UTXD0 pull up disable
+;;//// SIM GPIO
+;;// Clear bits
+d.s &MEM_CLASS:0xC0005348 %long %le 0x77777000
+d.s &MEM_CLASS:0xC0005358 %long %le 0x00000007
+;;// Set bits
+d.s &MEM_CLASS:0xC0005344 %long %le 0x11111000
+d.s &MEM_CLASS:0xC0005354 %long %le 0x00000001
+
+;;// SIM PUPD
+;;// Control PAD_SIM1_SIO PUPD pin. PUPD=0: pull up, PUPD=1: pull down.
+;;// Set bits
+d.s &MEM_CLASS:0xC0002454 %long %le 0x00000FC0
+;;// Clear bits, SIO pull up
+d.s &MEM_CLASS:0xC0002458 %long %le 0x00000480
+
+;;// SIM R1R0
+;;// R1R0=00:High-Z, R1R0=01:PU 45kohm;PD 75kohm,
+;;// R1R0=10:PU 5kohm;PD 75kohm, R1R0=11:PU 45kohm/5kohm;PD 75kohm/75kohm.
+;;// Set R1 bits
+d.s &MEM_CLASS:0xC0002484 %long %le 0x00000FC0
+
+PRINT "=============================="
+PRINT "Set MD EMI Remap!"
+PRINT "=============================="
+
+
+;Step 10 set MD EMI remap address (MD view: step 9) ==>review done
+;d.s &MEM_CLASS:0xC0001300 %long %le 0x00430041
+;d.s &MEM_CLASS:0xC0001304 %long %le 0x00470045
+;d.s &MEM_CLASS:0xC0001308 %long %le 0x004b0049
+;d.s &MEM_CLASS:0xC000130c %long %le 0x004f004d
+D.S 0xC0001300 %LE %LONG 0x00430041
+D.S 0xC0001304 %LE %LONG 0x00470045
+D.S 0xC0001308 %LE %LONG 0x004b0049
+D.S 0xC000130c %LE %LONG 0x004f004d
+
+
+PRINT "=============================="
+PRINT "Set AP2MD PATH Disable!"
+PRINT "=============================="
+
+; do AP to MD path disable
+&BASE_ADDR_AP2MD_Dummy = 0xC0001370
+&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN=0xC00012A0
+
+
+; Set reg_ap2md_dummy[0] = 1'b0
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp & 0xFFFFFFFE
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+; Set peri2md_protect_en
+; Write 0x1000_12A0[7] = 1'b1.
+; MD can access AP if reg_ap2md_dummy[0] = 1'b1,
+&temp=data.long(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN)
+&temp = &temp | 0x80
+D.S &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN %LE %LONG &temp
+wait 1.ms
+
+; Clear md2peri_protect_en
+; Write 0x1000_12AC[6] = 1'b1.
+&temp=data.long(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC)
+&temp = &temp | 0x40
+D.S &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp | 0x1
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+;Enalbe cache to speed loading
+;By setting bank 6 segment control attribute
+register.set cdmmbase 0x1fc1407
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor adapter_khz 2000
+steal monitor mips32 fastchannel 0 1 0x6f800000
+
+
+PRINT "=============================="
+PRINT "Start to Load elf !"
+PRINT "=============================="
+
+thread.select 1
+steal lo
+
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+PRINT "=============================="
+PRINT "Load elf Done!"
+PRINT "=============================="
+
+thread.select 1
+
+;&t=var.address(INT_Initialize_Phase1)
+;wait 20.ms
+;stop
+;steal set $pc = &INT_Initialize_Phase1
+;register.set pc &t
+
+;PRINT "=============================="
+;PRINT "Set PC to INT_Initialize_Phase1: &t"
+;PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/MT6765_EVB_Load_MD_Elf_With_DSP.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/MT6765_EVB_Load_MD_Elf_With_DSP.cmm
new file mode 100644
index 0000000..7369036
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/MT6765_EVB_Load_MD_Elf_With_DSP.cmm
@@ -0,0 +1,342 @@
+;sys.m prepare
+;LOCAL &TYPE
+
+
+system.mode attach
+
+; configure GCR_ACCESS Register
+; CoreTracer will access MO port via CPU to do following configuration
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+
+
+
+; do orginal APview_MT6765_disable_WDT.cmm
+LOCAL &BASE_MADDR_MDRGU
+&BASE_MADDR_MDRGU=0xA00F0000
+
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG 0x55000030
+
+
+
+PRINT "=============================="
+PRINT "config md_srclkena setting"
+PRINT "=============================="
+
+; /* Step 6 config md_srclkena setting */
+
+
+; /* (1) INFRA_MISC2 */
+&BASE_INFRACFG=(0xC0000000)
+; /* (2) SRCLKEN_O1 force on */
+&SPM_REG=(0xC0006000)
+
+
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(&BASE_INFRACFG+0x1F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+
+
+; /* (1) INFRA_MISC2 */
+; /* [3:0] : mdsrc_req_0_en = 4'b0001 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFFF0)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x1)
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFFF0)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x1)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFF0F)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x20)
+
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFF0F)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x20)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+; /* (2) SRCLKEN_O1 force on */
+; //MMRF request
+;D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+;D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x00215830 //set src clkena1 force on
+D.S &POWERON_CONFIG_EN %LE %LONG 0x0B160001
+D.S &SPM_POWER_ON_VAL1 %LE %LONG 0x00215830
+
+wait 1.ms
+
+
+
+PRINT "=============================="
+PRINT "config PLL setting"
+PRINT "=============================="
+
+; /* Step 5 config PLL setting */
+&BASE_MADDR_APMIXEDSYS=(0xC000C000)
+&BASE_MADDR_MDTOP_PLLMIXED=(0xA0140000)
+&BASE_MADDR_MDTOP_CLKSW=(0xA0150000)
+
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+®_MDTOP_PLLMIXED_MDTXPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x58)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0x84)
+
+&MD_PLL_MAGIC_NUM=(0x62930000)
+
+;;// initial CLKSQ_LPF
+&temp=data.long(AXI:®_APMIXEDSYS_AP_PLL_CON0)
+&temp=&temp|0x2
+d.s ®_APMIXEDSYS_AP_PLL_CON0 %long %le &temp
+;;// 100us
+wait 1.ms
+
+;;// Default md_srclkena_ack settle time = 136T 32K
+d.s ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E88
+
+;;// fixed 600MHz(/4), 343MHz(/7), 267MHz(/9) /* Fvco = 2400M */
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x801713B1
+;;// 300MHz /* Fvco = 2400M */
+d.s ®_MDTOP_PLLMIXED_MDTXPLL_CTL0 %long %le 0x80171400
+;;// 400MHz /* Fvco = 3600M */
+d.s ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80229E00
+;;// 672MHz /* Fvco = 3360M */
+d.s ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x80204E00
+;;// 864MHz /* Fvco = 3456M */
+d.s ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x80213C00
+
+;;// Polling until MDMCUPLL complete frequency adjustment
+;WHILE ((data.long(®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0
+;(
+;)
+wait 1.ms
+
+;;// Default disable BPI /7 clock
+&temp=data.long(®_MDTOP_PLLMIXED_MDBPIPLL_CTL1)
+&temp=&temp&(~0x80)
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL1 %long %le &temp
+
+;;/*TINFO="MDSYS_INIT: Update ABB MDPLL control register default value"*/
+d.s ®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x4C43100
+
+;;/* Force TXPLL ON due to TOPSM couldn't enable this PLL by default, TXPLL would be disable after DVFS Init.
+;; other PLL ON controlled by HW" */
+d.s ®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x100010
+
+;; /*
+;; * Wait MD bus clock ready
+;; * Once MD bus ready, other clock should be ready too
+;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+;; */
+;WHILE (data.long(®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000
+;(
+)
+wait 2.ms
+
+;;// Switch MDMCU & MD BUS clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x3)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch all clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x58103FC)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch SDF clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_SDF_CK_CTL)
+&temp=&temp|(0x10)
+d.s ®_MDTOP_CLKSW_SDF_CK_CTL %long %le &temp
+
+;;// Turn off all SW clock request, except ATB
+d.s ®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+;;// Mask all PLL ADJ RDY IRQ
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+;;// Make a record that means MD pll has been initialized.
+;;/* Note: We use "MD_PLL_MAGIC_NUM|0x1" to know PLL init in MD C code.
+;; If AP init PLL, it would be "MD_PLL_MAGIC_NUM". */
+d.s ®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+
+
+PRINT "=============================="
+PRINT "Set GPIO!"
+PRINT "=============================="
+;;////// Step 8: Set GPIO
+;;//// MD UART GPIO
+&BASE_ADDR_MDGPIO=0xC0005000
+&BASE_ADDR_IOCFG=0xC0002600
+D.S &BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_MDGPIO+0x420)&(0x00FFFFFF)
+D.S &BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_MDGPIO+0x420)|(0x55000000) ;//set GPIO150 to MD_URXD0 mode,set GPIO151 to MD_UTXD0 mode,
+D.S &BASE_ADDR_IOCFG+0x60 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x60)&(0xFF7FFFFF) ;//MD_URXD0 pull dowm disable
+D.S &BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)|(0x800000) ;//MD_URXD0 pull up enable
+D.S &BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)&(0xFEFFFFFF) ;//MD_UTXD0 pull up disable
+;;//// SIM GPIO
+;;// Clear bits
+d.s 0xC0005348 %long %le 0x77777000
+d.s 0xC0005358 %long %le 0x00000007
+;;// Set bits
+d.s 0xC0005344 %long %le 0x11111000
+d.s 0xC0005354 %long %le 0x00000001
+
+;;// SIM PUPD
+;;// Control PAD_SIM1_SIO PUPD pin. PUPD=0: pull up, PUPD=1: pull down.
+;;// Set bits
+d.s 0xC0002454 %long %le 0x00000FC0
+;;// Clear bits, SIO pull up
+d.s 0xC0002458 %long %le 0x00000480
+
+;;// SIM R1R0
+;;// R1R0=00:High-Z, R1R0=01:PU 45kohm;PD 75kohm,
+;;// R1R0=10:PU 5kohm;PD 75kohm, R1R0=11:PU 45kohm/5kohm;PD 75kohm/75kohm.
+;;// Set R1 bits
+d.s 0xC0002484 %long %le 0x00000FC0
+
+PRINT "=============================="
+PRINT "Set MD EMI Remap!"
+PRINT "=============================="
+
+
+;Step 10 set MD EMI remap address (MD view: step 9) ==>review done
+;d.s &MEM_CLASS:0xC0001300 %long %le 0x00430041
+;d.s &MEM_CLASS:0xC0001304 %long %le 0x00470045
+;d.s &MEM_CLASS:0xC0001308 %long %le 0x004b0049
+;d.s &MEM_CLASS:0xC000130c %long %le 0x004f004d
+D.S 0xC0001300 %LE %LONG 0x00430041
+D.S 0xC0001304 %LE %LONG 0x00470045
+D.S 0xC0001308 %LE %LONG 0x004b0049
+D.S 0xC000130c %LE %LONG 0x004f004d
+
+PRINT "=============================="
+PRINT "Set MD EMI Remap!"
+PRINT "=============================="
+
+
+;Step 10 set MD EMI remap address (MD view: step 9) ==>review done
+;d.s &MEM_CLASS:0xC0001300 %long %le 0x00430041
+;d.s &MEM_CLASS:0xC0001304 %long %le 0x00470045
+;d.s &MEM_CLASS:0xC0001308 %long %le 0x004b0049
+;d.s &MEM_CLASS:0xC000130c %long %le 0x004f004d
+D.S 0xC0001300 %LE %LONG 0x00430041
+D.S 0xC0001304 %LE %LONG 0x00470045
+D.S 0xC0001308 %LE %LONG 0x004b0049
+D.S 0xC000130c %LE %LONG 0x004f004d
+
+
+PRINT "=============================="
+PRINT "Set AP2MD PATH Disable!"
+PRINT "=============================="
+
+; do AP to MD path disable
+&BASE_ADDR_AP2MD_Dummy = 0xC0001370
+&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN=0xC00012A0
+
+
+; Set reg_ap2md_dummy[0] = 1'b0
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp & 0xFFFFFFFE
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+; Set peri2md_protect_en
+; Write 0x1000_12A0[7] = 1'b1.
+; MD can access AP if reg_ap2md_dummy[0] = 1'b1,
+&temp=data.long(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN)
+&temp = &temp | 0x80
+D.S &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN %LE %LONG &temp
+wait 1.ms
+
+; Clear md2peri_protect_en
+; Write 0x1000_12AC[6] = 1'b1.
+&temp=data.long(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC)
+&temp = &temp | 0x40
+D.S &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp | 0x1
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+
+
+;Enalbe cache to speed loading
+;By setting bank 6 segment control attribute
+register.set cdmmbase 0x1fc1407
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor adapter_khz 2000
+steal monitor mips32 fastchannel 0 1 0x6f800000
+
+
+PRINT "=============================="
+PRINT "Start to Load elf !"
+PRINT "=============================="
+
+thread.select 1
+steal lo
+
+steal source ../cmm/coretracer\config\easyLoader\load_dsp.py
+
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+PRINT "=============================="
+PRINT "Load elf Done!"
+PRINT "=============================="
+
+thread.select 1
+
+;&t=var.address(INT_Initialize_Phase1)
+;wait 20.ms
+;stop
+;steal set $pc = &INT_Initialize_Phase1
+;register.set pc &t
+
+;PRINT "=============================="
+;PRINT "Set PC to INT_Initialize_Phase1: &t"
+;PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/MT6765_EVB_Load_MD_Elf_With_DSP.cmm.bak b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/MT6765_EVB_Load_MD_Elf_With_DSP.cmm.bak
new file mode 100644
index 0000000..611678d
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/MT6765_EVB_Load_MD_Elf_With_DSP.cmm.bak
@@ -0,0 +1,343 @@
+;sys.m prepare
+;LOCAL &TYPE
+
+
+system.mode attach
+
+; configure GCR_ACCESS Register
+; CoreTracer will access MO port via CPU to do following configuration
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+
+
+
+; do orginal APview_MT6765_disable_WDT.cmm
+LOCAL &BASE_MADDR_MDRGU
+&BASE_MADDR_MDRGU=0xA00F0000
+
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG 0x55000030
+
+
+
+PRINT "=============================="
+PRINT "config md_srclkena setting"
+PRINT "=============================="
+
+; /* Step 6 config md_srclkena setting */
+
+
+; /* (1) INFRA_MISC2 */
+&BASE_INFRACFG=(0xC0000000)
+; /* (2) SRCLKEN_O1 force on */
+&SPM_REG=(0xC0006000)
+
+
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(&BASE_INFRACFG+0x1F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+
+
+; /* (1) INFRA_MISC2 */
+; /* [3:0] : mdsrc_req_0_en = 4'b0001 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFFF0)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x1)
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFFF0)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x1)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFF0F)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x20)
+
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFF0F)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x20)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+; /* (2) SRCLKEN_O1 force on */
+; //MMRF request
+;D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+;D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x00215830 //set src clkena1 force on
+D.S &POWERON_CONFIG_EN %LE %LONG 0x0B160001
+D.S &SPM_POWER_ON_VAL1 %LE %LONG 0x00215830
+
+wait 1.ms
+
+
+
+PRINT "=============================="
+PRINT "config PLL setting"
+PRINT "=============================="
+
+; /* Step 5 config PLL setting */
+&BASE_MADDR_APMIXEDSYS=(0xC000C000)
+&BASE_MADDR_MDTOP_PLLMIXED=(0xA0140000)
+&BASE_MADDR_MDTOP_CLKSW=(0xA0150000)
+
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+®_MDTOP_PLLMIXED_MDTXPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x58)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0x84)
+
+&MD_PLL_MAGIC_NUM=(0x62930000)
+
+;;// initial CLKSQ_LPF
+&temp=data.long(AXI:®_APMIXEDSYS_AP_PLL_CON0)
+&temp=&temp|0x2
+d.s ®_APMIXEDSYS_AP_PLL_CON0 %long %le &temp
+;;// 100us
+wait 1.ms
+
+;;// Default md_srclkena_ack settle time = 136T 32K
+d.s ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E88
+
+;;// fixed 600MHz(/4), 343MHz(/7), 267MHz(/9) /* Fvco = 2400M */
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x801713B1
+;;// 300MHz /* Fvco = 2400M */
+d.s ®_MDTOP_PLLMIXED_MDTXPLL_CTL0 %long %le 0x80171400
+;;// 400MHz /* Fvco = 3600M */
+d.s ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80229E00
+;;// 672MHz /* Fvco = 3360M */
+d.s ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x80204E00
+;;// 864MHz /* Fvco = 3456M */
+d.s ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x80213C00
+
+;;// Polling until MDMCUPLL complete frequency adjustment
+;WHILE ((data.long(®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0
+;(
+;)
+wait 1.ms
+
+;;// Default disable BPI /7 clock
+&temp=data.long(®_MDTOP_PLLMIXED_MDBPIPLL_CTL1)
+&temp=&temp&(~0x80)
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL1 %long %le &temp
+
+;;/*TINFO="MDSYS_INIT: Update ABB MDPLL control register default value"*/
+d.s ®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x4C43100
+
+;;/* Force TXPLL ON due to TOPSM couldn't enable this PLL by default, TXPLL would be disable after DVFS Init.
+;; other PLL ON controlled by HW" */
+d.s ®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x100010
+
+;; /*
+;; * Wait MD bus clock ready
+;; * Once MD bus ready, other clock should be ready too
+;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+;; */
+;WHILE (data.long(®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000
+;(
+)
+wait 2.ms
+
+;;// Switch MDMCU & MD BUS clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x3)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch all clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x58103FC)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch SDF clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_SDF_CK_CTL)
+&temp=&temp|(0x10)
+d.s ®_MDTOP_CLKSW_SDF_CK_CTL %long %le &temp
+
+;;// Turn off all SW clock request, except ATB
+d.s ®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+;;// Mask all PLL ADJ RDY IRQ
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+;;// Make a record that means MD pll has been initialized.
+;;/* Note: We use "MD_PLL_MAGIC_NUM|0x1" to know PLL init in MD C code.
+;; If AP init PLL, it would be "MD_PLL_MAGIC_NUM". */
+d.s ®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+
+
+PRINT "=============================="
+PRINT "Set GPIO!"
+PRINT "=============================="
+;;////// Step 8: Set GPIO
+;;//// MD UART GPIO
+&BASE_ADDR_MDGPIO=0xC0005000
+&BASE_ADDR_IOCFG=0xC0002600
+D.S AXI:&BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x420)&(0x00FFFFFF)
+D.S AXI:&BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x420)|(0x55000000) //set GPIO150 to MD_URXD0 mode,set GPIO151 to MD_UTXD0 mode,
+D.S AXI:&BASE_ADDR_IOCFG+0x60 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x60)&(0xFF7FFFFF) //MD_URXD0 pull dowm disable
+D.S AXI:&BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)|(0x800000) //MD_URXD0 pull up enable
+D.S AXI:&BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)&(0xFEFFFFFF) //MD_UTXD0 pull up disable
+
+;;//// SIM GPIO
+;;// Clear bits
+d.s &MEM_CLASS:0xC0005348 %long %le 0x77777000
+d.s &MEM_CLASS:0xC0005358 %long %le 0x00000007
+;;// Set bits
+d.s &MEM_CLASS:0xC0005344 %long %le 0x11111000
+d.s &MEM_CLASS:0xC0005354 %long %le 0x00000001
+
+;;// SIM PUPD
+;;// Control PAD_SIM1_SIO PUPD pin. PUPD=0: pull up, PUPD=1: pull down.
+;;// Set bits
+d.s &MEM_CLASS:0xC0002454 %long %le 0x00000FC0
+;;// Clear bits, SIO pull up
+d.s &MEM_CLASS:0xC0002458 %long %le 0x00000480
+
+;;// SIM R1R0
+;;// R1R0=00:High-Z, R1R0=01:PU 45kohm;PD 75kohm,
+;;// R1R0=10:PU 5kohm;PD 75kohm, R1R0=11:PU 45kohm/5kohm;PD 75kohm/75kohm.
+;;// Set R1 bits
+d.s &MEM_CLASS:0xC0002484 %long %le 0x00000FC0
+
+PRINT "=============================="
+PRINT "Set MD EMI Remap!"
+PRINT "=============================="
+
+
+;Step 10 set MD EMI remap address (MD view: step 9) ==>review done
+;d.s &MEM_CLASS:0xC0001300 %long %le 0x00430041
+;d.s &MEM_CLASS:0xC0001304 %long %le 0x00470045
+;d.s &MEM_CLASS:0xC0001308 %long %le 0x004b0049
+;d.s &MEM_CLASS:0xC000130c %long %le 0x004f004d
+D.S 0xC0001300 %LE %LONG 0x00430041
+D.S 0xC0001304 %LE %LONG 0x00470045
+D.S 0xC0001308 %LE %LONG 0x004b0049
+D.S 0xC000130c %LE %LONG 0x004f004d
+
+PRINT "=============================="
+PRINT "Set MD EMI Remap!"
+PRINT "=============================="
+
+
+;Step 10 set MD EMI remap address (MD view: step 9) ==>review done
+;d.s &MEM_CLASS:0xC0001300 %long %le 0x00430041
+;d.s &MEM_CLASS:0xC0001304 %long %le 0x00470045
+;d.s &MEM_CLASS:0xC0001308 %long %le 0x004b0049
+;d.s &MEM_CLASS:0xC000130c %long %le 0x004f004d
+D.S 0xC0001300 %LE %LONG 0x00430041
+D.S 0xC0001304 %LE %LONG 0x00470045
+D.S 0xC0001308 %LE %LONG 0x004b0049
+D.S 0xC000130c %LE %LONG 0x004f004d
+
+
+PRINT "=============================="
+PRINT "Set AP2MD PATH Disable!"
+PRINT "=============================="
+
+; do AP to MD path disable
+&BASE_ADDR_AP2MD_Dummy = 0xC0001370
+&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN=0xC00012A0
+
+
+; Set reg_ap2md_dummy[0] = 1'b0
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp & 0xFFFFFFFE
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+; Set peri2md_protect_en
+; Write 0x1000_12A0[7] = 1'b1.
+; MD can access AP if reg_ap2md_dummy[0] = 1'b1,
+&temp=data.long(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN)
+&temp = &temp | 0x80
+D.S &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN %LE %LONG &temp
+wait 1.ms
+
+; Clear md2peri_protect_en
+; Write 0x1000_12AC[6] = 1'b1.
+&temp=data.long(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC)
+&temp = &temp | 0x40
+D.S &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp | 0x1
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+
+
+;Enalbe cache to speed loading
+;By setting bank 6 segment control attribute
+register.set cdmmbase 0x1fc1407
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor adapter_khz 2000
+steal monitor mips32 fastchannel 0 1 0x6f800000
+
+
+PRINT "=============================="
+PRINT "Start to Load elf !"
+PRINT "=============================="
+
+thread.select 1
+steal lo
+
+steal source ../cmm/coretracer\config\easyLoader\load_dsp.py
+
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+PRINT "=============================="
+PRINT "Load elf Done!"
+PRINT "=============================="
+
+thread.select 1
+
+;&t=var.address(INT_Initialize_Phase1)
+;wait 20.ms
+;stop
+;steal set $pc = &INT_Initialize_Phase1
+;register.set pc &t
+
+;PRINT "=============================="
+;PRINT "Set PC to INT_Initialize_Phase1: &t"
+;PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/MT6765_EVB_Load_MD_Elf_With_SPRAM.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/MT6765_EVB_Load_MD_Elf_With_SPRAM.cmm
new file mode 100644
index 0000000..a1f4782
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/MT6765_EVB_Load_MD_Elf_With_SPRAM.cmm
@@ -0,0 +1,331 @@
+;sys.m prepare
+;LOCAL &TYPE
+
+
+system.mode attach
+
+; configure GCR_ACCESS Register
+; CoreTracer will access MO port via CPU to do following configuration
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+
+
+
+; do orginal APview_MT6765_disable_WDT.cmm
+LOCAL &BASE_MADDR_MDRGU
+&BASE_MADDR_MDRGU=0xA00F0000
+
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG 0x55000030
+
+
+
+PRINT "=============================="
+PRINT "config md_srclkena setting"
+PRINT "=============================="
+
+; /* Step 6 config md_srclkena setting */
+
+
+; /* (1) INFRA_MISC2 */
+&BASE_INFRACFG=(0xC0000000)
+; /* (2) SRCLKEN_O1 force on */
+&SPM_REG=(0xC0006000)
+
+
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(&BASE_INFRACFG+0x1F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+
+
+; /* (1) INFRA_MISC2 */
+; /* [3:0] : mdsrc_req_0_en = 4'b0001 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFFF0)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x1)
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFFF0)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x1)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFF0F)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x20)
+
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFF0F)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x20)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+; /* (2) SRCLKEN_O1 force on */
+; //MMRF request
+;D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+;D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x00215830 //set src clkena1 force on
+D.S &POWERON_CONFIG_EN %LE %LONG 0x0B160001
+D.S &SPM_POWER_ON_VAL1 %LE %LONG 0x00215830
+
+wait 1.ms
+
+
+
+PRINT "=============================="
+PRINT "config PLL setting"
+PRINT "=============================="
+
+; /* Step 5 config PLL setting */
+&BASE_MADDR_APMIXEDSYS=(0xC000C000)
+&BASE_MADDR_MDTOP_PLLMIXED=(0xA0140000)
+&BASE_MADDR_MDTOP_CLKSW=(0xA0150000)
+
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+®_MDTOP_PLLMIXED_MDTXPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x58)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0x84)
+
+&MD_PLL_MAGIC_NUM=(0x62930000)
+
+;;// initial CLKSQ_LPF
+&temp=data.long(AXI:®_APMIXEDSYS_AP_PLL_CON0)
+&temp=&temp|0x2
+d.s ®_APMIXEDSYS_AP_PLL_CON0 %long %le &temp
+;;// 100us
+wait 1.ms
+
+;;// Default md_srclkena_ack settle time = 136T 32K
+d.s ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E88
+
+;;// fixed 600MHz(/4), 343MHz(/7), 267MHz(/9) /* Fvco = 2400M */
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x801713B1
+;;// 300MHz /* Fvco = 2400M */
+d.s ®_MDTOP_PLLMIXED_MDTXPLL_CTL0 %long %le 0x80171400
+;;// 400MHz /* Fvco = 3600M */
+d.s ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80229E00
+;;// 672MHz /* Fvco = 3360M */
+d.s ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x80204E00
+;;// 864MHz /* Fvco = 3456M */
+d.s ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x80213C00
+
+;;// Polling until MDMCUPLL complete frequency adjustment
+;WHILE ((data.long(®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0
+;(
+;)
+wait 1.ms
+
+;;// Default disable BPI /7 clock
+&temp=data.long(®_MDTOP_PLLMIXED_MDBPIPLL_CTL1)
+&temp=&temp&(~0x80)
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL1 %long %le &temp
+
+;;/*TINFO="MDSYS_INIT: Update ABB MDPLL control register default value"*/
+d.s ®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x4C43100
+
+;;/* Force TXPLL ON due to TOPSM couldn't enable this PLL by default, TXPLL would be disable after DVFS Init.
+;; other PLL ON controlled by HW" */
+d.s ®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x100010
+
+;; /*
+;; * Wait MD bus clock ready
+;; * Once MD bus ready, other clock should be ready too
+;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+;; */
+;WHILE (data.long(®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000
+;(
+)
+wait 2.ms
+
+;;// Switch MDMCU & MD BUS clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x3)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch all clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x58103FC)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch SDF clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_SDF_CK_CTL)
+&temp=&temp|(0x10)
+d.s ®_MDTOP_CLKSW_SDF_CK_CTL %long %le &temp
+
+;;// Turn off all SW clock request, except ATB
+d.s ®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+;;// Mask all PLL ADJ RDY IRQ
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+;;// Make a record that means MD pll has been initialized.
+;;/* Note: We use "MD_PLL_MAGIC_NUM|0x1" to know PLL init in MD C code.
+;; If AP init PLL, it would be "MD_PLL_MAGIC_NUM". */
+d.s ®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+
+
+PRINT "=============================="
+PRINT "Set GPIO!"
+PRINT "=============================="
+;;////// Step 8: Set GPIO
+;;//// MD UART GPIO
+&BASE_ADDR_MDGPIO=0xC0005000
+&BASE_ADDR_IOCFG=0xC0002600
+D.S &BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_MDGPIO+0x420)&(0x00FFFFFF)
+D.S &BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_MDGPIO+0x420)|(0x55000000) ;//set GPIO150 to MD_URXD0 mode,set GPIO151 to MD_UTXD0 mode,
+D.S &BASE_ADDR_IOCFG+0x60 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x60)&(0xFF7FFFFF) ;//MD_URXD0 pull dowm disable
+D.S &BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)|(0x800000) ;//MD_URXD0 pull up enable
+D.S &BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)&(0xFEFFFFFF) ;//MD_UTXD0 pull up disable
+;;//// SIM GPIO
+;;// Clear bits
+d.s 0xC0005348 %long %le 0x77777000
+d.s 0xC0005358 %long %le 0x00000007
+;;// Set bits
+d.s 0xC0005344 %long %le 0x11111000
+d.s 0xC0005354 %long %le 0x00000001
+
+;;// SIM PUPD
+;;// Control PAD_SIM1_SIO PUPD pin. PUPD=0: pull up, PUPD=1: pull down.
+;;// Set bits
+d.s 0xC0002454 %long %le 0x00000FC0
+;;// Clear bits, SIO pull up
+d.s 0xC0002458 %long %le 0x00000480
+
+;;// SIM R1R0
+;;// R1R0=00:High-Z, R1R0=01:PU 45kohm;PD 75kohm,
+;;// R1R0=10:PU 5kohm;PD 75kohm, R1R0=11:PU 45kohm/5kohm;PD 75kohm/75kohm.
+;;// Set R1 bits
+d.s 0xC0002484 %long %le 0x00000FC0
+
+PRINT "=============================="
+PRINT "Set MD EMI Remap!"
+PRINT "=============================="
+
+
+;Step 10 set MD EMI remap address (MD view: step 9) ==>review done
+;d.s &MEM_CLASS:0xC0001300 %long %le 0x00430041
+;d.s &MEM_CLASS:0xC0001304 %long %le 0x00470045
+;d.s &MEM_CLASS:0xC0001308 %long %le 0x004b0049
+;d.s &MEM_CLASS:0xC000130c %long %le 0x004b0049
+D.S 0xC0001300 %LE %LONG 0x00430041
+D.S 0xC0001304 %LE %LONG 0x00470045
+D.S 0xC0001308 %LE %LONG 0x004b0049
+D.S 0xC000130c %LE %LONG 0x004b0049
+
+
+PRINT "=============================="
+PRINT "Set AP2MD PATH Disable!"
+PRINT "=============================="
+
+; do AP to MD path disable
+&BASE_ADDR_AP2MD_Dummy = 0xC0001370
+&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN=0x100012A0
+
+
+; Set reg_ap2md_dummy[0] = 1'b0
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp & 0xFFFFFFFE
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+; Set peri2md_protect_en
+; Write 0x1000_12A0[7] = 1'b1.
+; MD can access AP if reg_ap2md_dummy[0] = 1'b1,
+&temp=data.long(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN)
+&temp = &temp | 0x80
+D.S &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN %LE %LONG &temp
+wait 1.ms
+
+; Clear md2peri_protect_en
+; Write 0x1000_12AC[6] = 1'b1.
+&temp=data.long(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC)
+&temp = &temp | 0x40
+D.S &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp | 0x1
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+
+
+;Enalbe cache to speed loading
+steal monitor adapter_khz 2000
+
+PRINT "=============================="
+PRINT "Set MD Bus Way Disable!"
+PRINT "=============================="
+
+&BASE_ADDR_MDMCU_BUS_CONFIG = 0xA0330000
+
+&temp=data.long(&BASE_ADDR_MDMCU_BUS_CONFIG)
+&temp = &temp & 0xFFFFFFFD
+D.S &BASE_ADDR_MDMCU_BUS_CONFIG %LE %LONG &temp
+wait 1.ms
+
+PRINT "=============================="
+PRINT "Start to Load elf !"
+PRINT "=============================="
+
+thread.select 1
+steal source ../cmm/coretracer/single_core_basic_load_no_emi_codetracer_SPRAM.py
+
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+PRINT "=============================="
+PRINT "Load elf Done!"
+PRINT "=============================="
+
+thread.select 1
+
+;&t=var.address(INT_Initialize_Phase1)
+;wait 20.ms
+;stop
+;steal set $pc = &INT_Initialize_Phase1
+;register.set pc &t
+
+;PRINT "=============================="
+;PRINT "Set PC to INT_Initialize_Phase1: &t"
+;PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/MT6765_EVB_Load_MD_Elf_With_SPRAM.cmm.bak b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/MT6765_EVB_Load_MD_Elf_With_SPRAM.cmm.bak
new file mode 100644
index 0000000..37deb4f
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/MT6765_EVB_Load_MD_Elf_With_SPRAM.cmm.bak
@@ -0,0 +1,330 @@
+;sys.m prepare
+;LOCAL &TYPE
+
+
+system.mode attach
+
+; configure GCR_ACCESS Register
+; CoreTracer will access MO port via CPU to do following configuration
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+
+
+
+; do orginal APview_MT6765_disable_WDT.cmm
+LOCAL &BASE_MADDR_MDRGU
+&BASE_MADDR_MDRGU=0xA00F0000
+
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG 0x55000030
+
+
+
+PRINT "=============================="
+PRINT "config md_srclkena setting"
+PRINT "=============================="
+
+; /* Step 6 config md_srclkena setting */
+
+
+; /* (1) INFRA_MISC2 */
+&BASE_INFRACFG=(0xC0000000)
+; /* (2) SRCLKEN_O1 force on */
+&SPM_REG=(0xC0006000)
+
+
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(&BASE_INFRACFG+0x1F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+
+
+; /* (1) INFRA_MISC2 */
+; /* [3:0] : mdsrc_req_0_en = 4'b0001 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFFF0)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x1)
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFFF0)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x1)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFF0F)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x20)
+
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFF0F)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x20)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+; /* (2) SRCLKEN_O1 force on */
+; //MMRF request
+;D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+;D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x00215830 //set src clkena1 force on
+D.S &POWERON_CONFIG_EN %LE %LONG 0x0B160001
+D.S &SPM_POWER_ON_VAL1 %LE %LONG 0x00215830
+
+wait 1.ms
+
+
+
+PRINT "=============================="
+PRINT "config PLL setting"
+PRINT "=============================="
+
+; /* Step 5 config PLL setting */
+&BASE_MADDR_APMIXEDSYS=(0xC000C000)
+&BASE_MADDR_MDTOP_PLLMIXED=(0xA0140000)
+&BASE_MADDR_MDTOP_CLKSW=(0xA0150000)
+
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+®_MDTOP_PLLMIXED_MDTXPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x58)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0x84)
+
+&MD_PLL_MAGIC_NUM=(0x62930000)
+
+;;// initial CLKSQ_LPF
+&temp=data.long(AXI:®_APMIXEDSYS_AP_PLL_CON0)
+&temp=&temp|0x2
+d.s ®_APMIXEDSYS_AP_PLL_CON0 %long %le &temp
+;;// 100us
+wait 1.ms
+
+;;// Default md_srclkena_ack settle time = 136T 32K
+d.s ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E88
+
+;;// fixed 600MHz(/4), 343MHz(/7), 267MHz(/9) /* Fvco = 2400M */
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x801713B1
+;;// 300MHz /* Fvco = 2400M */
+d.s ®_MDTOP_PLLMIXED_MDTXPLL_CTL0 %long %le 0x80171400
+;;// 400MHz /* Fvco = 3600M */
+d.s ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80229E00
+;;// 672MHz /* Fvco = 3360M */
+d.s ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x80204E00
+;;// 864MHz /* Fvco = 3456M */
+d.s ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x80213C00
+
+;;// Polling until MDMCUPLL complete frequency adjustment
+;WHILE ((data.long(®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0
+;(
+;)
+wait 1.ms
+
+;;// Default disable BPI /7 clock
+&temp=data.long(®_MDTOP_PLLMIXED_MDBPIPLL_CTL1)
+&temp=&temp&(~0x80)
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL1 %long %le &temp
+
+;;/*TINFO="MDSYS_INIT: Update ABB MDPLL control register default value"*/
+d.s ®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x4C43100
+
+;;/* Force TXPLL ON due to TOPSM couldn't enable this PLL by default, TXPLL would be disable after DVFS Init.
+;; other PLL ON controlled by HW" */
+d.s ®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x100010
+
+;; /*
+;; * Wait MD bus clock ready
+;; * Once MD bus ready, other clock should be ready too
+;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+;; */
+;WHILE (data.long(®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000
+;(
+)
+wait 2.ms
+
+;;// Switch MDMCU & MD BUS clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x3)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch all clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x58103FC)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch SDF clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_SDF_CK_CTL)
+&temp=&temp|(0x10)
+d.s ®_MDTOP_CLKSW_SDF_CK_CTL %long %le &temp
+
+;;// Turn off all SW clock request, except ATB
+d.s ®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+;;// Mask all PLL ADJ RDY IRQ
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+;;// Make a record that means MD pll has been initialized.
+;;/* Note: We use "MD_PLL_MAGIC_NUM|0x1" to know PLL init in MD C code.
+;; If AP init PLL, it would be "MD_PLL_MAGIC_NUM". */
+d.s ®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+
+
+PRINT "=============================="
+PRINT "Set GPIO!"
+PRINT "=============================="
+;;////// Step 8: Set GPIO
+;;//// MD UART GPIO
+&BASE_ADDR_MDGPIO=0xC0005000
+&BASE_ADDR_IOCFG=0xC0002600
+D.S &BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x420)&(0x00FFFFFF)
+D.S &BASE_ADDR_MDGPIO+0x420 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x420)|(0x55000000) //set GPIO150 to MD_URXD0 mode,set GPIO151 to MD_UTXD0 mode,
+D.S &BASE_ADDR_IOCFG+0x60 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x60)&(0xFF7FFFFF) //MD_URXD0 pull dowm disable
+D.S &BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)|(0x800000) //MD_URXD0 pull up enable
+D.S &BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)&(0xFEFFFFFF) //MD_UTXD0 pull up disable
+;;//// SIM GPIO
+;;// Clear bits
+d.s 0xC0005348 %long %le 0x77777000
+d.s 0xC0005358 %long %le 0x00000007
+;;// Set bits
+d.s 0xC0005344 %long %le 0x11111000
+d.s 0xC0005354 %long %le 0x00000001
+
+;;// SIM PUPD
+;;// Control PAD_SIM1_SIO PUPD pin. PUPD=0: pull up, PUPD=1: pull down.
+;;// Set bits
+d.s 0xC0002454 %long %le 0x00000FC0
+;;// Clear bits, SIO pull up
+d.s 0xC0002458 %long %le 0x00000480
+
+;;// SIM R1R0
+;;// R1R0=00:High-Z, R1R0=01:PU 45kohm;PD 75kohm,
+;;// R1R0=10:PU 5kohm;PD 75kohm, R1R0=11:PU 45kohm/5kohm;PD 75kohm/75kohm.
+;;// Set R1 bits
+d.s 0xC0002484 %long %le 0x00000FC0
+PRINT "=============================="
+PRINT "Set MD EMI Remap!"
+PRINT "=============================="
+
+
+;Step 10 set MD EMI remap address (MD view: step 9) ==>review done
+;d.s &MEM_CLASS:0xC0001300 %long %le 0x00430041
+;d.s &MEM_CLASS:0xC0001304 %long %le 0x00470045
+;d.s &MEM_CLASS:0xC0001308 %long %le 0x004b0049
+;d.s &MEM_CLASS:0xC000130c %long %le 0x004b0049
+D.S 0xC0001300 %LE %LONG 0x00430041
+D.S 0xC0001304 %LE %LONG 0x00470045
+D.S 0xC0001308 %LE %LONG 0x004b0049
+D.S 0xC000130c %LE %LONG 0x004b0049
+
+
+PRINT "=============================="
+PRINT "Set AP2MD PATH Disable!"
+PRINT "=============================="
+
+; do AP to MD path disable
+&BASE_ADDR_AP2MD_Dummy = 0xC0001370
+&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN=0x100012A0
+
+
+; Set reg_ap2md_dummy[0] = 1'b0
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp & 0xFFFFFFFE
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+; Set peri2md_protect_en
+; Write 0x1000_12A0[7] = 1'b1.
+; MD can access AP if reg_ap2md_dummy[0] = 1'b1,
+&temp=data.long(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN)
+&temp = &temp | 0x80
+D.S &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN %LE %LONG &temp
+wait 1.ms
+
+; Clear md2peri_protect_en
+; Write 0x1000_12AC[6] = 1'b1.
+&temp=data.long(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC)
+&temp = &temp | 0x40
+D.S &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp | 0x1
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+
+
+;Enalbe cache to speed loading
+steal monitor adapter_khz 2000
+
+PRINT "=============================="
+PRINT "Set MD Bus Way Disable!"
+PRINT "=============================="
+
+&BASE_ADDR_MDMCU_BUS_CONFIG = 0xA0330000
+
+&temp=data.long(&BASE_ADDR_MDMCU_BUS_CONFIG)
+&temp = &temp & 0xFFFFFFFD
+D.S &BASE_ADDR_MDMCU_BUS_CONFIG %LE %LONG &temp
+wait 1.ms
+
+PRINT "=============================="
+PRINT "Start to Load elf !"
+PRINT "=============================="
+
+thread.select 1
+steal source ../cmm/coretracer/single_core_basic_load_no_emi_codetracer_SPRAM.py
+
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+PRINT "=============================="
+PRINT "Load elf Done!"
+PRINT "=============================="
+
+thread.select 1
+
+;&t=var.address(INT_Initialize_Phase1)
+;wait 20.ms
+;stop
+;steal set $pc = &INT_Initialize_Phase1
+;register.set pc &t
+
+;PRINT "=============================="
+;PRINT "Set PC to INT_Initialize_Phase1: &t"
+;PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/MT6765_MD_Only.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/MT6765_MD_Only.cmm
new file mode 100644
index 0000000..6b7df8c
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/MT6765_MD_Only.cmm
@@ -0,0 +1,52 @@
+;AP pmic workaround
+&MEM_CLASS="AXI"
+sys.m prepare
+wait 1.ms
+
+; Step 1 (AP CCCI only) Configure AP/MD shared buck through DVFSRC API
+; [Note] CVD script do NOT need this step
+; skip
+
+; Step 3 config MD related Buck
+; [Note] CVD script do NOT need this step
+; AP preloader should set Modem related buck
+; skip
+
+; Step 4 power on MTCMOS
+; [Note] CVD script do NOT need this step
+; skip
+
+; Step 5 disable MD access register
+do APview_MT6765_MD2PERI_disable.cmm
+
+; Step 6 config md_srclkena setting
+do APview_MT6765_md_srclkena.cmm
+
+; Step 7 config PLL setting
+do APview_MT6765_MD_PLL_Init.cmm
+
+; Step 8 Disable MD WDT
+do APview_MT6765_disable_WDT.cmm
+
+; Step 9 enable MD to Access AP Register
+do APview_MT6765_AP2MD_enable.cmm
+
+; Step 10 Trigger MD MCU to run (AP view)
+; [Note] Trigger MD MCU by debugger
+; skip
+
+; Step 11 set GPIO (MD view: step 7)
+do APview_MT6765_GPIO_MDUART0.cmm
+do APview_MT6765_GPIO_SIM.cmm
+
+;Step 12 Force on Debug Sys clock (MD view: step 8)
+;do APview_MT6765_MD_ForceOnDebugSys.cmm
+
+;Step 13 set MD EMI remap address (MD view: step 9)
+d.s &MEM_CLASS:0x10001300 %long %le 0x00430041
+d.s &MEM_CLASS:0x10001304 %long %le 0x00470045
+d.s &MEM_CLASS:0x10001308 %long %le 0x004b0049
+d.s &MEM_CLASS:0x1000130c %long %le 0x004f004d
+
+; Final Step: Trigger MD MCU to run
+; skip
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/L1Bypass.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/L1Bypass.act
new file mode 100644
index 0000000..a3c4b52
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/L1Bypass.act
@@ -0,0 +1,6 @@
+<?xml version="1.0"?>
+<Customize>
+ <Action name="L1AssertBypass" icon="">
+ <GDB>p/x L1_ASSERT_BYPASS=3</GDB>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/LoadDSPBin.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/LoadDSPBin.cmm
new file mode 100644
index 0000000..08b4a8c
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/LoadDSPBin.cmm
@@ -0,0 +1,17 @@
+system.mode attach
+
+register.set cdmmbase 0x1fc1407
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor mips32 fastchannel 0 1
+
+&temp_addr = var.address(dsp_bin_ro)
+&temp_addr = &temp_addr & 0x0FFFFFFF
+;&temp_addr = &temp_addr | 0xA0000000
+
+;data.load.bin U:\MT6292\UMOLYA\DEV\UMOLYA.BIANCO.BRINGUP.DEV\mcu\build\BIANCO_FPGA\L1S_L1DISABLE\bin\DSP_BIANCO_UMOLYA_BIANCO_BRINGUP_DEV_W17_04_LTE_P3.bin &temp_addr
+data.load.bin "D:\dsp123.bin" &temp_addr
+
+print "load dsp done!"
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+enddo
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/L1Bypass.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/L1Bypass.act
new file mode 100644
index 0000000..a3c4b52
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/L1Bypass.act
@@ -0,0 +1,6 @@
+<?xml version="1.0"?>
+<Customize>
+ <Action name="L1AssertBypass" icon="">
+ <GDB>p/x L1_ASSERT_BYPASS=3</GDB>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_AllIn1_LoadCode.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_AllIn1_LoadCode.launch
new file mode 100644
index 0000000..c4be7e6
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_AllIn1_LoadCode.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.cacheFile" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearExpression" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.LocalTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<intAttribute key="com.mediatek.ide.util.gdbPortNumber" value="3333"/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<stringAttribute key="com.mediatek.ide.util.ipAddress" value="localhost"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value="hb general_ex_handler"/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value="[CMMAUTOGEN_ROOT]"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="MT6293_Chip"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_AllIn1_LoadCode_With_DSP.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_AllIn1_LoadCode_With_DSP.launch
new file mode 100644
index 0000000..526e5a7
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_AllIn1_LoadCode_With_DSP.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.cacheFile" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearExpression" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.LocalTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<intAttribute key="com.mediatek.ide.util.gdbPortNumber" value="3333"/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<stringAttribute key="com.mediatek.ide.util.ipAddress" value="localhost"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value="hb general_ex_handler source ../cmm/coretracer/config/easyLoader/load_dsp.py"/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value="[CMMAUTOGEN_ROOT]"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="MT6293_Chip"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_AllIn1_LoadCode_non_halt.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_AllIn1_LoadCode_non_halt.launch
new file mode 100644
index 0000000..a215b4c
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_AllIn1_LoadCode_non_halt.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.cacheFile" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearExpression" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.LocalTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<intAttribute key="com.mediatek.ide.util.gdbPortNumber" value="3333"/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<stringAttribute key="com.mediatek.ide.util.ipAddress" value="localhost"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value="[CMMAUTOGEN_ROOT]"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="MT6293_Chip"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_AllIn1_LoadSymbol.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_AllIn1_LoadSymbol.launch
new file mode 100644
index 0000000..9efd844
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_AllIn1_LoadSymbol.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.cacheFile" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearExpression" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.LocalTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<intAttribute key="com.mediatek.ide.util.gdbPortNumber" value="3333"/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<stringAttribute key="com.mediatek.ide.util.ipAddress" value="localhost"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value="hb general_ex_handler hb INT_TEMP_general_ex_vector"/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value="[CMMAUTOGEN_ROOT]"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="MT6293_Chip"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
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diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_AllIn1_LoadSymbol_SPRAM.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_AllIn1_LoadSymbol_SPRAM.launch
new file mode 100644
index 0000000..f2b3528
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_AllIn1_LoadSymbol_SPRAM.launch
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diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_AllIn1_LoadSymbol_SPRAM.launch.bak b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_AllIn1_LoadSymbol_SPRAM.launch.bak
new file mode 100644
index 0000000..68d7768
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_AllIn1_LoadSymbol_SPRAM.launch.bak
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diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_AllIn1_LoadSymbol_non_halt.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_AllIn1_LoadSymbol_non_halt.launch
new file mode 100644
index 0000000..9df1701
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_AllIn1_LoadSymbol_non_halt.launch
@@ -0,0 +1,54 @@
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diff --git "a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadCode\0501\051.launch" "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadCode\0501\051.launch"
new file mode 100644
index 0000000..085a113
--- /dev/null
+++ "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadCode\0501\051.launch"
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diff --git "a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadCode\0502\051.launch" "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadCode\0502\051.launch"
new file mode 100644
index 0000000..05c2643
--- /dev/null
+++ "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadCode\0502\051.launch"
@@ -0,0 +1,54 @@
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diff --git "a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadCode\0503\051.launch" "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadCode\0503\051.launch"
new file mode 100644
index 0000000..a9756e3
--- /dev/null
+++ "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadCode\0503\051.launch"
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadCode.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadCode.launch
new file mode 100644
index 0000000..4a03a4a
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadCode.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadCode_All.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadCode_All.launch
new file mode 100644
index 0000000..9a9d267
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadCode_All.launch
@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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diff --git "a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadSymbol\0501\051.launch" "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadSymbol\0501\051.launch"
new file mode 100644
index 0000000..085a113
--- /dev/null
+++ "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadSymbol\0501\051.launch"
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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diff --git "a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadSymbol\0502\051.launch" "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadSymbol\0502\051.launch"
new file mode 100644
index 0000000..05c2643
--- /dev/null
+++ "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadSymbol\0502\051.launch"
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.cacheFile" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearExpression" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.RemoteTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<intAttribute key="com.mediatek.ide.util.gdbPortNumber" value="3668"/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<stringAttribute key="com.mediatek.ide.util.ipAddress" value="localhost"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value="hb general_ex_handler"/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value="[CMMAUTOGEN_ROOT]"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="Zion_evb_amp"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="attach"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git "a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadSymbol\0503\051.launch" "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadSymbol\0503\051.launch"
new file mode 100644
index 0000000..a9756e3
--- /dev/null
+++ "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadSymbol\0503\051.launch"
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.cacheFile" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearExpression" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.RemoteTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<intAttribute key="com.mediatek.ide.util.gdbPortNumber" value="3669"/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<stringAttribute key="com.mediatek.ide.util.ipAddress" value="localhost"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value="hb general_ex_handler"/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value="[CMMAUTOGEN_ROOT]"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="Zion_evb_amp"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="attach"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadSymbol.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadSymbol.launch
new file mode 100644
index 0000000..813e482
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadSymbol.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.cacheFile" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearExpression" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.RemoteTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<intAttribute key="com.mediatek.ide.util.gdbPortNumber" value="3666"/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<stringAttribute key="com.mediatek.ide.util.ipAddress" value="localhost"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value="hb general_ex_handler"/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value="[CMMAUTOGEN_ROOT]"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="Zion_evb_amp"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="attach"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadSymbol_All.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadSymbol_All.launch
new file mode 100644
index 0000000..1f510f6
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/MT6765_Alone_LoadSymbol_All.launch
@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.group.launchConfigurationType">
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.name" value="MT6765_Alone_LoadSymbol"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.name" value="MT6765_Alone_LoadSymbol(1)"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.name" value="MT6765_Alone_LoadSymbol(2)"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.name" value="MT6765_Alone_LoadSymbol(3)"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/easyLoader/CoreTracer_easy_loader.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/easyLoader/CoreTracer_easy_loader.py
new file mode 100644
index 0000000..cc2c2fe
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/easyLoader/CoreTracer_easy_loader.py
@@ -0,0 +1,149 @@
+#from imgtec import codescape
+import sys
+import time
+import os
+import gdb
+import Tkinter, tkFileDialog
+
+#get full path of python script
+file_path = os.path.dirname(os.path.abspath(__file__))
+#append python path into system path
+sys.path.append(file_path)
+
+import load_dsp
+
+app = None
+
+# load all elf
+def load_all_elf(elf_path):
+ time_str = time.time()
+ print "=== Start Loading ELF ==="
+ print "Image path: " + elf_path
+ if(os.path.exists(elf_path) == False):
+ print "[Error] UMOLY ELF doesn't exist: %s" %(elf_path)
+ else:
+ elf_path = elf_path.replace('\\', '/')
+ gdb_cmd = 'symbol-file '+ elf_path
+ print gdb_cmd
+ gdb.execute(gdb_cmd)
+ print "Load SYMBOL successfully"
+ # Add debug point
+ gdb_cmd = 'hb general_ex_vector'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'lo '+ elf_path
+ print gdb_cmd
+ gdb.execute(gdb_cmd)
+ print "Load ELF successfully"
+ time_end = time.time()
+ print("All loading is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+# load all symbol only
+def load_all_sym(elf_path):
+ time_str = time.time()
+ print "=== Start Loading SYMBOL ==="
+ print "Image path: " + elf_path
+ if(os.path.exists(elf_path) == False):
+ print "[Error] UMOLY ELF doesn't exist: %s" %(elf_path)
+ else:
+ elf_path = elf_path.replace('\\', '/')
+ gdb_cmd = 'symbol-file '+ elf_path
+ print gdb_cmd
+ gdb.execute(gdb_cmd)
+ print "Load SYMBOL successfully"
+ # Add debug point
+ gdb_cmd = 'hb general_ex_vector'
+ gdb.execute(gdb_cmd)
+ time_end = time.time()
+ print("All loading is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+# load dsp bin file
+#def load_dsp_bin(dsp_path):
+# time_str = time.time()
+# print "=== Start load dsp bin ==="
+# print "Dsp bin path: " + dsp_path
+# if(os.path.exists(dsp_path) == False):
+# print "[Error] UMOLY DSP binary doesn't exist: %s" %(dsp_path)
+# else:
+# gdb_cmd='thread 1'
+# gdb.execute(gdb_cmd)
+# ## a) need parsing: 0x13a0000 <dsp_bin_ro>
+# ##symbol_name='&dsp_bin_ro'
+# ##dsp_addr = gdb.parse_and_eval(symbol_name)
+# ## b) need parsing: $3 = 0x13a0000
+# ##gdb_cmd='p/x &dsp_bin_ro'
+# ##dsp_addr = gdb.execute(gdb_cmd, False, True)
+# symbol_name='dsp_bin_ro'
+# dsp_addr = gdb.parse_and_eval(symbol_name)
+# dsp_addr = str(dsp_addr.address).split(" ")
+# gdb_cmd = 'restore ' + dsp_path + ' binary ' + str(dsp_addr[0])
+# print gdb_cmd
+# gdb.execute(gdb_cmd)
+# time_end = time.time()
+# print("loading dsp is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+def thread_memory_Write(mem_addr, set_value):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def thread_memory_Read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ mem_value = mem_value[12:23]
+ hex_int = int(mem_value, 16)
+ return hex_int
+
+
+class gui_tk(Tkinter.Tk):
+ def __init__(self, parent):
+ Tkinter.Tk.__init__(self, parent)
+ elf_path = ""
+ dsp_path = ""
+ dsp_addr = ""
+ self.file_opt = options = {}
+ options['title'] = 'Choose a file'
+ self.parent = parent
+ self.initialize()
+
+ def initialize(self):
+ self.grid()
+ elf_button = Tkinter.Button(self, text=u"Load elf", command=self.elf_OnButtonClick)
+ elf_button.grid(column=0, row=1, sticky='W')
+
+ sym_button = Tkinter.Button(self, text=u"Load symbol", command=self.sym_OnButtonClick)
+ sym_button.grid(column=0, row=2, sticky='W')
+
+ dsp_button = Tkinter.Button(self, text=u"Load DSP bin", command=self.dsp_OnButtonClick)
+ dsp_button.grid(column=0, row=3, sticky='W')
+
+ def elf_OnButtonClick(self):
+ elf_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(elf_path) > 0:
+ print "You chose %s" % elf_path
+ load_all_elf(elf_path)
+ self.quit()
+
+ def sym_OnButtonClick(self):
+ elf_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(elf_path) > 0:
+ print "You chose %s" % elf_path
+ load_all_sym(elf_path)
+ self.quit()
+
+ def dsp_OnButtonClick(self):
+ dsp_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(dsp_path) > 0:
+ print "You chose %s" % dsp_path
+ load_dsp.load_dsp_bin(dsp_path)
+ self.quit()
+
+ def quit(self):
+ global app
+ print "=== Close Easy Loader ==="
+ app.destroy()
+
+if __name__ == "__main__":
+ print "=== Start Easy Loader ==="
+ app = gui_tk(None)
+ app.title('Easy Loader')
+ app.mainloop()
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/easyLoader/load_dsp.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/easyLoader/load_dsp.py
new file mode 100644
index 0000000..86e47fa
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/config/easyLoader/load_dsp.py
@@ -0,0 +1,106 @@
+#from imgtec import codescape
+import sys
+import time
+import os
+import gdb
+import binascii
+import Tkinter, tkFileDialog
+
+app = None
+dsp_header = 0x0
+dsp_magic = "4d4d4d01"
+
+# load dsp bin file
+def load_dsp_bin(dsp_path):
+ global dsp_header
+ time_str = time.time()
+ print "=== Start load dsp bin ==="
+ print "Dsp bin path: " + dsp_path
+ if(os.path.exists(dsp_path) == False):
+ print "DSP bin doesn't exist: %s" %(dsp_path)
+ print "[Error] Load DSP bin failed"
+ return
+ else:
+ with open(dsp_path, "rb") as dsp_bin:
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print "No header detected, continue"
+ else:
+ dsp_header = 0x200
+ dsp_bin.seek(dsp_header, os.SEEK_SET)
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print "Header detected, skip first 512B"
+ else:
+ print "DSP header detected at neither 0x0 nor 0x200"
+ print "Please check the bin is legal!"
+ print "[Error] Load DSP bin failed"
+ return
+ gdb_cmd='thread 1'
+ gdb.execute(gdb_cmd)
+ ## a) need parsing: 0x13a0000 <dsp_bin_ro>
+ ##symbol_name='&dsp_bin_ro'
+ ##dsp_addr = gdb.parse_and_eval(symbol_name)
+ ## b) need parsing: $3 = 0x13a0000
+ ##gdb_cmd='p/x &dsp_bin_ro'
+ ##dsp_addr = gdb.execute(gdb_cmd, False, True)
+ symbol_name='dsp_bin_ro'
+ dsp_addr = gdb.parse_and_eval(symbol_name)
+ dsp_addr = str(dsp_addr.address).split(" ")
+ dsp_addr = int(dsp_addr[0], 16) - dsp_header
+ print hex(dsp_addr)
+ gdb_cmd = 'monitor mips32 fastchannel 0 1'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'set $cdmmbase=0x1fc1407'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'set *0x1fc100d4=0x02030202'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = " ".join(['restore', dsp_path, 'binary', hex(dsp_addr), hex(dsp_header)])
+ print gdb_cmd
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'set *0x1fc100d4=0x02020202'
+ gdb.execute(gdb_cmd)
+ time_end = time.time()
+ print("loading dsp is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+
+class gui_tk(Tkinter.Tk):
+ def __init__(self, parent):
+ Tkinter.Tk.__init__(self, parent)
+ elf_path = ""
+ dsp_path = ""
+ dsp_addr = ""
+ self.file_opt = options = {}
+ options['title'] = 'Choose a file'
+ self.parent = parent
+ self.initialize()
+
+ def initialize(self):
+ self.grid()
+
+ dsp_button = Tkinter.Button(self, text=u"Load DSP bin =>", command=self.dsp_OnButtonClick)
+ dsp_button.grid(column=0, row=4, sticky='W')
+
+ def dsp_OnButtonClick(self):
+ dsp_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(dsp_path) > 0:
+ print "You chose %s" % dsp_path
+ load_dsp_bin(dsp_path)
+ self.quit()
+
+ def quit(self):
+ global app
+ print "=== Close Easy Loader ==="
+ app.destroy()
+
+def load_dsp_gui():
+ print "=== Start Easy Loader ==="
+ global app
+ app = gui_tk(None)
+ app.title('Easy Loader')
+ app.mainloop()
+
+
+if __name__ == "__main__":
+ load_dsp_gui()
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/single_core_basic_load_no_emi_codetracer_SPRAM.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/single_core_basic_load_no_emi_codetracer_SPRAM.py
new file mode 100644
index 0000000..f7458ff
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/coretracer/single_core_basic_load_no_emi_codetracer_SPRAM.py
@@ -0,0 +1,504 @@
+# <$ Name: Region Script $>
+
+import struct
+import re
+#import wx
+import os
+import time
+##import CSUtils
+##from imgtec import codescape
+from time import sleep
+##from CSUtils import DA
+import gdb
+import io
+import sys
+import Tkinter, tkFileDialog
+
+def get_selected_inferior():
+ """
+ Return the selected inferior in gdb.
+ """
+ # Woooh, another bug in gdb! Is there an end in sight?
+ # http://sourceware.org/bugzilla/show_bug.cgi?id=12212
+ return gdb.inferiors()[0]
+
+ selected_thread = gdb.selected_thread()
+
+ for inferior in gdb.inferiors():
+ for thread in inferior.threads():
+ if thread == selected_thread:
+ return inferior
+
+class gui_tk(Tkinter.Tk):
+ elf_path = ""
+ sym_path = ""
+ def __init__(self, parent):
+ Tkinter.Tk.__init__(self, parent)
+ self.file_opt = options = {}
+ options['title'] = 'Choose ELF and sym file'
+ self.parent = parent
+ self.initialize()
+
+ def initialize(self):
+ self.grid()
+ global elf_addr_entry
+ elf_addr_entry = Tkinter.Entry(self)
+ elf_addr_entry.grid(column=1, row=3)
+ elf_addr_entry.insert(20, "Choose ELF and sym")
+
+ elf_button = Tkinter.Button(self, text=u"Choose ELF file", command=self.elf_OnButtonClick)
+ elf_button.grid(column=0, row=4, sticky='W')
+
+ sym_button = Tkinter.Button(self, text=u"Choose sym file", command=self.sym_OnButtonClick)
+ sym_button.grid(column=2, row=4, sticky='W')
+
+ load_button = Tkinter.Button(self, text=u"Load all", command=self.load_OnButtonClick)
+ load_button.grid(column=4, row=4, sticky='W')
+
+ def elf_OnButtonClick(self):
+ self.elf_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(self.elf_path) > 0:
+ print "ELF file: %s" % self.elf_path
+
+ def sym_OnButtonClick(self):
+ self.sym_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(self.sym_path) > 0:
+ print "sym file: %s" % self.sym_path
+
+ def load_OnButtonClick(self):
+ self.load_all_elf()
+
+ def load_all_elf(self):
+ if(os.path.exists(self.elf_path) == False):
+ print "[Error] ELF doesn't exist: %s" %(self.elf_path)
+ return
+ else:
+ print "Using ELD file: %s" %(self.elf_path)
+
+ if(os.path.exists(self.sym_path) == False):
+ print "[Error] sym file doesn't exist: %s" %(self.sym_path)
+ return
+ else:
+ print "Using sym file: %s" %(self.sym_path)
+
+ regexp_spram = r'(\s*)(\d*)(\s*)(.SPRAM\d)(\s*)([a-fA-F\d]+)(\s*)([a-fA-F\d]+)(\s*)([a-fA-F\d]+)(\s*)([a-fA-F\d]+)(.*)'
+ pattern_spram = re.compile(regexp_spram)
+
+ regexp_spram_zi = r'(\s*)(\d*)(\s*)(.SPRAM\d_ZI)(\s*)([a-fA-F\d]+)(\s*)([a-fA-F\d]+)(\s*)([a-fA-F\d]+)(\s*)([a-fA-F\d]+)(.*)'
+ pattern_spram_zi= re.compile(regexp_spram_zi)
+
+ regexp_rom = r'(\s*)(\d*)(\s*)(EXTSRAM)(\s*)([a-fA-F\d]+)(\s*)([a-fA-F\d]+)(\s*)([a-fA-F\d]+)(\s*)([a-fA-F\d]+)(.*)'
+ pattern_rom = re.compile(regexp_rom)
+
+ regexp_extsram_zi = r'(\s*)(\d*)(\s*)(EXTSRAM_ZI)(\s*)([a-fA-F\d]+)(\s*)([a-fA-F\d]+)(\s*)([a-fA-F\d]+)(\s*)([a-fA-F\d]+)(.*)'
+ pattern_extsram_zi = re.compile(regexp_extsram_zi)
+
+ ispram_size = [0,0]
+ ispram_load_size = [0,0]
+ ispram_offset = [0,0]
+ ispram_addr = [0,0]
+
+ dspram_size = [0,0]
+ dspram_load_size = [0,0]
+ dspram_load_addr = [0,0]
+ dspram_offset = [0,0]
+ dspram_addr = [0,0]
+
+ dspram_zi_size = [0,0]
+ dspram_zi_addr = [0,0]
+
+ print "Finding ROM"
+ with open(self.sym_path,'r') as sym_file:
+ for line in sym_file:
+ if " EXTSRAM " in line:
+ p = pattern_rom.search(line)
+ load_size = int(p.group(6),16)
+ load_addr = int(p.group(8),16)
+ load_offset = int(p.group(12),16)
+ break
+ if load_size != 0:
+ print "ROM found at offset: 0x%x, load address: 0x%x, size %d bytes" %(load_offset, load_addr, load_size)
+ else:
+ print "ROM is empty!"
+
+ print "Finding EXTSRAM_ZI"
+ with open(self.sym_path,'r') as sym_file:
+ for line in sym_file:
+ if " EXTSRAM_ZI " in line:
+ p = pattern_extsram_zi.search(line)
+ load_zi_size = int(p.group(6),16)
+ load_zi_addr = int(p.group(8),16)
+ break
+ if load_size != 0:
+ print "EXTSRAM_ZI found, address: 0x%x, size %d bytes" %(load_zi_addr, load_zi_size)
+ else:
+ print "EXTSRAM_ZI is empty!"
+
+ print "Finding ISPRAM"
+ with open(self.sym_path,'r') as sym_file:
+ for core_idx in range(0, 2):
+ for line in sym_file:
+ if "ISPRAM0A" in line:
+ continue
+ if "ISPRAM0B" in line:
+ continue
+ if "ISPRAM0C" in line:
+ continue
+ if "ISPRAM" + str(core_idx) in line:
+ p = pattern_spram.search(line)
+ ispram_load_size[core_idx] = int(p.group(6),16)
+ ispram_offset[core_idx] = int(p.group(12),16)
+ break
+ if ispram_load_size[core_idx] != 0:
+ print "ISPRAM%d found at offset: 0x%x, size %d bytes" %(core_idx, ispram_offset[core_idx], ispram_load_size[core_idx])
+ else:
+ print "ISPRAM%d is empty" %(core_idx)
+
+ print "Finding DSPRAM"
+ with open(self.sym_path,'r') as sym_file:
+ for core_idx in range(0, 2):
+ for line in sym_file:
+ if "DSPRAM" + str(core_idx) in line:
+ p = pattern_spram.search(line)
+ dspram_load_size[core_idx] = int(p.group(6),16)
+ dspram_load_addr[core_idx] = int(p.group(8),16)
+ dspram_offset[core_idx] = int(p.group(12),16)
+ break
+ if dspram_load_size[core_idx] != 0:
+ print "DSPRAM%d found at offset: 0x%x, size %d bytes" %(core_idx, dspram_offset[core_idx], dspram_load_size[core_idx])
+ else:
+ print "DSPRAM%d is empty" %(core_idx)
+
+ print "Finding DSPRAM_ZI"
+ with open(self.sym_path,'r') as sym_file:
+ for core_idx in range(0, 2):
+ for line in sym_file:
+ if "DSPRAM" + str(core_idx) + "_ZI" in line:
+ p = pattern_spram_zi.search(line)
+ dspram_zi_size[core_idx] = int(p.group(6),16)
+ dspram_zi_addr[core_idx] = int(p.group(8),16)
+ break
+ if dspram_zi_size[core_idx] != 0:
+ print "DSPRAM%d_ZI found, address 0x%x, size %d bytes" %(core_idx, dspram_zi_addr[core_idx], dspram_zi_size[core_idx])
+ else:
+ print "DSPRAM%d_ZI is empty" %(core_idx)
+
+ gdb.execute('thread 1')
+ # load binary only on VPE0 of 0 core
+ gdb.execute('set *0x1F000020=0xF')
+ gdb.execute('set *0x1F000090=0xA0000000')
+ gdb.execute('set *0x1F000098=0xE0000002')
+ gdb.execute('set *0x1F0000A0=0xC0000000')
+ gdb.execute('set *0x1F0000A8=0xC0000002')
+ gdb.execute('set *0xA0060060=0x03231111')
+
+ # SPRAM1 L2 override to UC
+ gdb.execute('set *0x1F0000C0=0x9F200000')
+ gdb.execute('set *0x1F0000C8=0xFFE00055')
+ # L2 override to Cached
+ gdb.execute('set *0x1F0000B0=0x90000000')
+ gdb.execute('set *0x1F0000B8=0xFFE00071')
+
+ # Diable WDT
+ print("WDT disable ...")
+ mdrgu = (int((gdb.parse_and_eval('*0xA00F0100'))) & 0xFFFFFFFC) | 0x55000000
+ aprgu = (int((gdb.parse_and_eval('*0xC3670100'))) & 0xFFFFFFFE) | 0x55000000
+ gdb.execute('set *0xA00F0100=0x{0:x}'.format(mdrgu))
+ gdb.execute('set *0xC3670100=0x{0:x}'.format(aprgu))
+
+ gdb.execute('set *0x1F000060=0x1E000001')
+
+ ispram_size[0] = 180*1024
+ dspram_size[0] = 36*1024
+ ispram_size[1] = 144*1024
+ dspram_size[1] = 24*1024
+
+ gdb.execute('set *0x1E0000C0=0x{0:x}'.format(ispram_size[0]))
+ gdb.execute('set *0x1E0000C4=0x{0:x}'.format(dspram_size[0]))
+ gdb.execute('set *0x1E0000C8=0x{0:x}'.format(ispram_size[1]))
+ gdb.execute('set *0x1E0000CC=0x{0:x}'.format(dspram_size[1]))
+
+ for core_idx in range(0, 2):
+ gdb.execute('thread {0:d}'.format(core_idx + 1))
+
+ gdb.execute('monitor mips32 fastchannel 0 0')
+
+ ispram_addr[core_idx] = 0x9F000000 + (0x200000 * core_idx)
+ dspram_addr[core_idx] = 0x9F100000 + (0x200000 * core_idx)
+
+ # Enable CDMM
+ C0_CDMMBase = int(gdb.parse_and_eval('$cdmmbase'))
+ print "[Core%d] C0_CDMMBase before: 0x%x" % (core_idx, C0_CDMMBase)
+ C0_CDMMBase = C0_CDMMBase | (1 << 10)
+ gdb.execute('set $cdmmbase=0x{0:x}'.format(C0_CDMMBase))
+ C0_CDMMBase = int(gdb.parse_and_eval('$cdmmbase'))
+ print "[Core%d] C0_CDMMBase after: 0x%x" % (core_idx, C0_CDMMBase)
+
+ # Make bank9 cached
+ MPU_SEGMENT_CTRL2 = int(gdb.parse_and_eval('*0x1FC100D8'))
+ print "[Core%d] MPU_SEGMENT_CTRL2 before: 0x%x" % (core_idx, MPU_SEGMENT_CTRL2)
+ gdb.execute('set *0x1FC100D8=0x02020502')
+ MPU_SEGMENT_CTRL2 = int(gdb.parse_and_eval('*0x1FC100D8'))
+ print "[Core%d] MPU_SEGMENT_CTRL2 after: 0x%x" % (core_idx, MPU_SEGMENT_CTRL2)
+
+ # Enable Segment Ctrl
+ MPU_CONFIG = int(gdb.parse_and_eval('*0x1FC100C8')) & 0xFFFFFFFF
+ print "[Core%d] MPU_CONFIG before: 0x%x" % (core_idx, MPU_CONFIG)
+ MPU_CONFIG = MPU_CONFIG | 0x80000000
+ gdb.execute('set *0x1FC100C8=0x{0:x}'.format(MPU_CONFIG))
+ MPU_CONFIG = int(gdb.parse_and_eval('*0x1FC100C8')) & 0xFFFFFFFF
+ print "[Core%d] MPU_CONFIG after: 0x%x" % (core_idx, MPU_CONFIG)
+
+ print "zero mpu configuration"
+ address = 0x1FC100E0
+ for i in range(0,48):
+ gdb.execute('set *0x{0:x}=0'.format(address))
+ address += 4
+
+ # Configure SPRAM region MPU
+ print "start mpu configuration"
+ if core_idx == 0:
+ gdb.execute('set *0x1FC100E0=0x9F300000')
+ gdb.execute('set *0x1FC100E4=0x0000C88A')
+
+ gdb.execute('set *0x1FC100E8=0x9F200000')
+ gdb.execute('set *0x1FC100EC=0x0000C882')
+
+ gdb.execute('set *0x1FC100F0=0x9F100000')
+ gdb.execute('set *0x1FC100F4=0x0000C88A')
+
+ gdb.execute('set *0x1FC100F8=0x9F000000')
+ gdb.execute('set *0x1FC100FC=0x0000C802')
+
+ gdb.execute('set *0x1FC10100=0x90000000')
+ gdb.execute('set *0x1FC10104=0x0000C802')
+
+ gdb.execute('set *0x1FC10108=0x00000000')
+ gdb.execute('set *0x1FC1010C=0x0000D03A')
+ else:
+ gdb.execute('set *0x1FC100E0=0x9F300000')
+ gdb.execute('set *0x1FC100E4=0x0000C88A')
+
+ gdb.execute('set *0x1FC100E8=0x9F200000')
+ gdb.execute('set *0x1FC100EC=0x0000C882')
+
+ gdb.execute('set *0x1FC100F0=0x9F100000')
+ gdb.execute('set *0x1FC100F4=0x0000C88A')
+
+ gdb.execute('set *0x1FC100F8=0x9F000000')
+ gdb.execute('set *0x1FC100FC=0x0000C802')
+
+ gdb.execute('set *0x1FC10100=0x90000000')
+ gdb.execute('set *0x1FC10104=0x0000C802')
+
+ gdb.execute('set *0x1FC10108=0x00000000')
+ gdb.execute('set *0x1FC1010C=0x0000D03A')
+
+ gdb.execute('thread {0:d}'.format(core_idx + 1))
+ gdb.execute('set $status=0x0')
+ gdb.execute('set $ebase=0x9ff{0:x}0800'.format(4*core_idx))
+ #gdb.execute('set $config5=0x0')
+ C0_CAUSE = int(gdb.parse_and_eval("$cause"))
+ gdb.execute('set $cause=0x{0:x}'.format(C0_CAUSE & 0xffbfffff))
+ print "Initializind Core %d SPRAM. ISPRAM addr 0x%x, DSPRAM addr 0x%x" %(core_idx, ispram_addr[core_idx], dspram_addr[core_idx])
+
+ C0_ERRCTL = int(gdb.parse_and_eval("$errctl"))
+ gdb.execute('set $errctl=0x{0:x}'.format(C0_ERRCTL | (1 << 28)))
+
+ #Init SPRAM base addr
+ gdb.execute('set $dtaglo=0x{0:x}'.format(dspram_addr[core_idx] | (1 << 7)))
+ gdb.execute('monitor mips32 cacheop 0 0 9')
+ gdb.execute('set $itaglo=0x{0:x}'.format(ispram_addr[core_idx] | (1 << 7)))
+ gdb.execute('monitor mips32 cacheop 0 0 8')
+ #gdb.execute('handle SIGTRAP pass')
+ #gdb.execute('set $pc=0x90000000')
+ gdb.execute('set $ra=0x9ff{0:x}0000'.format(4*core_idx))
+ #return
+ gdb.execute('set $errctl=0x{0:x}'.format(C0_ERRCTL))
+ #return
+ # Load memory init code
+ if True:#load_size != 0:
+ #with io.open(self.elf_path, 'rb',0) as elf_file:
+ # elf_file.seek(load_offset, 1)
+ # gdb.selected_inferior().write_memory(load_addr, elf_file.read(load_size), load_size)
+
+
+ tmp_ispram_array = [0x8d050000,0x8d060004,0x4085e001,0x4086e801,0x000000c0,0xbd2c0000,0x0000000f,0x21080008,0x21290008,0x214afff8,0x1540fff5,0x00000000,0x03e00008,0x00000000,0xad200000,0x21290004,0x214afffc,0x1540fffc,0x00000000,0x03e00008,0x00000000,0x00000000]
+ with io.open(self.elf_path, 'rb',0) as elf_file:
+ elf_file.seek(ispram_offset[0]+0x300, 1)
+ #for i in range(0, 0x50/4):
+ # bytesFromELF = elf_file.read(4)
+ # print "Read from ELF: 0x%x", bytesFromELF.encode("hex")
+ # gdb.selected_inferior().write_memory(ispram_addr[0]+(i*0x4), bytesFromELF, 0x4)
+ # print "offset 0x%x, value: %s\n" % (i*0x4, bytesFromELF.encode("hex"))
+ gdb.selected_inferior().write_memory(ispram_addr[0]+0x300, elf_file.read(0x54), 0x54)
+ ##### try errCtrl + cacheop on ispram #####
+ #C0_ERRCTL = int(gdb.parse_and_eval("$errctl"))
+ #gdb.execute('set $errctl=0x{0:x}'.format(C0_ERRCTL | (1 << 28)))
+
+ #tmp_ispram_addr = 0x9f000300
+ #
+ #print "size(tmp_ispram_array) = %d" %(len(tmp_ispram_array))
+ #tmp_gpr_base = int(gdb.parse_and_eval("$t8"))
+ #for i in range(0, 11):
+ # print "iidatahi = 0x%x, idatalo=0x%x" %(tmp_ispram_array[2*i+1],tmp_ispram_array[2*i])
+ # gdb.execute('set $t8=0x{0:x}'.format(tmp_ispram_addr))
+ # gdb.execute('set $idatahi=0x{0:x}'.format(tmp_ispram_array[2*i+1]))
+ # gdb.execute('set $idatalo=0x{0:x}'.format(tmp_ispram_array[2*i]))
+ # gdb.execute('monitor mips32 cacheop 24 0 12')
+ # #gdb.execute('handle SIGTRAP pass')
+ # #gdb.execute('set $pc=0x90000000')
+ # gdb.execute('set $ra=0x9ff{0:x}0000'.format(4*core_idx))
+ # #return
+ # tmp_ispram_addr = tmp_ispram_addr + 0x8
+ #gdb.execute('set $errctl=0x{0:x}'.format(C0_ERRCTL))
+ ##### try errCtrl + cacheop on ispram #####
+ print "Init code Loaded"
+ #gdb.execute('set $errctl=0x{0:x}'.format(C0_ERRCTL | (1 << 28)))
+ #time.sleep(1)
+ gdb.execute('info threads')
+ gdb.execute('d')
+ if ispram_size[core_idx] != 0:
+ C0_ERRCTL = int(gdb.parse_and_eval("$errctl"))
+ gdb.execute('set $errctl=0x{0:x}'.format(C0_ERRCTL | (1 << 28)))
+ load_len = int(8 * round(ispram_load_size[core_idx]/8)) + 8
+ print "Load ISPRAM%d to 0x%x, size: %d" %(core_idx, ispram_addr[core_idx], load_len)
+ for load_round in range(0,6):
+ print "Load ISPRAM%d round %d to 0x%x"%(core_idx, load_round, ispram_addr[core_idx] + (dspram_size[core_idx] * load_round))
+ gdb.execute('set $t0=0x{0:x}'.format(dspram_addr[core_idx]))
+ #time.sleep(1)
+ gdb.execute('set $t1=0x{0:x}'.format(ispram_addr[core_idx] + (dspram_size[core_idx] * load_round)))
+ #time.sleep(1)
+ if load_len >= dspram_size[core_idx]:
+ gdb.execute('set $t2=0x{0:x}'.format(dspram_size[core_idx]))
+ time.sleep(1)
+ print "Load binary to DSPRAM"
+ with io.open(self.elf_path, 'rb',0) as elf_file:
+ elf_file.seek(ispram_offset[core_idx] + (dspram_size[core_idx] * load_round), 1)
+ print "Target:0x%x size:0x%x" % (dspram_addr[core_idx],dspram_size[core_idx])
+ gdb.execute('info threads')
+ get_selected_inferior().write_memory(dspram_addr[core_idx], elf_file.read(dspram_size[core_idx]), dspram_size[core_idx])
+ print "DSPRAM chunk loaded"
+ time.sleep(1)
+ gdb.execute('hb *0x9ff{0:x}0008 thread {1:x}'.format(4*core_idx,core_idx+1))
+ gdb.execute('set $pc=0x9ff{0:x}000c'.format(4*core_idx))
+ gdb.execute('set $gp=ispram_load_code')
+ print "Load Done"
+ gdb.execute('info b')
+ gdb.execute('p /x $pc')
+ gdb.execute('p /x $gp')
+
+ gdb.execute('c')
+ #return
+ gdb.execute('d')
+ #print "sleep done"
+ load_round = load_round + 1
+ load_len = load_len - dspram_size[core_idx]
+ elif load_len != 0:
+ gdb.execute('set $t2=0x{0:x}'.format(load_len))
+ with io.open(self.elf_path, 'rb') as elf_file:
+ elf_file.seek(ispram_offset[core_idx] + (dspram_size[core_idx] * load_round), 1)
+ print "Target:0x%x size:0x%x" % (dspram_addr[core_idx],load_len)
+ get_selected_inferior().write_memory(dspram_addr[core_idx], elf_file.read(load_len), load_len)
+ gdb.execute('set $pc=0x9ff{0:x}000c'.format(4*core_idx))
+ gdb.execute('set $gp=ispram_load_code')
+ gdb.execute('hb *0x9ff{0:x}0008 thread {1:x}'.format(4*core_idx,core_idx+1))
+ gdb.execute('c')
+
+ gdb.execute('d')
+ break
+ gdb.execute('set $errctl=0x{0:x}'.format(C0_ERRCTL))
+ print "Load ISPRAM%d done"%(core_idx)
+ else:
+ print "ISPRAM%d image is empty"%(core_idx)
+
+
+ for core_idx in range(0, 2):
+ gdb.execute('thread 1')
+ print "Loading DSPRAM%d image to: 0x%x" %(core_idx, dspram_load_addr[core_idx])
+ if dspram_load_size[core_idx] != 0:
+ with io.open(self.elf_path, 'rb') as elf_file:
+ elf_file.seek(dspram_offset[core_idx], 1)
+ get_selected_inferior().write_memory(dspram_load_addr[core_idx], elf_file.read(dspram_load_size[core_idx]), dspram_load_size[core_idx])
+ # Load DSPRAM always on core 0 to ensure L1 cache coherency
+ #gdb.execute('thread 1')
+
+ print "Initializing DSPRAM%d_ZI to: 0x%x" %(core_idx, dspram_zi_addr[core_idx])
+ if dspram_zi_size[core_idx] != 0:
+ # Do DSPRAM ZI always on core 0 to ensure L1 cache coherency
+ gdb.execute('thread 1')
+ gdb.execute('set $t1=0x{0:x}'.format(dspram_zi_addr[core_idx]))
+ gdb.execute('set $t2=0x{0:x}'.format(dspram_zi_size[core_idx]))
+ gdb.execute('set $pc=0x9ff{0:x}000c'.format(4*core_idx))
+ gdb.execute('set $gp=dspram_zi_loop')
+ gdb.execute('hb *0x9ff{0:x}0008 thread {1:x}'.format(4*core_idx,core_idx+1))
+ gdb.execute('c')
+ gdb.execute('d')
+ #time.sleep(4)
+ print "Load DSPRAM%d image done" %(core_idx)
+ #if core_idx != 0:
+ # gdb.execute('thread %d'%(core_idx + 1))
+ # gdb.execute('set $pc=0x9FF40000')
+
+
+ gdb.execute('thread 1')
+ #print "Load and lock L2 cache done"
+ gdb.execute('set *0x1FC10100=0x90000000')
+ gdb.execute('set *0x1FC10104=0x0000C805')
+
+ gdb.execute('thread 2')
+ #print "Load and lock L2 cache done"
+ gdb.execute('set *0x1FC10100=0x90000000')
+ gdb.execute('set *0x1FC10104=0x0000C805')
+
+ gdb.execute('thread 1')
+ #print "Load and lock L2 cache from 0x%x size 0x%x" %(load_zi_addr, load_zi_size)
+ #return
+ '''
+ if load_zi_size != 0:
+ print "EXTSRAM_ZI found, address: 0x%x, size %d bytes" %(load_zi_addr, load_zi_size)
+ load_zi_size = int(64 * round(load_zi_size/64))
+ print "EXTSRAM_ZI found, address: 0x%x, size %d bytes" %(load_zi_addr, load_zi_size)
+ gdb.execute('hb *0x9ff00008 thread 1')
+
+
+ while load_zi_size > 0:
+ print "WRITE 64 bytes from: 0x%x. STILL %d bytes to go" %(load_zi_addr, load_zi_size)
+ gdb.execute('info threads')
+ gdb.execute('set $t1=0x{0:x}'.format(load_zi_addr))
+ gdb.execute('set $t2=0x40')
+ gdb.execute('set $pc=0x9ff0000c')
+ gdb.execute('set $gp=l2_zi_loop')
+ load_zi_addr = load_zi_addr + 0x40
+ load_zi_size = load_zi_size - 0x40
+ gdb.execute('c')
+
+ #load_zi_size = 65536
+ #gdb.execute('info threads')
+ #gdb.execute('set $t1=0x{0:x}'.format(load_zi_addr))
+ #gdb.execute('set $t2=0x{0:x}'.format(load_zi_size))
+ #gdb.execute('set $pc=0x9ff0000c')
+ #gdb.execute('set $gp=l2_zi_loop')
+
+ #return
+ gdb.execute('c')
+ gdb.execute('d')
+ #time.sleep(60)
+
+ return
+ '''
+ gdb.execute('set $pc=INT_Vectors')
+ gdb.execute('hb *0x9f005180')
+ #gdb.execute('hb itc_init thread 2')
+ print "All loading is done"
+
+ def my_quit(self):
+ global app
+ print "=== Close Easy Loader ==="
+ app.destroy()
+
+if __name__ == "__main__":
+ app = gui_tk(None)
+ app.title("Load ELF")
+ app.mainloop()
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/mt6765-evb.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/mt6765-evb.cmm
new file mode 100644
index 0000000..26bffa7
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/mt6765-evb.cmm
@@ -0,0 +1,111 @@
+;*****************************************************************************
+; Copyright Statement:
+; --------------------
+; This software is protected by Copyright and the information contained
+; herein is confidential. The software may not be copied and the information
+; contained herein may not be used or disclosed except with the written
+; permission of MediaTek Inc. (C) 2011
+;
+;*****************************************************************************
+;;================================================
+;; PURPOSE: EVB Bring Up
+;; CREATE_DATE: 2016/04/01
+;; NOTE:
+;;================================================
+; Specify Core Number
+;=================================================
+
+&NR_CPUS=1
+; cluster 0 corebase: 0x8007000, 0x8007200, 0x8007400, 0x8007600
+; cluster 1 corebase: 0x8009000, 0x8009200, 0x8009400, 0x8009600
+
+;=================================================
+; Initialize CPU
+;=================================================
+&WDT_TEST=0
+if &WDT_TEST==0
+(
+ RESET
+ SYSTEM.OPTION ENRESET ON
+)
+
+SYSTEM.RESET
+SYSTEM.OPTION ENRESET ON
+SYSTEM.OPTION RESBREAK OFF
+SYSTEM.OPTION WAITRESET OFF
+
+SYSTEM.JTAGCLOCK 10.MHz;
+
+;SYSTEM.CPU CortexA7MPCore
+SYStem.CPU CORTEXA53;
+
+;R-T Memory Access
+SYSTEM.MULTICORE MEMORYACCESSPORT 0
+SYSTEM.MULTICORE DEBUGACCESSPORT 1
+
+;SYSTEM.MULTICORE COREBASE APB:0x80070000
+;Setting Core debug register access
+if &NR_CPUS==1
+(
+ SYStem.CONFIG CORENUMBER 1;
+ SYStem.CONFIG COREBASE 0x8D410000;
+ SYStem.CONFIG CTIBASE 0x8D420000;
+)
+else
+(
+ SYSTEM.CONFIG CORENUMBER 2;
+ SYSTEM.CONFIG COREBASE 0x80810000 0x80910000;
+ SYStem.CONFIG CTIBASE 0x80820000 0x80920000;
+)
+
+;=================================================
+; Attach and Stop CPU
+;=================================================
+SYStem.Up
+wait 200.us
+
+SETUP.IMASKHLL ON
+SETUP.IMASKASM ON
+
+;enable L2C 256KB
+D.S SD:0x102007f0 %LE %LONG 0x00010100 ;Enable L2C share SRAM, cluster 0
+D.S SD:0x102007f0 %LE %LONG 0x00010101 ;Enable L2C share SRAM, cluster 0
+
+; set_hw_breakpoint_by_def
+; setting attribute of breakpoints
+Break.Select Program OnChip
+Break.Select Hll OnChip
+Break.Select Spot OnChip
+Break.Select Read OnChip
+Break.Select Write OnChip
+
+D.S C15:0x1 0 ; Turn off MMU
+
+; disable wdt (debug purpose)
+D.S SD:0x10007000 %LE %LONG 0x22000000
+
+; Init DRAM
+;do MT6765_FPGA_DDR
+
+print "loading pre-loader image"
+d.load.elf preloader_evb6765_64_emmc_TINY.elf
+
+Y.SPATH.RESET ; reset all source path
+Y.SPATH.SRD ../../platform/mt6765/src/init
+Y.SPATH.SRD ../../platform/mt6765/src/core
+Y.SPATH.SRD ../../platform/mt6765/src/drivers
+Y.SPATH.SRD ../../platform/mt6765/src/security
+Y.SPATH.SRD ../../platform/common
+Y.SPATH.SRD ../../custom/evb6763_64_ufs
+
+
+Break.Select Program OnChip
+Break.Select Hll OnChip
+Break.Select Spot OnChip
+Break.Select Read OnChip
+Break.Select Write OnChip
+
+R.S T 0
+;winclear
+d.l
+enddo
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/preloader_evb6765_64_emmc_TINY.elf b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/preloader_evb6765_64_emmc_TINY.elf
new file mode 100644
index 0000000..1ef052c
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6765/preloader_evb6765_64_emmc_TINY.elf
Binary files differ
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APView_MT6771_EVB_UART_Test.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APView_MT6771_EVB_UART_Test.cmm
new file mode 100755
index 0000000..6bd2d57
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APView_MT6771_EVB_UART_Test.cmm
@@ -0,0 +1,35 @@
+;Cannon MD_UART0 port test
+;You should make sure GPIO84 has connected to UART port RXD pin,GPIO85 has connected to UART port TXD pin
+
+;port: MDUART0
+;Baudrate: 115200
+;&BASE_ADDR_MDUART0=0xB0010000
+sys.m prepare
+&BASE_ADDR_MDUART0=0x20010000
+&BASE_ADDR_MDGPIO=0x10005000
+&BASE_ADDR_IOCFG=0x11E80000
+
+D.S AXI:&BASE_ADDR_MDGPIO+0x310 %LE %LONG 0xCCC00000 //set GPIO13 to MD_URXD0 mode,set GPIO14 to MD_UTXD0 mode,
+D.S AXI:&BASE_ADDR_IOCFG+0x60 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x60)&(0xFFFFFF7F) //MD_UTXD0 pull disable
+D.S AXI:&BASE_ADDR_IOCFG+0x60 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x60)|(0x00000040) //MD_URXD0 pull enable
+D.S AXI:&BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)|(0x00000040) //MD_URXD0 pull up
+
+D.S AXI:&BASE_ADDR_MDUART0+0x24 %LE %LONG 0x03 //High Speed X
+D.S AXI:&BASE_ADDR_MDUART0+0x28 %LE %LONG 0xE1 //Sample count
+D.S AXI:&BASE_ADDR_MDUART0+0x2C %LE %LONG 0x71 //sample point
+D.S AXI:&BASE_ADDR_MDUART0+0x0C %LE %LONG 0x83 //Enable Divisor latch acess bit, and set 8bit length.
+D.S AXI:&BASE_ADDR_MDUART0+0x00 %LE %LONG 0x01 //sample point
+D.S AXI:&BASE_ADDR_MDUART0+0x04 %LE %LONG 0x00 //sample point
+D.S AXI:&BASE_ADDR_MDUART0+0x0C %LE %LONG 0x03 //Clear Divisor latch acess bit, and set 8bit length.
+
+&uart_lsr=0x0
+&uart_rxd=0x0
+PRINT "Please put char "U" from PC to EVB UART! Note: ASCII "U" remap to HEX is 0x55 "
+WHILE (&uart_lsr&0x01)!=0x01
+(
+ &uart_lsr=data.long(AXI:&BASE_ADDR_MDUART0+0x14)
+)
+&uart_rxd=data.long(AXI:&BASE_ADDR_MDUART0+0x0)
+PRINT "EVB UART Get data: &uart_rxd"
+D.S AXI:&BASE_ADDR_MDUART0+0x00 %LE %LONG &uart_rxd //Write data to UART, please check console.
+PRINT "EVB UART will send data to PC,please check!"
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_AP2MD_enable.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_AP2MD_enable.cmm
new file mode 100755
index 0000000..5a5e6e5
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_AP2MD_enable.cmm
@@ -0,0 +1,31 @@
+&MEM_CLASS="AXI"
+; do AP to MD path disable
+LOCAL &BASE_ADDR_AP2MD_Dummy
+LOCAL &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN
+LOCAL &temp
+
+&BASE_ADDR_AP2MD_Dummy=0x10001370
+&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN=0x100012A0
+
+; Set peri2md_protect_en
+; Write 0x1000_12A0[7] = 1'b1.
+; MD can access AP if reg_ap2md_dummy[0] = 1'b1,
+&temp=data.long(&MEM_CLASS:(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0x0))|0x80
+;PRINT "temp=" "&temp"
+;PRINT "&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0x0"
+D.S &MEM_CLASS:(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0x0) %LE %LONG &temp
+
+; Clear md2peri_protect_en
+; Write 0x1000_12AC[6] = 1'b1.
+&temp=data.long(&MEM_CLASS:(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC))|0x40
+;PRINT "temp=" "&temp"
+;PRINT "(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC)"
+D.S &MEM_CLASS:(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC) %LE %LONG &temp
+wait 1.ms
+
+; Set reg_ap2md_dummy[0] = 1'b1
+&temp=data.long(&MEM_CLASS:(&BASE_ADDR_AP2MD_Dummy+0x0))|0x1
+;PRINT "temp=" "&temp"
+;PRINT "BASE_ADDR_AP2MD_Dummy=" "&BASE_ADDR_AP2MD_Dummy"
+D.S &MEM_CLASS:(&BASE_ADDR_AP2MD_Dummy+0x0) %LE %LONG &temp
+wait 1.ms
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_Frequency_Meter.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_Frequency_Meter.cmm
new file mode 100755
index 0000000..3a080ac
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_Frequency_Meter.cmm
@@ -0,0 +1,535 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; SYLVIA MD Frequency Meter
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;;Select PLL
+LOCAL &key_in
+&key_in=0
+
+LOCAL &opt_cvd_connect
+&opt_cvd_connect="debug"
+
+;;;;;;;;;;;;;;;;;;;;;;;Below you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+LOCAL &mclass ;; Memory Class
+&mclass="axi"
+;&mclass="pm"
+
+LOCAL &clksw_base ;; MD CLKSW base address
+;&clksw_base=0xA0150000 ;; MD view APB
+;&clksw_base=0xA0096000 ;; MD view debug APB
+&clksw_base=0x20150000 ;; AP view MD system bus
+;&clksw_base=0x0D0D6000 ;; AP view MD debug sys
+
+LOCAL &pll_base ;; MD PLLMIXED base address
+;&pll_base=0xA0140000 ;; MD view APB
+;&pll_base=0xA0094000 ;; MD view debug APB
+&pll_base=0x20140000 ;; AP view MD system bus
+;&pll_base=0x0D0D4000 ;; AP view MD debug sys
+
+&fqmtr_fcksel_32k_index=0x17
+;;;;;;;;;;;;;;;;;;;;;;;Above you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LOCAL &fqmtr_winset ;; Frequency Meter Windoiw Setting (= Number of FIXED clock cycle)
+&fqmtr_winset=0x1ff
+&fqmtr_winset_for_32k=0x1E000
+
+LOCAL &fqmtr_fcksel_val ;; Frequency Meter FIXED clock selection
+&fqmtr_fcksel_val=0x1a ;; Select 26Mhz by default
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;All the PLL you could select;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+&SRC_STR_1="Reserved"
+&SRC_STR_2="Reserved"
+&SRC_STR_3="Reserved"
+&SRC_STR_4="Reserved"
+&SRC_STR_5="Reserved"
+&SRC_STR_6="Reserved"
+&SRC_STR_7="Reserved"
+&SRC_STR_8="Reserved"
+&SRC_STR_9="Reserved"
+&SRC_STR_10="TRACE_MON_clock"
+&SRC_STR_11="MDSYS_208M_clock"
+&SRC_STR_12="mdrxsys_rake_clock"
+&SRC_STR_13="mdrxsys_brp_clock"
+&SRC_STR_14="mdrxsys_vdsp_clock"
+&SRC_STR_15="mdtop_log_atb_clock"
+&SRC_STR_16="fesys_csys_clock"
+&SRC_STR_17="fesys_txsys_clock"
+&SRC_STR_18="fesys_bsi_clock"
+&SRC_STR_19="mdsys_mdcore_clock"
+&SRC_STR_20="mdsys_bus2x_nodcm_clock"
+&SRC_STR_21="mdsys_bus2x_clock"
+&SRC_STR_22="mdtop_dbg_clock"
+&SRC_STR_23="mdtop_f32k_clock"
+&SRC_STR_24="MDBPIPLL_0_DIV2_clock"
+&SRC_STR_25="MDBPIPLL_2_clock"
+&SRC_STR_26="MDBPIPLL_1_clock"
+&SRC_STR_27="MDBPIPLL_0_clock"
+&SRC_STR_28="MDTXPLL_clock"
+&SRC_STR_29="MDBRPPLL_clock"
+&SRC_STR_30="MDVDSPPLL_clock"
+&SRC_STR_31="MDMCUPLL_clock"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+DIALOG
+(&
+ HEADER "PLL Frequency Meter"
+ ICON ":chip"
+
+ POS 0. 0. 20. 1.
+ LINE "FQMTR Selection"
+ ; x y w h
+ POS 0. 1. 20. 1.
+ SEL.NONE: CHOOSEBOX "None"
+ (
+ &key_in=0x00
+ )
+;; SEL.1: CHOOSEBOX "&SRC_STR_1"
+;; (
+;; &key_in=0x1
+;; &key_str="&SRC_STR_1"
+;; )
+;; SEL.2: CHOOSEBOX "&SRC_STR_2"
+;; (
+;; &key_in=0x2
+;; &key_str="&SRC_STR_2"
+;; )
+;; SEL.3: CHOOSEBOX "&SRC_STR_3"
+;; (
+;; &key_in=0x3
+;; &key_str="&SRC_STR_3"
+;; )
+;; SEL.4: CHOOSEBOX "&SRC_STR_4"
+;; (
+;; &key_in=0x4
+;; &key_str="&SRC_STR_4"
+;; )
+;; SEL.5: CHOOSEBOX "&SRC_STR_5"
+;; (
+;; &key_in=0x5
+;; &key_str="&SRC_STR_5"
+;; )
+;; SEL.6: CHOOSEBOX "&SRC_STR_6"
+;; (
+;; &key_in=0x6
+;; &key_str="&SRC_STR_6"
+;; )
+;; SEL.7: CHOOSEBOX "&SRC_STR_7"
+;; (
+;; &key_in=0x7
+;; &key_str="&SRC_STR_7"
+;; )
+;; SEL.8: CHOOSEBOX "&SRC_STR_8"
+;; (
+;; &key_in=0x8
+;; &key_str="&SRC_STR_8"
+;; )
+;; SEL.9: CHOOSEBOX "&SRC_STR_9"
+;; (
+;; &key_in=0x9
+;; &key_str="&SRC_STR_9"
+;; )
+ SEL.10: CHOOSEBOX "&SRC_STR_10"
+ (
+ &key_in=0xA
+ &key_str="&SRC_STR_10"
+ )
+ SEL.11: CHOOSEBOX "&SRC_STR_11"
+ (
+ &key_in=0xB
+ &key_str="&SRC_STR_11"
+ )
+ SEL.12: CHOOSEBOX "&SRC_STR_12"
+ (
+ &key_in=0xC
+ &key_str="&SRC_STR_12"
+ )
+ SEL.13: CHOOSEBOX "&SRC_STR_13"
+ (
+ &key_in=0xD
+ &key_str="&SRC_STR_13"
+ )
+ SEL.14: CHOOSEBOX "&SRC_STR_14"
+ (
+ &key_in=0xE
+ &key_str="&SRC_STR_14"
+ )
+ SEL.15: CHOOSEBOX "&SRC_STR_15"
+ (
+ &key_in=0xF
+ &key_str="&SRC_STR_15"
+ )
+ SEL.16: CHOOSEBOX "&SRC_STR_16"
+ (
+ &key_in=0x10
+ &key_str="&SRC_STR_16"
+ )
+ SEL.17: CHOOSEBOX "&SRC_STR_17"
+ (
+ &key_in=0x11
+ &key_str="&SRC_STR_17"
+ )
+ SEL.18: CHOOSEBOX "&SRC_STR_18"
+ (
+ &key_in=0x12
+ &key_str="&SRC_STR_18"
+ )
+ SEL.19: CHOOSEBOX "&SRC_STR_19"
+ (
+ &key_in=0x13
+ &key_str="&SRC_STR_19"
+ )
+ SEL.20: CHOOSEBOX "&SRC_STR_20"
+ (
+ &key_in=0x14
+ &key_str="&SRC_STR_20"
+ )
+ SEL.21: CHOOSEBOX "&SRC_STR_21"
+ (
+ &key_in=0x15
+ &key_str="&SRC_STR_21"
+ )
+ SEL.22: CHOOSEBOX "&SRC_STR_22"
+ (
+ &key_in=0x16
+ &key_str="&SRC_STR_22"
+ )
+ SEL.23: CHOOSEBOX "&SRC_STR_23"
+ (
+ &key_in=0x17
+ &key_str="&SRC_STR_23"
+ )
+ SEL.24: CHOOSEBOX "&SRC_STR_24"
+ (
+ &key_in=0x18
+ &key_str="&SRC_STR_24"
+ )
+ SEL.25: CHOOSEBOX "&SRC_STR_25"
+ (
+ &key_in=0x19
+ &key_str="&SRC_STR_25"
+ )
+ SEL.26: CHOOSEBOX "&SRC_STR_26"
+ (
+ &key_in=0x1A
+ &key_str="&SRC_STR_26"
+ )
+ SEL.27: CHOOSEBOX "&SRC_STR_27"
+ (
+ &key_in=0x1B
+ &key_str="&SRC_STR_27"
+ )
+ SEL.28: CHOOSEBOX "&SRC_STR_28"
+ (
+ &key_in=0x1C
+ &key_str="&SRC_STR_28"
+ )
+ SEL.29: CHOOSEBOX "&SRC_STR_29"
+ (
+ &key_in=0x1D
+ &key_str="&SRC_STR_29"
+ )
+ SEL.30: CHOOSEBOX "&SRC_STR_30"
+ (
+ &key_in=0x1E
+ &key_str="&SRC_STR_30"
+ )
+ SEL.31: CHOOSEBOX "&SRC_STR_31"
+ (
+ &key_in=0x1F
+ &key_str="&SRC_STR_31"
+ )
+
+ POS 21. 0. 20. 1.
+ LINE "FQMTR Information"
+ INFO1: EDIT "Window Seting: &fqmtr_winset" ""
+ INFO2: EDIT "Fixed Clock: &fqmtr_fcksel_val" ""
+ INFO3: EDIT "32K measure support" ""
+
+ POSY 1. 20. 1.
+ LINE "FQMTR Result"
+ RESULT: EDIT "" ""
+
+ POSY 1. 20. 1.
+ DEFBUTTON "OK"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ IF &key_in!=0
+ (
+ GOSUB fqmtr_query &key_in &key_str 1
+ )
+ )
+
+ DEFBUTTON "LIST ALL"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ GOSUB fqmtr_list_all
+ )
+
+ DEFBUTTON "Force LIST main clk"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ GOSUB fqmtr_force_list_all
+ )
+
+ CLOSE
+ (
+ PRINT "bye~"
+ DIALOG.END
+ )
+)
+
+ ;; Disable EDIT of showing information
+ DIALOG.Disable INFO1
+ DIALOG.Disable INFO2
+ DIALOG.Disable INFO3
+ ;DIALOG.Disable RESULT
+STOP
+ENDDO
+
+;;;;;The main function to get the Frequency. &idx==> the clock you select, &str==> clock name, &info==>list more info and wait 5ms in the function
+;; &info=1 ==> for printing many PLLs at one time
+fqmtr_query:
+ENTRY &idx &str &info
+(
+ IF &info!=0
+ (
+ PRINT "&str: &idx"
+ PRINT "fqmtrsrc: 0x" FORMAT.HEX(2,&idx)
+ PRINT "opt_cvd_connect: &opt_cvd_connect"
+ )
+
+ LOCAL &unit
+ LOCAL &fqmtr_winset_26M
+ LOCAL &fqmtr_result
+ LOCAL &fqmtr_result_raw
+ LOCAL &fqmtr_result_str
+ LOCAL &safe_wait_cnt
+ LOCAL &safe_wait_cnt_max
+
+ &safe_wait_cnt=0
+
+ IF &fqmtr_fcksel_val==0x1a ;; base on 26M, unit:MHz
+ (
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &unit="Khz"
+ &fqmtr_winset_26M=&fqmtr_winset_for_32k
+ &safe_wait_cnt_max=500 ;;5000 ms = 5s ==> in real test, longer than 5s, so reduce it
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &unit="Mhz"
+ &fqmtr_winset_26M=&fqmtr_winset
+ &safe_wait_cnt_max=32 ;;32 ms
+ )
+ )
+ ELSE
+ (
+ &unit=""
+ )
+
+ IF "&opt_cvd_connect"=="none"
+ (
+ sys.m prepare
+ )
+ ELSE IF "&opt_cvd_connect"=="debug"
+ (
+ ; do nothing
+ )
+ ELSE
+ (
+ IF &info!=0
+ (
+ PRINT "No explicit CVD connection, use current status"
+ )
+ )
+
+ IF &idx==0
+ (
+ ;; This is used for connect CVD only, no FQMTR test
+ RETURN
+ )
+
+ ;;select source to a valid clock to let reset success.
+ Data.Set &mclass:(&clksw_base+0x0100) %LE %LONG 0x13
+ Data.Set &mclass:(&clksw_base+0x0104) %LE %LONG 0x0 ;reset frequency meter
+ WAIT 1ms
+
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ ;;For accurate, don't div 8 for 32K
+ Data.Set &mclass:(&clksw_base+0x0100) %LE %LONG (&idx)
+ )
+ ELSE ;; measure PLL and other module
+ (
+ ;;div 8 and select src
+ Data.Set &mclass:(&clksw_base+0x0100) %LE %LONG (0x0300)|(&idx)
+ )
+
+ Data.Set &mclass:(&clksw_base+0x0108) %LE %LONG &fqmtr_winset_26M
+ Data.Set &mclass:(&clksw_base+0x0104) %LE %LONG 0x1 ;enable frequency meter
+
+ ;; read status, to check polling done or not
+ &fqmtr_busy=DATA.LONG(&mclass:(&clksw_base+0x0104))&(1<<1)
+ WHILE &fqmtr_busy==0
+ (
+ ;PRINT ". &fqmtr_busy"
+ &fqmtr_busy=DATA.LONG(&mclass:(&clksw_base+0x0104))&(1<<1)
+ &safe_wait_cnt=&safe_wait_cnt+1
+ IF &safe_wait_cnt==&safe_wait_cnt_max
+ (
+ PRINT "[&str] Wait Fail, exit"
+ DIALOG.Set RESULT "Wait Fail(No clock), exit"
+ RETURN
+ )
+ ELSE
+ (
+;; PRINT "Waiting result. safe_wait_cnt=" "&safe_wait_cnt"
+ )
+ WAIT 1ms
+ )
+
+ ;; Calculate the result
+ &fqmtr_result_raw=DATA.LONG(&mclass:(&clksw_base+0x10c))
+
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*(0x3E8)/(&fqmtr_winset_26M+3)
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*8/(&fqmtr_winset_26M+3)
+ )
+
+ &fqmtr_result_dec=FORMAT.DECIMAL(0,&fqmtr_result)
+ &fqmtr_result_str=""+FORMAT.DECIMAL(0,&fqmtr_result)+" &unit"
+ IF &info==0
+ (
+ PRINT "0x" FORMAT.HEX(2,&idx) ",&fqmtr_result_dec,&unit,&str,&fqmtr_result_raw,"
+ )
+ ELSE
+ (
+ PRINT "Frequency Meter Result: &fqmtr_result_str (&fqmtr_result_raw)"
+ PRINT ""
+ )
+ DIALOG.Set RESULT "&fqmtr_result_str"
+
+ IF &info==0
+ (
+ WAIT 5ms
+ )
+
+ RETURN
+)
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+fqmtr_create_win:
+(
+ AREA.RESet
+ AREA.Create PLL_FMETER
+ AREA.Select PLL_FMETER
+ WinPOS 10.,0.,50.,35.,,, FMETER
+ AREA.view PLL_FMETER
+ AREA.Clear PLL_FMETER
+ RETURN
+)
+
+fqmtr_list_all:
+(
+ GOSUB fqmtr_create_win
+
+ ;GOSUB fqmtr_query 0x1 &SRC_STR_1 0
+ ;GOSUB fqmtr_query 0x2 &SRC_STR_2 0
+ ;GOSUB fqmtr_query 0x3 &SRC_STR_3 0
+ ;GOSUB fqmtr_query 0x4 &SRC_STR_4 0
+ ;GOSUB fqmtr_query 0x5 &SRC_STR_5 0
+ ;GOSUB fqmtr_query 0x6 &SRC_STR_6 0
+ ;GOSUB fqmtr_query 0x7 &SRC_STR_7 0
+ ;GOSUB fqmtr_query 0x8 &SRC_STR_8 0
+ ;GOSUB fqmtr_query 0x9 &SRC_STR_9 0
+ GOSUB fqmtr_query 0xA &SRC_STR_10 0
+ GOSUB fqmtr_query 0xB &SRC_STR_11 0
+ GOSUB fqmtr_query 0xC &SRC_STR_12 0
+ GOSUB fqmtr_query 0xD &SRC_STR_13 0
+ GOSUB fqmtr_query 0xE &SRC_STR_14 0
+ GOSUB fqmtr_query 0xF &SRC_STR_15 0
+ GOSUB fqmtr_query 0x10 &SRC_STR_16 0
+ GOSUB fqmtr_query 0x11 &SRC_STR_17 0
+ GOSUB fqmtr_query 0x12 &SRC_STR_18 0
+ GOSUB fqmtr_query 0x13 &SRC_STR_19 0
+ GOSUB fqmtr_query 0x14 &SRC_STR_20 0
+ GOSUB fqmtr_query 0x15 &SRC_STR_21 0
+ GOSUB fqmtr_query 0x16 &SRC_STR_22 0
+ GOSUB fqmtr_query 0x17 &SRC_STR_23 0
+ GOSUB fqmtr_query 0x18 &SRC_STR_24 0
+ GOSUB fqmtr_query 0x19 &SRC_STR_25 0
+ GOSUB fqmtr_query 0x1A &SRC_STR_26 0
+ GOSUB fqmtr_query 0x1B &SRC_STR_27 0
+ GOSUB fqmtr_query 0x1C &SRC_STR_28 0
+ GOSUB fqmtr_query 0x1D &SRC_STR_29 0
+ GOSUB fqmtr_query 0x1E &SRC_STR_30 0
+ GOSUB fqmtr_query 0x1F &SRC_STR_31 0
+ RETURN
+)
+
+fqmtr_force_list_all:
+(
+ GOSUB fqmtr_create_win
+
+ LOCAL &original_reg
+ LOCAL &original_BPIPLLCTL1_reg
+
+ &original_reg=DATA.LONG(&mclass:(&pll_base+0x10))
+ &original_BPIPLLCTL1_reg=DATA.LONG(&mclass:(&pll_base+0x64))
+
+ ; S/W force on all PLL
+ Data.Set &mclass:(&pll_base+0x10) %LE %LONG 0xFFFFFFFF
+
+ ; S/W force on BPI_1 PLL
+ Data.Set &mclass:(&pll_base+0x64) %LE %LONG &original_BPIPLLCTL1_reg|(0x80)
+
+ WAIT 1.s
+
+ ;GOSUB fqmtr_query 0x1 &SRC_STR_1 0
+ ;GOSUB fqmtr_query 0x2 &SRC_STR_2 0
+ ;GOSUB fqmtr_query 0x3 &SRC_STR_3 0
+ ;GOSUB fqmtr_query 0x4 &SRC_STR_4 0
+ ;GOSUB fqmtr_query 0x5 &SRC_STR_5 0
+ ;GOSUB fqmtr_query 0x6 &SRC_STR_6 0
+ ;GOSUB fqmtr_query 0x7 &SRC_STR_7 0
+ ;GOSUB fqmtr_query 0x8 &SRC_STR_8 0
+ ;GOSUB fqmtr_query 0x9 &SRC_STR_9 0
+ GOSUB fqmtr_query 0xA &SRC_STR_10 0
+ GOSUB fqmtr_query 0xB &SRC_STR_11 0
+ GOSUB fqmtr_query 0xC &SRC_STR_12 0
+ GOSUB fqmtr_query 0xD &SRC_STR_13 0
+ GOSUB fqmtr_query 0xE &SRC_STR_14 0
+ GOSUB fqmtr_query 0xF &SRC_STR_15 0
+ GOSUB fqmtr_query 0x10 &SRC_STR_16 0
+ GOSUB fqmtr_query 0x11 &SRC_STR_17 0
+ GOSUB fqmtr_query 0x12 &SRC_STR_18 0
+ GOSUB fqmtr_query 0x13 &SRC_STR_19 0
+ GOSUB fqmtr_query 0x14 &SRC_STR_20 0
+ GOSUB fqmtr_query 0x15 &SRC_STR_21 0
+ GOSUB fqmtr_query 0x16 &SRC_STR_22 0
+ GOSUB fqmtr_query 0x17 &SRC_STR_23 0
+ GOSUB fqmtr_query 0x18 &SRC_STR_24 0
+ GOSUB fqmtr_query 0x19 &SRC_STR_25 0
+ GOSUB fqmtr_query 0x1A &SRC_STR_26 0
+ GOSUB fqmtr_query 0x1B &SRC_STR_27 0
+ GOSUB fqmtr_query 0x1C &SRC_STR_28 0
+ GOSUB fqmtr_query 0x1D &SRC_STR_29 0
+ GOSUB fqmtr_query 0x1E &SRC_STR_30 0
+ GOSUB fqmtr_query 0x1F &SRC_STR_31 0
+
+ ; Revert to original value
+ Data.Set &mclass:(&pll_base+0x10) %LE %LONG &original_reg
+ Data.Set &mclass:(&pll_base+0x64) %LE %LONG &original_BPIPLLCTL1_reg
+
+ WAIT 1.s
+
+ RETURN
+)
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_GPIO_MDUART0.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_GPIO_MDUART0.cmm
new file mode 100755
index 0000000..00443d0
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_GPIO_MDUART0.cmm
@@ -0,0 +1,15 @@
+;Cannon MD_UART0 port test
+;You should make sure GPIO84 has connected to UART port RXD pin,GPIO85 has connected to UART port TXD pin
+
+;port: MDUART0
+;Baudrate: 115200
+;&BASE_ADDR_MDUART0=0xB0010000
+sys.m prepare
+&BASE_ADDR_MDUART0=0x20010000
+&BASE_ADDR_MDGPIO=0x10005000
+&BASE_ADDR_IOCFG=0x11E80000
+
+D.S AXI:&BASE_ADDR_MDGPIO+0x310 %LE %LONG 0xCCC00000 //set GPIO13 to MD_URXD0 mode,set GPIO14 to MD_UTXD0 mode,
+D.S AXI:&BASE_ADDR_IOCFG+0x60 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x60)&(0xFFFFFF7F) //MD_UTXD0 pull disable
+D.S AXI:&BASE_ADDR_IOCFG+0x60 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x60)|(0x00000040) //MD_URXD0 pull enable
+D.S AXI:&BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)|(0x00000040) //MD_URXD0 pull up
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_GPIO_SIM.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_GPIO_SIM.cmm
new file mode 100644
index 0000000..e26ae0f
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_GPIO_SIM.cmm
@@ -0,0 +1,9 @@
+// SIM GPIO
+d.s &MEM_CLASS:0x10005340 %long %le data.long(&MEM_CLASS:0x10005340)&(0x00000FFF)
+d.s &MEM_CLASS:0x10005340 %long %le data.long(&MEM_CLASS:0x10005340)|(0x11111000)
+
+d.s &MEM_CLASS:0x10005350 %long %le data.long(&MEM_CLASS:0x10005350)&(0xFFFFFFF0)
+d.s &MEM_CLASS:0x10005350 %long %le data.long(&MEM_CLASS:0x10005350)|(0x00000001)
+
+d.s &MEM_CLASS:0x11E700C0 %long %le data.long(&MEM_CLASS:0x11E700C0)&(0XFF8FFFF8)
+d.s &MEM_CLASS:0x11E700C0 %long %le data.long(&MEM_CLASS:0x11E700C0)|(0x00200002)
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_MD2PERI_disable.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_MD2PERI_disable.cmm
new file mode 100644
index 0000000..2354a68
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_MD2PERI_disable.cmm
@@ -0,0 +1,24 @@
+&MEM_CLASS="AXI"
+; do AP to MD path disable
+; MD cannot access AP after running this script
+LOCAL &BASE_ADDR_AP2MD_Dummy
+LOCAL &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN
+LOCAL &temp
+
+&BASE_ADDR_AP2MD_Dummy=0x10001370
+&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN=0x100012A0
+
+; Set reg_ap2md_dummy[0] = 1'b0
+&temp=data.long(&MEM_CLASS:(&BASE_ADDR_AP2MD_Dummy+0x0))&0xFFFFFFFE
+;PRINT "temp=" "&temp"
+;PRINT "BASE_ADDR_AP2MD_Dummy=" "&BASE_ADDR_AP2MD_Dummy"
+D.S &MEM_CLASS:(&BASE_ADDR_AP2MD_Dummy+0x0) %LE %LONG &temp
+wait 1.ms
+
+; Set md2peri_protect_en = 1'b1
+; Write 0x1000_12A8[6] = 1'b1.
+&temp=data.long(&MEM_CLASS:(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0x8))|0x40
+;PRINT "temp=" "&temp"
+;PRINT "(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0x8)"
+D.S &MEM_CLASS:(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0x8) %LE %LONG &temp
+wait 1.ms
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_MD_ForceOnDebugSys.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_MD_ForceOnDebugSys.cmm
new file mode 100755
index 0000000..76a11e0
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_MD_ForceOnDebugSys.cmm
@@ -0,0 +1,10 @@
+;Core1 force on
+d.s &MEM_CLASS:0x200D0004 %long %le 0xB2002383
+;ForceOn debug sys
+d.s &MEM_CLASS:0x20150010 %long %le data.long(&MEM_CLASS:0x20150010)|(0x00080008)
+d.s &MEM_CLASS:0x200D04B0 %long %le data.long(&MEM_CLASS:0x200D04B0)|(0x00000008)
+&temp=data.long(&MEM_CLASS:0x200D0590)
+IF (&temp&0x8008)!=0x8008
+(
+ PRINT "Force on debug sys clock fail"
+)
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_MD_PLL_Init.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_MD_PLL_Init.cmm
new file mode 100755
index 0000000..878bac3
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_MD_PLL_Init.cmm
@@ -0,0 +1,101 @@
+; /* Step 6 config PLL setting */
+;;==============================PLL init start==================================================
+;;sys.m prepare
+&MEM_CLASS="AXI"
+
+&BASE_MADDR_APMIXEDSYS=(0x1000C000)
+&BASE_MADDR_MDTOP_PLLMIXED=(0x20140000)
+&BASE_MADDR_MDTOP_CLKSW=(0x20150000)
+
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+®_MDTOP_PLLMIXED_MDTXPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x58)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+
+®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0x84)
+
+&MD_PLL_MAGIC_NUM=(0x62930000)
+
+;;//Enables clock square1 low-pass filter for 26M quality.
+d.s &MEM_CLASS:®_APMIXEDSYS_AP_PLL_CON0 %long %le data.long(&MEM_CLASS:®_APMIXEDSYS_AP_PLL_CON0)|0x2
+;;// 100us
+wait 1.ms
+
+;;// Default md_srclkena_ack settle time = 136T 32K
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E88
+
+;;// fixed 600MHz(/4), 343MHz(/7), 267MHz(/9) /* Fvco = 2400M */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x801713B1
+;;// 300MHz /* Fvco = 2400M */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDTXPLL_CTL0 %long %le 0x80171400
+;;// 400MHz /* Fvco = 3600M */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80229E00
+;;// 672MHz /* Fvco = 3360M */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x80204E00
+;;// 864MHz /* Fvco = 3456M */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x80213C00
+
+;;// Polling until MDMCUPLL complete frequency adjustment
+;WHILE ((data.long(&MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0
+;(
+;)
+wait 1.ms
+
+;;// Default disable BPI /7 clock
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDBPIPLL_CTL1 %long %le data.long(&MEM_CLASS:®_MDTOP_PLLMIXED_MDBPIPLL_CTL1)&0xFFFFFF7F
+
+;;/*TINFO="MDSYS_INIT: Update ABB MDPLL control register default value"*/
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x4C43100
+
+;;/* Force TXPLL ON due to TOPSM couldn't enable this PLL by default, TXPLL would be disable after DVFS Init.
+;; other PLL ON controlled by HW" */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x100010
+
+;; /*
+;; * Wait MD bus clock ready
+;; * Once MD bus ready, other clock should be ready too
+;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+;; */
+;WHILE (data.long(&MEM_CLASS:®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000
+;(
+;)
+wait 1.ms
+
+;;// Switch MDMCU & MD BUS clock to PLL frequency
+d.s &MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL)|(0x3)
+
+;;// Switch all clock to PLL frequency
+d.s &MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL)|(0x58103FC)
+
+;;// Switch SDF clock to PLL frequency
+d.s &MEM_CLASS:®_MDTOP_CLKSW_SDF_CK_CTL %long %le data.long(&MEM_CLASS:®_MDTOP_CLKSW_SDF_CK_CTL)|(0x10)
+
+;;// Turn off all SW clock request, except ATB
+d.s &MEM_CLASS:®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+;;// Mask all PLL ADJ RDY IRQ
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+;;// Make a record that means MD pll has been initialized.
+;;/* Note: We use "MD_PLL_MAGIC_NUM|0x1" to know PLL init in MD C code.
+;; If AP init PLL, it would be "MD_PLL_MAGIC_NUM". */
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_disable_WDT.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_disable_WDT.cmm
new file mode 100755
index 0000000..6ea39f8
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_disable_WDT.cmm
@@ -0,0 +1,11 @@
+;/* Step 8 Disable MD WDT */
+&MEM_CLASS="AXI"
+
+;&BASE_MADDR_MDRGU=0xA00F0000
+;&BASE_MADDR_APRGU=0xC0007000
+&BASE_MADDR_MDRGU=0x200F0000
+;&BASE_MADDR_APRGU=0x10007000
+
+D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+;D.S &MEM_CLASS:&BASE_MADDR_APRGU %LE %LONG 0x22000064
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_md_srclkena.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_md_srclkena.cmm
new file mode 100755
index 0000000..244a27c
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/APview_MT6771_md_srclkena.cmm
@@ -0,0 +1,33 @@
+; /* Step 6 config md_srclkena setting */
+&MEM_CLASS="AXI"
+
+; /* (1) INFRA_MISC2 */
+&BASE_INFRACFG=(0x10000000)
+; /* (2) SRCLKEN_O1 force on */
+&SPM_REG=(0x10006000)
+
+
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(&BASE_INFRACFG+0x1F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+
+
+; /* (1) INFRA_MISC2 */
+; /* [3:0] : mdsrc_req_0_en = 4'b0001 */
+d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFFF0)
+d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x1)
+
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 */
+d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFF0F)
+d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x20)
+
+; /* (2) SRCLKEN_O1 force on */
+//MMRF request
+D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x00215830 //set src clkena1 force on
+
+wait 1.ms
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/CoreTracer_MT6771_Disable_WDT.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/CoreTracer_MT6771_Disable_WDT.cmm
new file mode 100755
index 0000000..8ba2bba
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/CoreTracer_MT6771_Disable_WDT.cmm
@@ -0,0 +1,34 @@
+;sys.m prepare
+;LOCAL &TYPE
+
+
+system.mode attach
+
+; configure GCR_ACCESS Register
+; CoreTracer will access MO port via CPU to do following configuration
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+
+
+
+; do orginal APview_MT6771_disable_WDT.cmm
+LOCAL &BASE_MADDR_MDRGU
+&BASE_MADDR_MDRGU=0xA00F0000
+
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG 0x55000030
+
+PRINT "=============================="
+PRINT "Done disable MD WDT!"
+PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/Coretracer_MT6771_Frequency_Meter.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/Coretracer_MT6771_Frequency_Meter.cmm
new file mode 100755
index 0000000..1c41fbc
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/Coretracer_MT6771_Frequency_Meter.cmm
@@ -0,0 +1,219 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; MT6771 MD Frequency Meter
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+
+;;;;;;;;;;;;;;;;;;;;;;;Below you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LOCAL &clksw_base ;; MD CLKSW base address
+&clksw_base=0xA0150000 ;; MD view APB
+;&clksw_base=0xA0096000 ;; MD view debug APB
+;&clksw_base=0x20150000 ;; AP view MD system bus
+;&clksw_base=0x0D0D6000 ;; AP view MD debug sys
+
+LOCAL &pll_base ;; MD PLLMIXED base address
+&pll_base=0xA0140000 ;; MD view APB
+;&pll_base=0xA0094000 ;; MD view debug APB
+;&pll_base=0x20140000 ;; AP view MD system bus
+;&pll_base=0x0D0D4000 ;; AP view MD debug sys
+
+&fqmtr_fcksel_32k_index=0x17
+
+;;;;;;;;;;;;;;;;;;;;;;;Above you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LOCAL &fqmtr_winset ;; Frequency Meter Windoiw Setting (= Number of FIXED clock cycle)
+&fqmtr_winset=0x1ff
+&fqmtr_winset_for_32k=0x1E000
+
+LOCAL &fqmtr_fcksel_val ;; Frequency Meter FIXED clock selection
+&fqmtr_fcksel_val=0x1a ;; Select 26Mhz by default
+
+&SRC_STR_10="TRACE_MON_clock"
+&SRC_STR_11="MDSYS_208M_clock"
+&SRC_STR_12="mdrxsys_rake_clock"
+&SRC_STR_13="mdrxsys_brp_clock"
+&SRC_STR_14="mdrxsys_vdsp_clock"
+&SRC_STR_15="mdtop_log_atb_clock"
+&SRC_STR_16="fesys_csys_clock"
+&SRC_STR_17="fesys_txsys_clock"
+&SRC_STR_18="fesys_bsi_clock"
+&SRC_STR_19="mdsys_mdcore_clock"
+&SRC_STR_20="mdsys_bus2x_nodcm_clock"
+&SRC_STR_21="mdsys_bus2x_clock"
+&SRC_STR_22="mdtop_dbg_clock"
+&SRC_STR_23="mdtop_f32k_clock"
+&SRC_STR_24="MDBPIPLL_0_DIV2_clock"
+&SRC_STR_25="MDBPIPLL_2_clock"
+&SRC_STR_26="MDBPIPLL_1_clock"
+&SRC_STR_27="MDBPIPLL_0_clock"
+&SRC_STR_28="MDTXPLL_clock"
+&SRC_STR_29="MDBRPPLL_clock"
+&SRC_STR_30="MDVDSPPLL_clock"
+&SRC_STR_31="MDMCUPLL_clock"
+
+LOCAL &idx
+LOCAL &str
+&idx = 0xA;
+&str = "TRACE_MON_clock"
+GOSUB fqmtr_query
+&idx = 0xB;
+&str = "MDSYS_208M_clock"
+GOSUB fqmtr_query
+&idx = 0xC;
+&str = "mdrxsys_rake_clock"
+GOSUB fqmtr_query
+&idx = 0xD;
+&str = "mdrxsys_brp_clock"
+GOSUB fqmtr_query
+&idx = 0xE;
+&str = "mdrxsys_vdsp_clock"
+GOSUB fqmtr_query
+&idx = 0xF;
+&str = "mdtop_log_atb_clock"
+GOSUB fqmtr_query
+&idx = 0x10;
+&str = "fesys_csys_clock"
+GOSUB fqmtr_query
+&idx = 0x11;
+&str = "fesys_txsys_clock"
+GOSUB fqmtr_query
+&idx = 0x12;
+&str = "fesys_bsi_clock"
+GOSUB fqmtr_query
+&idx = 0x13;
+&str = "mdsys_mdcore_clock"
+GOSUB fqmtr_query
+&idx = 0x14;
+&str = "mdsys_bus2x_nodcm_clock"
+GOSUB fqmtr_query
+&idx = 0x15;
+&str = "mdsys_bus2x_clock"
+GOSUB fqmtr_query
+&idx = 0x16;
+&str = "mdtop_dbg_clock"
+GOSUB fqmtr_query
+&idx = 0x17;
+&str = "mdtop_f32k_clock"
+GOSUB fqmtr_query
+&idx = 0x18;
+&str = "MDBPIPLL_0_DIV2_clock"
+GOSUB fqmtr_query
+&idx = 0x19;
+&str = "MDBPIPLL_2_clock"
+GOSUB fqmtr_query
+&idx = 0x1A;
+&str = "MDBPIPLL_1_clock"
+GOSUB fqmtr_query
+&idx = 0x1B;
+&str = "MDBPIPLL_0_clock"
+GOSUB fqmtr_query
+&idx = 0x1C;
+&str = "MDTXPLL_clock"
+GOSUB fqmtr_query
+&idx = 0x1D;
+&str = "MDBRPPLL_clock"
+GOSUB fqmtr_query
+&idx = 0x1E;
+&str = "MDVDSPPLL_clock"
+GOSUB fqmtr_query
+&idx = 0x1F;
+&str = "MDMCUPLL_clock"
+GOSUB fqmtr_query
+
+&idx = 0x20;
+
+;;;;;The main function to get the Frequency. &idx==> the clock you select, &str==> clock name, &info==>list more info and wait 5ms in the function
+;; &info=1 ==> for printing many PLLs at one time
+fqmtr_query:
+ LOCAL &unit
+ LOCAL &fqmtr_winset_26M
+ LOCAL &fqmtr_result
+ LOCAL &fqmtr_result_raw
+ LOCAL &safe_wait_cnt
+ LOCAL &safe_wait_cnt_max
+
+ &safe_wait_cnt=0
+ IF &idx==0x20
+ (
+ RETURN
+ )
+ ELSE
+ (
+ IF &fqmtr_fcksel_val==0x1a ;; base on 26M, unit:MHz
+ (
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &unit="Khz"
+ &fqmtr_winset_26M=&fqmtr_winset_for_32k
+ &safe_wait_cnt_max=500 ;;5000 ms = 5s ==> in real test, longer than 5s, so reduce it
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &unit="Mhz"
+ &fqmtr_winset_26M=&fqmtr_winset
+ &safe_wait_cnt_max=32 ;;32 ms
+ )
+ )
+
+ ;;select source to a valid clock to let reset success.
+ Data.Set (&clksw_base+0x0100) %LE %LONG 0x13
+ Data.Set (&clksw_base+0x0104) %LE %LONG 0x0 ;reset frequency meter
+ WAIT 1000.us
+
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ ;;For accurate, don't div 8 for 32K
+ Data.Set (&clksw_base+0x0100) %LE %LONG (&idx)
+ )
+ ELSE ;; measure PLL and other module
+ (
+ ;;div 8 and select src
+ Data.Set (&clksw_base+0x0100) %LE %LONG (0x0300)|(&idx)
+ )
+
+ Data.Set (&clksw_base+0x0108) %LE %LONG &fqmtr_winset_26M
+ Data.Set (&clksw_base+0x0104) %LE %LONG 0x1 ;enable frequency meter
+
+ ;; read status, to check polling done or not
+ &fqmtr_busy=DATA.LONG(&clksw_base+0x0104)&(1<<1)
+
+ WHILE &fqmtr_busy==0
+ (
+; PRINT ". &fqmtr_busy"
+ &fqmtr_busy=DATA.LONG(&clksw_base+0x0104)&(1<<1)
+ &safe_wait_cnt=&safe_wait_cnt+1
+ IF &safe_wait_cnt==&safe_wait_cnt_max
+ (
+ PRINT "[&str] Wait Fail, exit"
+ RETURN
+ )
+ ELSE
+ (
+; PRINT "Waiting result. safe_wait_cnt=" "&safe_wait_cnt"
+ )
+ WAIT 1000.us
+
+ )
+
+ ;; Calculate the result
+ &fqmtr_result_raw=DATA.LONG(&clksw_base+0x10c)
+
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*(0x3E8)/(&fqmtr_winset_26M+3)
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*8/(&fqmtr_winset_26M+3)
+ )
+
+
+ &fqmtr_result_dec=&fqmtr_result
+ &fqmtr_result_dec=FORMAT.DECIMAL( 0 , &fqmtr_result )
+
+ PRINT " &idx , &fqmtr_result_dec &unit , &str "
+
+ WAIT 1000.us
+
+ RETURN
+ )
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/MT6771_Android_scatter.txt b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/MT6771_Android_scatter.txt
new file mode 100755
index 0000000..1fbd71a
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/MT6771_Android_scatter.txt
@@ -0,0 +1,596 @@
+############################################################################################################
+#
+# General Setting
+#
+############################################################################################################
+- general: MTK_PLATFORM_CFG
+ info:
+ - config_version: V1.1.2
+ platform: MT6771
+ project: evb6771_64_emmc
+ storage: EMMC
+ boot_channel: MSDC_0
+ block_size: 0x20000
+############################################################################################################
+#
+# Layout Setting
+#
+############################################################################################################
+- partition_index: SYS0
+ partition_name: preloader
+ file_name: preloader_evb6771_64_emmc_TINY.bin
+ is_download: true
+ type: SV5_BL_BIN
+ linear_start_addr: 0x0
+ physical_start_addr: 0x0
+ partition_size: 0x40000
+ region: EMMC_BOOT1_BOOT2
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: BOOTLOADERS
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS1
+ partition_name: pgpt
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x0
+ physical_start_addr: 0x0
+ partition_size: 0x8000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS2
+ partition_name: boot_para
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x8000
+ physical_start_addr: 0x8000
+ partition_size: 0x100000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS3
+ partition_name: recovery
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x108000
+ physical_start_addr: 0x108000
+ partition_size: 0x2000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS4
+ partition_name: para
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x2108000
+ physical_start_addr: 0x2108000
+ partition_size: 0x80000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS5
+ partition_name: expdb
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x2188000
+ physical_start_addr: 0x2188000
+ partition_size: 0x1400000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS6
+ partition_name: frp
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x3588000
+ physical_start_addr: 0x3588000
+ partition_size: 0x100000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS7
+ partition_name: nvcfg
+ file_name: NONE
+ is_download: false
+ type: EXT4_IMG
+ linear_start_addr: 0x3688000
+ physical_start_addr: 0x3688000
+ partition_size: 0x2000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: PROTECTED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS8
+ partition_name: nvdata
+ file_name: NONE
+ is_download: false
+ type: EXT4_IMG
+ linear_start_addr: 0x5688000
+ physical_start_addr: 0x5688000
+ partition_size: 0x4000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS9
+ partition_name: metadata
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x9688000
+ physical_start_addr: 0x9688000
+ partition_size: 0x2000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS10
+ partition_name: protect1
+ file_name: NONE
+ is_download: false
+ type: EXT4_IMG
+ linear_start_addr: 0xb688000
+ physical_start_addr: 0xb688000
+ partition_size: 0x800000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: PROTECTED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS11
+ partition_name: protect2
+ file_name: NONE
+ is_download: false
+ type: EXT4_IMG
+ linear_start_addr: 0xbe88000
+ physical_start_addr: 0xbe88000
+ partition_size: 0x978000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: PROTECTED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS12
+ partition_name: seccfg
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0xc800000
+ physical_start_addr: 0xc800000
+ partition_size: 0x800000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS13
+ partition_name: sec1
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0xd000000
+ physical_start_addr: 0xd000000
+ partition_size: 0x200000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS14
+ partition_name: proinfo
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0xd200000
+ physical_start_addr: 0xd200000
+ partition_size: 0x300000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: PROTECTED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS15
+ partition_name: md1img
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0xd500000
+ physical_start_addr: 0xd500000
+ partition_size: 0x4000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS16
+ partition_name: md1dsp
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x11500000
+ physical_start_addr: 0x11500000
+ partition_size: 0x1000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS17
+ partition_name: spmfw
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x12500000
+ physical_start_addr: 0x12500000
+ partition_size: 0x100000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS18
+ partition_name: gz1
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x12600000
+ physical_start_addr: 0x12600000
+ partition_size: 0x1000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS19
+ partition_name: gz2
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x13600000
+ physical_start_addr: 0x13600000
+ partition_size: 0x1000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS20
+ partition_name: nvram
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x14600000
+ physical_start_addr: 0x14600000
+ partition_size: 0x4000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: BINREGION
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS21
+ partition_name: lk
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x18600000
+ physical_start_addr: 0x18600000
+ partition_size: 0x100000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: true
+ reserve: 0x00
+
+- partition_index: SYS22
+ partition_name: lk2
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x18700000
+ physical_start_addr: 0x18700000
+ partition_size: 0x100000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS23
+ partition_name: boot
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x18800000
+ physical_start_addr: 0x18800000
+ partition_size: 0x2000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS24
+ partition_name: logo
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x1a800000
+ physical_start_addr: 0x1a800000
+ partition_size: 0x800000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: false
+ empty_boot_needed: true
+ reserve: 0x00
+
+- partition_index: SYS25
+ partition_name: odmdtbo
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x1b000000
+ physical_start_addr: 0x1b000000
+ partition_size: 0x1000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS26
+ partition_name: tee1
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x1c000000
+ physical_start_addr: 0x1c000000
+ partition_size: 0x500000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: true
+ reserve: 0x00
+
+- partition_index: SYS27
+ partition_name: tee2
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x1c500000
+ physical_start_addr: 0x1c500000
+ partition_size: 0xb00000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS28
+ partition_name: vendor
+ file_name: NONE
+ is_download: false
+ type: EXT4_IMG
+ linear_start_addr: 0x1d000000
+ physical_start_addr: 0x1d000000
+ partition_size: 0x25800000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS29
+ partition_name: system
+ file_name: NONE
+ is_download: false
+ type: EXT4_IMG
+ linear_start_addr: 0x42800000
+ physical_start_addr: 0x42800000
+ partition_size: 0xc0000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS30
+ partition_name: cache
+ file_name: NONE
+ is_download: false
+ type: EXT4_IMG
+ linear_start_addr: 0x102800000
+ physical_start_addr: 0x102800000
+ partition_size: 0x1b000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS31
+ partition_name: userdata
+ file_name: NONE
+ is_download: false
+ type: EXT4_IMG
+ linear_start_addr: 0x11d800000
+ physical_start_addr: 0x11d800000
+ partition_size: 0xc0000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS32
+ partition_name: flashinfo
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0xFFFF0080
+ physical_start_addr: 0xFFFF0080
+ partition_size: 0x1000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: false
+ is_reserved: true
+ operation_type: RESERVED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+- partition_index: SYS33
+ partition_name: sgpt
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0xFFFF0000
+ physical_start_addr: 0xFFFF0000
+ partition_size: 0x4200
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: false
+ is_reserved: true
+ operation_type: RESERVED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/MT6771_EVB_ETT.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/MT6771_EVB_ETT.cmm
new file mode 100755
index 0000000..33cecbf
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/MT6771_EVB_ETT.cmm
@@ -0,0 +1,53 @@
+;winclear
+
+
+system.reset
+SYSTEM.OPTION ENRESET ON
+SYStem.Option ResBreak OFF
+SYStem.Option WaitReset OFF
+SYStem.JtagClock 10.MHz
+
+SYStem.CPU CORTEXA53;
+Setting Core debug register access
+SYStem.CONFIG CORENUMBER 1;
+SYStem.CONFIG COREBASE 0x8D410000 0x8D510000 0x8D610000 0x8D710000 0x8D810000 0x8D910000 0x8DA10000 0x8DB10000;
+SYStem.CONFIG CTIBASE 0x8D420000 0x8D520000 0x8D620000 0x8D720000 0x8D820000 0x8D920000 0x8DA20000 0x8DB20000;
+;SYStem.CONFIG CORENUMBER 2;
+;SYStem.CONFIG COREBASE 0x80410000 0x80810000;
+;SYStem.CONFIG CTIBASE 0x80420000 0x80820000;
+
+
+
+SYStem.Up
+SETUP.IMASKHLL ON
+SETUP.IMASKASM ON
+SYStem.CONFIG SWDP ON
+
+; disable WDT
+d.s c:0x10007000 %le %long 0x22000064
+;d.s c:0x0 %le %long 0xEAFFFFFE
+;D.S SD:0x10202008 %LE %LONG 0x01
+D.S SD:0x0C5307F0 %LE %LONG 0x00000300 ;Enable L2C share SRAM (256K), cluster 0
+D.S SD:0x0C5307F0 %LE %LONG 0x00000301 ;Enable L2C share SRAM (256K), cluster 0
+
+
+d.load.elf ../out/MT6771_ETT/BIN/MT6771_ETT.elf /long
+
+core.select 0
+
+y.spath.reset
+Y.SPATH.SRD ../ett/ett
+Y.SPATH.SRD ../ett/Preloader/drivers
+;y.spath.srd ../inc
+;y.spath.srd ../inc/MT6771
+;y.spath.srd ../core/inc
+;y.spath.srd ../core/src
+;y.spath.srd ../arch/arm/inc
+y.spath.srd ../arch/arm/src
+;y.spath.srd ../arch/soc/inc
+y.spath.srd ../arch/soc/src
+;y.spath.srd ../ett/ett/inc/MT6771
+;y.spath.srd ../ett/ett/
+;y.spath.srd ../ett/Preloader/drivers/inc
+;y.spath.srd ../ett/Preloader/drivers
+d.l
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/MT6771_EVB_Load_MD_Elf.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/MT6771_EVB_Load_MD_Elf.cmm
new file mode 100755
index 0000000..7e75cb2
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/MT6771_EVB_Load_MD_Elf.cmm
@@ -0,0 +1,355 @@
+;sys.m prepare
+;LOCAL &TYPE
+
+
+system.mode attach
+
+; configure GCR_ACCESS Register
+; CoreTracer will access MO port via CPU to do following configuration
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+
+
+
+; do orginal APview_MT6771_disable_WDT.cmm
+LOCAL &BASE_MADDR_MDRGU
+&BASE_MADDR_MDRGU=0xA00F0000
+
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG 0x55000030
+
+
+
+PRINT "=============================="
+PRINT "config md_srclkena setting"
+PRINT "=============================="
+
+; /* Step 6 config md_srclkena setting */
+
+
+; /* (1) INFRA_MISC2 */
+&BASE_INFRACFG=(0xC0000000)
+; /* (2) SRCLKEN_O1 force on */
+&SPM_REG=(0xC0006000)
+
+
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(&BASE_INFRACFG+0x1F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+
+
+; /* (1) INFRA_MISC2 */
+; /* [3:0] : mdsrc_req_0_en = 4'b0001 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFFF0)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x1)
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFFF0)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x1)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFF0F)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x20)
+
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFF0F)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x20)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+; /* (2) SRCLKEN_O1 force on */
+; //MMRF request
+;D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+;D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x00215830 //set src clkena1 force on
+D.S &POWERON_CONFIG_EN %LE %LONG 0x0B160001
+D.S &SPM_POWER_ON_VAL1 %LE %LONG 0x00215830
+
+wait 1.ms
+
+
+
+PRINT "=============================="
+PRINT "config PLL setting"
+PRINT "=============================="
+
+; /* Step 5 config PLL setting */
+&BASE_MADDR_APMIXEDSYS=(0xC000C000)
+&BASE_MADDR_MDTOP_PLLMIXED=(0xA0140000)
+&BASE_MADDR_MDTOP_CLKSW=(0xA0150000)
+
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+®_MDTOP_PLLMIXED_MDTXPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x58)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0x84)
+
+&MD_PLL_MAGIC_NUM=(0x62930000)
+
+;;// initial CLKSQ_LPF
+&temp=data.long(AXI:®_APMIXEDSYS_AP_PLL_CON0)
+&temp=&temp|0x2
+d.s ®_APMIXEDSYS_AP_PLL_CON0 %long %le &temp
+;;// 100us
+wait 1.ms
+
+;;// Default md_srclkena_ack settle time = 136T 32K
+d.s ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E88
+
+;;// fixed 600MHz(/4), 343MHz(/7), 267MHz(/9) /* Fvco = 2400M */
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x801713B1
+;;// 300MHz /* Fvco = 2400M */
+d.s ®_MDTOP_PLLMIXED_MDTXPLL_CTL0 %long %le 0x80171400
+;;// 400MHz /* Fvco = 3600M */
+d.s ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80229E00
+;;// 672MHz /* Fvco = 3360M */
+d.s ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x80204E00
+;;// 864MHz /* Fvco = 3456M */
+d.s ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x80213C00
+
+;;// Polling until MDMCUPLL complete frequency adjustment
+;WHILE ((data.long(®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0
+;(
+;)
+wait 1.ms
+
+;;// Default disable BPI /7 clock
+&temp=data.long(®_MDTOP_PLLMIXED_MDBPIPLL_CTL1)
+&temp=&temp&(~0x80)
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL1 %long %le &temp
+
+;;/*TINFO="MDSYS_INIT: Update ABB MDPLL control register default value"*/
+d.s ®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x4C43100
+
+;;/* Force TXPLL ON due to TOPSM couldn't enable this PLL by default, TXPLL would be disable after DVFS Init.
+;; other PLL ON controlled by HW" */
+d.s ®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x100010
+
+;; /*
+;; * Wait MD bus clock ready
+;; * Once MD bus ready, other clock should be ready too
+;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+;; */
+;WHILE (data.long(®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000
+;(
+)
+wait 2.ms
+
+;;// Switch MDMCU & MD BUS clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x3)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch all clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x58103FC)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch SDF clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_SDF_CK_CTL)
+&temp=&temp|(0x10)
+d.s ®_MDTOP_CLKSW_SDF_CK_CTL %long %le &temp
+
+;;// Turn off all SW clock request, except ATB
+d.s ®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+;;// Mask all PLL ADJ RDY IRQ
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+;;// Make a record that means MD pll has been initialized.
+;;/* Note: We use "MD_PLL_MAGIC_NUM|0x1" to know PLL init in MD C code.
+;; If AP init PLL, it would be "MD_PLL_MAGIC_NUM". */
+d.s ®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+
+
+PRINT "=============================="
+PRINT "Set GPIO!"
+PRINT "=============================="
+
+// Step 8: Set GPIO
+
+&BASE_ADDR_MDGPIO=0xC0005000
+&BASE_ADDR_IOCFG=0xC1E80000
+
+// MD UART GPIO
+;D.S AXI:&BASE_ADDR_MDGPIO+0x310 %LE %LONG 0xCCC00000 //set GPIO13 to MD_URXD0 mode,set GPIO14 to MD_UTXD0 mode,
+;D.S AXI:&BASE_ADDR_IOCFG+0x60 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x60)&(0xFFFFFF7F) //MD_UTXD0 pull disable
+;D.S AXI:&BASE_ADDR_IOCFG+0x60 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x60)|(0x00000040) //MD_URXD0 pull enable
+;D.S AXI:&BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)|(0x00000040) //MD_URXD0 pull up
+D.S &BASE_ADDR_MDGPIO+0x310 %LE %LONG 0xCCC00000
+&temp=data.long(&BASE_ADDR_IOCFG+0x60)
+&temp=&temp&(0xFFFFFF7F)
+D.S &BASE_ADDR_IOCFG+0x60 %LE %LONG &temp
+&temp=data.long(&BASE_ADDR_IOCFG+0x60)
+&temp=&temp|(0x40)
+D.S &BASE_ADDR_IOCFG+0x60 %LE %LONG &temp
+&temp=data.long(&BASE_ADDR_IOCFG+0x80)
+&temp=&temp|(0x40)
+D.S &BASE_ADDR_IOCFG+0x80 %LE %LONG &temp
+
+
+// SIM GPIO
+;d.s &MEM_CLASS:0x10005340 %long %le data.long(&MEM_CLASS:0x10005340)&(0x00000FFF)
+;d.s &MEM_CLASS:0x10005340 %long %le data.long(&MEM_CLASS:0x10005340)|(0x11111000)
+
+&temp=data.long(0xC0005340)
+&temp=&temp &(0x00000FFF)
+D.S 0xC0005340 %LE %LONG &temp
+
+&temp=data.long(0xC0005340)
+&temp=&temp |(0x11111000)
+D.S 0xC0005340 %LE %LONG &temp
+
+;d.s &MEM_CLASS:0x10005350 %long %le data.long(&MEM_CLASS:0x10005350)&(0xFFFFFFF0)
+;d.s &MEM_CLASS:0x10005350 %long %le data.long(&MEM_CLASS:0x10005350)|(0x00000001)
+
+&temp=data.long(0xC0005350)
+&temp=&temp &(0xFFFFFFF0)
+D.S 0xC0005350 %LE %LONG &temp
+
+&temp=data.long(0xC0005350)
+&temp=&temp |(0x00000001)
+D.S 0xC0005350 %LE %LONG &temp
+
+;d.s &MEM_CLASS:0x11E700C0 %long %le data.long(&MEM_CLASS:0x11E700C0)&(0xFF8FFFF8)
+;d.s &MEM_CLASS:0x11E700C0 %long %le data.long(&MEM_CLASS:0x11E700C0)|(0x00200002)
+
+&temp=data.long(0xC1E700C0)
+&temp=&temp & (0xFF8FFFF8)
+D.S 0xC1E700C0 %LE %LONG &temp
+
+&temp=data.long(0xC1E700C0)
+&temp=&temp |(0x00200002)
+D.S 0xC1E700C0 %LE %LONG &temp
+
+
+
+
+PRINT "=============================="
+PRINT "Set MD EMI Remap!"
+PRINT "=============================="
+
+
+;Step 10 set MD EMI remap address (MD view: step 9) ==>review done
+;d.s &MEM_CLASS:0xC0001300 %long %le 0x00430041
+;d.s &MEM_CLASS:0xC0001304 %long %le 0x00470045
+;d.s &MEM_CLASS:0xC0001308 %long %le 0x004b0049
+;d.s &MEM_CLASS:0xC000130c %long %le 0x004f004d
+D.S 0xC0001300 %LE %LONG 0x00430041
+D.S 0xC0001304 %LE %LONG 0x00470045
+D.S 0xC0001308 %LE %LONG 0x004b0049
+D.S 0xC000130c %LE %LONG 0x004f004d
+
+
+PRINT "=============================="
+PRINT "Set AP2MD PATH Disable!"
+PRINT "=============================="
+
+; do AP to MD path disable
+&BASE_ADDR_AP2MD_Dummy = 0xC0001370
+&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN=0xC00012A0
+
+
+; Set reg_ap2md_dummy[0] = 1'b0
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp & 0xFFFFFFFE
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+; Set peri2md_protect_en
+; Write 0x1000_12A0[7] = 1'b1.
+; MD can access AP if reg_ap2md_dummy[0] = 1'b1,
+&temp=data.long(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN)
+&temp = &temp | 0x80
+D.S &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN %LE %LONG &temp
+wait 1.ms
+
+; Clear md2peri_protect_en
+; Write 0x1000_12AC[6] = 1'b1.
+&temp=data.long(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC)
+&temp = &temp | 0x40
+D.S &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp | 0x1
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+
+
+;Enalbe cache to speed loading
+;By setting bank 6 segment control attribute
+register.set cdmmbase 0x1fc1407
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor adapter_khz 2000
+steal monitor mips32 fastchannel 0 1 0x6f800000
+
+
+PRINT "=============================="
+PRINT "Start to Load elf !"
+PRINT "=============================="
+
+thread.select 1
+steal lo
+
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+PRINT "=============================="
+PRINT "Load elf Done!"
+PRINT "=============================="
+
+thread.select 1
+
+;&t=var.address(INT_Initialize_Phase1)
+;wait 20.ms
+;stop
+;steal set $pc = &INT_Initialize_Phase1
+;register.set pc &t
+
+;PRINT "=============================="
+;PRINT "Set PC to INT_Initialize_Phase1: &t"
+;PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/MT6771_EVB_Load_MD_Elf_With_DSP.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/MT6771_EVB_Load_MD_Elf_With_DSP.cmm
new file mode 100755
index 0000000..0a426e3
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/MT6771_EVB_Load_MD_Elf_With_DSP.cmm
@@ -0,0 +1,357 @@
+;sys.m prepare
+;LOCAL &TYPE
+
+
+system.mode attach
+
+; configure GCR_ACCESS Register
+; CoreTracer will access MO port via CPU to do following configuration
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+
+
+
+; do orginal APview_MT6771_disable_WDT.cmm
+LOCAL &BASE_MADDR_MDRGU
+&BASE_MADDR_MDRGU=0xA00F0000
+
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG 0x55000030
+
+
+
+PRINT "=============================="
+PRINT "config md_srclkena setting"
+PRINT "=============================="
+
+; /* Step 6 config md_srclkena setting */
+
+
+; /* (1) INFRA_MISC2 */
+&BASE_INFRACFG=(0xC0000000)
+; /* (2) SRCLKEN_O1 force on */
+&SPM_REG=(0xC0006000)
+
+
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(&BASE_INFRACFG+0x1F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+
+
+; /* (1) INFRA_MISC2 */
+; /* [3:0] : mdsrc_req_0_en = 4'b0001 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFFF0)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x1)
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFFF0)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x1)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 */
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFF0F)
+;d.s (&MEM_CLASS:&INFRA_MISC2) %long %le data.long(&MEM_CLASS:&INFRA_MISC2)|(0x20)
+
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp &(0xFFFFFF0F)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+&temp=data.long(&INFRA_MISC2)
+&temp=&temp |(0x20)
+D.S &INFRA_MISC2 %LE %LONG &temp
+
+
+
+; /* (2) SRCLKEN_O1 force on */
+; //MMRF request
+;D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+;D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x00215830 //set src clkena1 force on
+D.S &POWERON_CONFIG_EN %LE %LONG 0x0B160001
+D.S &SPM_POWER_ON_VAL1 %LE %LONG 0x00215830
+
+wait 1.ms
+
+
+
+PRINT "=============================="
+PRINT "config PLL setting"
+PRINT "=============================="
+
+; /* Step 5 config PLL setting */
+&BASE_MADDR_APMIXEDSYS=(0xC000C000)
+&BASE_MADDR_MDTOP_PLLMIXED=(0xA0140000)
+&BASE_MADDR_MDTOP_CLKSW=(0xA0150000)
+
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+®_MDTOP_PLLMIXED_MDTXPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x58)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0x84)
+
+&MD_PLL_MAGIC_NUM=(0x62930000)
+
+;;// initial CLKSQ_LPF
+&temp=data.long(AXI:®_APMIXEDSYS_AP_PLL_CON0)
+&temp=&temp|0x2
+d.s ®_APMIXEDSYS_AP_PLL_CON0 %long %le &temp
+;;// 100us
+wait 1.ms
+
+;;// Default md_srclkena_ack settle time = 136T 32K
+d.s ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E88
+
+;;// fixed 600MHz(/4), 343MHz(/7), 267MHz(/9) /* Fvco = 2400M */
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x801713B1
+;;// 300MHz /* Fvco = 2400M */
+d.s ®_MDTOP_PLLMIXED_MDTXPLL_CTL0 %long %le 0x80171400
+;;// 400MHz /* Fvco = 3600M */
+d.s ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80229E00
+;;// 672MHz /* Fvco = 3360M */
+d.s ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x80204E00
+;;// 864MHz /* Fvco = 3456M */
+d.s ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x80213C00
+
+;;// Polling until MDMCUPLL complete frequency adjustment
+;WHILE ((data.long(®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0
+;(
+;)
+wait 1.ms
+
+;;// Default disable BPI /7 clock
+&temp=data.long(®_MDTOP_PLLMIXED_MDBPIPLL_CTL1)
+&temp=&temp&(~0x80)
+d.s ®_MDTOP_PLLMIXED_MDBPIPLL_CTL1 %long %le &temp
+
+;;/*TINFO="MDSYS_INIT: Update ABB MDPLL control register default value"*/
+d.s ®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x4C43100
+
+;;/* Force TXPLL ON due to TOPSM couldn't enable this PLL by default, TXPLL would be disable after DVFS Init.
+;; other PLL ON controlled by HW" */
+d.s ®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x100010
+
+;; /*
+;; * Wait MD bus clock ready
+;; * Once MD bus ready, other clock should be ready too
+;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+;; */
+;WHILE (data.long(®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000
+;(
+)
+wait 2.ms
+
+;;// Switch MDMCU & MD BUS clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x3)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch all clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+&temp=&temp|(0x58103FC)
+d.s ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+;;// Switch SDF clock to PLL frequency
+&temp=data.long(®_MDTOP_CLKSW_SDF_CK_CTL)
+&temp=&temp|(0x10)
+d.s ®_MDTOP_CLKSW_SDF_CK_CTL %long %le &temp
+
+;;// Turn off all SW clock request, except ATB
+d.s ®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+;;// Mask all PLL ADJ RDY IRQ
+d.s ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+;;// Make a record that means MD pll has been initialized.
+;;/* Note: We use "MD_PLL_MAGIC_NUM|0x1" to know PLL init in MD C code.
+;; If AP init PLL, it would be "MD_PLL_MAGIC_NUM". */
+d.s ®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+
+
+PRINT "=============================="
+PRINT "Set GPIO!"
+PRINT "=============================="
+
+// Step 8: Set GPIO
+
+&BASE_ADDR_MDGPIO=0xC0005000
+&BASE_ADDR_IOCFG=0xC1E80000
+
+// MD UART GPIO
+;D.S AXI:&BASE_ADDR_MDGPIO+0x310 %LE %LONG 0xCCC00000 //set GPIO13 to MD_URXD0 mode,set GPIO14 to MD_UTXD0 mode,
+;D.S AXI:&BASE_ADDR_IOCFG+0x60 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x60)&(0xFFFFFF7F) //MD_UTXD0 pull disable
+;D.S AXI:&BASE_ADDR_IOCFG+0x60 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x60)|(0x00000040) //MD_URXD0 pull enable
+;D.S AXI:&BASE_ADDR_IOCFG+0x80 %LE %LONG data.long(AXI:&BASE_ADDR_IOCFG+0x80)|(0x00000040) //MD_URXD0 pull up
+D.S &BASE_ADDR_MDGPIO+0x310 %LE %LONG 0xCCC00000
+&temp=data.long(&BASE_ADDR_IOCFG+0x60)
+&temp=&temp&(0xFFFFFF7F)
+D.S &BASE_ADDR_IOCFG+0x60 %LE %LONG &temp
+&temp=data.long(&BASE_ADDR_IOCFG+0x60)
+&temp=&temp|(0x40)
+D.S &BASE_ADDR_IOCFG+0x60 %LE %LONG &temp
+&temp=data.long(&BASE_ADDR_IOCFG+0x80)
+&temp=&temp|(0x40)
+D.S &BASE_ADDR_IOCFG+0x80 %LE %LONG &temp
+
+
+// SIM GPIO
+;d.s &MEM_CLASS:0x10005340 %long %le data.long(&MEM_CLASS:0x10005340)&(0x00000FFF)
+;d.s &MEM_CLASS:0x10005340 %long %le data.long(&MEM_CLASS:0x10005340)|(0x11111000)
+
+&temp=data.long(0xC0005340)
+&temp=&temp &(0x00000FFF)
+D.S 0xC0005340 %LE %LONG &temp
+
+&temp=data.long(0xC0005340)
+&temp=&temp |(0x11111000)
+D.S 0xC0005340 %LE %LONG &temp
+
+;d.s &MEM_CLASS:0x10005350 %long %le data.long(&MEM_CLASS:0x10005350)&(0xFFFFFFF0)
+;d.s &MEM_CLASS:0x10005350 %long %le data.long(&MEM_CLASS:0x10005350)|(0x00000001)
+
+&temp=data.long(0xC0005350)
+&temp=&temp &(0xFFFFFFF0)
+D.S 0xC0005350 %LE %LONG &temp
+
+&temp=data.long(0xC0005350)
+&temp=&temp |(0x00000001)
+D.S 0xC0005350 %LE %LONG &temp
+
+;d.s &MEM_CLASS:0x11E700C0 %long %le data.long(&MEM_CLASS:0x11E700C0)&(0xFF8FFFF8)
+;d.s &MEM_CLASS:0x11E700C0 %long %le data.long(&MEM_CLASS:0x11E700C0)|(0x00200002)
+
+&temp=data.long(0xC1E700C0)
+&temp=&temp & (0xFF8FFFF8)
+D.S 0xC1E700C0 %LE %LONG &temp
+
+&temp=data.long(0xC1E700C0)
+&temp=&temp |(0x00200002)
+D.S 0xC1E700C0 %LE %LONG &temp
+
+
+
+
+PRINT "=============================="
+PRINT "Set MD EMI Remap!"
+PRINT "=============================="
+
+
+;Step 10 set MD EMI remap address (MD view: step 9) ==>review done
+;d.s &MEM_CLASS:0xC0001300 %long %le 0x00430041
+;d.s &MEM_CLASS:0xC0001304 %long %le 0x00470045
+;d.s &MEM_CLASS:0xC0001308 %long %le 0x004b0049
+;d.s &MEM_CLASS:0xC000130c %long %le 0x004f004d
+D.S 0xC0001300 %LE %LONG 0x00430041
+D.S 0xC0001304 %LE %LONG 0x00470045
+D.S 0xC0001308 %LE %LONG 0x004b0049
+D.S 0xC000130c %LE %LONG 0x004f004d
+
+
+PRINT "=============================="
+PRINT "Set AP2MD PATH Disable!"
+PRINT "=============================="
+
+; do AP to MD path disable
+&BASE_ADDR_AP2MD_Dummy = 0xC0001370
+&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN=0xC00012A0
+
+
+; Set reg_ap2md_dummy[0] = 1'b0
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp & 0xFFFFFFFE
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+; Set peri2md_protect_en
+; Write 0x1000_12A0[7] = 1'b1.
+; MD can access AP if reg_ap2md_dummy[0] = 1'b1,
+&temp=data.long(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN)
+&temp = &temp | 0x80
+D.S &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN %LE %LONG &temp
+wait 1.ms
+
+; Clear md2peri_protect_en
+; Write 0x1000_12AC[6] = 1'b1.
+&temp=data.long(&BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC)
+&temp = &temp | 0x40
+D.S &BASE_ADDR_INFRA_SET_CLEAR_PROT_EN+0xC %LE %LONG &temp
+wait 1.ms
+
+&temp=data.long(&BASE_ADDR_AP2MD_Dummy)
+&temp = &temp | 0x1
+D.S &BASE_ADDR_AP2MD_Dummy %LE %LONG &temp
+wait 1.ms
+
+
+
+;Enalbe cache to speed loading
+;By setting bank 6 segment control attribute
+register.set cdmmbase 0x1fc1407
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor adapter_khz 2000
+steal monitor mips32 fastchannel 0 1 0x6f800000
+
+
+PRINT "=============================="
+PRINT "Start to Load elf !"
+PRINT "=============================="
+
+thread.select 1
+steal lo
+
+steal source ../cmm/coretracer\config\easyLoader\load_dsp.py
+
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+PRINT "=============================="
+PRINT "Load elf Done!"
+PRINT "=============================="
+
+thread.select 1
+
+;&t=var.address(INT_Initialize_Phase1)
+;wait 20.ms
+;stop
+;steal set $pc = &INT_Initialize_Phase1
+;register.set pc &t
+
+;PRINT "=============================="
+;PRINT "Set PC to INT_Initialize_Phase1: &t"
+;PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/MT6771_MD_Only.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/MT6771_MD_Only.cmm
new file mode 100755
index 0000000..82dcd0f
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/MT6771_MD_Only.cmm
@@ -0,0 +1,52 @@
+;AP pmic workaround
+&MEM_CLASS="AXI"
+sys.m prepare
+wait 1.ms
+
+; Step 1 (AP CCCI only) Configure AP/MD shared buck through DVFSRC API
+; [Note] CVD script do NOT need this step
+; skip
+
+; Step 3 config MD related Buck
+; [Note] CVD script do NOT need this step
+; AP preloader should set Modem related buck
+; skip
+
+; Step 4 power on MTCMOS
+; [Note] CVD script do NOT need this step
+; skip
+
+; Step 5 disable MD access register
+do APview_MT6771_MD2PERI_disable.cmm
+
+; Step 6 config md_srclkena setting
+do APview_MT6771_md_srclkena.cmm
+
+; Step 7 config PLL setting
+do APview_MT6771_MD_PLL_Init.cmm
+
+; Step 8 Disable MD WDT
+do APview_MT6771_disable_WDT.cmm
+
+; Step 9 enable MD to Access AP Register
+do APview_MT6771_AP2MD_enable.cmm
+
+; Step 10 Trigger MD MCU to run (AP view)
+; [Note] Trigger MD MCU by debugger
+; skip
+
+; Step 11 set GPIO (MD view: step 7)
+do APview_MT6771_GPIO_MDUART0.cmm
+do APview_MT6771_GPIO_SIM.cmm
+
+;Step 12 Force on Debug Sys clock (MD view: step 8)
+;do APview_MT6771_MD_ForceOnDebugSys.cmm
+
+;Step 13 set MD EMI remap address (MD view: step 9)
+d.s &MEM_CLASS:0x10001300 %long %le 0x00430041
+d.s &MEM_CLASS:0x10001304 %long %le 0x00470045
+d.s &MEM_CLASS:0x10001308 %long %le 0x004b0049
+d.s &MEM_CLASS:0x1000130c %long %le 0x004f004d
+
+; Final Step: Trigger MD MCU to run
+; skip
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/L1Bypass.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/L1Bypass.act
new file mode 100755
index 0000000..a3c4b52
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/L1Bypass.act
@@ -0,0 +1,6 @@
+<?xml version="1.0"?>
+<Customize>
+ <Action name="L1AssertBypass" icon="">
+ <GDB>p/x L1_ASSERT_BYPASS=3</GDB>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/LoadDSPBin.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/LoadDSPBin.cmm
new file mode 100755
index 0000000..263524f
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/LoadDSPBin.cmm
@@ -0,0 +1,17 @@
+system.mode attach
+
+register.set cdmmbase 0x1fc1407
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor mips32 fastchannel 0 1
+
+&temp_addr = var.address(dsp_bin_ro)
+&temp_addr = &temp_addr & 0x0FFFFFFF
+;&temp_addr = &temp_addr | 0xA0000000
+
+data.load.bin U:\MT6292\UMOLYA\DEV\UMOLYA.BIANCO.BRINGUP.DEV\mcu\build\BIANCO_FPGA\L1S_L1DISABLE\bin\DSP_BIANCO_UMOLYA_BIANCO_BRINGUP_DEV_W17_04_LTE_P3.bin &temp_addr
+;data.load.bin "D:\dsp123.bin" &temp_addr
+
+print "load dsp done!"
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+enddo
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/L1Bypass.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/L1Bypass.act
new file mode 100755
index 0000000..a3c4b52
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/L1Bypass.act
@@ -0,0 +1,6 @@
+<?xml version="1.0"?>
+<Customize>
+ <Action name="L1AssertBypass" icon="">
+ <GDB>p/x L1_ASSERT_BYPASS=3</GDB>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_AllIn1_LoadCode.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_AllIn1_LoadCode.launch
new file mode 100755
index 0000000..c4be7e6
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_AllIn1_LoadCode.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
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diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_AllIn1_LoadCode_With_DSP.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_AllIn1_LoadCode_With_DSP.launch
new file mode 100755
index 0000000..526e5a7
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_AllIn1_LoadCode_With_DSP.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_AllIn1_LoadCode_non_halt.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_AllIn1_LoadCode_non_halt.launch
new file mode 100755
index 0000000..a215b4c
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_AllIn1_LoadCode_non_halt.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
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+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_AllIn1_LoadSymbol.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_AllIn1_LoadSymbol.launch
new file mode 100755
index 0000000..9efd844
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_AllIn1_LoadSymbol.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
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+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
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+<stringAttribute key="com.mediatek.ide.util.runCommands" value="hb general_ex_handler hb INT_TEMP_general_ex_vector"/>
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+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_AllIn1_LoadSymbol_non_halt.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_AllIn1_LoadSymbol_non_halt.launch
new file mode 100755
index 0000000..9df1701
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_AllIn1_LoadSymbol_non_halt.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
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+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
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+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="attach"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git "a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadCode\0501\051.launch" "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadCode\0501\051.launch"
new file mode 100755
index 0000000..085a113
--- /dev/null
+++ "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadCode\0501\051.launch"
@@ -0,0 +1,54 @@
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diff --git "a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadCode\0502\051.launch" "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadCode\0502\051.launch"
new file mode 100755
index 0000000..05c2643
--- /dev/null
+++ "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadCode\0502\051.launch"
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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diff --git "a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadCode\0503\051.launch" "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadCode\0503\051.launch"
new file mode 100755
index 0000000..a9756e3
--- /dev/null
+++ "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadCode\0503\051.launch"
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
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diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadCode.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadCode.launch
new file mode 100755
index 0000000..4a03a4a
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadCode.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
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diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadCode_All.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadCode_All.launch
new file mode 100755
index 0000000..8829a37
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadCode_All.launch
@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.group.launchConfigurationType">
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+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.name" value="MT6739_Alone_LoadCode(3)"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadCode_All.launch.bak b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadCode_All.launch.bak
new file mode 100755
index 0000000..8829a37
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadCode_All.launch.bak
@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.group.launchConfigurationType">
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+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.enabled" value="true"/>
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+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+</launchConfiguration>
diff --git "a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadSymbol\0501\051.launch" "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadSymbol\0501\051.launch"
new file mode 100755
index 0000000..085a113
--- /dev/null
+++ "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadSymbol\0501\051.launch"
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.cacheFile" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearExpression" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.RemoteTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<intAttribute key="com.mediatek.ide.util.gdbPortNumber" value="3667"/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<stringAttribute key="com.mediatek.ide.util.ipAddress" value="localhost"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value="hb general_ex_handler"/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value="[CMMAUTOGEN_ROOT]"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="Zion_evb_amp"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="attach"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git "a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadSymbol\0502\051.launch" "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadSymbol\0502\051.launch"
new file mode 100755
index 0000000..05c2643
--- /dev/null
+++ "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadSymbol\0502\051.launch"
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.cacheFile" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearExpression" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.RemoteTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<intAttribute key="com.mediatek.ide.util.gdbPortNumber" value="3668"/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<stringAttribute key="com.mediatek.ide.util.ipAddress" value="localhost"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value="hb general_ex_handler"/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value="[CMMAUTOGEN_ROOT]"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="Zion_evb_amp"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="attach"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git "a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadSymbol\0503\051.launch" "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadSymbol\0503\051.launch"
new file mode 100755
index 0000000..a9756e3
--- /dev/null
+++ "b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadSymbol\0503\051.launch"
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.cacheFile" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearExpression" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.RemoteTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<intAttribute key="com.mediatek.ide.util.gdbPortNumber" value="3669"/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<stringAttribute key="com.mediatek.ide.util.ipAddress" value="localhost"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value="hb general_ex_handler"/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value="[CMMAUTOGEN_ROOT]"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="Zion_evb_amp"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="attach"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadSymbol.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadSymbol.launch
new file mode 100755
index 0000000..813e482
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadSymbol.launch
@@ -0,0 +1,54 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="[CMMAUTOGEN_ELFPath]"/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.cacheFile" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearExpression" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.RemoteTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<intAttribute key="com.mediatek.ide.util.gdbPortNumber" value="3666"/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<stringAttribute key="com.mediatek.ide.util.ipAddress" value="localhost"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value="hb general_ex_handler"/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value="[CMMAUTOGEN_ROOT]"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="Zion_evb_amp"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="attach"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadSymbol_All.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadSymbol_All.launch
new file mode 100755
index 0000000..6578c62
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadSymbol_All.launch
@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.group.launchConfigurationType">
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.name" value="MT6739_Alone_LoadSymbol"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.name" value="MT6739_Alone_LoadSymbol(1)"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.name" value="MT6739_Alone_LoadSymbol(2)"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.name" value="MT6739_Alone_LoadSymbol(3)"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadSymbol_All.launch.bak b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadSymbol_All.launch.bak
new file mode 100755
index 0000000..6578c62
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/MT6771_Alone_LoadSymbol_All.launch.bak
@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.group.launchConfigurationType">
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.0.name" value="MT6739_Alone_LoadSymbol"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.1.name" value="MT6739_Alone_LoadSymbol(1)"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.2.name" value="MT6739_Alone_LoadSymbol(2)"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.action" value="NONE"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.enabled" value="true"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.mode" value="debug"/>
+<stringAttribute key="org.eclipse.cdt.launch.launchGroup.3.name" value="MT6739_Alone_LoadSymbol(3)"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/easyLoader/CoreTracer_easy_loader.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/easyLoader/CoreTracer_easy_loader.py
new file mode 100755
index 0000000..cc2c2fe
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/easyLoader/CoreTracer_easy_loader.py
@@ -0,0 +1,149 @@
+#from imgtec import codescape
+import sys
+import time
+import os
+import gdb
+import Tkinter, tkFileDialog
+
+#get full path of python script
+file_path = os.path.dirname(os.path.abspath(__file__))
+#append python path into system path
+sys.path.append(file_path)
+
+import load_dsp
+
+app = None
+
+# load all elf
+def load_all_elf(elf_path):
+ time_str = time.time()
+ print "=== Start Loading ELF ==="
+ print "Image path: " + elf_path
+ if(os.path.exists(elf_path) == False):
+ print "[Error] UMOLY ELF doesn't exist: %s" %(elf_path)
+ else:
+ elf_path = elf_path.replace('\\', '/')
+ gdb_cmd = 'symbol-file '+ elf_path
+ print gdb_cmd
+ gdb.execute(gdb_cmd)
+ print "Load SYMBOL successfully"
+ # Add debug point
+ gdb_cmd = 'hb general_ex_vector'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'lo '+ elf_path
+ print gdb_cmd
+ gdb.execute(gdb_cmd)
+ print "Load ELF successfully"
+ time_end = time.time()
+ print("All loading is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+# load all symbol only
+def load_all_sym(elf_path):
+ time_str = time.time()
+ print "=== Start Loading SYMBOL ==="
+ print "Image path: " + elf_path
+ if(os.path.exists(elf_path) == False):
+ print "[Error] UMOLY ELF doesn't exist: %s" %(elf_path)
+ else:
+ elf_path = elf_path.replace('\\', '/')
+ gdb_cmd = 'symbol-file '+ elf_path
+ print gdb_cmd
+ gdb.execute(gdb_cmd)
+ print "Load SYMBOL successfully"
+ # Add debug point
+ gdb_cmd = 'hb general_ex_vector'
+ gdb.execute(gdb_cmd)
+ time_end = time.time()
+ print("All loading is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+# load dsp bin file
+#def load_dsp_bin(dsp_path):
+# time_str = time.time()
+# print "=== Start load dsp bin ==="
+# print "Dsp bin path: " + dsp_path
+# if(os.path.exists(dsp_path) == False):
+# print "[Error] UMOLY DSP binary doesn't exist: %s" %(dsp_path)
+# else:
+# gdb_cmd='thread 1'
+# gdb.execute(gdb_cmd)
+# ## a) need parsing: 0x13a0000 <dsp_bin_ro>
+# ##symbol_name='&dsp_bin_ro'
+# ##dsp_addr = gdb.parse_and_eval(symbol_name)
+# ## b) need parsing: $3 = 0x13a0000
+# ##gdb_cmd='p/x &dsp_bin_ro'
+# ##dsp_addr = gdb.execute(gdb_cmd, False, True)
+# symbol_name='dsp_bin_ro'
+# dsp_addr = gdb.parse_and_eval(symbol_name)
+# dsp_addr = str(dsp_addr.address).split(" ")
+# gdb_cmd = 'restore ' + dsp_path + ' binary ' + str(dsp_addr[0])
+# print gdb_cmd
+# gdb.execute(gdb_cmd)
+# time_end = time.time()
+# print("loading dsp is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+def thread_memory_Write(mem_addr, set_value):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def thread_memory_Read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ mem_value = mem_value[12:23]
+ hex_int = int(mem_value, 16)
+ return hex_int
+
+
+class gui_tk(Tkinter.Tk):
+ def __init__(self, parent):
+ Tkinter.Tk.__init__(self, parent)
+ elf_path = ""
+ dsp_path = ""
+ dsp_addr = ""
+ self.file_opt = options = {}
+ options['title'] = 'Choose a file'
+ self.parent = parent
+ self.initialize()
+
+ def initialize(self):
+ self.grid()
+ elf_button = Tkinter.Button(self, text=u"Load elf", command=self.elf_OnButtonClick)
+ elf_button.grid(column=0, row=1, sticky='W')
+
+ sym_button = Tkinter.Button(self, text=u"Load symbol", command=self.sym_OnButtonClick)
+ sym_button.grid(column=0, row=2, sticky='W')
+
+ dsp_button = Tkinter.Button(self, text=u"Load DSP bin", command=self.dsp_OnButtonClick)
+ dsp_button.grid(column=0, row=3, sticky='W')
+
+ def elf_OnButtonClick(self):
+ elf_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(elf_path) > 0:
+ print "You chose %s" % elf_path
+ load_all_elf(elf_path)
+ self.quit()
+
+ def sym_OnButtonClick(self):
+ elf_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(elf_path) > 0:
+ print "You chose %s" % elf_path
+ load_all_sym(elf_path)
+ self.quit()
+
+ def dsp_OnButtonClick(self):
+ dsp_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(dsp_path) > 0:
+ print "You chose %s" % dsp_path
+ load_dsp.load_dsp_bin(dsp_path)
+ self.quit()
+
+ def quit(self):
+ global app
+ print "=== Close Easy Loader ==="
+ app.destroy()
+
+if __name__ == "__main__":
+ print "=== Start Easy Loader ==="
+ app = gui_tk(None)
+ app.title('Easy Loader')
+ app.mainloop()
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/easyLoader/load_dsp.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/easyLoader/load_dsp.py
new file mode 100755
index 0000000..86e47fa
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/coretracer/config/easyLoader/load_dsp.py
@@ -0,0 +1,106 @@
+#from imgtec import codescape
+import sys
+import time
+import os
+import gdb
+import binascii
+import Tkinter, tkFileDialog
+
+app = None
+dsp_header = 0x0
+dsp_magic = "4d4d4d01"
+
+# load dsp bin file
+def load_dsp_bin(dsp_path):
+ global dsp_header
+ time_str = time.time()
+ print "=== Start load dsp bin ==="
+ print "Dsp bin path: " + dsp_path
+ if(os.path.exists(dsp_path) == False):
+ print "DSP bin doesn't exist: %s" %(dsp_path)
+ print "[Error] Load DSP bin failed"
+ return
+ else:
+ with open(dsp_path, "rb") as dsp_bin:
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print "No header detected, continue"
+ else:
+ dsp_header = 0x200
+ dsp_bin.seek(dsp_header, os.SEEK_SET)
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print "Header detected, skip first 512B"
+ else:
+ print "DSP header detected at neither 0x0 nor 0x200"
+ print "Please check the bin is legal!"
+ print "[Error] Load DSP bin failed"
+ return
+ gdb_cmd='thread 1'
+ gdb.execute(gdb_cmd)
+ ## a) need parsing: 0x13a0000 <dsp_bin_ro>
+ ##symbol_name='&dsp_bin_ro'
+ ##dsp_addr = gdb.parse_and_eval(symbol_name)
+ ## b) need parsing: $3 = 0x13a0000
+ ##gdb_cmd='p/x &dsp_bin_ro'
+ ##dsp_addr = gdb.execute(gdb_cmd, False, True)
+ symbol_name='dsp_bin_ro'
+ dsp_addr = gdb.parse_and_eval(symbol_name)
+ dsp_addr = str(dsp_addr.address).split(" ")
+ dsp_addr = int(dsp_addr[0], 16) - dsp_header
+ print hex(dsp_addr)
+ gdb_cmd = 'monitor mips32 fastchannel 0 1'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'set $cdmmbase=0x1fc1407'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'set *0x1fc100d4=0x02030202'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = " ".join(['restore', dsp_path, 'binary', hex(dsp_addr), hex(dsp_header)])
+ print gdb_cmd
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'set *0x1fc100d4=0x02020202'
+ gdb.execute(gdb_cmd)
+ time_end = time.time()
+ print("loading dsp is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+
+class gui_tk(Tkinter.Tk):
+ def __init__(self, parent):
+ Tkinter.Tk.__init__(self, parent)
+ elf_path = ""
+ dsp_path = ""
+ dsp_addr = ""
+ self.file_opt = options = {}
+ options['title'] = 'Choose a file'
+ self.parent = parent
+ self.initialize()
+
+ def initialize(self):
+ self.grid()
+
+ dsp_button = Tkinter.Button(self, text=u"Load DSP bin =>", command=self.dsp_OnButtonClick)
+ dsp_button.grid(column=0, row=4, sticky='W')
+
+ def dsp_OnButtonClick(self):
+ dsp_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(dsp_path) > 0:
+ print "You chose %s" % dsp_path
+ load_dsp_bin(dsp_path)
+ self.quit()
+
+ def quit(self):
+ global app
+ print "=== Close Easy Loader ==="
+ app.destroy()
+
+def load_dsp_gui():
+ print "=== Start Easy Loader ==="
+ global app
+ app = gui_tk(None)
+ app.title('Easy Loader')
+ app.mainloop()
+
+
+if __name__ == "__main__":
+ load_dsp_gui()
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/mt6771-evb.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/mt6771-evb.cmm
new file mode 100755
index 0000000..9bd408c
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/mt6771-evb.cmm
@@ -0,0 +1,108 @@
+;*****************************************************************************
+; Copyright Statement:
+; --------------------
+; This software is protected by Copyright and the information contained
+; herein is confidential. The software may not be copied and the information
+; contained herein may not be used or disclosed except with the written
+; permission of MediaTek Inc. (C) 2011
+;
+;*****************************************************************************
+;;================================================
+;; PURPOSE: EVB Bring Up
+;; CREATE_DATE: 2017/10/20
+;; NOTE:
+;;================================================
+; Specify Core Number
+;=================================================
+
+&NR_CPUS=1
+; cluster 0 corebase: 0x8007000, 0x8007200, 0x8007400, 0x8007600
+; cluster 1 corebase: 0x8009000, 0x8009200, 0x8009400, 0x8009600
+
+;=================================================
+; Initialize CPU
+;=================================================
+&WDT_TEST=0
+if &WDT_TEST==0
+(
+ RESET
+ SYSTEM.OPTION ENRESET ON
+)
+
+SYSTEM.RESET
+SYSTEM.OPTION ENRESET ON
+SYSTEM.OPTION RESBREAK OFF
+SYSTEM.OPTION WAITRESET OFF
+
+SYSTEM.JTAGCLOCK 10.MHz;
+
+;SYSTEM.CPU CortexA7MPCore
+SYStem.CPU CORTEXA53;
+
+;R-T Memory Access
+SYSTEM.MULTICORE MEMORYACCESSPORT 0
+SYSTEM.MULTICORE DEBUGACCESSPORT 1
+
+;SYSTEM.MULTICORE COREBASE APB:0x80070000
+;Setting Core debug register access
+if &NR_CPUS==1
+(
+ SYStem.CONFIG CORENUMBER 1;
+ SYStem.CONFIG COREBASE 0x8D410000;
+ SYStem.CONFIG CTIBASE 0x8D420000;
+)
+else
+(
+ SYSTEM.CONFIG CORENUMBER 2;
+ SYSTEM.CONFIG COREBASE 0x80810000 0x80910000;
+ SYStem.CONFIG CTIBASE 0x80820000 0x80920000;
+)
+
+;=================================================
+; Attach and Stop CPU
+;=================================================
+SYStem.Up
+wait 200.us
+
+SETUP.IMASKHLL ON
+SETUP.IMASKASM ON
+
+;enable L2C 256KB
+D.S SD:0x0C5307F0 %LE %LONG 0x00010300 ;Enable L2C share SRAM (512K)
+D.S SD:0x0C5307F0 %LE %LONG 0x00010301 ;Enable L2C share SRAM (512K)
+
+; set_hw_breakpoint_by_def
+; setting attribute of breakpoints
+Break.Select Program OnChip
+Break.Select Hll OnChip
+Break.Select Spot OnChip
+Break.Select Read OnChip
+Break.Select Write OnChip
+
+D.S C15:0x1 0 ; Turn off MMU
+
+; disable wdt (debug purpose)
+D.S SD:0x10007000 %LE %LONG 0x22000000
+
+print "loading pre-loader image"
+d.load.elf ../../../../../../../../out/target/product/evb6771_64_emmc/obj/PRELOADER_OBJ/bin/preloader_evb6771_64_emmc.elf
+
+Y.SPATH.RESET ; reset all source path
+Y.SPATH.SRD ../../platform/mt6771/src/init
+Y.SPATH.SRD ../../platform/mt6771/src/core
+Y.SPATH.SRD ../../platform/mt6771/src/drivers
+Y.SPATH.SRD ../../platform/mt6771/src/security
+Y.SPATH.SRD ../../platform/common
+Y.SPATH.SRD ../../custom/evb6771_64_emmc
+
+
+Break.Select Program OnChip
+Break.Select Hll OnChip
+Break.Select Spot OnChip
+Break.Select Read OnChip
+Break.Select Write OnChip
+
+R.S T 0
+;winclear
+d.l
+enddo
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/preloader_evb6771_64_emmc_TINY.bin b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/preloader_evb6771_64_emmc_TINY.bin
new file mode 100755
index 0000000..6f62afc
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/preloader_evb6771_64_emmc_TINY.bin
Binary files differ
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/preloader_evb6771_64_emmc_TINY.elf b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/preloader_evb6771_64_emmc_TINY.elf
new file mode 100755
index 0000000..d0c02c8
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6771/preloader_evb6771_64_emmc_TINY.elf
Binary files differ
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/APView_MT6779_EVB_UART_Test.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/APView_MT6779_EVB_UART_Test.cmm
new file mode 100755
index 0000000..926ab2f
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/APView_MT6779_EVB_UART_Test.cmm
@@ -0,0 +1,39 @@
+;Lafite MD_UART0 port test
+;You should make sure GPIO47 has connected to UART port RXD pin,GPIO48 has connected to UART port TXD pin
+
+;port: MDUART0
+;Baudrate: 115200
+;&BASE_ADDR_MDUART0=0xB0010000
+sys.m prepare
+&BASE_ADDR_MDUART0=0x20010000
+&BASE_ADDR_MDGPIO=0x10005000
+&BASE_ADDR_IOCFG=0x11E20000
+
+
+D.S AXI:&BASE_ADDR_MDGPIO+0x358 %LE %LONG 0x70000000 ;//clear GPIO47 to GPIO mode.
+D.S AXI:&BASE_ADDR_MDGPIO+0x368 %LE %LONG 0x00000007 ;//clear GPIO48 to GPIO mode.
+D.S AXI:&BASE_ADDR_MDGPIO+0x354 %LE %LONG 0x40000000 ;//set GPIO47 to MD_URXD0 mode.
+D.S AXI:&BASE_ADDR_MDGPIO+0x364 %LE %LONG 0x00000004 ;//set GPIO48 to MD_UTXD0 mode.
+
+D.S AXI:&BASE_ADDR_IOCFG+0x68 %LE %LONG 0xC000 ;//MD_URXD0/MD_UTXD0 PD clear
+D.S AXI:&BASE_ADDR_IOCFG+0x84 %LE %LONG 0x8000 ;//MD_URXD0 PU set
+
+D.S AXI:&BASE_ADDR_MDUART0+0x24 %LE %LONG 0x03 ;//High Speed X
+D.S AXI:&BASE_ADDR_MDUART0+0x28 %LE %LONG 0xE1 ;//Sample count
+D.S AXI:&BASE_ADDR_MDUART0+0x2C %LE %LONG 0x71 ;//sample point
+D.S AXI:&BASE_ADDR_MDUART0+0x0C %LE %LONG 0x83 ;//Enable Divisor latch acess bit, and set 8bit length.
+D.S AXI:&BASE_ADDR_MDUART0+0x00 %LE %LONG 0x01 ;//sample point
+D.S AXI:&BASE_ADDR_MDUART0+0x04 %LE %LONG 0x00 ;//sample point
+D.S AXI:&BASE_ADDR_MDUART0+0x0C %LE %LONG 0x03 ;//Clear Divisor latch acess bit, and set 8bit length.
+
+&uart_lsr=0x0
+&uart_rxd=0x0
+PRINT "Please put char "U" from PC to EVB UART! Note: ASCII "U" remap to HEX is 0x55 "
+WHILE (&uart_lsr&0x01)!=0x01
+(
+ &uart_lsr=data.long(AXI:&BASE_ADDR_MDUART0+0x14)
+)
+&uart_rxd=data.long(AXI:&BASE_ADDR_MDUART0+0x0)
+PRINT "EVB UART Get data: &uart_rxd"
+D.S AXI:&BASE_ADDR_MDUART0+0x00 %LE %LONG &uart_rxd ;//Write data to UART, please check console.
+PRINT "EVB UART will send data to PC,please check!"
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/APview_MT6779_Frequency_Meter.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/APview_MT6779_Frequency_Meter.cmm
new file mode 100755
index 0000000..7c47864
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/APview_MT6779_Frequency_Meter.cmm
@@ -0,0 +1,540 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; EIGER MD Frequency Meter
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;;Select PLL
+LOCAL &key_in
+&key_in=0
+
+LOCAL &opt_cvd_connect
+&opt_cvd_connect="debug"
+
+;;;;;;;;;;;;;;;;;;;;;;;Below you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+LOCAL &mclass ;; Memory Class
+&mclass="axi"
+;&mclass="pm"
+
+LOCAL &clksw_base ;; MD CLKSW base address
+;&clksw_base=0xA0150000 ;; MD view APB
+;&clksw_base=0xA0096000 ;; MD view debug APB
+&clksw_base=0x20150000 ;; AP view MD system bus
+;&clksw_base=0x0D0D6000 ;; AP view MD debug sys
+
+LOCAL &pll_base ;; MD PLLMIXED base address
+;&pll_base=0xA0140000 ;; MD view APB
+;&pll_base=0xA0094000 ;; MD view debug APB
+&pll_base=0x20140000 ;; AP view MD system bus
+;&pll_base=0x0D0D4000 ;; AP view MD debug sys
+
+&fqmtr_fcksel_32k_index=0x17
+;;;;;;;;;;;;;;;;;;;;;;;Above you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LOCAL &fqmtr_winset ;; Frequency Meter Windoiw Setting (= Number of FIXED clock cycle)
+&fqmtr_winset=0x1ff
+&fqmtr_winset_for_32k=0x1E000
+
+LOCAL &fqmtr_fcksel_val ;; Frequency Meter FIXED clock selection
+&fqmtr_fcksel_val=0x1a ;; Select 26Mhz by default
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;All the PLL you could select;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+&SRC_STR_1="Reserved"
+&SRC_STR_2="Reserved"
+&SRC_STR_3="Reserved"
+&SRC_STR_4="MDBPI_PLL_D4"
+&SRC_STR_5="MDBPI_PLL_D6"
+&SRC_STR_6="mdsys_mml2_ck"
+&SRC_STR_7="fesys_rxagc_ck"
+&SRC_STR_8="mdrxsys_dfesync_ck"
+&SRC_STR_9="fesys_f208m_ck"
+&SRC_STR_10="TRACE_MON_clock"
+&SRC_STR_11="MDSYS_208M_clock"
+&SRC_STR_12="mdrxsys_rake_ck"
+&SRC_STR_13="mdrxsys_brp_ck"
+&SRC_STR_14="mdrxsys_vdsp_ck"
+&SRC_STR_15="mdtop_log_atb_ck"
+&SRC_STR_16="fesys_csys_ck"
+&SRC_STR_17="Reserved"
+&SRC_STR_18="fesys_bsi_ck"
+&SRC_STR_19="mdsys_mdcore_ck"
+&SRC_STR_20="mdsys_bus2x_nodcm_ck"
+&SRC_STR_21="mdsys_bus2x_ck"
+&SRC_STR_22="mdtop_dbg_ck"
+&SRC_STR_23="mdtop_f32k_ck"
+&SRC_STR_24="AD_MDBPIPLL_D7"
+&SRC_STR_25="AD_MDBPIPLL_D5"
+&SRC_STR_26="AD_MDBPIPLL_D4"
+&SRC_STR_27="AD_MDBPIPLL_D3"
+&SRC_STR_28="AD_MDBPIPLL_D2"
+&SRC_STR_29="AD_MDBRPPLL"
+&SRC_STR_30="AD_MDVDSPPLL"
+&SRC_STR_31="AD_MDMCUPLL"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+DIALOG
+(&
+ HEADER "PLL Frequency Meter"
+ ICON ":chip"
+
+ POS 0. 0. 20. 1.
+ LINE "FQMTR Selection"
+ ; x y w h
+ POS 0. 1. 20. 1.
+ SEL.NONE: CHOOSEBOX "None"
+ (
+ &key_in=0x00
+ )
+;; SEL.1: CHOOSEBOX "&SRC_STR_1"
+;; (
+;; &key_in=0x1
+;; &key_str="&SRC_STR_1"
+;; )
+;; SEL.2: CHOOSEBOX "&SRC_STR_2"
+;; (
+;; &key_in=0x2
+;; &key_str="&SRC_STR_2"
+;; )
+;; SEL.3: CHOOSEBOX "&SRC_STR_3"
+;; (
+;; &key_in=0x3
+;; &key_str="&SRC_STR_3"
+;; )
+ SEL.4: CHOOSEBOX "&SRC_STR_4"
+ (
+ &key_in=0x4
+ &key_str="&SRC_STR_4"
+ )
+ SEL.5: CHOOSEBOX "&SRC_STR_5"
+ (
+ &key_in=0x5
+ &key_str="&SRC_STR_5"
+ )
+ SEL.6: CHOOSEBOX "&SRC_STR_6"
+ (
+ &key_in=0x6
+ &key_str="&SRC_STR_6"
+ )
+ SEL.7: CHOOSEBOX "&SRC_STR_7"
+ (
+ &key_in=0x7
+ &key_str="&SRC_STR_7"
+ )
+ SEL.8: CHOOSEBOX "&SRC_STR_8"
+ (
+ &key_in=0x8
+ &key_str="&SRC_STR_8"
+ )
+ SEL.9: CHOOSEBOX "&SRC_STR_9"
+ (
+ &key_in=0x9
+ &key_str="&SRC_STR_9"
+ )
+ SEL.10: CHOOSEBOX "&SRC_STR_10"
+ (
+ &key_in=0xA
+ &key_str="&SRC_STR_10"
+ )
+ SEL.11: CHOOSEBOX "&SRC_STR_11"
+ (
+ &key_in=0xB
+ &key_str="&SRC_STR_11"
+ )
+ SEL.12: CHOOSEBOX "&SRC_STR_12"
+ (
+ &key_in=0xC
+ &key_str="&SRC_STR_12"
+ )
+ SEL.13: CHOOSEBOX "&SRC_STR_13"
+ (
+ &key_in=0xD
+ &key_str="&SRC_STR_13"
+ )
+ SEL.14: CHOOSEBOX "&SRC_STR_14"
+ (
+ &key_in=0xE
+ &key_str="&SRC_STR_14"
+ )
+ SEL.15: CHOOSEBOX "&SRC_STR_15"
+ (
+ &key_in=0xF
+ &key_str="&SRC_STR_15"
+ )
+ SEL.16: CHOOSEBOX "&SRC_STR_16"
+ (
+ &key_in=0x10
+ &key_str="&SRC_STR_16"
+ )
+;; SEL.17: CHOOSEBOX "&SRC_STR_17"
+;; (
+;; &key_in=0x11
+;; &key_str="&SRC_STR_17"
+;; )
+ SEL.18: CHOOSEBOX "&SRC_STR_18"
+ (
+ &key_in=0x12
+ &key_str="&SRC_STR_18"
+ )
+ SEL.19: CHOOSEBOX "&SRC_STR_19"
+ (
+ &key_in=0x13
+ &key_str="&SRC_STR_19"
+ )
+ SEL.20: CHOOSEBOX "&SRC_STR_20"
+ (
+ &key_in=0x14
+ &key_str="&SRC_STR_20"
+ )
+ SEL.21: CHOOSEBOX "&SRC_STR_21"
+ (
+ &key_in=0x15
+ &key_str="&SRC_STR_21"
+ )
+ SEL.22: CHOOSEBOX "&SRC_STR_22"
+ (
+ &key_in=0x16
+ &key_str="&SRC_STR_22"
+ )
+ SEL.23: CHOOSEBOX "&SRC_STR_23"
+ (
+ &key_in=0x17
+ &key_str="&SRC_STR_23"
+ )
+ SEL.24: CHOOSEBOX "&SRC_STR_24"
+ (
+ &key_in=0x18
+ &key_str="&SRC_STR_24"
+ )
+ SEL.25: CHOOSEBOX "&SRC_STR_25"
+ (
+ &key_in=0x19
+ &key_str="&SRC_STR_25"
+ )
+ SEL.26: CHOOSEBOX "&SRC_STR_26"
+ (
+ &key_in=0x1A
+ &key_str="&SRC_STR_26"
+ )
+ SEL.27: CHOOSEBOX "&SRC_STR_27"
+ (
+ &key_in=0x1B
+ &key_str="&SRC_STR_27"
+ )
+ SEL.28: CHOOSEBOX "&SRC_STR_28"
+ (
+ &key_in=0x1C
+ &key_str="&SRC_STR_28"
+ )
+ SEL.29: CHOOSEBOX "&SRC_STR_29"
+ (
+ &key_in=0x1D
+ &key_str="&SRC_STR_29"
+ )
+ SEL.30: CHOOSEBOX "&SRC_STR_30"
+ (
+ &key_in=0x1E
+ &key_str="&SRC_STR_30"
+ )
+ SEL.31: CHOOSEBOX "&SRC_STR_31"
+ (
+ &key_in=0x1F
+ &key_str="&SRC_STR_31"
+ )
+
+ POS 21. 0. 20. 1.
+ LINE "FQMTR Information"
+ INFO1: EDIT "Window Seting: &fqmtr_winset" ""
+ INFO2: EDIT "Fixed Clock: &fqmtr_fcksel_val" ""
+ INFO3: EDIT "32K measure support" ""
+
+ POSY 1. 20. 1.
+ LINE "FQMTR Result"
+ RESULT: EDIT "" ""
+
+ POSY 1. 20. 1.
+ DEFBUTTON "OK"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ IF &key_in!=0
+ (
+ GOSUB fqmtr_query &key_in &key_str 1
+ )
+ )
+
+ DEFBUTTON "LIST ALL"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ GOSUB fqmtr_list_all
+ )
+
+ DEFBUTTON "Force LIST main clk"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ GOSUB fqmtr_force_list_all
+ )
+
+ CLOSE
+ (
+ PRINT "bye~"
+ DIALOG.END
+ )
+)
+
+ ;; Disable EDIT of showing information
+ DIALOG.Disable INFO1
+ DIALOG.Disable INFO2
+ DIALOG.Disable INFO3
+ ;DIALOG.Disable RESULT
+STOP
+ENDDO
+
+;;;;;The main function to get the Frequency. &idx==> the clock you select, &str==> clock name, &info==>list more info and wait 5ms in the function
+;; &info=1 ==> for printing many PLLs at one time
+fqmtr_query:
+ENTRY &idx &str &info
+(
+ IF &info!=0
+ (
+ PRINT "&str: &idx"
+ PRINT "fqmtrsrc: 0x" FORMAT.HEX(2,&idx)
+ PRINT "opt_cvd_connect: &opt_cvd_connect"
+ )
+
+ LOCAL &unit
+ LOCAL &fqmtr_winset_26M
+ LOCAL &fqmtr_result
+ LOCAL &fqmtr_result_raw
+ LOCAL &fqmtr_result_str
+ LOCAL &safe_wait_cnt
+ LOCAL &safe_wait_cnt_max
+ LOCAL &fqmtr_busy
+
+ &safe_wait_cnt=0
+
+ IF &fqmtr_fcksel_val==0x1a ;; base on 26M, unit:MHz
+ (
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &unit="Khz"
+ &fqmtr_winset_26M=&fqmtr_winset_for_32k
+ &safe_wait_cnt_max=500 ;;5000 ms = 5s ==> in real test, longer than 5s, so reduce it
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &unit="Mhz"
+ &fqmtr_winset_26M=&fqmtr_winset
+ &safe_wait_cnt_max=32 ;;32 ms
+ )
+ )
+ ELSE
+ (
+ &unit=""
+ )
+
+ IF "&opt_cvd_connect"=="none"
+ (
+ sys.m prepare
+ )
+ ELSE IF "&opt_cvd_connect"=="debug"
+ (
+ ; do nothing
+ )
+ ELSE
+ (
+ IF &info!=0
+ (
+ PRINT "No explicit CVD connection, use current status"
+ )
+ )
+
+ IF &idx==0
+ (
+ ;; This is used for connect CVD only, no FQMTR test
+ RETURN
+ )
+
+ ;;select source to a valid clock to let reset success.
+ Data.Set &mclass:(&clksw_base+0x0200) %LE %LONG 0x13
+ Data.Set &mclass:(&clksw_base+0x0204) %LE %LONG 0x0 ;reset frequency meter
+ WAIT 1ms
+
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ ;;For accurate, don't div 8 for 32K
+ Data.Set &mclass:(&clksw_base+0x0200) %LE %LONG (&idx)
+ )
+ ELSE ;; measure PLL and other module
+ (
+ ;;div 8 and select src
+ Data.Set &mclass:(&clksw_base+0x0200) %LE %LONG (0x0300)|(&idx)
+ )
+
+ Data.Set &mclass:(&clksw_base+0x0208) %LE %LONG &fqmtr_winset_26M
+ Data.Set &mclass:(&clksw_base+0x0204) %LE %LONG 0x1 ;enable frequency meter
+
+ ;; read status, to check polling done or not
+ &fqmtr_busy=DATA.LONG(&mclass:(&clksw_base+0x0204))&(1<<1)
+ WHILE &fqmtr_busy==0
+ (
+ ;PRINT ". &fqmtr_busy"
+ &fqmtr_busy=DATA.LONG(&mclass:(&clksw_base+0x0204))&(1<<1)
+ &safe_wait_cnt=&safe_wait_cnt+1
+ IF &safe_wait_cnt==&safe_wait_cnt_max
+ (
+ PRINT "[&str] Wait Fail, exit"
+ DIALOG.Set RESULT "Wait Fail(No clock), exit"
+ RETURN
+ )
+ ELSE
+ (
+;; PRINT "Waiting result. safe_wait_cnt=" "&safe_wait_cnt"
+ )
+ WAIT 1ms
+ )
+
+ ;; Calculate the result
+ &fqmtr_result_raw=DATA.LONG(&mclass:(&clksw_base+0x20c))
+
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*(0x3E8)/&fqmtr_winset_26M
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*8/&fqmtr_winset_26M
+ )
+
+ &fqmtr_result_dec=FORMAT.DECIMAL(0,&fqmtr_result)
+ &fqmtr_result_str=""+FORMAT.DECIMAL(0,&fqmtr_result)+" &unit"
+ IF &info==0
+ (
+ PRINT "0x" FORMAT.HEX(2,&idx) ",&fqmtr_result_dec,&unit,&str,&fqmtr_result_raw,"
+ )
+ ELSE
+ (
+ PRINT "Frequency Meter Result: &fqmtr_result_str (&fqmtr_result_raw)"
+ PRINT ""
+ )
+ DIALOG.Set RESULT "&fqmtr_result_str"
+
+ IF &info==0
+ (
+ WAIT 5ms
+ )
+
+ RETURN
+)
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+fqmtr_create_win:
+(
+ AREA.RESet
+ AREA.Create PLL_FMETER
+ AREA.Select PLL_FMETER
+ WinPOS 10.,0.,50.,35.,,, FMETER
+ AREA.view PLL_FMETER
+ AREA.Clear PLL_FMETER
+ RETURN
+)
+
+fqmtr_list_all:
+(
+ GOSUB fqmtr_create_win
+
+ ;GOSUB fqmtr_query 0x1 &SRC_STR_1 0
+ ;GOSUB fqmtr_query 0x2 &SRC_STR_2 0
+ ;GOSUB fqmtr_query 0x3 &SRC_STR_3 0
+ GOSUB fqmtr_query 0x4 &SRC_STR_4 0
+ GOSUB fqmtr_query 0x5 &SRC_STR_5 0
+ GOSUB fqmtr_query 0x6 &SRC_STR_6 0
+ GOSUB fqmtr_query 0x7 &SRC_STR_7 0
+ GOSUB fqmtr_query 0x8 &SRC_STR_8 0
+ GOSUB fqmtr_query 0x9 &SRC_STR_9 0
+ GOSUB fqmtr_query 0xA &SRC_STR_10 0
+ GOSUB fqmtr_query 0xB &SRC_STR_11 0
+ GOSUB fqmtr_query 0xC &SRC_STR_12 0
+ GOSUB fqmtr_query 0xD &SRC_STR_13 0
+ GOSUB fqmtr_query 0xE &SRC_STR_14 0
+ GOSUB fqmtr_query 0xF &SRC_STR_15 0
+ GOSUB fqmtr_query 0x10 &SRC_STR_16 0
+ ;GOSUB fqmtr_query 0x11 &SRC_STR_17 0
+ GOSUB fqmtr_query 0x12 &SRC_STR_18 0
+ GOSUB fqmtr_query 0x13 &SRC_STR_19 0
+ GOSUB fqmtr_query 0x14 &SRC_STR_20 0
+ GOSUB fqmtr_query 0x15 &SRC_STR_21 0
+ GOSUB fqmtr_query 0x16 &SRC_STR_22 0
+ GOSUB fqmtr_query 0x17 &SRC_STR_23 0
+ GOSUB fqmtr_query 0x18 &SRC_STR_24 0
+ GOSUB fqmtr_query 0x19 &SRC_STR_25 0
+ GOSUB fqmtr_query 0x1A &SRC_STR_26 0
+ GOSUB fqmtr_query 0x1B &SRC_STR_27 0
+ GOSUB fqmtr_query 0x1C &SRC_STR_28 0
+ GOSUB fqmtr_query 0x1D &SRC_STR_29 0
+ GOSUB fqmtr_query 0x1E &SRC_STR_30 0
+ GOSUB fqmtr_query 0x1F &SRC_STR_31 0
+ RETURN
+)
+
+fqmtr_force_list_all:
+(
+ GOSUB fqmtr_create_win
+
+ LOCAL &original_reg
+ LOCAL &original_reg1
+ LOCAL &original_reg2
+
+ &original_reg=DATA.LONG(&mclass:(&pll_base+0x10))
+ &original_reg1=DATA.LONG(&mclass:(&clksw_base+0x10))
+ &original_reg2=DATA.LONG(&mclass:(&clksw_base+0x14))
+
+ ; S/W force on all PLL
+ Data.Set &mclass:(&pll_base+0x10) %LE %LONG 0xFFFFFFFF
+
+ ; S/W force on all module clock
+ Data.Set &mclass:(&clksw_base+0x10) %LE %LONG 0xFFFFFFFF
+ Data.Set &mclass:(&clksw_base+0x14) %LE %LONG 0xFFFFFFFF
+
+ WAIT 1.s
+
+ ;GOSUB fqmtr_query 0x1 &SRC_STR_1 0
+ ;GOSUB fqmtr_query 0x2 &SRC_STR_2 0
+ ;GOSUB fqmtr_query 0x3 &SRC_STR_3 0
+ GOSUB fqmtr_query 0x4 &SRC_STR_4 0
+ GOSUB fqmtr_query 0x5 &SRC_STR_5 0
+ GOSUB fqmtr_query 0x6 &SRC_STR_6 0
+ GOSUB fqmtr_query 0x7 &SRC_STR_7 0
+ GOSUB fqmtr_query 0x8 &SRC_STR_8 0
+ GOSUB fqmtr_query 0x9 &SRC_STR_9 0
+ GOSUB fqmtr_query 0xA &SRC_STR_10 0
+ GOSUB fqmtr_query 0xB &SRC_STR_11 0
+ GOSUB fqmtr_query 0xC &SRC_STR_12 0
+ GOSUB fqmtr_query 0xD &SRC_STR_13 0
+ GOSUB fqmtr_query 0xE &SRC_STR_14 0
+ GOSUB fqmtr_query 0xF &SRC_STR_15 0
+ GOSUB fqmtr_query 0x10 &SRC_STR_16 0
+ ;GOSUB fqmtr_query 0x11 &SRC_STR_17 0
+ GOSUB fqmtr_query 0x12 &SRC_STR_18 0
+ GOSUB fqmtr_query 0x13 &SRC_STR_19 0
+ GOSUB fqmtr_query 0x14 &SRC_STR_20 0
+ GOSUB fqmtr_query 0x15 &SRC_STR_21 0
+ GOSUB fqmtr_query 0x16 &SRC_STR_22 0
+ GOSUB fqmtr_query 0x17 &SRC_STR_23 0
+ GOSUB fqmtr_query 0x18 &SRC_STR_24 0
+ GOSUB fqmtr_query 0x19 &SRC_STR_25 0
+ GOSUB fqmtr_query 0x1A &SRC_STR_26 0
+ GOSUB fqmtr_query 0x1B &SRC_STR_27 0
+ GOSUB fqmtr_query 0x1C &SRC_STR_28 0
+ GOSUB fqmtr_query 0x1D &SRC_STR_29 0
+ GOSUB fqmtr_query 0x1E &SRC_STR_30 0
+ GOSUB fqmtr_query 0x1F &SRC_STR_31 0
+
+ ; Revert to original value
+ Data.Set &mclass:(&pll_base+0x10) %LE %LONG &original_reg
+ Data.Set &mclass:(&clksw_base+0x10) %LE %LONG &original_reg1
+ Data.Set &mclass:(&clksw_base+0x14) %LE %LONG &original_reg2
+
+ WAIT 1.s
+
+ RETURN
+)
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/APview_MT6779_GPIO_MDUART0.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/APview_MT6779_GPIO_MDUART0.cmm
new file mode 100755
index 0000000..8733245
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/APview_MT6779_GPIO_MDUART0.cmm
@@ -0,0 +1,18 @@
+;Lafite MD_UART0 port test
+;You should make sure GPIO47 has connected to UART port RXD pin,GPIO48 has connected to UART port TXD pin
+
+;port: MDUART0
+;Baudrate: 1500000
+;&BASE_ADDR_MDUART0=0xB0010000
+sys.m prepare
+&BASE_ADDR_MDUART0=0x20010000
+&BASE_ADDR_MDGPIO=0x10005000
+&BASE_ADDR_IOCFG=0x11E20000
+
+D.S AXI:&BASE_ADDR_MDGPIO+0x358 %LE %LONG 0x70000000 ;//clear GPIO47 to GPIO mode.
+D.S AXI:&BASE_ADDR_MDGPIO+0x368 %LE %LONG 0x00000007 ;//clear GPIO48 to GPIO mode.
+D.S AXI:&BASE_ADDR_MDGPIO+0x354 %LE %LONG 0x40000000 ;//set GPIO47 to MD_URXD0 mode.
+D.S AXI:&BASE_ADDR_MDGPIO+0x364 %LE %LONG 0x00000004 ;//set GPIO48 to MD_UTXD0 mode.
+
+D.S AXI:&BASE_ADDR_IOCFG+0x68 %LE %LONG 0xC000 ;//MD_URXD0/MD_UTXD0 PD clear
+D.S AXI:&BASE_ADDR_IOCFG+0x84 %LE %LONG 0x8000 ;//MD_URXD0 PU set
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/APview_MT6779_GPIO_SIM.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/APview_MT6779_GPIO_SIM.cmm
new file mode 100755
index 0000000..b3e5494
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/APview_MT6779_GPIO_SIM.cmm
@@ -0,0 +1,21 @@
+;;// SIM2 GPIO
+;;// SIM1 GPIO
+
+&temp=data.long(0x10005400)
+&temp=&temp & (0xFF000000)
+D.S 0x10005400 %LE %LONG &temp
+
+&temp=data.long(0x10005400)
+&temp=&temp | (0x00111111)
+D.S 0x10005400 %LE %LONG &temp
+
+;;// SIM2 PUPD
+;;// SIM1 PUPD
+
+&temp=data.long(0x11C20060)
+&temp=&temp & (0x0000003F)
+D.S 0x11C20060 %LE %LONG &temp
+
+&temp=data.long(0x11C20060)
+&temp=&temp | (0x00000480)
+D.S 0x11C20060 %LE %LONG &temp
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/APview_MT6779_MD_ForceOnDebugSys.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/APview_MT6779_MD_ForceOnDebugSys.cmm
new file mode 100755
index 0000000..32fce9b
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/APview_MT6779_MD_ForceOnDebugSys.cmm
@@ -0,0 +1,16 @@
+;Core1 force on
+d.s &MEM_CLASS:0x200D0004 %long %le 0xB2002482
+;Core2 force on
+d.s &MEM_CLASS:0x200D0008 %long %le 0xB2002382
+;ForceOn debug sys
+d.s &MEM_CLASS:0x20150010 %long %le data.long(&MEM_CLASS:0x20150010)|(0x00080008)
+d.s &MEM_CLASS:0x200D04B0 %long %le data.long(&MEM_CLASS:0x200D04B0)|(0x00000008)
+&temp=data.long(&MEM_CLASS:0x200D0590)
+IF (&temp&0x8)!=0x8
+(
+ PRINT "Force on debug sys clock fail"
+)
+ELSE
+(
+ PRINT "Force on debug sys clock success"
+)
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/APview_MT6779_MD_PLL_Init.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/APview_MT6779_MD_PLL_Init.cmm
new file mode 100755
index 0000000..83af786
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/APview_MT6779_MD_PLL_Init.cmm
@@ -0,0 +1,114 @@
+; /* Step 6 config PLL setting */
+;;==============================PLL init start==================================================
+;;sys.m prepare
+&MEM_CLASS="AXI"
+
+&BASE_MADDR_APMIXEDSYS=(0x1000C000)
+&BASE_MADDR_MDTOP_PLLMIXED=(0x20140000)
+&BASE_MADDR_MDTOP_CLKSW=(0x20150000)
+
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+®_MDTOP_PLLMIXED_PLL_SETTLE_26M_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x1C)
+®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+®_MDTOP_PLLMIXED_MDMCUPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x44)
+®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+®_MDTOP_PLLMIXED_MDVDSPPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x4C)
+®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+®_MDTOP_PLLMIXED_MDBRPPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x54)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+®_MDTOP_PLLMIXED_PLL_DIV_EN=(&BASE_MADDR_MDTOP_PLLMIXED+0x118)
+®_MDTOP_PLLMIXED_PLL_SRC_SEL=(&BASE_MADDR_MDTOP_PLLMIXED+0x120)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+
+®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+®_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x60)
+®_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x70)
+®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0xA4)
+
+&MD_PLL_MAGIC_NUM=(0x62950000)
+
+;;//Enables clock square1 low-pass filter for 26M quality.
+d.s &MEM_CLASS:®_APMIXEDSYS_AP_PLL_CON0 %long %le data.long(&MEM_CLASS:®_APMIXEDSYS_AP_PLL_CON0)|0x2
+;;// 100us
+wait 1.ms
+
+;;// Default md_srclkena_ack settle time = 154T 32K
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02021C9A
+
+;;//Change ABBPLL_SETTLE_26M to 0x2F2==>29us
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_SETTLE_26M_CTL %long %le 0x17920803
+
+;;// set mdmcupll/mdvdsppll/mdbrppll posdiv to 0
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_CTL1 %long %le data.long(&MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_CTL1)&0xFFFFFFFD
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDVDSPPLL_CTL1 %long %le data.long(&MEM_CLASS:®_MDTOP_PLLMIXED_MDVDSPPLL_CTL1)&0xFFFFFFFD
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDBRPPLL_CTL1 %long %le data.long(&MEM_CLASS:®_MDTOP_PLLMIXED_MDBRPPLL_CTL1)&0xFFFFFEFE
+
+;;// set pll srouce from AP clock divider
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_SRC_SEL %long %le 0x00000000
+;;// set pll clock enable in AP clock divider
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_DIV_EN %long %le data.long(&MEM_CLASS:®_MDTOP_PLLMIXED_PLL_DIV_EN)|0x080202
+
+;;// Fixed Fvco = 1800Mhz. (/2)900M, (/3)600M, (/4)450M, (/5)360M, (/6)300M, (/7)257M
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x80114EC5
+;;// Fvco = 3725Mhz. 3725/5 = 745Mhz
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x8023D200
+;;// Fvco = 3000Mhz. 3000/3 = 1000Mhz
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x801CD800
+;;// Fvco = 3000Mhz. 3000/3 = 1000Mhz
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x801CD800
+
+;;// LOG_ATB = 100Mhz (mdbpipll_d3_div2_ck/3)
+d.s &MEM_CLASS:®_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL %long %le 0x00000002
+;;// MML2_DFS_PLLSEL=MDBPIPLL_D4 ; MML2_DFS_DIVSEL=divided-by 1
+d.s &MEM_CLASS:®_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL %long %le 0x00000010
+
+;;// Polling until MDMCUPLL complete frequency adjustment
+;WHILE ((data.long(&MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0()
+wait 1.ms
+
+;; PLL ON controlled by HW
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x00000000
+
+;; Update ABB MDPLL control register default value
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x04C63200
+
+;; /*
+;; * Wait MD bus clock ready
+;; * Once MD bus ready, other clock should be ready too
+;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+;; */
+;WHILE (data.long(&MEM_CLASS:®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000()
+wait 1.ms
+
+;;=================Switch clock source to PLL====================
+;;// Switch MDMCU & MD BUS clock to PLL frequency
+d.s &MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL)|(0x3)
+
+;;// Switch all clock to PLL frequency
+d.s &MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL)|(0x31811F5C)
+
+;;// Turn off all SW clock request, except ATB
+d.s &MEM_CLASS:®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+;;// Switch SDF clock to PLL frequency
+d.s &MEM_CLASS:®_MDTOP_CLKSW_SDF_CK_CTL %long %le data.long(&MEM_CLASS:®_MDTOP_CLKSW_SDF_CK_CTL)|(0x11)
+
+;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+;;// Mask all PLL ADJ RDY IRQ
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+;;// Make a record that means MD pll has been initialized.
+d.s &MEM_CLASS:®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/APview_MT6779_disable_WDT.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/APview_MT6779_disable_WDT.cmm
new file mode 100755
index 0000000..6ea39f8
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/APview_MT6779_disable_WDT.cmm
@@ -0,0 +1,11 @@
+;/* Step 8 Disable MD WDT */
+&MEM_CLASS="AXI"
+
+;&BASE_MADDR_MDRGU=0xA00F0000
+;&BASE_MADDR_APRGU=0xC0007000
+&BASE_MADDR_MDRGU=0x200F0000
+;&BASE_MADDR_APRGU=0x10007000
+
+D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+;D.S &MEM_CLASS:&BASE_MADDR_APRGU %LE %LONG 0x22000064
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/APview_MT6779_md_srclkena.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/APview_MT6779_md_srclkena.cmm
new file mode 100755
index 0000000..6288805
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/APview_MT6779_md_srclkena.cmm
@@ -0,0 +1,22 @@
+; /* Step 3 config md_srclkena setting */
+&MEM_CLASS="AXI"
+
+; /* SPM base */
+&SPM_REG=(0x10006000)
+
+; /* (1) INFRA_MISC2 */
+&INFRA_MISC2=(0x10001F0C)
+; /* (2) SRCLKEN_O1 force on */
+&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+
+; /* (1) INFRA_MISC2 */
+; /* [7:4] : mdsrc_req_1_en = 4'b0010 [3:0] : mdsrc_req_0_en = 4'b0001 */
+®_temp=data.long(&MEM_CLASS:&INFRA_MISC2)&(0xFFFFFF00)
+D.S (&MEM_CLASS:&INFRA_MISC2) %long %le (®_temp)|(0x00000021)
+
+; /* (2) SRCLKEN_O1 force on */
+D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x80215830 //set src clkena1 force on
+
+wait 1.ms
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/CoreTracer_MT6779_Disable_WDT.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/CoreTracer_MT6779_Disable_WDT.cmm
new file mode 100755
index 0000000..fc9f7b7
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/CoreTracer_MT6779_Disable_WDT.cmm
@@ -0,0 +1,34 @@
+;sys.m prepare
+;LOCAL &TYPE
+
+
+system.mode attach
+
+; configure GCR_ACCESS Register
+; CoreTracer will access MO port via CPU to do following configuration
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+
+
+
+; do orginal APview_MT6779_disable_WDT.cmm
+LOCAL &BASE_MADDR_MDRGU
+&BASE_MADDR_MDRGU=0xA00F0000
+
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG 0x55000030
+
+PRINT "=============================="
+PRINT "Done disable MD WDT!"
+PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/Coretracer_MT6779_Frequency_Meter.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/Coretracer_MT6779_Frequency_Meter.cmm
new file mode 100755
index 0000000..f91c643
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/Coretracer_MT6779_Frequency_Meter.cmm
@@ -0,0 +1,240 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; MT6295M MD Frequency Meter
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+system.mode attach
+
+;;;;;;;;;;;;;;;;;;;;;;;Below you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LOCAL &clksw_base ;; MD CLKSW base address
+&clksw_base=0xA0150000 ;; MD view APB
+;&clksw_base=0xA0096000 ;; MD view debug APB
+;&clksw_base=0x20150000 ;; AP view MD system bus
+;&clksw_base=0x0D0D6000 ;; AP view MD debug sys
+
+LOCAL &pll_base ;; MD PLLMIXED base address
+&pll_base=0xA0140000 ;; MD view APB
+;&pll_base=0xA0094000 ;; MD view debug APB
+;&pll_base=0x20140000 ;; AP view MD system bus
+;&pll_base=0x0D0D4000 ;; AP view MD debug sys
+
+&fqmtr_fcksel_32k_index=0x17
+
+;;;;;;;;;;;;;;;;;;;;;;;Above you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LOCAL &fqmtr_winset ;; Frequency Meter Windoiw Setting (= Number of FIXED clock cycle)
+&fqmtr_winset=0x1ff
+&fqmtr_winset_for_32k=0x1E000
+
+LOCAL &fqmtr_fcksel_val ;; Frequency Meter FIXED clock selection
+&fqmtr_fcksel_val=0x1a ;; Select 26Mhz by default
+
+&SRC_STR_4="MDBPI_PLL_D4"
+&SRC_STR_5="MDBPI_PLL_D6"
+&SRC_STR_6="mdsys_mml2_ck"
+&SRC_STR_7="fesys_rxagc_ck"
+&SRC_STR_8="mdrxsys_dfesync_ck"
+&SRC_STR_9="fesys_f208m_ck"
+&SRC_STR_10="TRACE_MON_clock"
+&SRC_STR_11="MDSYS_208M_clock"
+&SRC_STR_12="mdrxsys_rake_ck"
+&SRC_STR_13="mdrxsys_brp_ck"
+&SRC_STR_14="mdrxsys_vdsp_ck"
+&SRC_STR_15="mdtop_log_atb_ck"
+&SRC_STR_16="fesys_csys_ck"
+&SRC_STR_18="fesys_bsi_ck"
+&SRC_STR_19="mdsys_mdcore_ck"
+&SRC_STR_20="mdsys_bus2x_nodcm_ck"
+&SRC_STR_21="mdsys_bus2x_ck"
+&SRC_STR_22="mdtop_dbg_ck"
+&SRC_STR_23="mdtop_f32k_ck"
+&SRC_STR_24="AD_MDBPIPLL_D7"
+&SRC_STR_25="AD_MDBPIPLL_D5"
+&SRC_STR_26="AD_MDBPIPLL_D4"
+&SRC_STR_27="AD_MDBPIPLL_D3"
+&SRC_STR_28="AD_MDBPIPLL_D2"
+&SRC_STR_29="AD_MDBRPPLL"
+&SRC_STR_30="AD_MDVDSPPLL"
+&SRC_STR_31="AD_MDMCUPLL"
+
+LOCAL &idx
+LOCAL &str
+&idx = 0x4;
+&str = "MDBPI_PLL_D4"
+GOSUB fqmtr_query
+&idx = 0x5;
+&str = "MDBPI_PLL_D6"
+GOSUB fqmtr_query
+&idx = 0x6;
+&str = "mdsys_mml2_ck"
+GOSUB fqmtr_query
+&idx = 0x7;
+&str = "fesys_rxagc_ck"
+GOSUB fqmtr_query
+&idx = 0x8;
+&str = "mdrxsys_dfesync_ck"
+GOSUB fqmtr_query
+&idx = 0x9;
+&str = "fesys_f208m_ck"
+GOSUB fqmtr_query
+&idx = 0xA;
+&str = "TRACE_MON_clock"
+GOSUB fqmtr_query
+&idx = 0xB;
+&str = "MDSYS_208M_clock"
+GOSUB fqmtr_query
+&idx = 0xC;
+&str = "mdrxsys_rake_ck"
+GOSUB fqmtr_query
+&idx = 0xD;
+&str = "mdrxsys_brp_ck"
+GOSUB fqmtr_query
+&idx = 0xE;
+&str = "mdrxsys_vdsp_ck"
+GOSUB fqmtr_query
+&idx = 0xF;
+&str = "mdtop_log_atb_ck"
+GOSUB fqmtr_query
+&idx = 0x10;
+&str = "fesys_csys_ck"
+GOSUB fqmtr_query
+&idx = 0x12;
+&str = "fesys_bsi_ck"
+GOSUB fqmtr_query
+&idx = 0x13;
+&str = "mdsys_mdcore_ck"
+GOSUB fqmtr_query
+&idx = 0x14;
+&str = "mdsys_bus2x_nodcm_ck"
+GOSUB fqmtr_query
+&idx = 0x15;
+&str = "mdsys_bus2x_ck"
+GOSUB fqmtr_query
+&idx = 0x16;
+&str = "mdtop_dbg_ck"
+GOSUB fqmtr_query
+&idx = 0x17;
+&str = "mdtop_f32k_ck"
+GOSUB fqmtr_query
+&idx = 0x18;
+&str = "AD_MDBPIPLL_D7"
+GOSUB fqmtr_query
+&idx = 0x19;
+&str = "AD_MDBPIPLL_D5"
+GOSUB fqmtr_query
+&idx = 0x1A;
+&str = "AD_MDBPIPLL_D4"
+GOSUB fqmtr_query
+&idx = 0x1B;
+&str = "AD_MDBPIPLL_D3"
+GOSUB fqmtr_query
+&idx = 0x1C;
+&str = "AD_MDBPIPLL_D2"
+GOSUB fqmtr_query
+&idx = 0x1D;
+&str = "AD_MDBRPPLL"
+GOSUB fqmtr_query
+&idx = 0x1E;
+&str = "AD_MDVDSPPLL"
+GOSUB fqmtr_query
+&idx = 0x1F;
+&str = "AD_MDMCUPLL"
+GOSUB fqmtr_query
+
+&idx = 0x20;
+
+;;;;;The main function to get the Frequency. &idx==> the clock you select, &str==> clock name, &info==>list more info and wait 5ms in the function
+;; &info=1 ==> for printing many PLLs at one time
+fqmtr_query:
+ LOCAL &unit
+ LOCAL &fqmtr_winset_26M
+ LOCAL &fqmtr_result
+ LOCAL &fqmtr_result_raw
+ LOCAL &safe_wait_cnt
+ LOCAL &safe_wait_cnt_max
+ LOCAL &fqmtr_busy
+
+ &safe_wait_cnt=0
+ IF &idx==0x20
+ (
+ RETURN
+ )
+ ELSE
+ (
+ IF &fqmtr_fcksel_val==0x1a ;; base on 26M, unit:MHz
+ (
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &unit="Khz"
+ &fqmtr_winset_26M=&fqmtr_winset_for_32k
+ &safe_wait_cnt_max=500 ;;5000 ms = 5s ==> in real test, longer than 5s, so reduce it
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &unit="Mhz"
+ &fqmtr_winset_26M=&fqmtr_winset
+ &safe_wait_cnt_max=32 ;;32 ms
+ )
+ )
+
+ ;;select source to a valid clock to let reset success.
+ Data.Set (&clksw_base+0x0200) %LE %LONG 0x13
+ Data.Set (&clksw_base+0x0204) %LE %LONG 0x0 ;reset frequency meter
+ WAIT 1000.us
+
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ ;;For accurate, don't div 8 for 32K
+ Data.Set (&clksw_base+0x0200) %LE %LONG (&idx)
+ )
+ ELSE ;; measure PLL and other module
+ (
+ ;;div 8 and select src
+ Data.Set (&clksw_base+0x0200) %LE %LONG (0x0300)|(&idx)
+ )
+
+ Data.Set (&clksw_base+0x0208) %LE %LONG &fqmtr_winset_26M
+ Data.Set (&clksw_base+0x0204) %LE %LONG 0x1 ;enable frequency meter
+
+ ;; read status, to check polling done or not
+ &fqmtr_busy=DATA.LONG(&clksw_base+0x0204)&(1<<1)
+
+ WHILE &fqmtr_busy==0
+ (
+; PRINT ". &fqmtr_busy"
+ &fqmtr_busy=DATA.LONG(&clksw_base+0x0204)&(1<<1)
+ &safe_wait_cnt=&safe_wait_cnt+1
+ IF &safe_wait_cnt==&safe_wait_cnt_max
+ (
+ PRINT "[&str] Wait Fail, exit"
+ RETURN
+ )
+ ELSE
+ (
+; PRINT "Waiting result. safe_wait_cnt=" "&safe_wait_cnt"
+ )
+ WAIT 1000.us
+
+ )
+
+ ;; Calculate the result
+ &fqmtr_result_raw=DATA.LONG(&clksw_base+0x20c)
+
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*(0x3E8)/(&fqmtr_winset_26M+3)
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*8/(&fqmtr_winset_26M+3)
+ )
+
+ &fqmtr_result_dec=&fqmtr_result
+ &fqmtr_result_dec=FORMAT.DECIMAL( 0 , &fqmtr_result )
+
+ PRINT " &idx , &fqmtr_result_dec &unit , &str "
+
+ WAIT 1000.us
+
+ RETURN
+ )
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/Coretracer_PMIC_Golden_Setting_Dump.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/Coretracer_PMIC_Golden_Setting_Dump.cmm
new file mode 100755
index 0000000..9994046
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/Coretracer_PMIC_Golden_Setting_Dump.cmm
@@ -0,0 +1,264 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; MT6779 PMIC golden setting dump
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+system.mode attach
+
+;; CLOCK & RESET
+PRINT "=== CLOCK & RESET ==="
+&MODULE_SW_CG_0_STA=0xC0001090
+&MODULE_SW_CG_2_STA=0xC00010AC
+&ULPOSC_CON=0xC0006440
+&PMICW_CLOCK_CTRL=0xC0001108
+&INFRA_GLOBALCON_RST2_STA=0xC0001148
+
+&tmp=DATA.LONG(&MODULE_SW_CG_0_STA)
+IF ((&tmp) & (0xF))!=0
+(
+ PRINT "FAIL!! MODULE_SW_CG_0_STA &MODULE_SW_CG_0_STA = &tmp , [3:0] != 0"
+)
+ELSE
+(
+ PRINT "Pass. MODULE_SW_CG_0_STA &MODULE_SW_CG_0_STA = &tmp"
+)
+
+&tmp=DATA.LONG(&MODULE_SW_CG_2_STA)
+IF ((&tmp) & (0x100))!=0
+(
+ PRINT "FAIL!! MODULE_SW_CG_2_STA &MODULE_SW_CG_2_STA = &tmp , [8] != 0"
+)
+ELSE
+(
+ PRINT "Pass. MODULE_SW_CG_2_STA &MODULE_SW_CG_2_STA = &tmp"
+)
+
+&tmp=DATA.LONG(&ULPOSC_CON)
+IF (&tmp)!=0
+(
+ PRINT "FAIL!! ULPOSC_CON &ULPOSC_CON = &tmp != 0"
+)
+ELSE
+(
+ PRINT "Pass. ULPOSC_CON &ULPOSC_CON = &tmp"
+)
+
+&tmp=DATA.LONG(&PMICW_CLOCK_CTRL)
+IF ((&tmp) & (0x1FFF))!=0xD
+(
+ PRINT "FAIL!! PMICW_CLOCK_CTRL &PMICW_CLOCK_CTRL = &tmp , [12:0] != 0xD"
+)
+ELSE
+(
+ PRINT "Pass. PMICW_CLOCK_CTRL &PMICW_CLOCK_CTRL = &tmp"
+)
+
+&tmp=DATA.LONG(&INFRA_GLOBALCON_RST2_STA)
+IF ((&tmp) & (0x1))!=0x0
+(
+ PRINT "FAIL!! INFRA_GLOBALCON_RST2_STA &INFRA_GLOBALCON_RST2_STA = &tmp , [0] != 0"
+)
+ELSE
+(
+ PRINT "Pass. INFRA_GLOBALCON_RST2_STA &INFRA_GLOBALCON_RST2_STA = &tmp"
+)
+
+
+
+;; GPIO
+PRINT "=== GPIO ==="
+&GPIO_GPIO_MODE23=0xC0005470
+&IOCFG_RM_DRV_CFG0=0xC1C20000
+
+&tmp=DATA.LONG(&GPIO_GPIO_MODE23)
+IF ((&tmp) & (0xFFFF))!=0x1111
+(
+ PRINT "FAIL!! GPIO_GPIO_MODE23 &GPIO_GPIO_MODE23 = &tmp != 0x1111"
+)
+ELSE
+(
+ PRINT "Pass. GPIO_GPIO_MODE23 &GPIO_GPIO_MODE23 = &tmp"
+)
+
+&tmp=DATA.LONG(&IOCFG_RM_DRV_CFG0)
+IF ((&tmp) & (0x1F8000))!=0x048000
+(
+ PRINT "FAIL!! IOCFG_RM_DRV_CFG0 &IOCFG_RM_DRV_CFG0 = &tmp , [20:18] != 1, [17:15] != 1"
+)
+ELSE
+(
+ PRINT "Pass. IOCFG_RM_DRV_CFG0 &IOCFG_RM_DRV_CFG0 = &tmp"
+)
+
+
+
+;; PMIC_WRAP
+PRINT "=== PMIC_WRAP ==="
+&MUX_SEL=0xC000D000
+&WRAP_EN=0xC000D004
+&HPRIO_ARB_EN=0xC000D06C
+
+&WACS0_EN=0xC000D08C
+&INIT_DONE0=0xC000D090
+&WACS1_EN=0xC000D094
+&INIT_DONE1=0xC000D098
+&WACS2_EN=0xC000D09C
+&INIT_DONE2=0xC000D0A0
+&WACS3_EN=0xC000D0A4
+&INIT_DONE3=0xC000D0A8
+
+&WACS0_RDATA=0xC000DC04
+&WACS1_RDATA=0xC000DC14
+&WACS2_RDATA=0xC000DC24
+&WACS3_RDATA=0xC000DC34
+
+&tmp=DATA.LONG(&MUX_SEL)
+IF ((&tmp) & (0x1))!=0x0
+(
+ PRINT "FAIL!! MUX_SEL &MUX_SEL = &tmp , [0] != 0"
+)
+ELSE
+(
+ PRINT "Pass. MUX_SEL &MUX_SEL = &tmp"
+)
+
+&tmp=DATA.LONG(&WRAP_EN)
+IF ((&tmp) & (0x1))!=0x1
+(
+ PRINT "FAIL!! WRAP_EN &WRAP_EN = &tmp , [0] != 1"
+)
+ELSE
+(
+ PRINT "Pass. WRAP_EN &WRAP_EN = &tmp"
+)
+
+&tmp=DATA.LONG(&HPRIO_ARB_EN)
+IF &tmp!=0xFBB7F
+(
+ PRINT "FAIL!! HPRIO_ARB_EN &HPRIO_ARB_EN = &tmp != 0xFBB7F"
+)
+ELSE
+(
+ PRINT "Pass. HPRIO_ARB_EN &HPRIO_ARB_EN = &tmp"
+)
+
+&tmp=DATA.LONG(&WACS0_EN)
+IF ((&tmp) & (0x1))!=0x1
+(
+ PRINT "FAIL!! WACS0_EN &WACS0_EN = &tmp , [0] != 1"
+)
+ELSE
+(
+ PRINT "Pass. WACS0_EN &WACS0_EN = &tmp"
+)
+
+&tmp=DATA.LONG(&INIT_DONE0)
+IF ((&tmp) & (0x1))!=0x1
+(
+ PRINT "FAIL!! INIT_DONE0 &INIT_DONE0 = &tmp , [0] != 1"
+)
+ELSE
+(
+ PRINT "Pass. INIT_DONE0 &INIT_DONE0 = &tmp"
+)
+
+&tmp=DATA.LONG(&WACS1_EN)
+IF ((&tmp) & (0x1))!=0x1
+(
+ PRINT "FAIL!! WACS1_EN &WACS1_EN = &tmp , [0] != 1"
+)
+ELSE
+(
+ PRINT "Pass. WACS1_EN &WACS1_EN = &tmp"
+)
+
+&tmp=DATA.LONG(&INIT_DONE1)
+IF ((&tmp) & (0x1))!=0x1
+(
+ PRINT "FAIL!! INIT_DONE1 &INIT_DONE1 = &tmp , [0] != 1"
+)
+ELSE
+(
+ PRINT "Pass. INIT_DONE1 &INIT_DONE1 = &tmp"
+)
+
+&tmp=DATA.LONG(&WACS2_EN)
+IF ((&tmp) & (0x1))!=0x1
+(
+ PRINT "FAIL!! WACS2_EN &WACS2_EN = &tmp , [0] != 1"
+)
+ELSE
+(
+ PRINT "Pass. WACS2_EN &WACS2_EN = &tmp"
+)
+
+&tmp=DATA.LONG(&INIT_DONE2)
+IF ((&tmp) & (0x1))!=0x1
+(
+ PRINT "FAIL!! INIT_DONE2 &INIT_DONE2 = &tmp , [0] != 1"
+)
+ELSE
+(
+ PRINT "Pass. INIT_DONE2 &INIT_DONE2 = &tmp"
+)
+
+&tmp=DATA.LONG(&WACS3_EN)
+IF ((&tmp) & (0x1))!=0x1
+(
+ PRINT "FAIL!! WACS3_EN &WACS3_EN = &tmp , [0] != 1"
+)
+ELSE
+(
+ PRINT "Pass. WACS3_EN &WACS3_EN = &tmp"
+)
+
+&tmp=DATA.LONG(&INIT_DONE3)
+IF ((&tmp) & (0x1))!=0x1
+(
+ PRINT "FAIL!! INIT_DONE3 &INIT_DONE3 = &tmp , [0] != 1"
+)
+ELSE
+(
+ PRINT "Pass. INIT_DONE3 &INIT_DONE3 = &tmp"
+)
+
+&tmp=DATA.LONG(&WACS0_RDATA)
+IF ((&tmp) & (0x600000))!=0x600000
+(
+ PRINT "FAIL!! WACS0_RDATA &WACS0_RDATA = &tmp , [21] != 1, [22] != 1"
+)
+ELSE
+(
+ PRINT "Pass. WACS0_RDATA &WACS0_RDATA = &tmp"
+)
+
+&tmp=DATA.LONG(&WACS1_RDATA)
+IF ((&tmp) & (0x600000))!=0x600000
+(
+ PRINT "FAIL!! WACS1_RDATA &WACS1_RDATA = &tmp , [21] != 1, [22] != 1"
+)
+ELSE
+(
+ PRINT "Pass. WACS1_RDATA &WACS1_RDATA = &tmp"
+)
+
+&tmp=DATA.LONG(&WACS2_RDATA)
+IF ((&tmp) & (0x600000))!=0x600000
+(
+ PRINT "FAIL!! WACS2_RDATA &WACS2_RDATA = &tmp , [21] != 1, [22] != 1"
+)
+ELSE
+(
+ PRINT "Pass. WACS2_RDATA &WACS2_RDATA = &tmp"
+)
+
+&tmp=DATA.LONG(&WACS3_RDATA)
+IF ((&tmp) & (0x600000))!=0x600000
+(
+ PRINT "FAIL!! WACS3_RDATA &WACS3_RDATA = &tmp , [21] != 1, [22] != 1"
+)
+ELSE
+(
+ PRINT "Pass. WACS3_RDATA &WACS3_RDATA = &tmp"
+)
+
+ENDDO
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/MT6779_Android_scatter.txt b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/MT6779_Android_scatter.txt
new file mode 100755
index 0000000..d057765
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/MT6779_Android_scatter.txt
@@ -0,0 +1,1209 @@
+############################################################################################################
+#
+# General Setting
+#
+############################################################################################################
+- general: MTK_PLATFORM_CFG
+ info:
+ - config_version: V2.1.0
+ platform: MT6779
+ project: evb6779_64
+############################################################################################################
+#
+# EMMC Layout Setting
+#
+############################################################################################################
+- storage_type: EMMC
+ description:
+ - general: MTK_STORAGE_CFG
+ info:
+ - storage: EMMC
+ boot_channel: MSDC_0
+ block_size: 0x20000
+
+ - partition_index: SYS0
+ partition_name: preloader
+ file_name: preloader_evb6779_64.bin
+ is_download: true
+ type: SV5_BL_BIN
+ linear_start_addr: 0x0
+ physical_start_addr: 0x0
+ partition_size: 0x40000
+ region: EMMC_BOOT1_BOOT2
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: BOOTLOADERS
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS1
+ partition_name: pgpt
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x0
+ physical_start_addr: 0x0
+ partition_size: 0x8000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS2
+ partition_name: boot_para
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x8000
+ physical_start_addr: 0x8000
+ partition_size: 0x100000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS3
+ partition_name: recovery
+ file_name: recovery.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x108000
+ physical_start_addr: 0x108000
+ partition_size: 0x2000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS4
+ partition_name: para
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x2108000
+ physical_start_addr: 0x2108000
+ partition_size: 0x80000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS5
+ partition_name: expdb
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x2188000
+ physical_start_addr: 0x2188000
+ partition_size: 0x1400000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS6
+ partition_name: frp
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x3588000
+ physical_start_addr: 0x3588000
+ partition_size: 0x100000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS7
+ partition_name: vbmeta
+ file_name: vbmeta.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x3688000
+ physical_start_addr: 0x3688000
+ partition_size: 0x800000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS8
+ partition_name: nvcfg
+ file_name: NONE
+ is_download: false
+ type: EXT4_IMG
+ linear_start_addr: 0x3e88000
+ physical_start_addr: 0x3e88000
+ partition_size: 0x2000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: PROTECTED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS9
+ partition_name: nvdata
+ file_name: NONE
+ is_download: false
+ type: EXT4_IMG
+ linear_start_addr: 0x5e88000
+ physical_start_addr: 0x5e88000
+ partition_size: 0x4000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS10
+ partition_name: metadata
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x9e88000
+ physical_start_addr: 0x9e88000
+ partition_size: 0x2000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS11
+ partition_name: protect1
+ file_name: NONE
+ is_download: false
+ type: EXT4_IMG
+ linear_start_addr: 0xbe88000
+ physical_start_addr: 0xbe88000
+ partition_size: 0x800000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: PROTECTED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS12
+ partition_name: protect2
+ file_name: NONE
+ is_download: false
+ type: EXT4_IMG
+ linear_start_addr: 0xc688000
+ physical_start_addr: 0xc688000
+ partition_size: 0x978000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: PROTECTED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS13
+ partition_name: seccfg
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0xd000000
+ physical_start_addr: 0xd000000
+ partition_size: 0x800000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS14
+ partition_name: sec1
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0xd800000
+ physical_start_addr: 0xd800000
+ partition_size: 0x200000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS15
+ partition_name: proinfo
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0xda00000
+ physical_start_addr: 0xda00000
+ partition_size: 0x300000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: PROTECTED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS16
+ partition_name: nvram
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0xdd00000
+ physical_start_addr: 0xdd00000
+ partition_size: 0x4000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: BINREGION
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS17
+ partition_name: md1img
+ file_name: md1img.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x11d00000
+ physical_start_addr: 0x11d00000
+ partition_size: 0x8000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS18
+ partition_name: spmfw
+ file_name: spmfw.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x19d00000
+ physical_start_addr: 0x19d00000
+ partition_size: 0x100000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS19
+ partition_name: gz1
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x19e00000
+ physical_start_addr: 0x19e00000
+ partition_size: 0x1000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS20
+ partition_name: gz2
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x1ae00000
+ physical_start_addr: 0x1ae00000
+ partition_size: 0x1000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS21
+ partition_name: lk
+ file_name: lk.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x1be00000
+ physical_start_addr: 0x1be00000
+ partition_size: 0x100000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: true
+ reserve: 0x00
+
+ - partition_index: SYS22
+ partition_name: lk2
+ file_name: lk.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x1bf00000
+ physical_start_addr: 0x1bf00000
+ partition_size: 0x100000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS23
+ partition_name: boot
+ file_name: boot.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x1c000000
+ physical_start_addr: 0x1c000000
+ partition_size: 0x2000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS24
+ partition_name: logo
+ file_name: logo.bin
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x1e000000
+ physical_start_addr: 0x1e000000
+ partition_size: 0x800000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: false
+ empty_boot_needed: true
+ reserve: 0x00
+
+ - partition_index: SYS25
+ partition_name: dtbo
+ file_name: dtbo.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x1e800000
+ physical_start_addr: 0x1e800000
+ partition_size: 0x800000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS26
+ partition_name: tee1
+ file_name: tee.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x1f000000
+ physical_start_addr: 0x1f000000
+ partition_size: 0x500000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: true
+ reserve: 0x00
+
+ - partition_index: SYS27
+ partition_name: tee2
+ file_name: tee.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x1f500000
+ physical_start_addr: 0x1f500000
+ partition_size: 0xb00000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS28
+ partition_name: vendor
+ file_name: vendor.img
+ is_download: true
+ type: EXT4_IMG
+ linear_start_addr: 0x20000000
+ physical_start_addr: 0x20000000
+ partition_size: 0x38800000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS29
+ partition_name: system
+ file_name: system.img
+ is_download: true
+ type: EXT4_IMG
+ linear_start_addr: 0x58800000
+ physical_start_addr: 0x58800000
+ partition_size: 0xc0000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS30
+ partition_name: cache
+ file_name: cache.img
+ is_download: true
+ type: EXT4_IMG
+ linear_start_addr: 0x118800000
+ physical_start_addr: 0x118800000
+ partition_size: 0x1b000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS31
+ partition_name: userdata
+ file_name: userdata.img
+ is_download: true
+ type: EXT4_IMG
+ linear_start_addr: 0x133800000
+ physical_start_addr: 0x133800000
+ partition_size: 0xc0000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS32
+ partition_name: otp
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0xFFFF01d8
+ physical_start_addr: 0xFFFF01d8
+ partition_size: 0x2b00000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: false
+ is_reserved: true
+ operation_type: RESERVED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS33
+ partition_name: flashinfo
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0xFFFF0080
+ physical_start_addr: 0xFFFF0080
+ partition_size: 0x1000000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: false
+ is_reserved: true
+ operation_type: RESERVED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS34
+ partition_name: sgpt
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0xFFFF0000
+ physical_start_addr: 0xFFFF0000
+ partition_size: 0x8000
+ region: EMMC_USER
+ storage: HW_STORAGE_EMMC
+ boundary_check: false
+ is_reserved: true
+ operation_type: RESERVED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+############################################################################################################
+#
+# UFS Layout Setting
+#
+############################################################################################################
+- storage_type: UFS
+ description:
+ - general: MTK_STORAGE_CFG
+ info:
+ - storage: UFS
+ boot_channel: UFSHCI_0
+ block_size: 0x80000
+
+ - partition_index: SYS0
+ partition_name: preloader
+ file_name: preloader_evb6779_64.bin
+ is_download: true
+ type: SV5_BL_BIN
+ linear_start_addr: 0x0
+ physical_start_addr: 0x0
+ partition_size: 0x40000
+ region: UFS_LU0_LU1
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: BOOTLOADERS
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS1
+ partition_name: pgpt
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x0
+ physical_start_addr: 0x0
+ partition_size: 0x8000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS2
+ partition_name: boot_para
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x8000
+ physical_start_addr: 0x8000
+ partition_size: 0x100000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS3
+ partition_name: recovery
+ file_name: recovery.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x108000
+ physical_start_addr: 0x108000
+ partition_size: 0x2000000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS4
+ partition_name: para
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x2108000
+ physical_start_addr: 0x2108000
+ partition_size: 0x80000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS5
+ partition_name: expdb
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x2188000
+ physical_start_addr: 0x2188000
+ partition_size: 0x1400000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS6
+ partition_name: frp
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x3588000
+ physical_start_addr: 0x3588000
+ partition_size: 0x100000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS7
+ partition_name: vbmeta
+ file_name: vbmeta.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x3688000
+ physical_start_addr: 0x3688000
+ partition_size: 0x800000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS8
+ partition_name: nvcfg
+ file_name: NONE
+ is_download: false
+ type: EXT4_IMG
+ linear_start_addr: 0x3e88000
+ physical_start_addr: 0x3e88000
+ partition_size: 0x2000000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: PROTECTED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS9
+ partition_name: nvdata
+ file_name: NONE
+ is_download: false
+ type: EXT4_IMG
+ linear_start_addr: 0x5e88000
+ physical_start_addr: 0x5e88000
+ partition_size: 0x4000000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS10
+ partition_name: metadata
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x9e88000
+ physical_start_addr: 0x9e88000
+ partition_size: 0x2000000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS11
+ partition_name: protect1
+ file_name: NONE
+ is_download: false
+ type: EXT4_IMG
+ linear_start_addr: 0xbe88000
+ physical_start_addr: 0xbe88000
+ partition_size: 0x800000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: PROTECTED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS12
+ partition_name: protect2
+ file_name: NONE
+ is_download: false
+ type: EXT4_IMG
+ linear_start_addr: 0xc688000
+ physical_start_addr: 0xc688000
+ partition_size: 0x978000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: PROTECTED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS13
+ partition_name: seccfg
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0xd000000
+ physical_start_addr: 0xd000000
+ partition_size: 0x800000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS14
+ partition_name: sec1
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0xd800000
+ physical_start_addr: 0xd800000
+ partition_size: 0x200000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS15
+ partition_name: proinfo
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0xda00000
+ physical_start_addr: 0xda00000
+ partition_size: 0x300000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: PROTECTED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS16
+ partition_name: nvram
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0xdd00000
+ physical_start_addr: 0xdd00000
+ partition_size: 0x4000000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: BINREGION
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS17
+ partition_name: md1img
+ file_name: md1img.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x11d00000
+ physical_start_addr: 0x11d00000
+ partition_size: 0x8000000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS18
+ partition_name: spmfw
+ file_name: spmfw.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x19d00000
+ physical_start_addr: 0x19d00000
+ partition_size: 0x100000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS19
+ partition_name: gz1
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x19e00000
+ physical_start_addr: 0x19e00000
+ partition_size: 0x1000000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS20
+ partition_name: gz2
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0x1ae00000
+ physical_start_addr: 0x1ae00000
+ partition_size: 0x1000000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: INVISIBLE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS21
+ partition_name: lk
+ file_name: lk.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x1be00000
+ physical_start_addr: 0x1be00000
+ partition_size: 0x100000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: true
+ reserve: 0x00
+
+ - partition_index: SYS22
+ partition_name: lk2
+ file_name: lk.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x1bf00000
+ physical_start_addr: 0x1bf00000
+ partition_size: 0x100000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS23
+ partition_name: boot
+ file_name: boot.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x1c000000
+ physical_start_addr: 0x1c000000
+ partition_size: 0x2000000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS24
+ partition_name: logo
+ file_name: logo.bin
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x1e000000
+ physical_start_addr: 0x1e000000
+ partition_size: 0x800000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: false
+ empty_boot_needed: true
+ reserve: 0x00
+
+ - partition_index: SYS25
+ partition_name: dtbo
+ file_name: dtbo.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x1e800000
+ physical_start_addr: 0x1e800000
+ partition_size: 0x800000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS26
+ partition_name: tee1
+ file_name: tee.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x1f000000
+ physical_start_addr: 0x1f000000
+ partition_size: 0x500000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: true
+ reserve: 0x00
+
+ - partition_index: SYS27
+ partition_name: tee2
+ file_name: tee.img
+ is_download: true
+ type: NORMAL_ROM
+ linear_start_addr: 0x1f500000
+ physical_start_addr: 0x1f500000
+ partition_size: 0xb00000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS28
+ partition_name: vendor
+ file_name: vendor.img
+ is_download: true
+ type: EXT4_IMG
+ linear_start_addr: 0x20000000
+ physical_start_addr: 0x20000000
+ partition_size: 0x38800000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS29
+ partition_name: system
+ file_name: system.img
+ is_download: true
+ type: EXT4_IMG
+ linear_start_addr: 0x58800000
+ physical_start_addr: 0x58800000
+ partition_size: 0xc0000000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: true
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS30
+ partition_name: cache
+ file_name: cache.img
+ is_download: true
+ type: EXT4_IMG
+ linear_start_addr: 0x118800000
+ physical_start_addr: 0x118800000
+ partition_size: 0x1b000000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS31
+ partition_name: userdata
+ file_name: userdata.img
+ is_download: true
+ type: EXT4_IMG
+ linear_start_addr: 0x133800000
+ physical_start_addr: 0x133800000
+ partition_size: 0xc0000000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: true
+ is_reserved: false
+ operation_type: UPDATE
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS32
+ partition_name: flashinfo
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0xFFFF0020
+ physical_start_addr: 0xFFFF0020
+ partition_size: 0x1000000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: false
+ is_reserved: true
+ operation_type: RESERVED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
+ - partition_index: SYS33
+ partition_name: sgpt
+ file_name: NONE
+ is_download: false
+ type: NORMAL_ROM
+ linear_start_addr: 0xFFFF0000
+ physical_start_addr: 0xFFFF0000
+ partition_size: 0x8000
+ region: UFS_LU2
+ storage: HW_STORAGE_UFS
+ boundary_check: false
+ is_reserved: true
+ operation_type: RESERVED
+ is_upgradable: false
+ empty_boot_needed: false
+ reserve: 0x00
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/MT6779_EVB_Load_MD_Elf.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/MT6779_EVB_Load_MD_Elf.cmm
new file mode 100755
index 0000000..c89c189
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/MT6779_EVB_Load_MD_Elf.cmm
@@ -0,0 +1,276 @@
+;sys.m prepare
+;LOCAL &TYPE
+
+system.mode attach
+
+; configure GCR_ACCESS Register ++++++++++++++++++++++++++++++++++++++++++++++++
+; CoreTracer will access MO port via CPU to do following configuration
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+; Disable WDT ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;APview_MT6779_disable_WDT.cmm
+LOCAL &BASE_MADDR_MDRGU
+&BASE_MADDR_MDRGU=0xA00F0000
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG 0x55000030
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+; /* Step 3 config md_srclkena setting */+++++++++++++++++++++++++++++++++++++++
+; Move to APCCCI power on sequence step 2...
+;;;;PRINT "=============================="
+;;;;PRINT "config md_srclkena setting"
+;;;;PRINT "=============================="
+;;;;; /* SPM base */
+;;;;&SPM_REG=(0xC0006000)
+;;;;
+;;;;; /* (1) INFRA_MISC2 */
+;;;;&INFRA_MISC2=(0xC0001F0C)
+;;;;; /* (2) SRCLKEN_O1 force on */
+;;;;&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+;;;;&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+;;;;
+;;;;; /* (1) INFRA_MISC2 */
+;;;;; /* [7:4] : mdsrc_req_1_en = 4'b0010 [3:0] : mdsrc_req_0_en = 4'b0001 */
+;;;;&temp=data.long(&INFRA_MISC2)
+;;;;&temp=&temp & (0xFFFFFF00)
+;;;;D.S &INFRA_MISC2 %LE %LONG (&temp)|(0x00000021)
+;;;;
+;;;;; /* (2) SRCLKEN_O1 force on */
+;;;;;D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+;;;;;D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x80215830 //set src clkena1 force on
+;;;;D.S &POWERON_CONFIG_EN %LE %LONG 0x0B160001
+;;;;D.S &SPM_POWER_ON_VAL1 %LE %LONG 0x80215830
+;;;;
+;;;;wait 1.ms
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+; MD PLL related, init 26M quality++++++++++++++++++++++++++++++++++++++++++++++
+PRINT "=============================="
+PRINT "initial CLKSQ_LPF for 26M quality"
+PRINT "=============================="
+&BASE_MADDR_APMIXEDSYS=(0xC000C000)
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+;;// initial CLKSQ_LPF
+&temp=data.long(®_APMIXEDSYS_AP_PLL_CON0)
+&temp=&temp|0x2
+D.S ®_APMIXEDSYS_AP_PLL_CON0 %long %le &temp
+
+wait 1.ms
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+; MD PLL init ==> It could cancel from Gen95..
+&pll_init = 0x0
+IF &pll_init==0x1 ;; MD PLL init
+(
+ &BASE_MADDR_MDTOP_PLLMIXED=(0xA0140000)
+ &BASE_MADDR_MDTOP_CLKSW=(0xA0150000)
+
+ ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+ ®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+ ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+ ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+ ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+ ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+ ®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+ ®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+ ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+ ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+ ®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+ ®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+ ®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+ ®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+ ®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+ ®_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x60)
+ ®_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x70)
+ ®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0xA4)
+
+ &MD_PLL_MAGIC_NUM=(0x62950000)
+ ;;-------------------------------------------------------
+
+ ;;// Default md_srclkena_ack settle time = 124T 32K
+ D.S ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E7C
+
+ ;;// Fixed Fvco = 1800Mhz. (/2)900M, (/3)600M, (/4)450M, (/5)360M, (/6)300M, (/7)257M
+ D.S ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x80114EC5
+ ;;// Fvco = 3600Mhz. 3600/6 = 600Mhz
+ D.S ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80229E00
+ ;;// Fvco = 3400Mhz. 3400/4 = 850Mhz
+ D.S ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x8020B200
+ ;;// Fvco = 3600Mhz. 3600/4 = 900Mhz
+ D.S ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x80229E00
+
+ ;;// LOG_ATB = 100Mhz (mdbpipll_d3_div2_ck/3)
+ D.S ®_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL %long %le 0x00000002
+ ;;// MML2_DFS_PLLSEL=MDBPIPLL_D4 ; MML2_DFS_DIVSEL=divided-by 1
+ D.S ®_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL %long %le 0x00000010
+
+ ;;// Polling until MDMCUPLL complete frequency adjustment
+ ;WHILE ((data.long(&MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0()
+ wait 1.ms
+
+ ;; PLL ON controlled by HW
+ D.S ®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x00000000
+
+ ;; Update ABB MDPLL control register default value
+ D.S ®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x4C43100
+
+ ;; /*
+ ;; * Wait MD bus clock ready
+ ;; * Once MD bus ready, other clock should be ready too
+ ;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+ ;; */
+ ;WHILE (data.long(&MEM_CLASS:®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000()
+ wait 1.ms
+
+ ;;=================Switch clock source to PLL====================
+ ;;// Switch MDMCU & MD BUS clock to PLL frequency
+ ;D.S ®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(®_MDTOP_CLKSW_CLKSEL_CTL)|(0x3)
+ &temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+ &temp=&temp|0x3
+ D.S ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+ ;;// Switch all clock to PLL frequency
+ ;D.S ®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(®_MDTOP_CLKSW_CLKSEL_CTL)|(0x31811F5C)
+ &temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+ &temp=&temp|0x31811F5C
+ D.S ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+ ;;// Turn off all SW clock request, except ATB
+ D.S ®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+ ;;// Switch SDF clock to PLL frequency
+ ;D.S ®_MDTOP_CLKSW_SDF_CK_CTL %long %le data.long(®_MDTOP_CLKSW_SDF_CK_CTL)|(0x11)
+ &temp=data.long(®_MDTOP_CLKSW_SDF_CK_CTL)
+ &temp=&temp|0x11
+ D.S ®_MDTOP_CLKSW_SDF_CK_CTL %long %le &temp
+
+ ;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+ D.S ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+ ;;// Mask all PLL ADJ RDY IRQ
+ D.S ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+ ;;// Make a record that means MD pll has been initialized.
+ D.S ®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+)
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+;; Set UART GPIO(owner: UART, Yao Xue) +++++++++++++++++++++++++++++++++++++++++
+;;APview_MT6779_GPIO_MDUART0.cmm
+PRINT "=============================="
+PRINT "Set GPIO!"
+PRINT "=============================="
+
+;Lafite MD_UART0 port test
+;You should make sure GPIO47 has connected to UART port RXD pin, GPIO48 has connected to UART port TXD pin
+;port: MDUART0
+;Baudrate: 1500000
+&BASE_ADDR_MDGPIO=0xC0005000
+&BASE_ADDR_IOCFG=0xC1E20000
+
+;//clear GPIO47 to GPIO mode.
+D.S &BASE_ADDR_MDGPIO+0x358 %LE %LONG 0x70000000
+;//clear GPIO48 to GPIO mode.
+D.S &BASE_ADDR_MDGPIO+0x368 %LE %LONG 0x00000007
+;//set GPIO47 to MD_URXD0 mode.
+D.S &BASE_ADDR_MDGPIO+0x354 %LE %LONG 0x40000000
+;//set GPIO48 to MD_UTXD0 mode.
+D.S &BASE_ADDR_MDGPIO+0x364 %LE %LONG 0x00000004
+
+D.S &BASE_ADDR_IOCFG+0x68 %LE %LONG 0xC000 ;//MD_URXD0/MD_UTXD0 PD clear
+D.S &BASE_ADDR_IOCFG+0x84 %LE %LONG 0x8000 ;//MD_URXD0 PU set
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+;; Set SIM GPIO(owner: SIM, Ansel Liao) ++++++++++++++++++++++++++++++++++++++++
+;;APview_MT6779_GPIO_SIM.cmm
+;;// SIM2 GPIO
+;;// SIM1 GPIO
+
+&temp=data.long(0xC0005400)
+&temp=&temp & (0xFF000000)
+D.S 0xC0005400 %LE %LONG &temp
+
+&temp=data.long(0xC0005400)
+&temp=&temp | (0x00111111)
+D.S 0xC0005400 %LE %LONG &temp
+
+;;// SIM2 PUPD
+;;// SIM1 PUPD
+
+&temp=data.long(0xC1C20060)
+&temp=&temp & (0x0000003F)
+D.S 0xC1C20060 %LE %LONG &temp
+
+&temp=data.long(0xC1C20060)
+&temp=&temp | (0x00000480)
+D.S 0xC1C20060 %LE %LONG &temp
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+;set MD EMI remap address(owner: AP CCCI, Yanjie Jiang) ++++++++++++++++++++++++
+PRINT "=============================="
+PRINT "Set MD EMI Remap!"
+PRINT "=============================="
+;d.s &MEM_CLASS:0xC0001300 %long %le 0x00430041
+;d.s &MEM_CLASS:0xC0001304 %long %le 0x00470045
+;d.s &MEM_CLASS:0xC0001308 %long %le 0x004b0049
+;d.s &MEM_CLASS:0xC000130c %long %le 0x004f004d
+D.S 0xC0001300 %LE %LONG 0x00430041
+D.S 0xC0001304 %LE %LONG 0x00470045
+D.S 0xC0001308 %LE %LONG 0x004b0049
+D.S 0xC000130c %LE %LONG 0x004f004d
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+;Enable cache to speed loading & load ELF+++++++++++++++++++++++++++++++++++++++
+;By setting bank 6 segment control attribute
+register.set cdmmbase 0x1fc1407
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor adapter_khz 2000
+steal monitor mips32 fastchannel 0 1 0x6f800000
+
+PRINT "=============================="
+PRINT "Start to Load elf !"
+PRINT "=============================="
+
+thread.select 1
+steal lo
+
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+PRINT "=============================="
+PRINT "Load elf Done!"
+PRINT "=============================="
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+thread.select 1
+
+;&t=var.address(INT_Initialize_Phase1)
+;wait 20.ms
+;stop
+;steal set $pc = &INT_Initialize_Phase1
+;register.set pc &t
+
+;PRINT "=============================="
+;PRINT "Set PC to INT_Initialize_Phase1: &t"
+;PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/MT6779_EVB_Load_MD_Elf_BigRam_Load.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/MT6779_EVB_Load_MD_Elf_BigRam_Load.cmm
new file mode 100755
index 0000000..323611e
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/MT6779_EVB_Load_MD_Elf_BigRam_Load.cmm
@@ -0,0 +1,305 @@
+;sys.m prepare
+;LOCAL &TYPE
+
+system.mode attach
+
+; configure GCR_ACCESS Register ++++++++++++++++++++++++++++++++++++++++++++++++
+; CoreTracer will access MO port via CPU to do following configuration
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+; Disable WDT ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;APview_MT6779_disable_WDT.cmm
+LOCAL &BASE_MADDR_MDRGU
+&BASE_MADDR_MDRGU=0xA00F0000
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG 0x55000030
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+; /* Step 3 config md_srclkena setting */+++++++++++++++++++++++++++++++++++++++
+; Move to APCCCI power on sequence step 2...
+;;;;PRINT "=============================="
+;;;;PRINT "config md_srclkena setting"
+;;;;PRINT "=============================="
+;;;;; /* SPM base */
+;;;;&SPM_REG=(0xC0006000)
+;;;;
+;;;;; /* (1) INFRA_MISC2 */
+;;;;&INFRA_MISC2=(0xC0001F0C)
+;;;;; /* (2) SRCLKEN_O1 force on */
+;;;;&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+;;;;&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+;;;;
+;;;;; /* (1) INFRA_MISC2 */
+;;;;; /* [7:4] : mdsrc_req_1_en = 4'b0010 [3:0] : mdsrc_req_0_en = 4'b0001 */
+;;;;&temp=data.long(&INFRA_MISC2)
+;;;;&temp=&temp & (0xFFFFFF00)
+;;;;D.S &INFRA_MISC2 %LE %LONG (&temp)|(0x00000021)
+;;;;
+;;;;; /* (2) SRCLKEN_O1 force on */
+;;;;;D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+;;;;;D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x80215830 //set src clkena1 force on
+;;;;D.S &POWERON_CONFIG_EN %LE %LONG 0x0B160001
+;;;;D.S &SPM_POWER_ON_VAL1 %LE %LONG 0x80215830
+;;;;
+;;;;wait 1.ms
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+; MD PLL related, init 26M quality++++++++++++++++++++++++++++++++++++++++++++++
+PRINT "=============================="
+PRINT "initial CLKSQ_LPF for 26M quality"
+PRINT "=============================="
+&BASE_MADDR_APMIXEDSYS=(0xC000C000)
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+;;// initial CLKSQ_LPF
+&temp=data.long(®_APMIXEDSYS_AP_PLL_CON0)
+&temp=&temp|0x2
+D.S ®_APMIXEDSYS_AP_PLL_CON0 %long %le &temp
+
+wait 1.ms
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+; MD PLL init ==> It could cancel from Gen95..
+&pll_init = 0x0
+IF &pll_init==0x1 ;; MD PLL init
+(
+ &BASE_MADDR_MDTOP_PLLMIXED=(0xA0140000)
+ &BASE_MADDR_MDTOP_CLKSW=(0xA0150000)
+
+ ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+ ®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+ ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+ ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+ ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+ ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+ ®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+ ®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+ ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+ ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+ ®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+ ®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+ ®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+ ®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+ ®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+ ®_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x60)
+ ®_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x70)
+ ®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0xA4)
+
+ &MD_PLL_MAGIC_NUM=(0x62950000)
+ ;;-------------------------------------------------------
+
+ ;;// Default md_srclkena_ack settle time = 124T 32K
+ D.S ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E7C
+
+ ;;// Fixed Fvco = 1800Mhz. (/2)900M, (/3)600M, (/4)450M, (/5)360M, (/6)300M, (/7)257M
+ D.S ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x80114EC5
+ ;;// Fvco = 3600Mhz. 3600/6 = 600Mhz
+ D.S ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80229E00
+ ;;// Fvco = 3400Mhz. 3400/4 = 850Mhz
+ D.S ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x8020B200
+ ;;// Fvco = 3600Mhz. 3600/4 = 900Mhz
+ D.S ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x80229E00
+
+ ;;// LOG_ATB = 100Mhz (mdbpipll_d3_div2_ck/3)
+ D.S ®_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL %long %le 0x00000002
+ ;;// MML2_DFS_PLLSEL=MDBPIPLL_D4 ; MML2_DFS_DIVSEL=divided-by 1
+ D.S ®_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL %long %le 0x00000010
+
+ ;;// Polling until MDMCUPLL complete frequency adjustment
+ ;WHILE ((data.long(&MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0()
+ wait 1.ms
+
+ ;; PLL ON controlled by HW
+ D.S ®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x00000000
+
+ ;; Update ABB MDPLL control register default value
+ D.S ®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x4C43100
+
+ ;; /*
+ ;; * Wait MD bus clock ready
+ ;; * Once MD bus ready, other clock should be ready too
+ ;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+ ;; */
+ ;WHILE (data.long(&MEM_CLASS:®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000()
+ wait 1.ms
+
+ ;;=================Switch clock source to PLL====================
+ ;;// Switch MDMCU & MD BUS clock to PLL frequency
+ ;D.S ®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(®_MDTOP_CLKSW_CLKSEL_CTL)|(0x3)
+ &temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+ &temp=&temp|0x3
+ D.S ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+ ;;// Switch all clock to PLL frequency
+ ;D.S ®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(®_MDTOP_CLKSW_CLKSEL_CTL)|(0x31811F5C)
+ &temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+ &temp=&temp|0x31811F5C
+ D.S ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+ ;;// Turn off all SW clock request, except ATB
+ D.S ®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+ ;;// Switch SDF clock to PLL frequency
+ ;D.S ®_MDTOP_CLKSW_SDF_CK_CTL %long %le data.long(®_MDTOP_CLKSW_SDF_CK_CTL)|(0x11)
+ &temp=data.long(®_MDTOP_CLKSW_SDF_CK_CTL)
+ &temp=&temp|0x11
+ D.S ®_MDTOP_CLKSW_SDF_CK_CTL %long %le &temp
+
+ ;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+ D.S ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+ ;;// Mask all PLL ADJ RDY IRQ
+ D.S ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+ ;;// Make a record that means MD pll has been initialized.
+ D.S ®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+)
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+;; Set UART GPIO(owner: UART, Yao Xue) +++++++++++++++++++++++++++++++++++++++++
+;;APview_MT6779_GPIO_MDUART0.cmm
+PRINT "=============================="
+PRINT "Set GPIO!"
+PRINT "=============================="
+
+;Lafite MD_UART0 port test
+;You should make sure GPIO47 has connected to UART port RXD pin, GPIO48 has connected to UART port TXD pin
+;port: MDUART0
+;Baudrate: 1500000
+&BASE_ADDR_MDGPIO=0xC0005000
+&BASE_ADDR_IOCFG=0xC1E20000
+
+D.S &BASE_ADDR_MDGPIO+0x358 %LE %LONG 0x70000000 ;//clear GPIO47 to GPIO mode.
+D.S &BASE_ADDR_MDGPIO+0x368 %LE %LONG 0x00000007 ;//clear GPIO48 to GPIO mode.
+D.S &BASE_ADDR_MDGPIO+0x354 %LE %LONG 0x40000000 ;//set GPIO47 to MD_URXD0 mode.
+D.S &BASE_ADDR_MDGPIO+0x364 %LE %LONG 0x00000004 ;//set GPIO48 to MD_UTXD0 mode.
+
+D.S &BASE_ADDR_IOCFG+0x68 %LE %LONG 0xC000 ;//MD_URXD0/MD_UTXD0 PD clear
+D.S &BASE_ADDR_IOCFG+0x84 %LE %LONG 0x8000 ;//MD_URXD0 PU set
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+;; Set SIM GPIO(owner: SIM, Ansel Liao) ++++++++++++++++++++++++++++++++++++++++
+;;APview_MT6779_GPIO_SIM.cmm
+;;// SIM2 GPIO
+;;// SIM1 GPIO
+
+&temp=data.long(0xC0005400)
+&temp=&temp & (0xFF000000)
+D.S 0xC0005400 %LE %LONG &temp
+
+&temp=data.long(0xC0005400)
+&temp=&temp | (0x00111111)
+D.S 0xC0005400 %LE %LONG &temp
+
+;;// SIM2 PUPD
+;;// SIM1 PUPD
+
+&temp=data.long(0xC1C20060)
+&temp=&temp & (0x0000003F)
+D.S 0xC1C20060 %LE %LONG &temp
+
+&temp=data.long(0xC1C20060)
+&temp=&temp | (0x00000480)
+D.S 0xC1C20060 %LE %LONG &temp
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+;set MD EMI remap address(owner: AP CCCI, Yanjie Jiang) ++++++++++++++++++++++++
+PRINT "=============================="
+PRINT "Set MD EMI Remap!"
+PRINT "=============================="
+;d.s &MEM_CLASS:0xC0001300 %long %le 0x00430041
+;d.s &MEM_CLASS:0xC0001304 %long %le 0x00470045
+;d.s &MEM_CLASS:0xC0001308 %long %le 0x004b0049
+;d.s &MEM_CLASS:0xC000130c %long %le 0x004f004d
+D.S 0xC0001300 %LE %LONG 0x00430041
+D.S 0xC0001304 %LE %LONG 0x00470045
+D.S 0xC0001308 %LE %LONG 0x004b0049
+D.S 0xC000130c %LE %LONG 0x004f004d
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+&BASE_ADDR_BUS=0xA0330000
+
+;;Power on BigRam
+PRINT "=============================="
+PRINT "Power on BigRam ..."
+PRINT "=============================="
+DATA.SET 0xAB810008 %LE %LONG 0x7FF
+DATA.SET 0xAB830000 %LE %LONG 0x1
+
+;;;;;;;;;;Disable EMI Path
+PRINT "=============================="
+PRINT "Disable EMI Path"
+PRINT "=============================="
+;;1)mask other si decerr
+®_value=DATA.LONG(&BASE_ADDR_BUS+0x24)|0x3C
+DATA.SET (&BASE_ADDR_BUS+0x24) %LE %LONG ®_value
+
+;;2)reset and clear all decerr status
+®_value=DATA.LONG(&BASE_ADDR_BUS+0x10) & (0xFFFFFFE0)
+DATA.SET (&BASE_ADDR_BUS+0x10) %LE %LONG ®_value
+®_value=DATA.LONG(&BASE_ADDR_BUS+0x10) | 0x1F
+DATA.SET (&BASE_ADDR_BUS+0x10) %LE %LONG ®_value
+
+;;3)disable mm port to emi path (mm_1x4_way_en)
+®_value=DATA.LONG(&BASE_ADDR_BUS) & (0xFFFFFFFD)
+DATA.SET &BASE_ADDR_BUS %LE %LONG ®_value
+
+;;4)enable bus decerr enable (bus_dec_err_en)
+®_value=DATA.LONG(&BASE_ADDR_BUS+0x10) | 0x40000000
+DATA.SET (&BASE_ADDR_BUS+0x10) %LE %LONG ®_value
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;Enable cache to speed loading & load ELF+++++++++++++++++++++++++++++++++++++++
+;By setting bank 6 segment control attribute
+;register.set cdmmbase 0x1fc1407
+;D.S 0x1FC100D4 %LE %LONG 0x02030202
+;steal monitor adapter_khz 2000
+
+;Disable fastchannel to access EMI
+steal monitor mips32 fastchannel 0 0 0x6f800000
+
+PRINT "=============================="
+PRINT "Start to Load elf !"
+PRINT "=============================="
+
+thread.select 1
+steal lo
+
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+PRINT "=============================="
+PRINT "Load elf Done!"
+PRINT "=============================="
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+thread.select 1
+
+&tt=var.address(INT_Vectors)
+register.set pc &tt
+steal flushreg
+
+;PRINT "=============================="
+;PRINT "Set PC to INT_Vectors: &t"
+;PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/MT6779_EVB_Load_MD_Elf_With_DSP.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/MT6779_EVB_Load_MD_Elf_With_DSP.cmm
new file mode 100755
index 0000000..2b42373
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/MT6779_EVB_Load_MD_Elf_With_DSP.cmm
@@ -0,0 +1,279 @@
+;sys.m prepare
+;LOCAL &TYPE
+
+system.mode attach
+
+; configure GCR_ACCESS Register ++++++++++++++++++++++++++++++++++++++++++++++++
+; CoreTracer will access MO port via CPU to do following configuration
+D.S 0x1F000020 %LE %LONG 0x0000000F
+D.S 0x1F000090 %LE %LONG 0xA0000000
+D.S 0x1F000098 %LE %LONG 0xE0000002
+D.S 0x1F0000A0 %LE %LONG 0xC0000000
+D.S 0x1F0000A8 %LE %LONG 0xC0000002
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+; Disable WDT ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+;APview_MT6779_disable_WDT.cmm
+LOCAL &BASE_MADDR_MDRGU
+&BASE_MADDR_MDRGU=0xA00F0000
+
+PRINT "=============================="
+PRINT "Disable MD WDT!"
+PRINT "=============================="
+
+;D.S &MEM_CLASS:&BASE_MADDR_MDRGU+0x100 %LE %LONG (0x55000030)
+D.S &BASE_MADDR_MDRGU+0x0100 %LE %LONG 0x55000030
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+; /* Step 3 config md_srclkena setting */+++++++++++++++++++++++++++++++++++++++
+; Move to APCCCI power on sequence step 2...
+;;;;PRINT "=============================="
+;;;;PRINT "config md_srclkena setting"
+;;;;PRINT "=============================="
+;;;;; /* SPM base */
+;;;;&SPM_REG=(0xC0006000)
+;;;;
+;;;;; /* (1) INFRA_MISC2 */
+;;;;&INFRA_MISC2=(0xC0001F0C)
+;;;;; /* (2) SRCLKEN_O1 force on */
+;;;;&POWERON_CONFIG_EN=(&SPM_REG+0x0)
+;;;;&SPM_POWER_ON_VAL1=(&SPM_REG+0x8)
+;;;;
+;;;;; /* (1) INFRA_MISC2 */
+;;;;; /* [7:4] : mdsrc_req_1_en = 4'b0010 [3:0] : mdsrc_req_0_en = 4'b0001 */
+;;;;&temp=data.long(&INFRA_MISC2)
+;;;;&temp=&temp & (0xFFFFFF00)
+;;;;D.S &INFRA_MISC2 %LE %LONG (&temp)|(0x00000021)
+;;;;
+;;;;; /* (2) SRCLKEN_O1 force on */
+;;;;;D.S (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001 //set SPM register for clkenal force on
+;;;;;D.S (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG 0x80215830 //set src clkena1 force on
+;;;;D.S &POWERON_CONFIG_EN %LE %LONG 0x0B160001
+;;;;D.S &SPM_POWER_ON_VAL1 %LE %LONG 0x80215830
+;;;;
+;;;;wait 1.ms
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+; MD PLL related, init 26M quality++++++++++++++++++++++++++++++++++++++++++++++
+PRINT "=============================="
+PRINT "initial CLKSQ_LPF for 26M quality"
+PRINT "=============================="
+&BASE_MADDR_APMIXEDSYS=(0xC000C000)
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+
+;;// initial CLKSQ_LPF
+&temp=data.long(®_APMIXEDSYS_AP_PLL_CON0)
+&temp=&temp|0x2
+D.S ®_APMIXEDSYS_AP_PLL_CON0 %long %le &temp
+
+wait 1.ms
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+; MD PLL init ==> It could cancel from Gen95..
+&pll_init = 0x0
+IF &pll_init==0x1 ;; MD PLL init
+(
+ &BASE_MADDR_MDTOP_PLLMIXED=(0xA0140000)
+ &BASE_MADDR_MDTOP_CLKSW=(0xA0150000)
+
+ ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+ ®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+ ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+ ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+ ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+ ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x60)
+ ®_MDTOP_PLLMIXED_MDBPIPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x64)
+ ®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x104)
+ ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+ ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+ ®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0xC00)
+ ®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+ ®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+ ®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+ ®_MDTOP_CLKSW_SDF_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+ ®_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x60)
+ ®_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x70)
+ ®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0xA4)
+
+ &MD_PLL_MAGIC_NUM=(0x62950000)
+ ;;-------------------------------------------------------
+
+ ;;// Default md_srclkena_ack settle time = 124T 32K
+ D.S ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL %long %le 0x02020E7C
+
+ ;;// Fixed Fvco = 1800Mhz. (/2)900M, (/3)600M, (/4)450M, (/5)360M, (/6)300M, (/7)257M
+ D.S ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0 %long %le 0x80114EC5
+ ;;// Fvco = 3600Mhz. 3600/6 = 600Mhz
+ D.S ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0 %long %le 0x80229E00
+ ;;// Fvco = 3400Mhz. 3400/4 = 850Mhz
+ D.S ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 %long %le 0x8020B200
+ ;;// Fvco = 3600Mhz. 3600/4 = 900Mhz
+ D.S ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0 %long %le 0x80229E00
+
+ ;;// LOG_ATB = 100Mhz (mdbpipll_d3_div2_ck/3)
+ D.S ®_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL %long %le 0x00000002
+ ;;// MML2_DFS_PLLSEL=MDBPIPLL_D4 ; MML2_DFS_DIVSEL=divided-by 1
+ D.S ®_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL %long %le 0x00000010
+
+ ;;// Polling until MDMCUPLL complete frequency adjustment
+ ;WHILE ((data.long(&MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_STS)>>14)&0x1)!=0()
+ wait 1.ms
+
+ ;; PLL ON controlled by HW
+ D.S ®_MDTOP_PLLMIXED_PLL_ON_CTL %long %le 0x00000000
+
+ ;; Update ABB MDPLL control register default value
+ D.S ®_MDTOP_PLLMIXED_MDPLL_CTL1 %long %le 0x4C43100
+
+ ;; /*
+ ;; * Wait MD bus clock ready
+ ;; * Once MD bus ready, other clock should be ready too
+ ;; * In FPGA, the following status checking must be removed since there is no flex ck gen in FPGA.
+ ;; */
+ ;WHILE (data.long(&MEM_CLASS:®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS)&0x8000)!=0x8000()
+ wait 1.ms
+
+ ;;=================Switch clock source to PLL====================
+ ;;// Switch MDMCU & MD BUS clock to PLL frequency
+ ;D.S ®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(®_MDTOP_CLKSW_CLKSEL_CTL)|(0x3)
+ &temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+ &temp=&temp|0x3
+ D.S ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+ ;;// Switch all clock to PLL frequency
+ ;D.S ®_MDTOP_CLKSW_CLKSEL_CTL %long %le data.long(®_MDTOP_CLKSW_CLKSEL_CTL)|(0x31811F5C)
+ &temp=data.long(®_MDTOP_CLKSW_CLKSEL_CTL)
+ &temp=&temp|0x31811F5C
+ D.S ®_MDTOP_CLKSW_CLKSEL_CTL %long %le &temp
+
+ ;;// Turn off all SW clock request, except ATB
+ D.S ®_MDTOP_CLKSW_CLKON_CTL %long %le 0x1
+
+ ;;// Switch SDF clock to PLL frequency
+ ;D.S ®_MDTOP_CLKSW_SDF_CK_CTL %long %le data.long(®_MDTOP_CLKSW_SDF_CK_CTL)|(0x11)
+ &temp=data.long(®_MDTOP_CLKSW_SDF_CK_CTL)
+ &temp=&temp|0x11
+ D.S ®_MDTOP_CLKSW_SDF_CK_CTL %long %le &temp
+
+ ;;// Clear PLL ADJ RDY IRQ fired by initial period adjustment
+ D.S ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ %long %le 0xFFFF
+
+ ;;// Mask all PLL ADJ RDY IRQ
+ D.S ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK %long %le 0xFFFF
+
+ ;;// Make a record that means MD pll has been initialized.
+ D.S ®_MDTOP_PLLMIXED_PLL_DUMMY %long %le &MD_PLL_MAGIC_NUM
+)
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+;; Set UART GPIO(owner: UART, Yao Xue) +++++++++++++++++++++++++++++++++++++++++
+;;APview_MT6779_GPIO_MDUART0.cmm
+PRINT "=============================="
+PRINT "Set GPIO!"
+PRINT "=============================="
+
+;Lafite MD_UART0 port test
+;You should make sure GPIO47 has connected to UART port RXD pin, GPIO48 has connected to UART port TXD pin
+;port: MDUART0
+;Baudrate: 1500000
+&BASE_ADDR_MDGPIO=0xC0005000
+&BASE_ADDR_IOCFG=0xC1E20000
+
+D.S &BASE_ADDR_MDGPIO+0x358 %LE %LONG 0x70000000 ;//clear GPIO47 to GPIO mode.
+D.S &BASE_ADDR_MDGPIO+0x368 %LE %LONG 0x00000007 ;//clear GPIO48 to GPIO mode.
+D.S &BASE_ADDR_MDGPIO+0x354 %LE %LONG 0x40000000 ;//set GPIO47 to MD_URXD0 mode.
+D.S &BASE_ADDR_MDGPIO+0x364 %LE %LONG 0x00000004 ;//set GPIO48 to MD_UTXD0 mode.
+
+D.S &BASE_ADDR_IOCFG+0x68 %LE %LONG 0xC000 ;//MD_URXD0/MD_UTXD0 PD clear
+D.S &BASE_ADDR_IOCFG+0x84 %LE %LONG 0x8000 ;//MD_URXD0 PU set
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+;; Set SIM GPIO(owner: SIM, Ansel Liao) ++++++++++++++++++++++++++++++++++++++++
+;;APview_MT6779_GPIO_SIM.cmm
+;;// SIM2 GPIO
+;;// SIM1 GPIO
+
+&temp=data.long(0xC0005400)
+&temp=&temp & (0xFF000000)
+D.S 0xC0005400 %LE %LONG &temp
+
+&temp=data.long(0xC0005400)
+&temp=&temp | (0x00111111)
+D.S 0xC0005400 %LE %LONG &temp
+
+;;// SIM2 PUPD
+;;// SIM1 PUPD
+
+&temp=data.long(0xC1C20060)
+&temp=&temp & (0x0000003F)
+D.S 0xC1C20060 %LE %LONG &temp
+
+&temp=data.long(0xC1C20060)
+&temp=&temp | (0x00000480)
+D.S 0xC1C20060 %LE %LONG &temp
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+;set MD EMI remap address(owner: AP CCCI, Yanjie Jiang) ++++++++++++++++++++++++
+PRINT "=============================="
+PRINT "Set MD EMI Remap!"
+PRINT "=============================="
+;d.s &MEM_CLASS:0xC0001300 %long %le 0x00430041
+;d.s &MEM_CLASS:0xC0001304 %long %le 0x00470045
+;d.s &MEM_CLASS:0xC0001308 %long %le 0x004b0049
+;d.s &MEM_CLASS:0xC000130c %long %le 0x004f004d
+D.S 0xC0001300 %LE %LONG 0x00430041
+D.S 0xC0001304 %LE %LONG 0x00470045
+D.S 0xC0001308 %LE %LONG 0x004b0049
+D.S 0xC000130c %LE %LONG 0x004f004d
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+;Enable cache to speed loading & load ELF+++++++++++++++++++++++++++++++++++++++
+;By setting bank 6 segment control attribute
+register.set cdmmbase 0x1fc1407
+D.S 0x1FC100D4 %LE %LONG 0x02030202
+steal monitor adapter_khz 2000
+steal monitor mips32 fastchannel 0 1 0x6f800000
+
+PRINT "=============================="
+PRINT "Start to Load elf !"
+PRINT "=============================="
+
+thread.select 1
+steal lo
+
+PRINT "=============================="
+PRINT "Load MD elf Done."
+PRINT "Please start to load DSP bin!"
+PRINT "=============================="
+
+steal source ../cmm/coretracer/config/easyLoader/load_dsp.py
+
+D.S 0x1FC100D4 %LE %LONG 0x02020202
+PRINT "=============================="
+PRINT "Load DSP bin Done!"
+PRINT "=============================="
+;;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+thread.select 1
+
+;&t=var.address(INT_Initialize_Phase1)
+;wait 20.ms
+;stop
+;steal set $pc = &INT_Initialize_Phase1
+;register.set pc &t
+
+;PRINT "=============================="
+;PRINT "Set PC to INT_Initialize_Phase1: &t"
+;PRINT "=============================="
+
+ENDDO
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/MT6779_MD_Only.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/MT6779_MD_Only.cmm
new file mode 100755
index 0000000..19684eb
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/MT6779_MD_Only.cmm
@@ -0,0 +1,42 @@
+;AP pmic workaround
+&MEM_CLASS="AXI"
+sys.m prepare
+wait 1.ms
+
+; Step 1 config MD related Buck
+; [Note] CVD script do NOT need this step
+; skip
+
+; Step 2 config md_srclkena setting
+; do APview_MT6779_md_srclkena.cmm
+
+; Step 3 power on MTCMOS
+; [Note] CVD script do NOT need this step
+; skip
+
+; Step 4 config PLL setting ==> only need to config 26M quality
+&BASE_MADDR_APMIXEDSYS=(0x1000C000)
+®_APMIXEDSYS_AP_PLL_CON0=(&BASE_MADDR_APMIXEDSYS+0x0)
+;;//Enables clock square1 low-pass filter for 26M quality.
+d.s &MEM_CLASS:®_APMIXEDSYS_AP_PLL_CON0 %long %le data.long(&MEM_CLASS:®_APMIXEDSYS_AP_PLL_CON0)|0x2
+wait 1.ms
+;;do APview_MT6779_MD_PLL_Init.cmm ;;PLL init ==> no need from Gen95
+
+; Step 4.5 Disable MD WDT
+do APview_MT6779_disable_WDT.cmm
+
+; Step 5 set GPIO
+do APview_MT6779_GPIO_MDUART0.cmm
+do APview_MT6779_GPIO_SIM.cmm
+
+;Step 6 Force on Debug Sys clock
+;do APview_MT6779_MD_ForceOnDebugSys.cmm
+
+;Step 7 set MD EMI remap address (MD view: step 9)
+d.s &MEM_CLASS:0x10001300 %long %le 0x00430041
+d.s &MEM_CLASS:0x10001304 %long %le 0x00470045
+d.s &MEM_CLASS:0x10001308 %long %le 0x004b0049
+d.s &MEM_CLASS:0x1000130c %long %le 0x004f004d
+
+; Final Step: Trigger MD MCU to run
+; skip
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/L2CacheTag_Parser/Customize.dtd b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/L2CacheTag_Parser/Customize.dtd
new file mode 100644
index 0000000..977cb81
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/L2CacheTag_Parser/Customize.dtd
@@ -0,0 +1,17 @@
+<!ELEMENT Customize (Toolbar*,MainMenu*)>
+<!ELEMENT Toolbar (GDB*,SHELL*,PYSWTBOT*,CMM*,Menu*,MenuItem*)>
+<!ELEMENT MainMenu (Menu*,MenuItem*)>
+<!ELEMENT Menu (Menu*,MenuItem*)>
+<!ELEMENT MenuItem (GDB*,SHELL*,PYSWTBOT*,CMM*)>
+<!ATTLIST Toolbar name CDATA #REQUIRED>
+<!ATTLIST Toolbar icon CDATA #REQUIRED>
+<!ATTLIST MainMenu name CDATA #REQUIRED>
+<!ATTLIST MainMenu icon CDATA #REQUIRED>
+<!ATTLIST Menu name CDATA #REQUIRED>
+<!ATTLIST Menu icon CDATA #REQUIRED>
+<!ATTLIST MenuItem name CDATA #REQUIRED>
+<!ATTLIST MenuItem icon CDATA #REQUIRED>
+<!ELEMENT GDB (#PCDATA)>
+<!ELEMENT SHELL (#PCDATA)>
+<!ELEMENT PYSWTBOT (#PCDATA)>
+<!ELEMENT CMM (#PCDATA)>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/L2CacheTag_Parser/L2cacheTag.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/L2CacheTag_Parser/L2cacheTag.act
new file mode 100755
index 0000000..bf63f8e
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/L2CacheTag_Parser/L2cacheTag.act
@@ -0,0 +1,6 @@
+<?xml version="1.0"?>
+<Customize>
+ <Action name="L2cacheTag">
+ <GDBSource>L2cacheTag.py</GDBSource>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/L2CacheTag_Parser/L2cacheTag.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/L2CacheTag_Parser/L2cacheTag.py
new file mode 100755
index 0000000..b3cbbb9
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/L2CacheTag_Parser/L2cacheTag.py
@@ -0,0 +1,221 @@
+import sys
+import time
+import os
+sys.path.append(os.path.dirname(os.path.realpath(__file__)))
+import gdb
+import struct
+from operator import itemgetter, attrgetter
+from TCF import Event, Result
+import TCF as client
+
+
+host = 'localhost'
+port = 1534
+
+result = gdb.execute('show env tcfport', to_string=True)
+if not result == None:
+ portstr = str(result)
+ try:
+ port = int(portstr[portstr.index('=')+2:])
+ except:
+ print 'parse fail: ' + portstr
+
+output = ''
+
+def parse_core(var, array_index, array_index_2):
+ global output
+ gdb_cmd = "x/1x " + var + "[%d]" %(array_index)
+ if array_index_2 >= 0:
+ gdb_cmd += "[%d]" %(array_index_2)
+ content = gdb.execute(gdb_cmd, True, to_string=True)
+ content = content.replace(":", " ")
+ content = content.split(" ")[0]
+ content = int(content,16)
+ return content
+
+def parse_array(var, index_num):
+ global output
+ result_array = []
+ for i in range(index_num):
+ result_array.append(parse_core(var, i, -1))
+ return result_array
+
+def parse_array_2dim(var, index_num1, index_num2):
+ global output
+ result_array = []
+ for i in range(index_num1):
+ for j in range(index_num2):
+ result_array.append(parse_core(var, i, j))
+ return result_array
+
+def parse_global_variable(var):
+ global output
+ gdb_cmd = "p/x " + var
+ content = gdb.execute(gdb_cmd, True, to_string=True)
+ content = content.split(" ")
+ if len(content) == 3:
+ return int(content[2],16)
+ else:
+ var_len = len(content) - 2
+ if var_len>=200:
+ output += "Fail with var_len larger than 200\n"
+ return parse_array(var, var_len)
+
+ gdb_cmd = "x/" + str(var_len) + "x " + var
+ content = gdb.execute(gdb_cmd, True, to_string=True)
+ # format GDB x/x command results
+ content = content.replace(":", "")
+ content = content.replace("\n", "\t")
+ content = content.split("\t")
+
+ for i in range(0,len(content),1):
+ output += str(i) + ": " + content[i] + "\n"
+
+ # # remove redundant gdb information
+ del content[-1] # The last one is always empty because the '\t'
+
+ loop_num = var_len/4 + var_len
+
+ if var_len%4 != 0:
+ loop_num -= var_len%4
+ else:
+ loop_num -= 5
+
+
+ del content[0]
+
+ return content
+ return str(len(content))
+
+def print_array(name_str, array_var):
+ global output
+
+ if type(array_var) is int:
+ output += name_str + ": %8X" %(array_var) + "\n"
+
+ elif type(array_var) is list:
+ output += name_str + ": \n"
+ var_len = len(array_var)
+ for i in range(0,var_len,1):
+ output += str(i) + ": %8X" %(array_var[i]) + "\n"
+ output += "\n"
+
+def parse_l2cache_tag_all():
+ l2cahe_line_num = 8*2048
+ parse_loop_num = l2cahe_line_num/200
+ last_parse_num = l2cahe_line_num%200
+
+
+
+def parse_tag(L23TagLo):
+ global output
+
+ tag=((L23TagLo>>0xF)<<0xF)
+ valid=((L23TagLo)&(1<<0x7))>>(0x7)
+ dirty=((L23TagLo)&(1<<0x6))>>(0x6)
+ lock=((L23TagLo)&(1<<0x5))>>(0x5)
+
+ output += " Tag = "+"0x%8x" %(tag)
+ output += ", Valid = "+"0x%1x" %(valid)
+ output += ", Dirty = "+"0x%1x" %(dirty)
+ output += ", Lock = "+"0x%1x \n" %(lock)
+
+
+def check_tag_locked_valid(L23TagLo):
+
+ tag=((L23TagLo>>0xF)<<0xF)
+ valid=((L23TagLo)&(1<<0x7))>>(0x7)
+ dirty=((L23TagLo)&(1<<0x6))>>(0x6)
+ lock=((L23TagLo)&(1<<0x5))>>(0x5)
+ if (valid==1) and (lock == 1):
+ return True
+ else:
+ return False
+
+def parse_range_address(start_addr, length):
+ global output
+ global l2cache_lock_fail_tag
+ index_way = 0x0
+ loop_count_way = 0x8
+
+ index_line = (start_addr>>0x6)&(0x7FF)
+ loop_count_line = (length>>(0x6))+index_line
+
+ while index_line < loop_count_line:
+
+ output += " Index "+"0x%4x" %(index_line) +": \n"
+ while index_way < loop_count_way:
+ L23TagLo = l2cache_lock_fail_tag[index_way*0x800+index_line]
+ output += " Way %d" %(index_way)+":"
+ parse_tag(L23TagLo)
+ index_way += 1
+ index_line += 1
+ index_way = 0
+
+
+def check_range_address_locked_valid(start_addr, length):
+ global output
+ global l2cache_lock_fail_tag
+ index_way = 0x0
+ loop_count_way = 0x8
+ per_address_check_result = False
+ total_result = True
+
+ index_line = (start_addr>>0x6)&(0x7FF)
+ loop_count_line = (length>>(0x6))+index_line
+ loop_index = 0
+
+ while index_line < loop_count_line:
+ checkAddress = start_addr + loop_index*64
+ tagCompare = (checkAddress >> (0x6 + 0xB))
+ while index_way < loop_count_way:
+ L23TagLo = l2cache_lock_fail_tag[index_way*0x800+index_line]
+ if (check_tag_locked_valid(L23TagLo) == True) and ((L23TagLo >> (0x6 + 0xB)) == tagCompare):
+ per_address_check_result = True
+ index_way += 1
+
+ if per_address_check_result == False:
+ output += "checkAddress = %8x : FAIL\n" %(checkAddress)
+ parse_range_address(checkAddress, 64)
+ total_result = False
+ else:
+ output += "checkAddress = %8x : PASS\n" %(checkAddress)
+ index_line += 1
+ index_way = 0
+ loop_index += 1
+ per_address_check_result = False
+ return total_result
+
+# Main Function
+l2cache_lock_fail_tag_magic = parse_global_variable("l2cache_lock_fail_tag_magic")
+if l2cache_lock_fail_tag_magic != 0x10306451:
+ output += "L2cacheTag magic number is wrong, it may be some situations below \n"
+ output += " 1) L2cacheTag not be dumped. (memory dump unfinished)\n"
+ output += " 2) Not exist any locked region, or all regions are unlocked.\n"
+else:
+ l2cache_lock_fail_tag = parse_array("l2cache_lock_fail_tag", 8*2048)
+
+ dl2cm_linker_symbol = parse_array_2dim("dl2cm_linker_symbol", 18, 6)
+
+ dl2cm_lock_label = parse_global_variable("dl2cm_lock_label")
+
+ i=0
+ summarized_result = False
+ for i in range(0,32,1):
+ if ((dl2cm_lock_label>>i) & 0x1) != 1:
+ # output += "bypass\n"
+ continue
+ output += "Checking Dynamic Locked Section #%d \n" %(i)
+ start_addr = dl2cm_linker_symbol[6*i]
+ length = dl2cm_linker_symbol[6*i+1]
+ output += "start_addr=%8X, length=%8x " %(start_addr, length) + "\n"
+ summarized_result = check_range_address_locked_valid(start_addr,length)
+ # check_range_address_unlocked()
+ output += "===== Summarized Result : %s ==========\n" %("PASS" if (summarized_result==True) else "FAIL")
+
+
+
+tcf = client.TCFThread(host, int(port))
+tcf.start()
+tcf.send(['E','UI','text','L2cacheTag','Text',output])
+tcf.close()
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/L2CacheTag_Parser/TCF.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/L2CacheTag_Parser/TCF.py
new file mode 100755
index 0000000..1c32411
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/L2CacheTag_Parser/TCF.py
@@ -0,0 +1,170 @@
+import getopt
+from multiprocessing import Queue
+import socket
+import sys
+from threading import Thread
+
+SPLITTER = '\x00'
+EOL = '\x03\x01'
+HEADER = '\x03\x03'
+LEN_EOL = len((SPLITTER + EOL))
+
+class Event():
+ def __init__(self, args):
+ b = bytearray(args).split(SPLITTER.encode('utf_8'))
+ self.servicename = b[1]
+ self.eventname = b[2]
+ self.data = b[3]
+ self.elements = b[3:]
+
+ def getServiceName(self):
+ return self.servicename.decode('utf_8')
+
+ def getEventName(self):
+ return self.eventname.decode('utf_8')
+
+ def getData(self):
+ return self.data.decode('utf_8')
+
+ def getElement(self, index):
+ if len(self.elements) == 0:
+ return ''
+ return self.elements[index]
+
+ def toString(self):
+ datastr = ''
+ for b in self.elements:
+ if not b == EOL:
+ datastr = datastr + ' ' + b.decode('utf_8')
+ return 'Event ' + self.getServiceName() + ' ' + self.getEventName() + ' ' + datastr
+
+class Result():
+ def __init__(self, args):
+ b = bytearray(args).split(SPLITTER.encode('utf_8'))
+ self.type = b[0]
+ self.token = b[1]
+ self.data = b[2]
+ self.elements = b[2:]
+
+ def getType(self):
+ return self.type.decode('utf_8')
+
+ def getToken(self):
+ return self.token.decode('utf_8')
+
+ def getData(self):
+ return self.data.decode('utf_8')
+
+ def getElement(self, index):
+ if len(self.elements) == 0:
+ return ''
+ return self.elements[index]
+
+ def toString(self):
+ datastr = ''
+ for b in self.elements:
+ if not b == EOL:
+ datastr = datastr + ' ' + b.decode('utf_8')
+ return self.getType() + ' ' + self.getToken() + ' ' + datastr
+
+class TCFThread(Thread):
+ def __init__(self, host='localhost', port='1534'):
+ Thread.__init__(self)
+ try:
+ opts, args = getopt.getopt(sys.argv[1:],"h:p:",["host=","port="])
+ for opt, arg in opts:
+ if opt in ("-h", "--host"):
+ host = arg
+ elif opt in ("-p", "--port"):
+ port = int(arg)
+ except getopt.GetoptError:
+ pass
+ self.tcf_terminator = (SPLITTER + EOL).encode('utf_8')
+ self.tcf = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+ self.tcf.connect((host, int(port)))
+ self.queue = Queue()
+ self.send(['E','Locator','Hello','["ZeroCopy"]'])
+
+ def run(self):
+ remain = None
+ while 1:
+ try:
+ data = self.tcf.recv(1024)
+ if remain == None:
+ remain = data
+ else:
+ remain = remain + data
+
+ if bytearray(data).endswith(self.tcf_terminator):
+ res, rem = getData(remain)
+ if bytearray(res).startswith('E'.encode('utf_8')):
+ self.queue.put(Event(res))
+ elif bytearray(res).startswith('R'.encode('utf_8')):
+ self.queue.put(Result(res))
+ remain = rem
+ except:
+ break
+ self.tcf.close()
+
+ def get(self):
+ if not self.queue.empty():
+ return self.queue.get()
+ else:
+ return None
+
+ def send(self, args):
+ for arg in args:
+ self.tcf.send(str(arg + SPLITTER).encode('utf_8'))
+ self.tcf.send(EOL.encode('utf_8'))
+
+ def rawsend(self, rawarg):
+ self.tcf.send(rawarg)
+
+ def close(self):
+ self.tcf.shutdown(1)
+ self.tcf.close()
+
+def getData(arg):
+ data = bytearray(arg)
+ result = None
+ remain = None
+ if data.startswith(HEADER.encode('utf_8')):
+ ind = data.index(HEADER.encode('utf_8'))+2
+ leng, cnt = getDataLength(data, ind, 0)
+ ind = ind + cnt + 1
+ result = data[ind:ind+leng-1]
+ remain = data[ind+leng-1:]
+ else:
+ ind = data.index((SPLITTER + EOL).encode('utf_8'))
+ if not ind == -1:
+ result = data[:ind]
+ remain = data[ind:]
+ else:
+ result = None
+ remain = data
+
+ if not remain == None and bytearray(remain).startswith((SPLITTER + EOL).encode('utf_8')):
+ remain = remain[LEN_EOL:]
+
+# print('result: \'' + str(result) + '\'')
+# print('remain: \'' + str(remain) + '\'')
+# sys.stdout.flush()
+ return result, remain
+
+def getDataLength(_rec, ind, count):
+ rec_bytes = bytearray(_rec);
+ leng = rec_bytes[ind]
+ mulp = 0
+ if count == 0:
+ mulp = 1
+ else:
+ mulp = 128 * count
+
+ if leng & 0x80 == 0:
+ return leng * mulp, count
+ else:
+ num, cnt = getDataLength(rec_bytes, ind + 1, count + 1)
+ return ((leng & 0x7f) * mulp) + num, cnt
+
+def doEcaspe(arg):
+ return str(arg).replace('\\', '\\\\').replace('\"', '\\\"')
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/L2CacheTag_Parser/gdbsrc.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/L2CacheTag_Parser/gdbsrc.act
new file mode 100755
index 0000000..1c0236d
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/L2CacheTag_Parser/gdbsrc.act
@@ -0,0 +1,7 @@
+<?xml version="1.0"?>
+<!DOCTYPE Customize SYSTEM "Customize.dtd">
+<Customize>
+ <Action name="gdb source" icon="">
+ <GDBSource>print.py</GDBSource>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/L2CacheTag_Parser/kill.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/L2CacheTag_Parser/kill.act
new file mode 100755
index 0000000..bf4ef65
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/L2CacheTag_Parser/kill.act
@@ -0,0 +1,7 @@
+<?xml version="1.0"?>
+<!DOCTYPE Customize SYSTEM "Customize.dtd">
+<Customize>
+ <Toolbar name="Kill" icon="">
+ <GDB>kill</GDB>
+ </Toolbar>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/L2CacheTag_Parser/print.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/L2CacheTag_Parser/print.py
new file mode 100755
index 0000000..06572ab
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/L2CacheTag_Parser/print.py
@@ -0,0 +1 @@
+print 1+2
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/MPU_Parser/Customize.dtd b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/MPU_Parser/Customize.dtd
new file mode 100644
index 0000000..977cb81
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/MPU_Parser/Customize.dtd
@@ -0,0 +1,17 @@
+<!ELEMENT Customize (Toolbar*,MainMenu*)>
+<!ELEMENT Toolbar (GDB*,SHELL*,PYSWTBOT*,CMM*,Menu*,MenuItem*)>
+<!ELEMENT MainMenu (Menu*,MenuItem*)>
+<!ELEMENT Menu (Menu*,MenuItem*)>
+<!ELEMENT MenuItem (GDB*,SHELL*,PYSWTBOT*,CMM*)>
+<!ATTLIST Toolbar name CDATA #REQUIRED>
+<!ATTLIST Toolbar icon CDATA #REQUIRED>
+<!ATTLIST MainMenu name CDATA #REQUIRED>
+<!ATTLIST MainMenu icon CDATA #REQUIRED>
+<!ATTLIST Menu name CDATA #REQUIRED>
+<!ATTLIST Menu icon CDATA #REQUIRED>
+<!ATTLIST MenuItem name CDATA #REQUIRED>
+<!ATTLIST MenuItem icon CDATA #REQUIRED>
+<!ELEMENT GDB (#PCDATA)>
+<!ELEMENT SHELL (#PCDATA)>
+<!ELEMENT PYSWTBOT (#PCDATA)>
+<!ELEMENT CMM (#PCDATA)>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/MPU_Parser/TCF.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/MPU_Parser/TCF.py
new file mode 100755
index 0000000..1c32411
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/MPU_Parser/TCF.py
@@ -0,0 +1,170 @@
+import getopt
+from multiprocessing import Queue
+import socket
+import sys
+from threading import Thread
+
+SPLITTER = '\x00'
+EOL = '\x03\x01'
+HEADER = '\x03\x03'
+LEN_EOL = len((SPLITTER + EOL))
+
+class Event():
+ def __init__(self, args):
+ b = bytearray(args).split(SPLITTER.encode('utf_8'))
+ self.servicename = b[1]
+ self.eventname = b[2]
+ self.data = b[3]
+ self.elements = b[3:]
+
+ def getServiceName(self):
+ return self.servicename.decode('utf_8')
+
+ def getEventName(self):
+ return self.eventname.decode('utf_8')
+
+ def getData(self):
+ return self.data.decode('utf_8')
+
+ def getElement(self, index):
+ if len(self.elements) == 0:
+ return ''
+ return self.elements[index]
+
+ def toString(self):
+ datastr = ''
+ for b in self.elements:
+ if not b == EOL:
+ datastr = datastr + ' ' + b.decode('utf_8')
+ return 'Event ' + self.getServiceName() + ' ' + self.getEventName() + ' ' + datastr
+
+class Result():
+ def __init__(self, args):
+ b = bytearray(args).split(SPLITTER.encode('utf_8'))
+ self.type = b[0]
+ self.token = b[1]
+ self.data = b[2]
+ self.elements = b[2:]
+
+ def getType(self):
+ return self.type.decode('utf_8')
+
+ def getToken(self):
+ return self.token.decode('utf_8')
+
+ def getData(self):
+ return self.data.decode('utf_8')
+
+ def getElement(self, index):
+ if len(self.elements) == 0:
+ return ''
+ return self.elements[index]
+
+ def toString(self):
+ datastr = ''
+ for b in self.elements:
+ if not b == EOL:
+ datastr = datastr + ' ' + b.decode('utf_8')
+ return self.getType() + ' ' + self.getToken() + ' ' + datastr
+
+class TCFThread(Thread):
+ def __init__(self, host='localhost', port='1534'):
+ Thread.__init__(self)
+ try:
+ opts, args = getopt.getopt(sys.argv[1:],"h:p:",["host=","port="])
+ for opt, arg in opts:
+ if opt in ("-h", "--host"):
+ host = arg
+ elif opt in ("-p", "--port"):
+ port = int(arg)
+ except getopt.GetoptError:
+ pass
+ self.tcf_terminator = (SPLITTER + EOL).encode('utf_8')
+ self.tcf = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+ self.tcf.connect((host, int(port)))
+ self.queue = Queue()
+ self.send(['E','Locator','Hello','["ZeroCopy"]'])
+
+ def run(self):
+ remain = None
+ while 1:
+ try:
+ data = self.tcf.recv(1024)
+ if remain == None:
+ remain = data
+ else:
+ remain = remain + data
+
+ if bytearray(data).endswith(self.tcf_terminator):
+ res, rem = getData(remain)
+ if bytearray(res).startswith('E'.encode('utf_8')):
+ self.queue.put(Event(res))
+ elif bytearray(res).startswith('R'.encode('utf_8')):
+ self.queue.put(Result(res))
+ remain = rem
+ except:
+ break
+ self.tcf.close()
+
+ def get(self):
+ if not self.queue.empty():
+ return self.queue.get()
+ else:
+ return None
+
+ def send(self, args):
+ for arg in args:
+ self.tcf.send(str(arg + SPLITTER).encode('utf_8'))
+ self.tcf.send(EOL.encode('utf_8'))
+
+ def rawsend(self, rawarg):
+ self.tcf.send(rawarg)
+
+ def close(self):
+ self.tcf.shutdown(1)
+ self.tcf.close()
+
+def getData(arg):
+ data = bytearray(arg)
+ result = None
+ remain = None
+ if data.startswith(HEADER.encode('utf_8')):
+ ind = data.index(HEADER.encode('utf_8'))+2
+ leng, cnt = getDataLength(data, ind, 0)
+ ind = ind + cnt + 1
+ result = data[ind:ind+leng-1]
+ remain = data[ind+leng-1:]
+ else:
+ ind = data.index((SPLITTER + EOL).encode('utf_8'))
+ if not ind == -1:
+ result = data[:ind]
+ remain = data[ind:]
+ else:
+ result = None
+ remain = data
+
+ if not remain == None and bytearray(remain).startswith((SPLITTER + EOL).encode('utf_8')):
+ remain = remain[LEN_EOL:]
+
+# print('result: \'' + str(result) + '\'')
+# print('remain: \'' + str(remain) + '\'')
+# sys.stdout.flush()
+ return result, remain
+
+def getDataLength(_rec, ind, count):
+ rec_bytes = bytearray(_rec);
+ leng = rec_bytes[ind]
+ mulp = 0
+ if count == 0:
+ mulp = 1
+ else:
+ mulp = 128 * count
+
+ if leng & 0x80 == 0:
+ return leng * mulp, count
+ else:
+ num, cnt = getDataLength(rec_bytes, ind + 1, count + 1)
+ return ((leng & 0x7f) * mulp) + num, cnt
+
+def doEcaspe(arg):
+ return str(arg).replace('\\', '\\\\').replace('\"', '\\\"')
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/MPU_Parser/gdbsrc.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/MPU_Parser/gdbsrc.act
new file mode 100755
index 0000000..1c0236d
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/MPU_Parser/gdbsrc.act
@@ -0,0 +1,7 @@
+<?xml version="1.0"?>
+<!DOCTYPE Customize SYSTEM "Customize.dtd">
+<Customize>
+ <Action name="gdb source" icon="">
+ <GDBSource>print.py</GDBSource>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/MPU_Parser/kill.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/MPU_Parser/kill.act
new file mode 100755
index 0000000..bf4ef65
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/MPU_Parser/kill.act
@@ -0,0 +1,7 @@
+<?xml version="1.0"?>
+<!DOCTYPE Customize SYSTEM "Customize.dtd">
+<Customize>
+ <Toolbar name="Kill" icon="">
+ <GDB>kill</GDB>
+ </Toolbar>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/MPU_Parser/mpu.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/MPU_Parser/mpu.act
new file mode 100755
index 0000000..0183c94
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/MPU_Parser/mpu.act
@@ -0,0 +1,6 @@
+<?xml version="1.0"?>
+<Customize>
+ <Action name="MPU">
+ <GDBSource>mpu.py</GDBSource>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/MPU_Parser/mpu.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/MPU_Parser/mpu.py
new file mode 100755
index 0000000..d3ced9f
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/MPU_Parser/mpu.py
@@ -0,0 +1,228 @@
+import sys
+import time
+import os
+sys.path.append(os.path.dirname(os.path.realpath(__file__)))
+import gdb
+import struct
+from operator import itemgetter, attrgetter
+from TCF import Event, Result
+import TCF as client
+
+host = 'localhost'
+port = 1534
+
+result = gdb.execute('show env tcfport', to_string=True)
+if not result == None:
+ portstr = str(result)
+ try:
+ port = int(portstr[portstr.index('=')+2:])
+ except:
+ print 'parse fail: ' + portstr
+
+output = ''
+
+bank_size = 0x10000000
+bank_0 = 0x0
+bank_1 = 0x10000000
+bank_2 = 0x20000000
+bank_3 = 0x30000000
+bank_4 = 0x40000000
+bank_5 = 0x50000000
+bank_6 = 0x60000000
+bank_7 = 0x70000000
+bank_8 = 0x80000000
+bank_9 = 0x90000000
+bank_A = 0xA0000000
+bank_B = 0xB0000000
+bank_C = 0xC0000000
+bank_D = 0xD0000000
+bank_E = 0xE0000000
+bank_F = 0xF0000000
+
+# En[15] Size[14:10] Count[9:6] RI[5] WI[4] XI[3] CCA[2:0]
+mpu_FDC_offset = 0xc0
+mpu_ACSR_offset = 0x0
+mpu_Config_offset = 0x8
+mpu_SegmentControl_0_offset = 0x10
+mpu_SegmentControl_1_offset = 0x14
+mpu_SegmentControl_2_offset = 0x18
+mpu_SegmentControl_3_offset = 0x1c
+mpu_settings = []
+mpu_map = []
+
+class setting:
+ def __init__(self, idx, base_addr, end_addr, reg, En, Size, Count, RI, WI, XI, CCA, Protect):
+ self.idx = idx
+ self.base_addr = base_addr
+ self.end_addr = end_addr
+ self.reg = reg
+ self.En = En
+ self.Size = Size
+ self.Count = Count
+ self.RI = RI
+ self.WI = WI
+ self.XI = XI
+ self.CCA = CCA
+ self.Protect = Protect
+ def __repr__(self):
+ return repr((self.idx, self.base_addr, self.end_addr, self.reg, self.En, self.Size, self.Count, self.RI, self.WI, self.XI, self.CCA, self.Protect))
+
+class result:
+ def __init__(self, base_addr, end_addr, RI, WI, XI, CCA, Protect):
+ self.base_addr = base_addr
+ self.end_addr = end_addr
+ self.RI = RI
+ self.WI = WI
+ self.XI = XI
+ self.CCA = CCA
+ self.Protect = Protect
+ def __repr__(self):
+ return repr((self.base_addr, self.end_addr, self.RI, self.WI, self.XI, self.CCA, self.Protect))
+
+def CCA_cfg(cca):
+ return {
+ 2 : 'UC',
+ 3 : 'WB',
+ 4 : 'CWBE',
+ 5 : 'CWB',
+ 7 : 'UCA',
+ }.get(cca, ' ')
+
+def RI_cfg(ri):
+ return {
+ 0 : '--',
+ 1 : 'RI',
+ }.get(ri, '-')
+
+def WI_cfg(wi):
+ return {
+ 0 : '--',
+ 1 : 'WI',
+ }.get(wi, '-')
+
+def XI_cfg(xi):
+ return {
+ 0 : '--',
+ 1 : 'XI',
+ }.get(xi, '-')
+
+gdb_cmd = "p/x $cdmmbase"
+cdmm_content = gdb.execute(gdb_cmd, True, to_string=True)
+cdmm_content = cdmm_content.split(" ")
+cdmmbase_str = cdmm_content[2]
+cdmmbase = int(cdmmbase_str, 16) + mpu_FDC_offset
+cdmmbase_str = "0x1fc100c0"
+gdb_cmd = "x/72x " + cdmmbase_str
+#gdb_cmd = "x/72x " + cdmmbase
+memory_content = gdb.execute(gdb_cmd, True, to_string=True)
+
+# format GDB x/x command results
+memory_content = memory_content.replace(":", "")
+memory_content = memory_content.replace("\n", "\t")
+memory_content = memory_content.split("\t")
+
+# remove redundant gdb information
+for i in range(90, 0, -5):
+ del memory_content[i]
+
+del memory_content[0]
+
+# parsing MPU_ACSR register (offset 0x0)
+mpu_ACSR = int(memory_content[mpu_ACSR_offset/4], 16)
+
+# parsing MPU_Config register (offset 0x8)
+# En[31], Excr[19], ExcW[18], ExcX[17], Exc_Reg_Match[16], Exc_Reg_Num[12:8], Num_Regions[4:0]
+mpu_Config = int(memory_content[mpu_Config_offset/4], 16)
+mpu_Config_En = (mpu_Config&0x80000000)>>31
+mpu_Config_ExcR = (mpu_Config&0x80000)>>19
+mpu_Config_ExcW = (mpu_Config&0x40000)>>18
+mpu_Config_ExcX = (mpu_Config&0x20000)>>17
+mpu_Config_Exc_Reg_Match = (mpu_Config&0x10000)>>16
+mpu_Config_Exc_Reg_Num = (mpu_Config&0x1f00)>>8
+mpu_Config_Num_Regions = (mpu_Config&0x1f) + 1 # count = ctrl + 1
+# print "MPU_Config", mpu_Config_En, mpu_Config_ExcR, mpu_Config_ExcW, mpu_Config_ExcX, mpu_Config_Exc_Reg_Match, mpu_Config_Exc_Reg_Num,mpu_Config_Num_Regions
+
+# MPU Segment Control Registers (offset 0x10 0x14 0x18 0x1c)
+# RI[29,21,13,5] WI[28,20,12,4] XI[27,19,11,3] CCA[26:24, 18:16, 10:8, 2:0]
+mpu_SegmentControl_0 = int(memory_content[mpu_SegmentControl_0_offset/4], 16)
+mpu_settings.append(setting(0, bank_0, bank_0 + bank_size * 1 - 1, (mpu_SegmentControl_0&0xFF), 1, bank_size, 1, (mpu_SegmentControl_0&0x20)>>5, (mpu_SegmentControl_0&0x10)>>4, (mpu_SegmentControl_0&0x8)>>3, (mpu_SegmentControl_0&0x7), 'SC'))
+mpu_settings.append(setting(1, bank_1, bank_1 + bank_size * 1 - 1, (mpu_SegmentControl_0&0xFF00)>>8, 1, bank_size, 1, (mpu_SegmentControl_0&0x2000)>>13, (mpu_SegmentControl_0&0x1000)>>12, (mpu_SegmentControl_0&0x800)>>11, (mpu_SegmentControl_0&0x700)>>8, 'SC'))
+mpu_settings.append(setting(2, bank_2, bank_2 + bank_size * 1 - 1, (mpu_SegmentControl_0&0xFF0000)>>16, 1, bank_size, 1, (mpu_SegmentControl_0&0x200000)>>21, (mpu_SegmentControl_0&0x100000)>>20, (mpu_SegmentControl_0&0x80000)>>19, (mpu_SegmentControl_0&0x70000)>>16, 'SC'))
+mpu_settings.append(setting(3, bank_3, bank_3 + bank_size * 1 - 1, (mpu_SegmentControl_0&0xFF000000)>>24, 1, bank_size, 1, (mpu_SegmentControl_0&0x20000000)>>29, (mpu_SegmentControl_0&0x10000000)>>28, (mpu_SegmentControl_0&0x8000000)>>27, (mpu_SegmentControl_0&0x7000000)>>24, 'SC'))
+
+mpu_SegmentControl_1 = int(memory_content[mpu_SegmentControl_1_offset/4], 16)
+mpu_settings.append(setting(4, bank_4, bank_4 + bank_size * 1 - 1, (mpu_SegmentControl_1&0xFF), 1, bank_size, 1, (mpu_SegmentControl_1&0x20)>>5, (mpu_SegmentControl_1&0x10)>>4, (mpu_SegmentControl_1&0x8)>>3, (mpu_SegmentControl_1&0x7), 'SC'))
+mpu_settings.append(setting(5, bank_5, bank_5 + bank_size * 1 - 1, (mpu_SegmentControl_1&0xFF00)>>8, 1, bank_size, 1, (mpu_SegmentControl_1&0x2000)>>13, (mpu_SegmentControl_1&0x1000)>>12, (mpu_SegmentControl_1&0x800)>>11, (mpu_SegmentControl_1&0x700)>>8, 'SC'))
+mpu_settings.append(setting(6, bank_6, bank_6 + bank_size * 1 - 1, (mpu_SegmentControl_1&0xFF0000)>>16, 1, bank_size, 1, (mpu_SegmentControl_1&0x200000)>>21, (mpu_SegmentControl_1&0x100000)>>20, (mpu_SegmentControl_1&0x80000)>>19, (mpu_SegmentControl_1&0x70000)>>16, 'SC'))
+mpu_settings.append(setting(7, bank_7, bank_7 + bank_size * 1 - 1, (mpu_SegmentControl_1&0xFF000000)>>24, 1, bank_size, 1, (mpu_SegmentControl_1&0x20000000)>>29, (mpu_SegmentControl_1&0x10000000)>>28, (mpu_SegmentControl_1&0x8000000)>>27, (mpu_SegmentControl_1&0x7000000)>>24, 'SC'))
+
+mpu_SegmentControl_2 = int(memory_content[mpu_SegmentControl_2_offset/4], 16)
+mpu_settings.append(setting(8, bank_8, bank_8 + bank_size * 1 - 1, (mpu_SegmentControl_2&0xFF), 1, bank_size, 1, (mpu_SegmentControl_2&0x20)>>5, (mpu_SegmentControl_2&0x10)>>4, (mpu_SegmentControl_2&0x8)>>3, (mpu_SegmentControl_2&0x7), 'SC'))
+mpu_settings.append(setting(9, bank_9, bank_9 + bank_size * 1 - 1, (mpu_SegmentControl_2&0xFF00)>>8, 1, bank_size, 1, (mpu_SegmentControl_2&0x2000)>>13, (mpu_SegmentControl_2&0x1000)>>12, (mpu_SegmentControl_2&0x800)>>11, (mpu_SegmentControl_2&0x700)>>8, 'SC'))
+mpu_settings.append(setting(10, bank_A, bank_A + bank_size * 1 - 1, (mpu_SegmentControl_2&0xFF0000)>>16, 1, bank_size, 1, (mpu_SegmentControl_2&0x200000)>>21, (mpu_SegmentControl_2&0x100000)>>20, (mpu_SegmentControl_2&0x80000)>>19, (mpu_SegmentControl_2&0x70000)>>16, 'SC'))
+mpu_settings.append(setting(11, bank_B, bank_B + bank_size * 1 - 1, (mpu_SegmentControl_2&0xFF000000)>>24, 1, bank_size, 1, (mpu_SegmentControl_2&0x20000000)>>29, (mpu_SegmentControl_2&0x10000000)>>28, (mpu_SegmentControl_2&0x8000000)>>27, (mpu_SegmentControl_2&0x7000000)>>24, 'SC'))
+
+mpu_SegmentControl_3 = int(memory_content[mpu_SegmentControl_3_offset/4], 16)
+mpu_settings.append(setting(12, bank_C, bank_C + bank_size * 1 - 1, (mpu_SegmentControl_3&0xFF), 1, bank_size, 1, (mpu_SegmentControl_3&0x20)>>5, (mpu_SegmentControl_3&0x10)>>4, (mpu_SegmentControl_3&0x8)>>3, (mpu_SegmentControl_3&0x7), 'SC'))
+mpu_settings.append(setting(13, bank_D, bank_D + bank_size * 1 - 1, (mpu_SegmentControl_3&0xFF00)>>8, 1, bank_size, 1, (mpu_SegmentControl_3&0x2000)>>13, (mpu_SegmentControl_3&0x1000)>>12, (mpu_SegmentControl_3&0x800)>>11, (mpu_SegmentControl_3&0x700)>>8, 'SC'))
+mpu_settings.append(setting(14, bank_E, bank_E + bank_size * 1 - 1, (mpu_SegmentControl_3&0xFF0000)>>16, 1, bank_size, 1, (mpu_SegmentControl_3&0x200000)>>21, (mpu_SegmentControl_3&0x100000)>>20, (mpu_SegmentControl_3&0x80000)>>19, (mpu_SegmentControl_3&0x70000)>>16, 'SC'))
+mpu_settings.append(setting(15, bank_F, bank_F + bank_size * 1 - 1, (mpu_SegmentControl_3&0xFF000000)>>24, 1, bank_size, 1, (mpu_SegmentControl_3&0x20000000)>>29, (mpu_SegmentControl_3&0x10000000)>>28, (mpu_SegmentControl_3&0x8000000)>>27, (mpu_SegmentControl_3&0x7000000)>>24, 'SC'))
+
+for i in range(0, len(mpu_settings), 1):
+ mpu_map.append(result(mpu_settings[i].base_addr, mpu_settings[i].end_addr, mpu_settings[i].RI, mpu_settings[i].WI, mpu_settings[i].XI, mpu_settings[i].CCA, mpu_settings[i].Protect))
+
+# parse MPU Region Base Address Register and Region Control Register
+# Base Address Register
+# Base_Addr [31:5]
+# Region Control Register
+# En[15] Size[14:10] Count[9:6] RI[5] WI[4] XI[3] CCA[2:0]
+for i in range(0, mpu_Config_Num_Regions, 1):
+ addr = int(memory_content[i*2+8], 16)
+ ctrl = int(memory_content[i*2+9], 16)
+ mpu_ctrl_Size = pow(2, ((ctrl&0x7C00)>>10))
+ mpu_ctrl_Count = ((ctrl&0x3C0)>>6) + 1
+ mpu_ctrl_RI = (ctrl&0x20)>>5
+ mpu_ctrl_WI = (ctrl&0x10)>>4
+ mpu_ctrl_XI = (ctrl&0x8)>>3
+ mpu_ctrl_CCA = ctrl&0x7
+ end_addr = addr + mpu_ctrl_Size * mpu_ctrl_Count - 1
+ if ((ctrl&0x8000)>>15) == 1:
+ mpu_settings.append(setting(16+i, addr, addr + mpu_ctrl_Size * mpu_ctrl_Count - 1, ctrl, (ctrl&0x8000)>>15, mpu_ctrl_Size, mpu_ctrl_Count, mpu_ctrl_RI, mpu_ctrl_WI, mpu_ctrl_XI, mpu_ctrl_CCA, 'RC'))
+ output += "Region %2d, base=0x%8x, end=0x%8x (size=0x%8x, count=0x%x), RI=%d, WI=%d, XI=%d, CCA=%d\n" %(i, addr, addr + mpu_ctrl_Size * mpu_ctrl_Count, mpu_ctrl_Size, mpu_ctrl_Count, mpu_ctrl_RI, mpu_ctrl_WI, mpu_ctrl_XI, mpu_ctrl_CCA)
+ for j in range(0, len(mpu_map), 1):
+ # shrink head part
+ if (mpu_map[j].base_addr <= addr) and (mpu_map[j].end_addr <= end_addr) and (mpu_map[j].end_addr >= addr) :
+ mpu_map[j].end_addr = addr - 1
+ # remove fully covered sub part
+ elif (mpu_map[j].base_addr >= addr) and (mpu_map[j].end_addr <= end_addr) :
+ mpu_map[j].base_addr = -1
+ mpu_map[j].end_addr = -1
+ # shrink tail part
+ elif (mpu_map[j].base_addr <= end_addr) and (mpu_map[j].end_addr >= end_addr) and (mpu_map[j].base_addr >= addr):
+ mpu_map[j].base_addr = end_addr + 1
+ # fully covered by previous region
+ elif (mpu_map[j].base_addr < addr) and (mpu_map[j].end_addr > end_addr) :
+ mpu_map.append(result(end_addr + 1, mpu_map[j].end_addr, mpu_map[j].RI, mpu_map[j].WI, mpu_map[j].XI, mpu_map[j].CCA, mpu_map[j].Protect))
+ mpu_map[j].end_addr = addr - 1
+ break
+ mpu_map.append(result(addr, end_addr, mpu_ctrl_RI, mpu_ctrl_WI, mpu_ctrl_XI, mpu_ctrl_CCA, 'RC'))
+
+output += '\n'
+
+mpu_map = sorted(mpu_map, key=attrgetter('base_addr'))
+
+# remove empty or illegal region, merge range with same attributes
+for i in range(len(mpu_map)-1, -1, -1):
+ if (mpu_map[i].end_addr == -1) or mpu_map[i].base_addr >= mpu_map[i].end_addr:
+ mpu_map.pop(i)
+ if (i>=1) and (mpu_map[i].RI == mpu_map[i-1].RI) and (mpu_map[i].WI == mpu_map[i-1].WI) and (mpu_map[i].XI == mpu_map[i-1].XI) and (mpu_map[i].CCA == mpu_map[i-1].CCA) and (mpu_map[i].Protect == mpu_map[i-1].Protect):
+ mpu_map[i-1].end_addr = mpu_map[i].end_addr
+ mpu_map.pop(i)
+
+for i in range(0, len(mpu_map), 1):
+ output += "%8x ~ %8x %s %s %s %s \t %s" %(mpu_map[i].base_addr, mpu_map[i].end_addr, RI_cfg(mpu_map[i].RI), WI_cfg(mpu_map[i].WI), XI_cfg(mpu_map[i].XI), CCA_cfg(mpu_map[i].CCA), mpu_map[i].Protect) + '\n'
+
+tcf = client.TCFThread(host, int(port))
+tcf.start()
+tcf.send(['E','UI','text','MPU','Text',output])
+tcf.close()
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/MPU_Parser/print.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/MPU_Parser/print.py
new file mode 100755
index 0000000..06572ab
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/MPU_Parser/print.py
@@ -0,0 +1 @@
+print 1+2
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/config/L1Bypass.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/config/L1Bypass.act
new file mode 100755
index 0000000..a3c4b52
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/config/L1Bypass.act
@@ -0,0 +1,6 @@
+<?xml version="1.0"?>
+<Customize>
+ <Action name="L1AssertBypass" icon="">
+ <GDB>p/x L1_ASSERT_BYPASS=3</GDB>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/config/MT6779_AllIn1_LoadSymbol.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/config/MT6779_AllIn1_LoadSymbol.launch
new file mode 100755
index 0000000..2b2470c
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/config/MT6779_AllIn1_LoadSymbol.launch
@@ -0,0 +1,62 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="../../../bin/MT6779_SP_PCB01_MT6779_S00.elf"/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.cache.FilePath" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.cache.gdbIndexElf" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.LocalTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.debuggerIpAddress" value="localhost"/>
+<intAttribute key="com.mediatek.ide.util.debuggerPortNumber" value="3333"/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<intAttribute key="com.mediatek.ide.util.gdbPortNumber" value="3333"/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value="mem 0x00000000 0x4fffffff rw mem 0x60000000 0xffffffff rw "/>
+<stringAttribute key="com.mediatek.ide.util.ipAddress" value="localhost"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value="hb general_ex_handler hb INT_TEMP_general_ex_vector hb CTI_Triggered_ex_handler"/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.substitute_path_no_translate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="MT6295-Lafite-Chip"/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.args" value="-f board/mips/mt6295_mips_chip_lafite.cfg -c "adapter_khz 10000""/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.cmds" value=""/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.widget.args" value="{"Clock_10000":"10000"}"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="attach"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
+<booleanAttribute key="org.eclipse.debug.core.capture_output" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_OUTPUT_ON" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/config/MT6779_AllIn1_LoadSymbol_BigRam.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/config/MT6779_AllIn1_LoadSymbol_BigRam.launch
new file mode 100755
index 0000000..32dc1dc
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/config/MT6779_AllIn1_LoadSymbol_BigRam.launch
@@ -0,0 +1,62 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="../../../bin/MT6779_SP_PCB01_MT6779_S00.elf"/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.cache.FilePath" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.cache.gdbIndexElf" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.LocalTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.debuggerIpAddress" value="localhost"/>
+<intAttribute key="com.mediatek.ide.util.debuggerPortNumber" value="3333"/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<intAttribute key="com.mediatek.ide.util.gdbPortNumber" value="3333"/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=" "/>
+<stringAttribute key="com.mediatek.ide.util.ipAddress" value="localhost"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.substitute_path_no_translate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="MT6295-Lafite-Chip"/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.args" value="-f board/mips/mt6295_mips_chip_lafite.cfg -c "adapter_khz 10000""/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.cmds" value=""/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.widget.args" value="{"Clock_10000":"10000"}"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="attach"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
+<booleanAttribute key="org.eclipse.debug.core.capture_output" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_OUTPUT_ON" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/config/easyLoader/load_dsp.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/config/easyLoader/load_dsp.py
new file mode 100755
index 0000000..86e47fa
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/coretracer/config/easyLoader/load_dsp.py
@@ -0,0 +1,106 @@
+#from imgtec import codescape
+import sys
+import time
+import os
+import gdb
+import binascii
+import Tkinter, tkFileDialog
+
+app = None
+dsp_header = 0x0
+dsp_magic = "4d4d4d01"
+
+# load dsp bin file
+def load_dsp_bin(dsp_path):
+ global dsp_header
+ time_str = time.time()
+ print "=== Start load dsp bin ==="
+ print "Dsp bin path: " + dsp_path
+ if(os.path.exists(dsp_path) == False):
+ print "DSP bin doesn't exist: %s" %(dsp_path)
+ print "[Error] Load DSP bin failed"
+ return
+ else:
+ with open(dsp_path, "rb") as dsp_bin:
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print "No header detected, continue"
+ else:
+ dsp_header = 0x200
+ dsp_bin.seek(dsp_header, os.SEEK_SET)
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print "Header detected, skip first 512B"
+ else:
+ print "DSP header detected at neither 0x0 nor 0x200"
+ print "Please check the bin is legal!"
+ print "[Error] Load DSP bin failed"
+ return
+ gdb_cmd='thread 1'
+ gdb.execute(gdb_cmd)
+ ## a) need parsing: 0x13a0000 <dsp_bin_ro>
+ ##symbol_name='&dsp_bin_ro'
+ ##dsp_addr = gdb.parse_and_eval(symbol_name)
+ ## b) need parsing: $3 = 0x13a0000
+ ##gdb_cmd='p/x &dsp_bin_ro'
+ ##dsp_addr = gdb.execute(gdb_cmd, False, True)
+ symbol_name='dsp_bin_ro'
+ dsp_addr = gdb.parse_and_eval(symbol_name)
+ dsp_addr = str(dsp_addr.address).split(" ")
+ dsp_addr = int(dsp_addr[0], 16) - dsp_header
+ print hex(dsp_addr)
+ gdb_cmd = 'monitor mips32 fastchannel 0 1'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'set $cdmmbase=0x1fc1407'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'set *0x1fc100d4=0x02030202'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = " ".join(['restore', dsp_path, 'binary', hex(dsp_addr), hex(dsp_header)])
+ print gdb_cmd
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'set *0x1fc100d4=0x02020202'
+ gdb.execute(gdb_cmd)
+ time_end = time.time()
+ print("loading dsp is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+
+class gui_tk(Tkinter.Tk):
+ def __init__(self, parent):
+ Tkinter.Tk.__init__(self, parent)
+ elf_path = ""
+ dsp_path = ""
+ dsp_addr = ""
+ self.file_opt = options = {}
+ options['title'] = 'Choose a file'
+ self.parent = parent
+ self.initialize()
+
+ def initialize(self):
+ self.grid()
+
+ dsp_button = Tkinter.Button(self, text=u"Load DSP bin =>", command=self.dsp_OnButtonClick)
+ dsp_button.grid(column=0, row=4, sticky='W')
+
+ def dsp_OnButtonClick(self):
+ dsp_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(dsp_path) > 0:
+ print "You chose %s" % dsp_path
+ load_dsp_bin(dsp_path)
+ self.quit()
+
+ def quit(self):
+ global app
+ print "=== Close Easy Loader ==="
+ app.destroy()
+
+def load_dsp_gui():
+ print "=== Start Easy Loader ==="
+ global app
+ app = gui_tk(None)
+ app.title('Easy Loader')
+ app.mainloop()
+
+
+if __name__ == "__main__":
+ load_dsp_gui()
+
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/mt6779-evb.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/mt6779-evb.cmm
new file mode 100755
index 0000000..2071281
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/mt6779-evb.cmm
@@ -0,0 +1,116 @@
+;*****************************************************************************
+; Copyright Statement:
+; --------------------
+; This software is protected by Copyright and the information contained
+; herein is confidential. The software may not be copied and the information
+; contained herein may not be used or disclosed except with the written
+; permission of MediaTek Inc. (C) 2011
+;
+;*****************************************************************************
+
+;=================================================
+; Specify Core Number
+;=================================================
+
+&NR_CPUS=1
+; cluster 0 corebase: 0x8007000, 0x8007200, 0x8007400, 0x8007600
+; cluster 1 corebase: 0x8009000, 0x8009200, 0x8009400, 0x8009600
+
+;=================================================
+; Initialize CPU
+;=================================================
+SYStem.RESet;
+SYStem.Option ENRESET ON;
+SYStem.Option ResBreak OFF;
+SYStem.Option WaitReset 100.ms;
+
+SYStem.JtagClock 10.MHz;
+
+;SYStem.CPU Ananke;
+SYStem.CPU CORTEXA53;
+
+
+if &NR_CPUS==1
+(
+ SYStem.CONFIG CORENUMBER 1;
+ SYStem.CONFIG COREBASE 0x8E010000;
+ SYStem.CONFIG CTIBASE 0x8E020000;
+)
+;=================================================
+; Attach and Stop CPU
+;=================================================
+SYSTEM.UP
+
+SETUP.IMASKHLL ON
+SETUP.IMASKASM ON
+
+;=================================================
+; Initialize EMI
+;=================================================
+&init_emi=0 ; 0: not init
+ ; 1: init
+IF &init_emi==1
+(
+ ;do Eiger_FPGA_DDR_V7_20170705_v2.cmm
+ do Eiger_FPGA_DDR_V7_20170803.cmm
+)
+;=================================================
+; register
+;=================================================
+&RGU=0x10007000
+
+;=================================================
+; disable wdt (debug purpose)
+;=================================================
+D.S SD:&RGU+0x0000 %LE %LONG 0x22000064
+
+; for pmic power latch (RGU + 0xA4)
+D.S SD:&RGU+0x00A4 %LE %LONG 0x66000001
+
+;=================================================
+; L3C share sram init
+;=================================================
+; Turn off MMU
+;D.S C15:0x1 0x00C50838
+
+; L3C share enable
+D.S SD:0x0C53C8D0 %LE %LONG 0x00070300
+
+;=================================================
+; Load Preloader Symbol
+;=================================================
+Y.SPATH.RESET ; reset all source path
+Y.SPATH.SRD ../../../platform/mt6779/src/init
+Y.SPATH.SRD ../../../platform/mt6779/src/core
+Y.SPATH.SRD ../../../platform/mt6779/src/drivers
+Y.SPATH.SRD ../../../platform/mt6779/src/security
+Y.SPATH.SRD ../../../platform/common
+Y.SPATH.SRD ../../../platform/common/bootctrl
+Y.SPATH.SRD ../../../platform/common/emimpu
+Y.SPATH.SRD ../../../platform/common/loader
+Y.SPATH.SRD ../../../platform/common/mblock
+Y.SPATH.SRD ../../../platform/common/partition
+Y.SPATH.SRD ../../../platform/common/storage/intf
+Y.SPATH.SRD ../../../platform/common/storage/mmc
+Y.SPATH.SRD ../../../platform/common/storage/ufs
+Y.SPATH.SRD ../../../platform/common/trustzone
+Y.SPATH.SRD ../../../platform/common/uart
+Y.SPATH.SRD ../../../platform/common/watchdog/wdt_v2
+Y.SPATH.SRD ../../../custom/evb6779_64
+
+Break.Select Program OnChip
+Break.Select Hll OnChip
+Break.Select Spot OnChip
+Break.Select Read OnChip
+Break.Select Write OnChip
+
+R.S T 0
+
+print "loading pre-loader image"
+d.load.elf ./preloader_evb6779_64_TINY.elf
+r.s pc 0x00201000
+
+;winclear
+d.l
+;go
+enddo
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/preloader_evb6779_64_TINY.bin b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/preloader_evb6779_64_TINY.bin
new file mode 100755
index 0000000..5c41055
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/preloader_evb6779_64_TINY.bin
Binary files differ
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/preloader_evb6779_64_TINY.elf b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/preloader_evb6779_64_TINY.elf
new file mode 100755
index 0000000..d67e7c5
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6779/preloader_evb6779_64_TINY.elf
Binary files differ
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/AP_UART_log_Checker/FullLoad_Checker/FullLoad_Checker.bat b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/AP_UART_log_Checker/FullLoad_Checker/FullLoad_Checker.bat
new file mode 100755
index 0000000..b606ecf
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/AP_UART_log_Checker/FullLoad_Checker/FullLoad_Checker.bat
@@ -0,0 +1,30 @@
+@echo off
+
+echo ...
+echo ...Finding "md1 load fail"...
+findstr /lin /c:"md1 load fail" %~dp0*.txt
+if NOT ERRORLEVEL 1 (
+ echo ...String Found...
+ echo ...load MD img FAILED...
+) else (
+ echo ...String Not Found...
+ echo ...Load MD img SUCCESS...
+)
+
+echo ...
+echo ...Finding "<6>[ 9.419579] .(2)[237:ccci_ctrl][ccci1/fsm]control message 0x0,0x0".....
+findstr /lin /c:"[ccci1/fsm]control message 0x0,0x0" %~dp0*.txt
+if NOT ERRORLEVEL 1 (
+ echo ...String Found...
+) else (
+ echo ...String Not Found...
+)
+
+echo ...
+echo ...Finding "<6>[ 9.426288] .(2)[228:ccci_fsm1][ccci1/fsm]command 1 is completed 1 by fsm_main_thread".....
+findstr /lin /c:"[ccci1/fsm]command 1 is completed 1 by fsm_main_thread" %~dp0*.txt
+if NOT ERRORLEVEL 1 (
+ echo ...String Found...
+) else (
+ echo ...String Not Found...
+)
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/AP_UART_log_Checker/dummyAP_Checker/dummyAP_Checker.bat b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/AP_UART_log_Checker/dummyAP_Checker/dummyAP_Checker.bat
new file mode 100755
index 0000000..c03cdb5
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/AP_UART_log_Checker/dummyAP_Checker/dummyAP_Checker.bat
@@ -0,0 +1,21 @@
+@echo off
+
+echo ...
+echo ...Finding "md1 load fail"...
+findstr /lin /c:"md1 load fail" %~dp0*.txt
+if NOT ERRORLEVEL 1 (
+ echo ...String Found...
+ echo ...load MD img FAILED...
+) else (
+ echo ...String Not Found...
+ echo ...Load MD img SUCCESS...
+)
+
+echo ...
+echo ...Finding "while(1)".....
+findstr /lin /c:"while(1)" %~dp0*.txt
+if NOT ERRORLEVEL 1 (
+ echo ...String Found...
+) else (
+ echo ...String Not Found...
+)
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/CVD/APview_MT6853_Frequency_Meter.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/CVD/APview_MT6853_Frequency_Meter.cmm
new file mode 100755
index 0000000..590bee9
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/CVD/APview_MT6853_Frequency_Meter.cmm
@@ -0,0 +1,764 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; MARGAUX MD Frequency Meter
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;;Select PLL
+LOCAL &key_in
+&key_in=0
+
+LOCAL &opt_cvd_connect
+&opt_cvd_connect="debug"
+
+;;;;;;;;;;;;;;;;;;;;;;;Below you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+LOCAL &mclass ;; Memory Class
+&mclass="axi"
+;&mclass="pm"
+
+LOCAL &clksw_base ;; MD CLKSW base address
+;&clksw_base=0xA0150000 ;; MD view APB
+;&clksw_base=0xA0616000 ;; MD view debug APB
+&clksw_base=0x20150000 ;; AP view MD system bus
+;&clksw_base=0x0D116000 ;; AP view MD debug sys
+
+LOCAL &pll_base ;; MD PLLMIXED base address
+;&pll_base=0xA0140000 ;; MD view APB
+;&pll_base=0xA0614000 ;; MD view debug APB
+&pll_base=0x20140000 ;; AP view MD system bus
+;&pll_base=0x0D114000 ;; AP view MD debug sys
+
+&fqmtr_fcksel_32k_index=0x17
+;;;;;;;;;;;;;;;;;;;;;;;Above you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LOCAL &fqmtr_winset ;; Frequency Meter Windoiw Setting (= Number of FIXED clock cycle)
+&fqmtr_winset=0x1ff
+&fqmtr_winset_for_32k=0x1E000
+
+LOCAL &fqmtr_fcksel_val ;; Frequency Meter FIXED clock selection
+&fqmtr_fcksel_val=0x1a ;; Select 26Mhz by default
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;All the PLL you could select;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+&SRC_STR_0="AD_MDNRPLL5"
+&SRC_STR_1="AD_MDNRPLL4_1"
+&SRC_STR_2="AD_MDNRPLL4_0"
+&SRC_STR_3="AD_MDNRPLL3"
+&SRC_STR_4="AD_MDNRPLL2"
+&SRC_STR_5="AD_MDNRPLL1"
+&SRC_STR_6="AD_MDNRPLL0"
+&SRC_STR_7="MDSYS_NRL2_CLOCK"
+&SRC_STR_8="MDRXSYS_DFESYNC_CLOCK"
+&SRC_STR_9="MDTOP_F216P7M_CLOCK"
+&SRC_STR_10="TRACE_MON_CLOCK"
+&SRC_STR_11="MDSYS_216P7M_CLOCK"
+&SRC_STR_12="MDRXSYS_RAKE_CLOCK"
+&SRC_STR_13="MDRXSYS_BRP_CLOCK"
+&SRC_STR_14="MDRXSYS_VDSP_CLOCK"
+&SRC_STR_15="MDTOP_LOG_ATB_CLOCK"
+&SRC_STR_16="FESYS_CSYS_CLOCK"
+&SRC_STR_17="MDSYS_SHAOLIN_CLOCK"
+&SRC_STR_18="FESYS_BSI_CLOCK"
+&SRC_STR_19="MDSYS_MDCORE_CLOCK"
+&SRC_STR_20="MDSYS_BUS2X_NODCM_CLOCK"
+&SRC_STR_21="MDSYS_BUS4X_CLOCK"
+&SRC_STR_22="MDTOP_DBG_CLOCK"
+&SRC_STR_23="MDTOP_F32K_CLOCK"
+&SRC_STR_24="AD_MDBPI_PLL_D7"
+&SRC_STR_25="AD_MDBPI_PLL_D5"
+&SRC_STR_26="AD_MDBPI_PLL_D4"
+&SRC_STR_27="AD_MDBPI_PLL_D3"
+&SRC_STR_28="AD_MDBPI_PLL_D2"
+&SRC_STR_29="AD_MDBRP_PLL"
+&SRC_STR_30="AD_MDVDSP_PLL"
+&SRC_STR_31="AD_MDMCU_PLL"
+&SRC_STR_32="null_32"
+&SRC_STR_33="null_33"
+&SRC_STR_34="null_34"
+&SRC_STR_35="null_35"
+&SRC_STR_36="null_36"
+&SRC_STR_37="null_37"
+&SRC_STR_38="null_38"
+&SRC_STR_39="null_39"
+&SRC_STR_40="null_40"
+&SRC_STR_41="null_41"
+&SRC_STR_42="null_42"
+&SRC_STR_43="null_43"
+&SRC_STR_44="null_44"
+&SRC_STR_45="null_45"
+&SRC_STR_46="DFESYS_RXDFE_BB_CORE_CLOCK"
+&SRC_STR_47="AD_MDNRPLL4_2"
+&SRC_STR_48="MDTOP_BUS4X_FIXED_CLOCK"
+&SRC_STR_49="DA_DRF_26M_CLOCK"
+&SRC_STR_50="MDTOP_BUS4X_CLOCK"
+&SRC_STR_51="RXCPC_CPC_CLOCK"
+&SRC_STR_52="null_52"
+&SRC_STR_53="RXDDMBRP_RXDBRP_CLOCK"
+&SRC_STR_54="RXDDMBRP_RXDDM_CLOCK"
+&SRC_STR_55="MCORE_MCORE_CLOCK"
+&SRC_STR_56="VCOREHRAM_VCORE_CLOCK"
+&SRC_STR_57="VCOREHRAM_HRAM_CLOCK"
+&SRC_STR_58="FESYS_TXBSRP_CLOCK"
+&SRC_STR_59="FESYS_MDPLL_CLOCK"
+&SRC_STR_60="TX_CS_NR_RXT2F_NR_CLOCK"
+&SRC_STR_61="TX_CS_NR_TXBSRP_NR_CLOCK"
+&SRC_STR_62="TX_CS_NR_CM_NR_CLOCK"
+&SRC_STR_63="TX_CS_NR_CS_NR_CLOCK"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+DIALOG
+(&
+ HEADER "PLL Frequency Meter"
+ ICON ":chip"
+
+ POS 0. 0. 45. 1.
+ LINE "----------------------------FQMTR Selection(Error Rate: +/- 1Mhz)----------------------------"
+ ; x y w h
+ POS 0. 1. 20. 1.
+ SEL.NONE: CHOOSEBOX "None"
+ (
+ &key_in=0xF00
+ )
+ SEL.0: CHOOSEBOX "&SRC_STR_0"
+ (
+ &key_in=0x0
+ &key_str="&SRC_STR_0"
+ )
+ SEL.1: CHOOSEBOX "&SRC_STR_1"
+ (
+ &key_in=0x1
+ &key_str="&SRC_STR_1"
+ )
+ SEL.2: CHOOSEBOX "&SRC_STR_2"
+ (
+ &key_in=0x2
+ &key_str="&SRC_STR_2"
+ )
+ SEL.3: CHOOSEBOX "&SRC_STR_3"
+ (
+ &key_in=0x3
+ &key_str="&SRC_STR_3"
+ )
+ SEL.4: CHOOSEBOX "&SRC_STR_4"
+ (
+ &key_in=0x4
+ &key_str="&SRC_STR_4"
+ )
+ SEL.5: CHOOSEBOX "&SRC_STR_5"
+ (
+ &key_in=0x5
+ &key_str="&SRC_STR_5"
+ )
+ SEL.6: CHOOSEBOX "&SRC_STR_6"
+ (
+ &key_in=0x6
+ &key_str="&SRC_STR_6"
+ )
+ SEL.7: CHOOSEBOX "&SRC_STR_7"
+ (
+ &key_in=0x7
+ &key_str="&SRC_STR_7"
+ )
+ SEL.8: CHOOSEBOX "&SRC_STR_8"
+ (
+ &key_in=0x8
+ &key_str="&SRC_STR_8"
+ )
+ SEL.9: CHOOSEBOX "&SRC_STR_9"
+ (
+ &key_in=0x9
+ &key_str="&SRC_STR_9"
+ )
+ SEL.10: CHOOSEBOX "&SRC_STR_10"
+ (
+ &key_in=0xA
+ &key_str="&SRC_STR_10"
+ )
+ SEL.11: CHOOSEBOX "&SRC_STR_11"
+ (
+ &key_in=0xB
+ &key_str="&SRC_STR_11"
+ )
+ SEL.12: CHOOSEBOX "&SRC_STR_12"
+ (
+ &key_in=0xC
+ &key_str="&SRC_STR_12"
+ )
+ SEL.13: CHOOSEBOX "&SRC_STR_13"
+ (
+ &key_in=0xD
+ &key_str="&SRC_STR_13"
+ )
+ SEL.14: CHOOSEBOX "&SRC_STR_14"
+ (
+ &key_in=0xE
+ &key_str="&SRC_STR_14"
+ )
+ SEL.15: CHOOSEBOX "&SRC_STR_15"
+ (
+ &key_in=0xF
+ &key_str="&SRC_STR_15"
+ )
+ SEL.16: CHOOSEBOX "&SRC_STR_16"
+ (
+ &key_in=0x10
+ &key_str="&SRC_STR_16"
+ )
+ SEL.17: CHOOSEBOX "&SRC_STR_17"
+ (
+ &key_in=0x11
+ &key_str="&SRC_STR_17"
+ )
+ SEL.18: CHOOSEBOX "&SRC_STR_18"
+ (
+ &key_in=0x12
+ &key_str="&SRC_STR_18"
+ )
+ SEL.19: CHOOSEBOX "&SRC_STR_19"
+ (
+ &key_in=0x13
+ &key_str="&SRC_STR_19"
+ )
+ SEL.20: CHOOSEBOX "&SRC_STR_20"
+ (
+ &key_in=0x14
+ &key_str="&SRC_STR_20"
+ )
+ SEL.21: CHOOSEBOX "&SRC_STR_21"
+ (
+ &key_in=0x15
+ &key_str="&SRC_STR_21"
+ )
+ SEL.22: CHOOSEBOX "&SRC_STR_22"
+ (
+ &key_in=0x16
+ &key_str="&SRC_STR_22"
+ )
+ SEL.23: CHOOSEBOX "&SRC_STR_23"
+ (
+ &key_in=0x17
+ &key_str="&SRC_STR_23"
+ )
+ SEL.24: CHOOSEBOX "&SRC_STR_24"
+ (
+ &key_in=0x18
+ &key_str="&SRC_STR_24"
+ )
+ SEL.25: CHOOSEBOX "&SRC_STR_25"
+ (
+ &key_in=0x19
+ &key_str="&SRC_STR_25"
+ )
+ SEL.26: CHOOSEBOX "&SRC_STR_26"
+ (
+ &key_in=0x1A
+ &key_str="&SRC_STR_26"
+ )
+ SEL.27: CHOOSEBOX "&SRC_STR_27"
+ (
+ &key_in=0x1B
+ &key_str="&SRC_STR_27"
+ )
+ SEL.28: CHOOSEBOX "&SRC_STR_28"
+ (
+ &key_in=0x1C
+ &key_str="&SRC_STR_28"
+ )
+ SEL.29: CHOOSEBOX "&SRC_STR_29"
+ (
+ &key_in=0x1D
+ &key_str="&SRC_STR_29"
+ )
+ SEL.30: CHOOSEBOX "&SRC_STR_30"
+ (
+ &key_in=0x1E
+ &key_str="&SRC_STR_30"
+ )
+ SEL.31: CHOOSEBOX "&SRC_STR_31"
+ (
+ &key_in=0x1F
+ &key_str="&SRC_STR_31"
+ )
+
+ POS 21. 1. 25. 1.
+;; SEL.32: CHOOSEBOX "&SRC_STR_32"
+;; (
+;; &key_in=0x20
+;; &key_str="&SRC_STR_32"
+;; )
+;; SEL.33: CHOOSEBOX "&SRC_STR_33"
+;; (
+;; &key_in=0x21
+;; &key_str="&SRC_STR_33"
+;; )
+ SEL.46: CHOOSEBOX "&SRC_STR_46"
+ (
+ &key_in=0x2E
+ &key_str="&SRC_STR_46"
+ )
+ SEL.47: CHOOSEBOX "&SRC_STR_47"
+ (
+ &key_in=0x2F
+ &key_str="&SRC_STR_47"
+ )
+ SEL.48: CHOOSEBOX "&SRC_STR_48"
+ (
+ &key_in=0x30
+ &key_str="&SRC_STR_48"
+ )
+ SEL.49: CHOOSEBOX "&SRC_STR_49"
+ (
+ &key_in=0x31
+ &key_str="&SRC_STR_49"
+ )
+ SEL.50: CHOOSEBOX "&SRC_STR_50"
+ (
+ &key_in=0x32
+ &key_str="&SRC_STR_50"
+ )
+ SEL.51: CHOOSEBOX "&SRC_STR_51"
+ (
+ &key_in=0x33
+ &key_str="&SRC_STR_51"
+ )
+;; SEL.52: CHOOSEBOX "&SRC_STR_52"
+;; (
+;; &key_in=0x34
+;; &key_str="&SRC_STR_52"
+;; )
+ SEL.53: CHOOSEBOX "&SRC_STR_53"
+ (
+ &key_in=0x35
+ &key_str="&SRC_STR_53"
+ )
+ SEL.54: CHOOSEBOX "&SRC_STR_54"
+ (
+ &key_in=0x36
+ &key_str="&SRC_STR_54"
+ )
+ SEL.55: CHOOSEBOX "&SRC_STR_55"
+ (
+ &key_in=0x37
+ &key_str="&SRC_STR_55"
+ )
+ SEL.56: CHOOSEBOX "&SRC_STR_56"
+ (
+ &key_in=0x38
+ &key_str="&SRC_STR_56"
+ )
+ SEL.57: CHOOSEBOX "&SRC_STR_57"
+ (
+ &key_in=0x39
+ &key_str="&SRC_STR_57"
+ )
+ SEL.58: CHOOSEBOX "&SRC_STR_58"
+ (
+ &key_in=0x3A
+ &key_str="&SRC_STR_58"
+ )
+ SEL.59: CHOOSEBOX "&SRC_STR_59"
+ (
+ &key_in=0x3B
+ &key_str="&SRC_STR_59"
+ )
+ SEL.60: CHOOSEBOX "&SRC_STR_60"
+ (
+ &key_in=0x3C
+ &key_str="&SRC_STR_60"
+ )
+ SEL.61: CHOOSEBOX "&SRC_STR_61"
+ (
+ &key_in=0x3D
+ &key_str="&SRC_STR_61"
+ )
+ SEL.62: CHOOSEBOX "&SRC_STR_62"
+ (
+ &key_in=0x3E
+ &key_str="&SRC_STR_62"
+ )
+ SEL.63: CHOOSEBOX "&SRC_STR_63"
+ (
+ &key_in=0x3F
+ &key_str="&SRC_STR_63"
+ )
+
+ POS 46. 0. 20. 1.
+ LINE "FQMTR Information"
+ INFO1: EDIT "Window Seting: &fqmtr_winset" ""
+ INFO2: EDIT "Fixed Clock: &fqmtr_fcksel_val" ""
+ INFO3: EDIT "32K measure support" ""
+
+ POSY 1. 20. 1.
+ LINE "FQMTR Result"
+ LINE "(Error Rate: +/- 1Mhz)"
+ RESULT: EDIT "" ""
+
+ POSY 1. 20. 1.
+ DEFBUTTON "OK"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ IF &key_in!=0xF00
+ (
+ GOSUB fqmtr_query &key_in &key_str 1
+ )
+ )
+
+ DEFBUTTON "LIST ALL"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ GOSUB fqmtr_list_all
+ )
+
+ DEFBUTTON "Force LIST main clk"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ GOSUB fqmtr_force_list_all
+ )
+
+ CLOSE
+ (
+ PRINT "bye~"
+ DIALOG.END
+ )
+)
+
+ ;; Disable EDIT of showing information
+ DIALOG.Disable INFO1
+ DIALOG.Disable INFO2
+ DIALOG.Disable INFO3
+ ;DIALOG.Disable RESULT
+STOP
+ENDDO
+
+;;;;;The main function to get the Frequency. &idx==> the clock you select, &str==> clock name, &info==>list more info and wait 5ms in the function
+;; &info=1 ==> for printing many PLLs at one time
+fqmtr_query:
+ENTRY &idx &str &info
+(
+ IF &info!=0
+ (
+ PRINT "&str: &idx"
+ PRINT "fqmtrsrc: 0x" FORMAT.HEX(2,&idx)
+ PRINT "opt_cvd_connect: &opt_cvd_connect"
+ )
+
+ LOCAL &unit
+ LOCAL &fqmtr_winset_26M
+ LOCAL &fqmtr_result
+ LOCAL &fqmtr_result_raw
+ LOCAL &fqmtr_result_str
+ LOCAL &safe_wait_cnt
+ LOCAL &safe_wait_cnt_max
+ LOCAL &fqmtr_busy
+
+ &safe_wait_cnt=0
+
+ IF &fqmtr_fcksel_val==0x1a ;; base on 26M, unit:MHz
+ (
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &unit="Khz"
+ &fqmtr_winset_26M=&fqmtr_winset_for_32k
+ &safe_wait_cnt_max=500 ;;5000 ms = 5s ==> in real test, longer than 5s, so reduce it
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &unit="Mhz"
+ &fqmtr_winset_26M=&fqmtr_winset
+ &safe_wait_cnt_max=32 ;;32 ms
+ )
+ )
+ ELSE
+ (
+ &unit=""
+ )
+
+ IF "&opt_cvd_connect"=="none"
+ (
+ sys.m prepare
+ )
+ ELSE IF "&opt_cvd_connect"=="debug"
+ (
+ ; do nothing
+ )
+ ELSE
+ (
+ IF &info!=0
+ (
+ PRINT "No explicit CVD connection, use current status"
+ )
+ )
+
+;; IF &idx==0
+;; (
+ ;; This is used for connect CVD only, no FQMTR test
+;; RETURN
+;; )
+
+ ;;select source to a valid clock to let reset success.
+ Data.Set &mclass:(&clksw_base+0x0400) %LE %LONG 0x13
+ Data.Set &mclass:(&clksw_base+0x0404) %LE %LONG 0x0 ;reset frequency meter
+ WAIT 1ms
+
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ ;;For accurate, don't div 8 for 32K
+ Data.Set &mclass:(&clksw_base+0x0400) %LE %LONG (&idx)
+ )
+ ELSE ;; measure PLL and other module
+ (
+ ;;div 8 and select src
+ Data.Set &mclass:(&clksw_base+0x0400) %LE %LONG (0x0300)|(&idx)
+ )
+
+ Data.Set &mclass:(&clksw_base+0x0408) %LE %LONG &fqmtr_winset_26M
+ Data.Set &mclass:(&clksw_base+0x0404) %LE %LONG 0x1 ;enable frequency meter
+
+ ;; read status, to check polling done or not
+ &fqmtr_busy=DATA.LONG(&mclass:(&clksw_base+0x0404))&(1<<1)
+ WHILE &fqmtr_busy==0
+ (
+ ;PRINT ". &fqmtr_busy"
+ &fqmtr_busy=DATA.LONG(&mclass:(&clksw_base+0x0404))&(1<<1)
+ &safe_wait_cnt=&safe_wait_cnt+1
+ IF &safe_wait_cnt==&safe_wait_cnt_max
+ (
+ PRINT "[&str] Wait Fail, exit"
+ DIALOG.Set RESULT "Wait Fail(No clock), exit"
+ RETURN
+ )
+ ELSE
+ (
+;; PRINT "Waiting result. safe_wait_cnt=" "&safe_wait_cnt"
+ )
+ WAIT 1ms
+ )
+
+ ;; Calculate the result
+ &fqmtr_result_raw=DATA.LONG(&mclass:(&clksw_base+0x40c))
+
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*(0x3E8)/(&fqmtr_winset_26M+3)
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*8/(&fqmtr_winset_26M+3)
+ )
+
+ &fqmtr_result_dec=FORMAT.DECIMAL(0,&fqmtr_result)
+ &fqmtr_result_str=""+FORMAT.DECIMAL(0,&fqmtr_result)+" &unit"
+ IF &info==0
+ (
+ PRINT "0x" FORMAT.HEX(2,&idx) ",&fqmtr_result_dec,&unit,&str,&fqmtr_result_raw,"
+ )
+ ELSE
+ (
+ PRINT "Frequency Meter Result: &fqmtr_result_str (&fqmtr_result_raw)"
+ PRINT ""
+ )
+ DIALOG.Set RESULT "&fqmtr_result_str"
+
+ IF &info==0
+ (
+ WAIT 5ms
+ )
+
+ RETURN
+)
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+fqmtr_create_win:
+(
+ AREA.RESet
+ AREA.Create PLL_FMETER
+ AREA.Select PLL_FMETER
+ WinPOS 10.,0.,70.,35.,,, FMETER
+ AREA.view PLL_FMETER
+ AREA.Clear PLL_FMETER
+ RETURN
+)
+
+fqmtr_list_all:
+(
+ GOSUB fqmtr_create_win
+
+ PRINT "Note: The Error Rate of Frequency Meter is +/-1 MHz!!"
+ PRINT ""
+ GOSUB fqmtr_query 0x0 &SRC_STR_0 0
+ GOSUB fqmtr_query 0x1 &SRC_STR_1 0
+ GOSUB fqmtr_query 0x2 &SRC_STR_2 0
+ GOSUB fqmtr_query 0x3 &SRC_STR_3 0
+ GOSUB fqmtr_query 0x4 &SRC_STR_4 0
+ GOSUB fqmtr_query 0x5 &SRC_STR_5 0
+ GOSUB fqmtr_query 0x6 &SRC_STR_6 0
+ GOSUB fqmtr_query 0x7 &SRC_STR_7 0
+ GOSUB fqmtr_query 0x8 &SRC_STR_8 0
+ GOSUB fqmtr_query 0x9 &SRC_STR_9 0
+ GOSUB fqmtr_query 0xA &SRC_STR_10 0
+ GOSUB fqmtr_query 0xB &SRC_STR_11 0
+ GOSUB fqmtr_query 0xC &SRC_STR_12 0
+ GOSUB fqmtr_query 0xD &SRC_STR_13 0
+ GOSUB fqmtr_query 0xE &SRC_STR_14 0
+ GOSUB fqmtr_query 0xF &SRC_STR_15 0
+ GOSUB fqmtr_query 0x10 &SRC_STR_16 0
+ GOSUB fqmtr_query 0x11 &SRC_STR_17 0
+ GOSUB fqmtr_query 0x12 &SRC_STR_18 0
+ GOSUB fqmtr_query 0x13 &SRC_STR_19 0
+ GOSUB fqmtr_query 0x14 &SRC_STR_20 0
+ GOSUB fqmtr_query 0x15 &SRC_STR_21 0
+ GOSUB fqmtr_query 0x16 &SRC_STR_22 0
+ GOSUB fqmtr_query 0x17 &SRC_STR_23 0
+ GOSUB fqmtr_query 0x18 &SRC_STR_24 0
+ GOSUB fqmtr_query 0x19 &SRC_STR_25 0
+ GOSUB fqmtr_query 0x1A &SRC_STR_26 0
+ GOSUB fqmtr_query 0x1B &SRC_STR_27 0
+ GOSUB fqmtr_query 0x1C &SRC_STR_28 0
+ GOSUB fqmtr_query 0x1D &SRC_STR_29 0
+ GOSUB fqmtr_query 0x1E &SRC_STR_30 0
+ GOSUB fqmtr_query 0x1F &SRC_STR_31 0
+; GOSUB fqmtr_query 0x20 &SRC_STR_32 0
+; GOSUB fqmtr_query 0x21 &SRC_STR_33 0
+; GOSUB fqmtr_query 0x22 &SRC_STR_34 0
+; GOSUB fqmtr_query 0x23 &SRC_STR_35 0
+; GOSUB fqmtr_query 0x24 &SRC_STR_36 0
+; GOSUB fqmtr_query 0x25 &SRC_STR_37 0
+; GOSUB fqmtr_query 0x26 &SRC_STR_38 0
+; GOSUB fqmtr_query 0x27 &SRC_STR_39 0
+; GOSUB fqmtr_query 0x28 &SRC_STR_40 0
+; GOSUB fqmtr_query 0x29 &SRC_STR_41 0
+; GOSUB fqmtr_query 0x2A &SRC_STR_42 0
+; GOSUB fqmtr_query 0x2B &SRC_STR_43 0
+; GOSUB fqmtr_query 0x2C &SRC_STR_44 0
+; GOSUB fqmtr_query 0x2D &SRC_STR_45 0
+ GOSUB fqmtr_query 0x2E &SRC_STR_46 0
+ GOSUB fqmtr_query 0x2F &SRC_STR_47 0
+ GOSUB fqmtr_query 0x30 &SRC_STR_48 0
+ GOSUB fqmtr_query 0x31 &SRC_STR_49 0
+ GOSUB fqmtr_query 0x32 &SRC_STR_50 0
+ GOSUB fqmtr_query 0x33 &SRC_STR_51 0
+; GOSUB fqmtr_query 0x34 &SRC_STR_52 0
+ GOSUB fqmtr_query 0x35 &SRC_STR_53 0
+ GOSUB fqmtr_query 0x36 &SRC_STR_54 0
+ GOSUB fqmtr_query 0x37 &SRC_STR_55 0
+ GOSUB fqmtr_query 0x38 &SRC_STR_56 0
+ GOSUB fqmtr_query 0x39 &SRC_STR_57 0
+ GOSUB fqmtr_query 0x3A &SRC_STR_58 0
+ GOSUB fqmtr_query 0x3B &SRC_STR_59 0
+ GOSUB fqmtr_query 0x3C &SRC_STR_60 0
+ GOSUB fqmtr_query 0x3D &SRC_STR_61 0
+ GOSUB fqmtr_query 0x3E &SRC_STR_62 0
+ GOSUB fqmtr_query 0x3F &SRC_STR_63 0
+ RETURN
+)
+
+fqmtr_force_list_all:
+(
+ GOSUB fqmtr_create_win
+
+ PRINT "Note: The Error Rate of Frequency Meter is +/-1 MHz!!"
+ PRINT ""
+
+ LOCAL &original_reg
+ LOCAL &original_reg_clksw_10
+ LOCAL &original_reg_clksw_14
+ LOCAL &original_reg_clksw_18
+ LOCAL &original_reg_clksw_20
+ LOCAL &tmp
+
+ &original_reg=DATA.LONG(&mclass:(&pll_base+0x10))
+
+ ; S/W force on all PLL
+ Data.Set &mclass:(&pll_base+0x10) %LE %LONG 0xFFFFFFFF
+
+ &original_reg_clksw_10=DATA.LONG(&mclass:(&clksw_base+0x10))
+ &original_reg_clksw_14=DATA.LONG(&mclass:(&clksw_base+0x14))
+ &original_reg_clksw_18=DATA.LONG(&mclass:(&clksw_base+0x18))
+ &original_reg_clksw_20=DATA.LONG(&mclass:(&clksw_base+0x20))
+
+ ; S/W force request all module clock
+ Data.Set &mclass:(&clksw_base+0x10) %long %le 0xFFFFFFFF
+ Data.Set &mclass:(&clksw_base+0x14) %long %le 0xFFFFFFFF
+ Data.Set &mclass:(&clksw_base+0x18) %long %le 0xFFFFFFFF
+ &tmp = data.long(&clksw_base+0x20)|(0x10077)
+ Data.Set &mclass:(&clksw_base+0x20) %long %le &tmp
+
+ WAIT 1.s
+
+ GOSUB fqmtr_query 0x0 &SRC_STR_0 0
+ GOSUB fqmtr_query 0x1 &SRC_STR_1 0
+ GOSUB fqmtr_query 0x2 &SRC_STR_2 0
+ GOSUB fqmtr_query 0x3 &SRC_STR_3 0
+ GOSUB fqmtr_query 0x4 &SRC_STR_4 0
+ GOSUB fqmtr_query 0x5 &SRC_STR_5 0
+ GOSUB fqmtr_query 0x6 &SRC_STR_6 0
+ GOSUB fqmtr_query 0x7 &SRC_STR_7 0
+ GOSUB fqmtr_query 0x8 &SRC_STR_8 0
+ GOSUB fqmtr_query 0x9 &SRC_STR_9 0
+ GOSUB fqmtr_query 0xA &SRC_STR_10 0
+ GOSUB fqmtr_query 0xB &SRC_STR_11 0
+ GOSUB fqmtr_query 0xC &SRC_STR_12 0
+ GOSUB fqmtr_query 0xD &SRC_STR_13 0
+ GOSUB fqmtr_query 0xE &SRC_STR_14 0
+ GOSUB fqmtr_query 0xF &SRC_STR_15 0
+ GOSUB fqmtr_query 0x10 &SRC_STR_16 0
+ GOSUB fqmtr_query 0x11 &SRC_STR_17 0
+ GOSUB fqmtr_query 0x12 &SRC_STR_18 0
+ GOSUB fqmtr_query 0x13 &SRC_STR_19 0
+ GOSUB fqmtr_query 0x14 &SRC_STR_20 0
+ GOSUB fqmtr_query 0x15 &SRC_STR_21 0
+ GOSUB fqmtr_query 0x16 &SRC_STR_22 0
+ GOSUB fqmtr_query 0x17 &SRC_STR_23 0
+ GOSUB fqmtr_query 0x18 &SRC_STR_24 0
+ GOSUB fqmtr_query 0x19 &SRC_STR_25 0
+ GOSUB fqmtr_query 0x1A &SRC_STR_26 0
+ GOSUB fqmtr_query 0x1B &SRC_STR_27 0
+ GOSUB fqmtr_query 0x1C &SRC_STR_28 0
+ GOSUB fqmtr_query 0x1D &SRC_STR_29 0
+ GOSUB fqmtr_query 0x1E &SRC_STR_30 0
+ GOSUB fqmtr_query 0x1F &SRC_STR_31 0
+; GOSUB fqmtr_query 0x20 &SRC_STR_32 0
+; GOSUB fqmtr_query 0x21 &SRC_STR_33 0
+; GOSUB fqmtr_query 0x22 &SRC_STR_34 0
+; GOSUB fqmtr_query 0x23 &SRC_STR_35 0
+; GOSUB fqmtr_query 0x24 &SRC_STR_36 0
+; GOSUB fqmtr_query 0x25 &SRC_STR_37 0
+; GOSUB fqmtr_query 0x26 &SRC_STR_38 0
+; GOSUB fqmtr_query 0x27 &SRC_STR_39 0
+; GOSUB fqmtr_query 0x28 &SRC_STR_40 0
+; GOSUB fqmtr_query 0x29 &SRC_STR_41 0
+; GOSUB fqmtr_query 0x2A &SRC_STR_42 0
+; GOSUB fqmtr_query 0x2B &SRC_STR_43 0
+; GOSUB fqmtr_query 0x2C &SRC_STR_44 0
+; GOSUB fqmtr_query 0x2D &SRC_STR_45 0
+ GOSUB fqmtr_query 0x2E &SRC_STR_46 0
+ GOSUB fqmtr_query 0x2F &SRC_STR_47 0
+ GOSUB fqmtr_query 0x30 &SRC_STR_48 0
+ GOSUB fqmtr_query 0x31 &SRC_STR_49 0
+ GOSUB fqmtr_query 0x32 &SRC_STR_50 0
+ GOSUB fqmtr_query 0x33 &SRC_STR_51 0
+; GOSUB fqmtr_query 0x34 &SRC_STR_52 0
+ GOSUB fqmtr_query 0x35 &SRC_STR_53 0
+ GOSUB fqmtr_query 0x36 &SRC_STR_54 0
+ GOSUB fqmtr_query 0x37 &SRC_STR_55 0
+ GOSUB fqmtr_query 0x38 &SRC_STR_56 0
+ GOSUB fqmtr_query 0x39 &SRC_STR_57 0
+ GOSUB fqmtr_query 0x3A &SRC_STR_58 0
+ GOSUB fqmtr_query 0x3B &SRC_STR_59 0
+ GOSUB fqmtr_query 0x3C &SRC_STR_60 0
+ GOSUB fqmtr_query 0x3D &SRC_STR_61 0
+ GOSUB fqmtr_query 0x3E &SRC_STR_62 0
+ GOSUB fqmtr_query 0x3F &SRC_STR_63 0
+
+ ; Revert to original value
+ Data.Set &mclass:(&pll_base+0x10) %LE %LONG &original_reg
+
+ Data.Set &mclass:(&clksw_base+0x10) %LE %LONG &original_reg_clksw_10
+ Data.Set &mclass:(&clksw_base+0x14) %LE %LONG &original_reg_clksw_14
+ Data.Set &mclass:(&clksw_base+0x18) %LE %LONG &original_reg_clksw_18
+ Data.Set &mclass:(&clksw_base+0x20) %LE %LONG &original_reg_clksw_20
+
+ WAIT 1.s
+
+ RETURN
+)
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/CVD/MT6853_MD_Only.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/CVD/MT6853_MD_Only.cmm
new file mode 100755
index 0000000..39fd916
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/CVD/MT6853_MD_Only.cmm
@@ -0,0 +1,294 @@
+sys.m prepare
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Common Macro
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+&MEM_CLASS="AXI"
+;;; MD DAP ;;;
+;&AP_REG_BASE=0xC0000000
+;&MD_REG_BASE=0xA0000000
+;;; AP DAP ;;;
+&AP_REG_BASE=0x10000000
+&MD_REG_BASE=0x20000000
+;;; Control PLL init ;;;
+&ENABLE_PLL_INIT=0x1
+
+wait 1.ms
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; [Note]:
+;; 1. If AP touching MD, Request DAPC(Neal Liu)/PMS(Hanna Chiang) for access right
+;; Margaux Review On-going
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+&ADDR_A=(&AP_REG_BASE+0x00030F00)
+&ADDR_B=(&AP_REG_BASE+0x00030A00)
+Data.Set &MEM_CLASS:&ADDR_A %LE %LONG (Data.Long(&MEM_CLASS:&ADDR_A) & 0xFFFFFFFB)
+Data.Set &MEM_CLASS:&ADDR_B %LE %LONG (Data.Long(&MEM_CLASS:&ADDR_B) | 0x1)
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Step 0: Disable MD/AP WDT
+; Margaux Review Done
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+PRINT "Step 0: Disable MD/AP WDT"
+&BASE_ADDR_MDRGU=(&MD_REG_BASE+0x000F0100)
+&BASE_ADDR_APRGU=(&AP_REG_BASE+0x00007000)
+Data.Set &MEM_CLASS:(&BASE_ADDR_MDRGU) %LE %LONG ((Data.Long(&MEM_CLASS:&BASE_ADDR_MDRGU)&0xFFFFFFFC)|0x55000000)
+Data.Set &MEM_CLASS:(&BASE_ADDR_APRGU) %LE %LONG ((Data.Long(&MEM_CLASS:&BASE_ADDR_APRGU)&0xFFFFFFFE)|0x22000000)
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Step 0.1: Disable PMIC power latch (Jeter Chen/Brian-py Chen)
+; Margaux Review Done
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+PRINT "Step 0.1: Disable PMIC power latch (Jeter Chen/Brian-py Chen)"
+&BASE_ADDR_APRGU_PMIC_PWR_LATCH=(&AP_REG_BASE+0x00007000+0x000000A4)
+Data.Set &MEM_CLASS:&BASE_ADDR_APRGU_PMIC_PWR_LATCH %LE %LONG 0x66000001
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Step 1: Config MD related Buck (Chao-Kai/Wen Su)
+;; Margaux Review Done
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; AP preloader should set Modem related buck, i.e., void vmd1_pmic_setting_on(void)
+; Settings should be:
+; - VMODEM: 0.8V,
+; - VSRAM_MD: 0.8V,
+; - VNR: 0.8V,
+; - VDIGRF:0.7V
+; Check with preloader/PMIC owner if not set
+; skip
+PRINT "Step 1: Config MD related Buck (Chao-Kai/Wen Su)"
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Step 2: Configure md_srclkena setting (Yuyang/Hank Wang)
+; - Configure md_srclkena strategy to turn on 26M/RF
+; Margaux Review Done
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+PRINT "Step 2: Configure md_srclkena setting (Yuyang/Hank Wang)"
+&INFRA_MISC2=(&AP_REG_BASE+0x00001F0C)
+&BASE_ADDR_APSPM=(&AP_REG_BASE+0x00006000)
+&POWERON_CONFIG_EN=(&BASE_ADDR_APSPM+0x00000000)
+&SPM_POWER_ON_VAL1=(&BASE_ADDR_APSPM+0x00000008)
+
+; [3:0] : mdsrc_req_0_en = 4'b0001, [7:4] : mdsrc_req_1_en = 4'b0010
+Data.Set (&MEM_CLASS:&INFRA_MISC2) %LE %LONG ((Data.Long(&MEM_CLASS:&INFRA_MISC2)&0xFFFFFF00)|0x21)
+
+; set SPM register for clkenal force on
+Data.Set (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001
+; Set src clkena1 force on, 0x10006008|= 0x1 << 21
+Data.Set (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG (Data.Long(&MEM_CLASS:&SPM_POWER_ON_VAL1)|0x200000)
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Step 3: Power on MD MTCMOS (AP PLL: YY Huang/AP SPM: Hank Wang/MD TOPSM: Andy.Chiang)
+; Margaux Review Done
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; AP SPM owner gen code to AP PLL owner, and provide the API, i.e., clk_prepare_enable
+; to CCCI for execution
+; skip
+PRINT "Step 3: Power on MD MTCMOS (AP PLL: YY Huang/AP SPM: Hank Wang/MD TOPSM: Andy.Chiang)"
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Step 4 Enable MDMCU clock (Jun-Ying Huang/ Hanna Chiang)
+; - PLL init step has been removed here and implemented by BootROM
+; Margaux Review Done
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+PRINT "Step 4 Enable MDMCU clock (Jun-Ying Huang/ Hanna Chiang)"
+&QUALITY_26M_ADDR=(&AP_REG_BASE+0x0000C000)
+Data.Set (&MEM_CLASS:&QUALITY_26M_ADDR) %LE %LONG 0x15
+wait 1.s
+Data.Set (&MEM_CLASS:&QUALITY_26M_ADDR) %LE %LONG 0x17
+wait 1.s
+
+IF &ENABLE_PLL_INIT==0x1
+(
+ &BASE_MADDR_MDTOP_PLLMIXED=(&MD_REG_BASE+0x00140000)
+ &BASE_MADDR_MDTOP_CLKSW=(&MD_REG_BASE+0x00150000)
+ ®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+ ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+ ®_MDTOP_PLLMIXED_PLL_SETTLE_26M_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x20)
+ ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+ ;;®_MDTOP_PLLMIXED_MDMCUPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x44)
+ ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+ ;;®_MDTOP_PLLMIXED_MDVDSPPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x4C)
+ ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+ ;;®_MDTOP_PLLMIXED_MDBRPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x54)
+ ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x58)
+ ®_MDTOP_PLLMIXED_MDNRPLL0_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x68)
+ ;;®_MDTOP_PLLMIXED_MDNRPLL0_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x6C)
+ ®_MDTOP_PLLMIXED_MDNRPLL1_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x70)
+ ;;®_MDTOP_PLLMIXED_MDNRPLL1_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x74)
+ ®_MDTOP_PLLMIXED_MDNRPLL2_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x78)
+ ®_MDTOP_PLLMIXED_MDNRPLL2_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x7C)
+ ®_MDTOP_PLLMIXED_MDNRPLL3_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x80)
+ ®_MDTOP_PLLMIXED_MDNRPLL3_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x84)
+ ®_MDTOP_PLLMIXED_MDNRPLL4_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x88)
+ ;;®_MDTOP_PLLMIXED_MDNRPLL4_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x8C)
+ ®_MDTOP_PLLMIXED_MDNRPLL5_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x90)
+ ;;®_MDTOP_PLLMIXED_MDNRPLL5_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x94)
+ ®_MDTOP_PLLMIXED_MDPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x98)
+ ®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x9C)
+
+ ®_MDTOP_PLLMIXED_PLL_DIV_EN0=(&BASE_MADDR_MDTOP_PLLMIXED+0x124)
+ ®_MDTOP_PLLMIXED_PLL_DIV_EN3=(&BASE_MADDR_MDTOP_PLLMIXED+0x130)
+ ®_MDTOP_PLLMIXED_PLL_SRC_SEL=(&BASE_MADDR_MDTOP_PLLMIXED+0x140)
+
+ ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+ ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+
+ ®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0x800)
+ ®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+ ®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+ ®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+ ®_MDTOP_CLKSW_CLKSEL_CTL_2=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+ ®_MDTOP_CLKSW_SDF_ATB_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x2C)
+ ®_MDTOP_CLKSW_CLK_DUMMY=(&BASE_MADDR_MDTOP_CLKSW+0xF00)
+
+ ®_MDTOP_CLKSW_DFESYNC_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x5C)
+ ®_MDTOP_CLKSW_HRAM_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x8C)
+ ;;®_MDTOP_CLKSW_BUS2X_NODCM_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0xBC)
+ ®_MDTOP_CLKSW_SHAOLIN_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x78)
+ ;;®_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x70)
+ ;;®_MDTOP_CLKSW_MCORE_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x94)
+ ;;®_MDTOP_CLKSW_VCORE_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x90)
+
+ ®_MDTOP_CLKSW_NR_CS_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x84)
+ ®_MDTOP_CLKSW_NR_CM_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x88)
+ ®_MDTOP_CLKSW_NR_RXT2F_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0xAC)
+ ®_MDTOP_CLKSW_NR_TXBSRP_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0xA8)
+
+ ®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0xCC)
+
+ &MD_PLL_MAGIC_NUM=0x62970000
+
+ ;; Default md_srclkena_ack settle time = 81+4T 32K
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL) %LE %LONG 0x02021C53
+
+ ;;Change ABBPLL_SETTLE_26M to 0x2F2==>29us
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_PLL_SETTLE_26M_CTL) %LE %LONG 0x17920803
+
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_CLK_DUMMY) %LE %LONG 0x00DFFFFF
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_PLL_SRC_SEL) %LE %LONG 0x0
+
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_SHAOLIN_DFS_FLEXCKGEN_SEL) %LE %LONG 0x10 ;; to NRPLL1
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_DFESYNC_FLEXCKGEN_SEL) %LE %LONG 0x11 ;; to BPIPLL
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_HRAM_DFS_FLEXCKGEN_SEL) %LE %LONG 0x30 ;; to NRPLL4_1_CK 800Mhz
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_NR_RXT2F_DFS_FLEXCKGEN_SEL) %LE %LONG 0x01
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_NR_CS_DFS_FLEXCKGEN_SEL) %LE %LONG 0x00
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_NR_CM_DFS_FLEXCKGEN_SEL) %LE %LONG 0x00
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_NR_TXBSRP_DFS_FLEXCKGEN_SEL) %LE %LONG 0x00
+
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_PLL_DIV_EN0) %LE %LONG 0x2F020202
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_PLL_DIV_EN3) %LE %LONG 0x00000003
+
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDBPIPLL_CTL0) %LE %LONG 0x80114EC5 ;; Fixed Fvco = 1800Mhz
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDBRPPLL_CTL0) %LE %LONG 0x801FBB13 ;; Fvco = 3300Mhz. 3300/3 = 1100Mhz more setting in PLL_SEC_SW_VERSION_ENHANCE()
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0) %LE %LONG 0x801D2276 ;; Fvco = 3030Mhz. 3030/3 = 1010Mhz
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_CTL0) %LE %LONG 0x801FBB13 ;; Fvco = 3300Mhz. 3300/3 = 1100Mhz
+
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDPLL_CTL0) %LE %LONG 0x80190000 ;; Fvco = 2600Mhz. 2600/4 = 650Mhz
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDPLL_CTL1) %LE %LONG 0x12
+
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDNRPLL2_CTL1) %LE %LONG 0x12
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDNRPLL3_CTL1) %LE %LONG 0x12
+
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDNRPLL0_CTL0) %LE %LONG 0x80133B13 ;; Fvco = 2000Mhz. 2000/2 = 1000Mhz
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDNRPLL1_CTL0) %LE %LONG 0x801713B1 ;; Fvco = 2400Mhz. 2400/2 = 1200Mhz
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDNRPLL2_CTL0) %LE %LONG 0x801AEC4E ;; Fvco = 2800Mhz. 2800/4 = 700Mhz
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDNRPLL3_CTL0) %LE %LONG 0x80180000 ;; Fvco = 2496Mhz. 2496/4 = 624Mhz
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDNRPLL4_CTL0) %LE %LONG 0x800F6276 ;; Fvco = 1600Mhz. 1600/1 = 1600Mhz
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDNRPLL5_CTL0) %LE %LONG 0x801CD890 ;; Fvco = 3000Mhz. 3000/2 = 1500Mhz
+
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_PLL_ON_CTL) %LE %LONG 0x0;
+
+ wait 1.ms ;;MO_Sync()
+
+ ;; Polling until MDMCUPLL complete frequency adjustment
+ ;; Once MDMCUPLL complete, other PLL should complete too
+ ;;while ((*REG_MDTOP_PLLMIXED_MDMCUPLL_STS >> 14)&0x1);
+ wait 1.ms
+
+ ;; Wait MD bus clock ready
+ ;; Once MD bus ready, other clock should be ready too
+ ;;while ((*REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS & 0x8000) != 0x8000);
+ wait 1.ms
+
+ ;; Switch clock source to PLL
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL) %LE %LONG (Data.Long(&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL)|0x3) ;; switch MDMCU & MD BUS clock to PLL frequency
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL) %LE %LONG (Data.Long(&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL)|0xFFFFFFFC) ;; switch all clock to PLL frequency
+
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL_2) %LE %LONG (Data.Long(&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL_2)|0x4)
+
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_CLKON_CTL) %LE %LONG 0x3; ;; Turn off all SW clock request
+
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_SDF_ATB_CK_CTL) %LE %LONG (Data.Long(&MEM_CLASS:®_MDTOP_CLKSW_SDF_ATB_CK_CTL)|0x1104011) ;; switch SDF clock to PLL frequency
+ wait 1.ms ;;MO_Sync();
+
+ ;; Clear PLL ADJ RDY IRQ fired by initial period adjustment
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ) %LE %LONG 0xFFFF;
+
+ ;; Mask all PLL ADJ RDY IRQ
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK) %LE %LONG 0xFFFF;
+ wait 1.ms ;;MO_Sync();
+
+ ;; Make a record that means MD pll has been initialized.
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_PLL_DUMMY) %LE %LONG &MD_PLL_MAGIC_NUM;
+ wait 1.ms ;;MO_Sync();
+)
+
+
+;; ==== Supplement ====
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Step 5: Custom GPIO settings
+; Margaux Bypass
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+PRINT "Step 5: Custom GPIO settings"
+; DIGRF settings
+&BASE_ADDR_GPIO=(&AP_REG_BASE+0x00005000)
+&GPIO_MODE5_ADDR=(&BASE_ADDR_GPIO+0x350)
+&GPIO_MODE6_ADDR=(&BASE_ADDR_GPIO+0x360)
+&GPIO_MODE7_ADDR=(&BASE_ADDR_GPIO+0x370)
+&GPIO_MODE7_SET_ADDR=(&BASE_ADDR_GPIO+0x374)
+&GPIO_MODE7_CLR_ADDR=(&BASE_ADDR_GPIO+0x378)
+
+; Clear GPIO62(DIGRF_IRQ), GPIO60(MIPI_M_SDATA), GPIO59(MIPI_M_SCLK)
+;;;Data.Set (&MEM_CLASS:&GPIO_MODE7_CLR_ADDR) %LE %LONG 0x07077000
+; Set GPIO62(DIGRF_IRQ), GPIO60(MIPI_M_SDATA), GPIO59(MIPI_M_SCLK)
+;;;Data.Set (&MEM_CLASS:&GPIO_MODE7_SET_ADDR) %LE %LONG 0x01011000
+
+; Check GPIO43~GPIO50 all default value = 4b'0001
+;;;&tmp=Data.Long(&MEM_CLASS:&GPIO_MODE5_ADDR)
+;;;PRINT "[GPIO_MODE5 0x" &GPIO_MODE5_ADDR "].[31:12] = " %HEX &tmp " == 0x1111_1xxx?"
+;;;&tmp=Data.Long(&MEM_CLASS:&GPIO_MODE6_ADDR)
+;;;PRINT "[GPIO_MODE6 0x" &GPIO_MODE6_ADDR "].[31:12] = " %HEX &tmp " == 0xxxx_x111?"
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Step 6: EMI Remap MD<->AP Banks (Rich Chen/Neal Liu for SEC world)
+; Margaux Review Done
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+PRINT "Step 6: EMI Remap MD<->AP Banks (Rich Chen/Neal Liu for SEC world)"
+&BCRM_INFRA_AO=(&AP_REG_BASE+0x00043000)
+
+&ADDR_A=(&AP_REG_BASE+0x00030F00)
+&ADDR_B=(&AP_REG_BASE+0x00030A00)
+Data.Set &MEM_CLASS:&ADDR_A %LE %LONG (Data.Long(&MEM_CLASS:&ADDR_A) & 0xFFFFFFFB)
+Data.Set &MEM_CLASS:&ADDR_B %LE %LONG (Data.Long(&MEM_CLASS:&ADDR_B) | 0x1)
+
+;MD Bank0<->AP Bank4,MD Bank1->AP Bank5,MD Bank4->AP Bank6
+Data.Set &MEM_CLASS:(&BCRM_INFRA_AO+0x00) %LE %LONG 0x02208420 ; MD bank0 1st~3rd 32MB
+Data.Set &MEM_CLASS:(&BCRM_INFRA_AO+0x04) %LE %LONG 0x02509023 ; MD bank0 4th~6th 32MB
+Data.Set &MEM_CLASS:(&BCRM_INFRA_AO+0x08) %LE %LONG 0x02809C26 ; MD bank0 7th~8th 32MB and bank1 1st 32MB
+Data.Set &MEM_CLASS:(&BCRM_INFRA_AO+0x0C) %LE %LONG 0x02B0A829 ; MD bank1 2nd~4th 32MB
+Data.Set &MEM_CLASS:(&BCRM_INFRA_AO+0x10) %LE %LONG 0x02E0B42C ; MD bank1 5th~7th 32MB
+Data.Set &MEM_CLASS:(&BCRM_INFRA_AO+0x14) %LE %LONG 0x0300002F ; MD bank1 8th 32MB and reserved and bank4 1st 32MB
+Data.Set &MEM_CLASS:(&BCRM_INFRA_AO+0x18) %LE %LONG 0x0330C831 ; MD bank4 2nd~4th 32MB
+Data.Set &MEM_CLASS:(&BCRM_INFRA_AO+0x1C) %LE %LONG 0x0360D434 ; MD bank4 5th~7th 32MB
+Data.Set &MEM_CLASS:(&BCRM_INFRA_AO+0x20) %LE %LONG 0x00000037 ; MD bank4 8th 32MB
+
+&USB_CUSTOM_SETTING=(&AP_REG_BASE+0x0020A100)
+Data.Set &MEM_CLASS:&USB_CUSTOM_SETTING %LE %LONG 0x40
+
+PRINT "Settings done..."
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/Coretracer_MT6853_Frequency_Meter.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/Coretracer_MT6853_Frequency_Meter.py
new file mode 100755
index 0000000..98cb7db
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/Coretracer_MT6853_Frequency_Meter.py
@@ -0,0 +1,115 @@
+#;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+## MARGAUX MD Frequency Meter
+#;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+#source D:\Coretracer_MT6885_Frequency_Meter.py
+import sys
+import time
+import os
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+
+#MD Side
+REG_CLKSW_BASE=0xA0150000
+
+#==============Below you should change for each project;====================
+fqmtr_fcksel_32k_index=0x17 #32K clock index
+valid_clk_index=0x13 # Use 0x13==>mdsys_mdcore_ck as a valid clock to reset Frequency Meter
+
+Clock_List=(
+ (0, "AD_MDNRPLL5"), (1, "AD_MDNRPLL4_1"), (2, "AD_MDNRPLL4_0"), (3, "AD_MDNRPLL3"), (4, "AD_MDNRPLL2"),
+ (5, "AD_MDNRPLL1"), (6, "AD_MDNRPLL0"), (7, "MDSYS_NRL2_CLOCK"), (8, "MDRXSYS_DFESYNC_CLOCK"), (9, "MDTOP_F216P7M_CLOCK"),
+ (10, "TRACE_MON_CLOCK"), (11, "MDSYS_216P7M_CLOCK"), (12, "MDRXSYS_RAKE_CLOCK"), (13, "MDRXSYS_BRP_CLOCK"), (14, "MDRXSYS_VDSP_CLOCK"),
+ (15, "MDTOP_LOG_ATB_CLOCK"), (16, "FESYS_CSYS_CLOCK"), (17, "MDSYS_SHAOLIN_CLOCK"), (18, "FESYS_BSI_CLOCK"), (19, "MDSYS_MDCORE_CLOCK"),
+ (20, "MDSYS_BUS2X_NODCM_CLOCK"), (21, "MDSYS_BUS4X_CLOCK"), (22, "MDTOP_DBG_CLOCK"), (23, "MDTOP_F32K_CLOCK"), (24, "AD_MDBPI_PLL_D7"),
+ (25, "AD_MDBPI_PLL_D5"), (26, "AD_MDBPI_PLL_D4"), (27, "AD_MDBPI_PLL_D3"), (28, "AD_MDBPI_PLL_D2"), (29, "AD_MDBRP_PLL"),
+ (30, "AD_MDVDSP_PLL"), (31, "AD_MDMCU_PLL"), (32, "null"), (33, "null"), (34, "null"),
+ (35, "null"), (36, "null"), (37, "null"), (38, "null"), (39, "null"),
+ (40, "null"), (41, "null"), (42, "null"), (43, "null"), (44, "null"),
+ (45, "null"), (46, "DFESYS_RXDFE_BB_CORE_CLOCK"), (47, "AD_MDNRPLL4_2"), (48, "MDTOP_BUS4X_FIXED_CLOCK"), (49, "DA_DRF_26M_CLOCK"),
+ (50, "MDTOP_BUS4X_CLOCK"), (51, "RXCPC_CPC_CLOCK"), (52, "null"), (53, "RXDDMBRP_RXDBRP_CLOCK"), (54, "RXDDMBRP_RXDDM_CLOCK"),
+ (55, "MCORE_MCORE_CLOCK"), (56, "VCOREHRAM_VCORE_CLOCK"), (57, "VCOREHRAM_HRAM_CLOCK"), (58, "FESYS_TXBSRP_CLOCK"), (59, "FESYS_MDPLL_CLOCK"),
+ (60, "TX_CS_NR_RXT2F_NR_CLOCK"), (61, "TX_CS_NR_TXBSRP_NR_CLOCK"), (62, "TX_CS_NR_CM_NR_CLOCK"), (63, "TX_CS_NR_CS_NR_CLOCK") )
+#==============Above you should change for each project;====================
+
+REG_CKMON_CTL=REG_CLKSW_BASE+0x400
+REG_FREQ_METER_CTL=REG_CLKSW_BASE+0x404
+REG_FREQ_METER_XTAL_CNT=REG_CLKSW_BASE+0x408
+REG_FREQ_METER_CKMON_CNT=REG_CLKSW_BASE+0x40C
+
+fqmtr_winset=0x1ff #Frequency Meter Windoiw Setting (= Number of FIXED clock cycle)
+fqmtr_winset_for_32k=0x1E000
+
+#Frequency Meter FIXED clock selection
+fqmtr_fcksel_val=26 #Select 26Mhz by default
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ mem_value = mem_value[12:23]
+ hex_int = int(mem_value, 16)
+ return hex_int
+
+def fqmtr_query(idx, clock_name):
+ #print("Running fqmtr_query() %s idx=%d"%(clock_name, idx))
+ if idx>=64 or idx<0 or clock_name=="null":
+ return
+ else:
+ #select source to a valid clock to let reset success.
+ memory_write(REG_CKMON_CTL, valid_clk_index)
+ memory_write(REG_FREQ_METER_CTL, 0x0) #reset frequency meter
+ time.sleep(1)
+
+ if idx==fqmtr_fcksel_32k_index: #measure 32K
+ unit="Khz"
+ fqmtr_winset_26M=fqmtr_winset_for_32k
+ safe_wait_cnt_max=50 #50 * 0.1 =5 sec
+ memory_write(REG_CKMON_CTL, idx) #For accurate, don't div 8 for 32K
+ else: #measure PLL and other module
+ unit="Mhz"
+ fqmtr_winset_26M=fqmtr_winset
+ safe_wait_cnt_max=1 #1 * 0.1 = 0.1 sec
+ memory_write(REG_CKMON_CTL, idx|0x300) #div 8 and select src
+
+ memory_write(REG_FREQ_METER_XTAL_CNT, fqmtr_winset_26M)
+ memory_write(REG_FREQ_METER_CTL, 1) #enable frequency meter
+ safe_wait_cnt=0
+
+ while memory_read(REG_FREQ_METER_CTL)&0x2==0:
+ safe_wait_cnt+=1
+ if safe_wait_cnt==safe_wait_cnt_max:
+ print("%2d.(0x%-2X) %-26s Wait Fail"%(idx , idx, clock_name))
+ return
+ time.sleep(0.1)
+
+ #Calculate the result
+ fqmtr_result_raw=memory_read(REG_FREQ_METER_CKMON_CNT)
+
+ if idx==fqmtr_fcksel_32k_index: #measure 32K
+ fqmtr_result=fqmtr_result_raw*fqmtr_fcksel_val*(0x3E8)/(fqmtr_winset_26M+3)
+ else: #measure PLL and other module
+ fqmtr_result=fqmtr_result_raw*fqmtr_fcksel_val*(8)/(fqmtr_winset_26M+3)
+
+ print("%2d.(0x%-2X) %-25s %4d%s"%(idx, idx, clock_name, fqmtr_result, unit))
+
+if __name__ == "__main__":
+ print("Note: The Error Rate of Frequency Meter is +/-1 MHz!!")
+ #print("sys.argv=%s, len(sys.argv)=%d"%(sys.argv, len(sys.argv)))
+ input=64
+
+ if 0<=input<64:#Only measure specified clock
+ fqmtr_query(Clock_List[input][0], Clock_List[input][1])
+ else:#measure all
+ for index, name in Clock_List:
+ #print("Running main() %s index=%d"%(name, index))
+ fqmtr_query(index, name)
+
+ print("===========Done=============\n\n")
+
+
+
+
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/MT6853.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/MT6853.launch
new file mode 100755
index 0000000..deccc8e
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/MT6853.launch
@@ -0,0 +1,58 @@
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+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value="hb general_ex_handler hb INT_TEMP_general_ex_vector"/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.substitute_path_no_translate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="MT6297_Chip"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="localclock" value="5000"/>
+<booleanAttribute key="org.eclipse.debug.core.capture_output" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_OUTPUT_ON" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="com.mediatek.ide.dsf.gdb.core.launching.MtkGdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/Prepare_Mode_remote.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/Prepare_Mode_remote.launch
new file mode 100755
index 0000000..b574245
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/Prepare_Mode_remote.launch
@@ -0,0 +1,58 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.ui.focus_threads" value=""/>
+<stringAttribute key="com.mediatek.ide.dsf.mvpu.dbg_file" value=""/>
+<stringAttribute key="com.mediatek.ide.dsf.mvpu.imageloader.pattern_file" value=""/>
+<stringAttribute key="com.mediatek.ide.dsf.mvpu.pattern_file" value=""/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value=""/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.cache.FilePath" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.cache.gdbIndexElf" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.RemoteTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.debuggerIpAddress" value="localhost"/>
+<intAttribute key="com.mediatek.ide.util.debuggerPortNumber" value="3667"/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.original.location" value="C:\Users\mtk11711\Downloads\Prepare_Mode_remote.launch"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.substitute_path_no_translate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="Prepare"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="localclock" value="10000"/>
+<booleanAttribute key="org.eclipse.debug.core.capture_output" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_OUTPUT_ON" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="com.mediatek.ide.dsf.gdb.core.launching.MtkGdbProcessFactory"/>
+<stringAttribute key="saved_expressions<seperator>Unknown<seperator>AXI" value="0xa0000000,0xc0022000,0xc0030f00,0xc0030a00,0xc0007000,0xa0310004,0xc0030F00,0xc0030A00,0xc0001f0c,0xc00700a4,0xc00070a4"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/SSButton.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/SSButton.act
new file mode 100755
index 0000000..12d8920
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/SSButton.act
@@ -0,0 +1,14 @@
+<Customize>
+ <Action name="LoadDSP">
+ <GDBSource>coretracer_load_dsp.py</GDBSource>
+ </Action>
+ <Action name="SWLA">
+ <GDBSource>coretracer_swla.py</GDBSource>
+ </Action>
+ <Action name="restoreCallStack">
+ <GDBSource>coretracer_restore_callstack.py</GDBSource>
+ </Action>
+ <Action name="DspExceptionInfo">
+ <GDBSource>../../../dsp_debug_info_CoreTracer.py</GDBSource>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/TCF.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/TCF.py
new file mode 100755
index 0000000..bb8c771
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/TCF.py
@@ -0,0 +1,172 @@
+import getopt
+from multiprocessing import Queue
+import socket
+import sys
+from threading import Thread
+import time
+
+SPLITTER = '\x00'
+EOL = '\x03\x01'
+HEADER = '\x03\x03'
+LEN_EOL = len((SPLITTER + EOL))
+
+class Event():
+ def __init__(self, args):
+ b = bytearray(args).split(SPLITTER.encode('utf_8'))
+ self.servicename = b[1]
+ self.eventname = b[2]
+ self.data = b[3]
+ self.elements = b[3:]
+
+ def getServiceName(self):
+ return self.servicename.decode('utf_8')
+
+ def getEventName(self):
+ return self.eventname.decode('utf_8')
+
+ def getData(self):
+ return self.data.decode('utf_8')
+
+ def getElement(self, index):
+ if len(self.elements) == 0:
+ return ''
+ return self.elements[index]
+
+ def toString(self):
+ datastr = ''
+ for b in self.elements:
+ if not b == EOL:
+ datastr = datastr + ' ' + b.decode('utf_8')
+ return 'Event ' + self.getServiceName() + ' ' + self.getEventName() + ' ' + datastr
+
+class Result():
+ def __init__(self, args):
+ b = bytearray(args).split(SPLITTER.encode('utf_8'))
+ self.type = b[0]
+ self.token = b[1]
+ self.data = b[2]
+ self.elements = b[2:]
+
+ def getType(self):
+ return self.type.decode('utf_8')
+
+ def getToken(self):
+ return self.token.decode('utf_8')
+
+ def getData(self):
+ return self.data.decode('utf_8')
+
+ def getElement(self, index):
+ if len(self.elements) == 0:
+ return ''
+ return self.elements[index]
+
+ def toString(self):
+ datastr = ''
+ for b in self.elements:
+ if not b == EOL:
+ datastr = datastr + ' ' + b.decode('utf_8')
+ return self.getType() + ' ' + self.getToken() + ' ' + datastr
+
+class TCFThread(Thread):
+ def __init__(self, host='localhost', port='1534'):
+ Thread.__init__(self)
+ try:
+ opts, args = getopt.getopt(sys.argv[1:],"h:p:",["host=","port="])
+ for opt, arg in opts:
+ if opt in ("-h", "--host"):
+ host = arg
+ elif opt in ("-p", "--port"):
+ port = int(arg)
+ except getopt.GetoptError:
+ pass
+ self.tcf_terminator = (SPLITTER + EOL).encode('utf_8')
+ self.tcf = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+ self.tcf.connect((host, int(port)))
+ self.queue = Queue()
+ self.send(['E','Locator','Hello','["ZeroCopy"]'])
+
+ def run(self):
+ remain = None
+ while 1:
+ try:
+ data = self.tcf.recv(1024)
+ if remain == None:
+ remain = data
+ else:
+ remain = remain + data
+
+ if bytearray(data).endswith(self.tcf_terminator):
+ res, rem = getData(remain)
+ if bytearray(res).startswith('E'.encode('utf_8')):
+ self.queue.put(Event(res))
+ elif bytearray(res).startswith('R'.encode('utf_8')):
+ self.queue.put(Result(res))
+ remain = rem
+ except:
+ break
+ time.sleep(0.1)
+ self.tcf.close()
+
+ def get(self):
+ if not self.queue.empty():
+ return self.queue.get()
+ else:
+ return None
+
+ def send(self, args):
+ for arg in args:
+ self.tcf.send(str(arg + SPLITTER).encode('utf_8'))
+ self.tcf.send(EOL.encode('utf_8'))
+
+ def rawsend(self, rawarg):
+ self.tcf.send(rawarg)
+
+ def close(self):
+ self.tcf.shutdown(1)
+ self.tcf.close()
+
+def getData(arg):
+ data = bytearray(arg)
+ result = None
+ remain = None
+ if data.startswith(HEADER.encode('utf_8')):
+ ind = data.index(HEADER.encode('utf_8'))+2
+ leng, cnt = getDataLength(data, ind, 0)
+ ind = ind + cnt + 1
+ result = data[ind:ind+leng-1]
+ remain = data[ind+leng-1:]
+ else:
+ ind = data.index((SPLITTER + EOL).encode('utf_8'))
+ if not ind == -1:
+ result = data[:ind]
+ remain = data[ind:]
+ else:
+ result = None
+ remain = data
+
+ if not remain == None and bytearray(remain).startswith((SPLITTER + EOL).encode('utf_8')):
+ remain = remain[LEN_EOL:]
+
+# print('result: \'' + str(result) + '\'')
+# print('remain: \'' + str(remain) + '\'')
+# sys.stdout.flush()
+ return result, remain
+
+def getDataLength(_rec, ind, count):
+ rec_bytes = bytearray(_rec);
+ leng = rec_bytes[ind]
+ mulp = 0
+ if count == 0:
+ mulp = 1
+ else:
+ mulp = 128 * count
+
+ if leng & 0x80 == 0:
+ return leng * mulp, count
+ else:
+ num, cnt = getDataLength(rec_bytes, ind + 1, count + 1)
+ return ((leng & 0x7f) * mulp) + num, cnt
+
+def doEcaspe(arg):
+ return str(arg).replace('\\', '\\\\').replace('\"', '\\\"')
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/TCF.pyc b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/TCF.pyc
new file mode 100755
index 0000000..f47f3c8
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/TCF.pyc
Binary files differ
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/coretracer_PMIC_Golden_Setting_Dump_MT6853.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/coretracer_PMIC_Golden_Setting_Dump_MT6853.py
new file mode 100755
index 0000000..50f5177
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/coretracer_PMIC_Golden_Setting_Dump_MT6853.py
@@ -0,0 +1,93 @@
+#;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+## MARGAUX PMIC Golden Setting Dump
+#;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+import sys
+import time
+import os
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+
+#MD Side
+AP_REG_BASE=0xC0000000
+MD_REG_BASE=0xA0000000
+
+
+# (Name, Reg, Mask, checkvalue)
+PMIC_List=(
+#"=== SRCLKEN_O1 Check ==="
+#("PRINT_TITLE", "=== SRCLKEN_O1 Check ==="),
+#("RC_MISC_0", 0xC00065B4, 0x1, 0x3),
+
+#"=== CLOCK & RESET ==="
+("PRINT_TITLE", "=== CLOCK & RESET ==="),
+("MODULE_SW_CG_0_STA", 0xC0001090, 0x970F, 0x0),
+("PMICW_CLOCK_CTRL", 0xC0001108, 0xF, 0x0),
+#("ULPOSC_CON", 0xC0006420, 0x8, 0x0),
+("INFRA_GLOBALCON_RST2_STA", 0xC0001148, 0x1, 0x0),
+
+#"=== GPIO ==="
+("PRINT_TITLE", "=== GPIO ==="),
+("GPIO_GPIO_MODE18", 0xC0005420, 0x7777000, 0x1111000),
+#("IOCFG_LM_DRV_CFG1", 0xC1E20010, 0x7, 0x0),
+
+#"=== PMIC_WRAP ==="
+("PMIF_SPI_PMIF_INIT_DONE", 0xC0026000, 0xFFFFFFFF, 0x1),
+("PMIF_SPI_PMIF_ARB_EN", 0xC0026150, 0x7FEF, 0x776F),
+("PMIF_SPI_PMIF_CMDISSUE_EN", 0xC00263B8, 0xFFFFFFFF, 0x1),
+("SWINF_0_INIT_DONE", 0xC0026C28, 0x8001, 0x8001),
+("SWINF_2_INIT_DONE", 0xC0026CA8, 0x8001, 0x8001),
+
+
+)
+#==============Above you should change for each project;====================
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ mem_value = mem_value[12:23]
+ hex_int = int(mem_value, 16)
+ return hex_int
+
+def MO_Port_Enable():
+ print("MO port enable ..")
+ """
+ enable shaolin MO port
+ """
+ memory_write(0x1F000020, 0xF)
+ memory_write(0x1F000090, 0xA0000000)
+ memory_write(0x1F000098, 0xE0000002)
+ memory_write(0x1F0000A0, 0xC0000000)
+ memory_write(0x1F0000A8, 0xC0000002)
+
+
+def golden_setting_query(name_str, reg_addr, reg_mask, match_value):
+ temp_val = memory_read(reg_addr)
+ if((temp_val & reg_mask) != match_value):
+ print("FAIL!! " + name_str + " " + str(hex(reg_addr)) + " = " + str(hex(temp_val)))
+ else:
+ print("PASS!! " + name_str + " " + str(hex(reg_addr)) + " = " + str(hex(temp_val)))
+
+
+if __name__ == "__main__":
+ print("Start PMIC Golden Setting Dump")
+
+ # If you need to dump before MD init, please enable this.
+ #MO_Port_Enable()
+
+ for i in range(len(PMIC_List)):
+ if(PMIC_List[i][0] == "PRINT_TITLE"):
+ print(PMIC_List[i][1])
+ else:
+ golden_setting_query(PMIC_List[i][0], PMIC_List[i][1], PMIC_List[i][2], PMIC_List[i][3])
+
+ print("===========Done=============\n\n")
+
+
+
+
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/coretracer_basic_init.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/coretracer_basic_init.py
new file mode 100755
index 0000000..34a8715
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/coretracer_basic_init.py
@@ -0,0 +1,362 @@
+import sys
+import time
+import os
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+
+#MD Side
+AP_REG_BASE=0xC0000000
+MD_REG_BASE=0xA0000000
+
+#AP side
+#AP_REG_BASE=0x10000000
+#MD_REG_BASE=0x20000000
+
+def switch_to_axi_mode():
+ '''
+ Description:
+ Not Neccesary in Power-on sequence flow
+ To access AXI w/o CPU
+ It will speedup loading code by bypassing CPU.
+ Usage:
+ tinyBL, dummyAP. Do not use in FullLoad.
+ PIC:
+ Coretracer owner (Jessie Kuo / DP2_DM7)
+ Review:
+ Margaux done
+ '''
+ print("Switch to AXI port ..")
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ mem_value = mem_value[12:23]
+ hex_int = int(mem_value, 16)
+ return hex_int
+
+def WDT_Disable():
+ """
+ Description:
+ diable WDT function
+ [in] thread, codescape thread object
+ PIC:
+ MD WDT PIC: Yao Xue
+ AP WDT PIC: Freddy Hsin/OSS1_SS9
+ Review:
+ Margaux done
+ """
+ #MD WDT default off, but still disable again
+ #enable MD WDT: DRV_REG(0XB00F0100) = (0x55 <<24) | (DRV_REG(0XB00F0100) &0x3);
+ #disable MD WDT: DRV_REG(0XB00F0100) = (0x55 <<24) | (DRV_REG(0XB00F0100) & 0xFFFFFFFC);
+
+ print("WDT disable ..")
+ mdrgu = 0xA00F0000 + 0x0100
+ aprgu = 0xC0007000
+ memory_write(mdrgu, (memory_read(mdrgu) & 0xFFFFFFFC) | 0x55000000)
+ memory_write(aprgu, (memory_read(aprgu) & 0xFFFFFFFE) | 0x22000000)
+
+def MD_SRCLKENA():
+ print("MD_SRCLKENA config ..")
+ """
+ Description:
+ INFRA_MISC2 (0x10001F0C)
+ [3:0] : mdsrc_req_0_en = 4'b0001
+ [7:4] : mdsrc_req_1_en = 4'b0010
+ PIC:
+ AP SPM(Fraser Chang)
+ Review:
+ Margaux done
+ """
+ infra_misc2_addr = AP_REG_BASE + 0x1f0c
+ memory_write(infra_misc2_addr, (memory_read(infra_misc2_addr) & 0xFFFFFF00) | 0x21)
+
+ """
+ SRCLKEN_O1 Force RF On
+ PIC: Clare Li/Fraser Chang
+ """
+ addr1 = AP_REG_BASE + 0x6000
+ addr2 = AP_REG_BASE + 0x6008
+ memory_write(addr1, 0x0B160001) # magic key
+ memory_write(addr2, memory_read(addr2) | (1<<21) ) #set bit[21]
+ """
+ Owner: Albert-ZL Huang
+ Make sure SPM setting HW mode timing.
+ """
+
+def Config_26M_Quality():
+ '''
+ Description:
+ Neccesary in Power-on sequence flow.
+ Cover by MD script in tinyBL.
+ Cover by AP script in dummyAP.
+ Usage:
+ tinyBL
+ PIC:
+ Jun-Ying.Huang/Hanna.Chiang
+ Review:
+ Margaux done
+ '''
+ print("Config 26M Quality ..")
+ addr = AP_REG_BASE + 0xC000
+ #Configure 0xC000C000(MD view AP sys) to 0x15
+ memory_write(addr, 0x15)
+ time.sleep(0.001)
+ #Configure 0xC000C000(MD view AP sys) to 0x15
+ memory_write(addr, 0x17)
+ time.sleep(0.001)
+
+def MD_Remap(adr=None):
+ print("MD EMI Remap ..")
+ """MD reamp config
+ [in] thread, codescape thread object
+ [in] adr, user specific remap address (ap infra memory map view, 32M alignment)
+ default: emi start address
+ """
+ '''
+ Description:
+ Neccesary in Power-on sequence flow.
+ Cover by MD script in tinyBL.
+ Cover by AP script in dummyAP and fullAP.
+ To set AP bus remap setting for MDAP address remapping.
+ It should be config before we load code into EMI.
+ Usage:
+ tinyBL
+ PIC:
+ AP Bus DE (Ryan-CR Yang/Justin Gu)
+ Review:
+ Margaux done
+ '''
+
+ bcrm_infra_ao = AP_REG_BASE + 0x43000
+
+ memory_write((AP_REG_BASE + 0x44F00),(memory_read(AP_REG_BASE + 0x44F00) & 0xFFFFFFFB))
+ memory_write((AP_REG_BASE + 0x44A00),(memory_read(AP_REG_BASE + 0x44A00) | 0x40))
+ # MD bank 0 -> AP bank 4
+ # MD bank 1 -> AP bank 5
+ # MD bank 4 -> AP bank 6
+ memory_write((bcrm_infra_ao + 0x00),( ((0x40000000)>>25)+(((0x42000000)>>25)<<10) + (((0x44000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x04,( ((0x46000000)>>25)+(((0x48000000)>>25)<<10) + (((0x4A000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x08,( ((0x4C000000)>>25)+(((0x4E000000)>>25)<<10) + (((0x50000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x0C,( ((0x52000000)>>25)+(((0x54000000)>>25)<<10) + (((0x56000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x10,( ((0x58000000)>>25)+(((0x5A000000)>>25)<<10) + (((0x5C000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x14,( ((0x5E000000)>>25)+(((0xFFFFFFFF)>>25)<<10) + (((0x60000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x18,( ((0x62000000)>>25)+(((0x64000000)>>25)<<10) + (((0x66000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x1C,( ((0x68000000)>>25)+(((0x6A000000)>>25)<<10) + (((0x6C000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x20,( ((0x6E000000)>>25)+(((0xFFFFFFFF)>>25)<<10) + (((0xFFFFFFFF)>>25)<<20) ) )
+
+
+def MO_Port_Enable():
+ print("MO port enable ..")
+ """
+ enable shaolin MO port
+ """
+ memory_write(0x1F000020, 0xF)
+ memory_write(0x1F000090, 0xA0000000)
+ memory_write(0x1F000098, 0xE0000002)
+ memory_write(0x1F0000A0, 0xC0000000)
+ memory_write(0x1F0000A8, 0xC0000002)
+
+def Petrus_MD_PLL_Init():
+ #http://mtkteams.mediatek.inc/sites/WCT/CD1/DE1_DE2/Shared%20Documents/U3G_U4G%20modemsys/Petrus/Clock/md_global_con_top/06_Sample_C_code/01_mdpll_init/Petrus_mdpll_init_20190606.c
+ '''
+ Description:
+ Not neccesary in Power-on sequence flow. It should cover by MD init flow
+ This API is for Issue support.
+ DSP team may need it to init PLL.
+ Usage:
+ tinyBL, dummyAP. Do not use in FullLoad.
+ PIC:
+ PLL owner(Jun-Ying Huang/SSE_SS3)
+ Review:
+ Margaux noneed to use, no change
+ '''
+ print("MD PLL Init ..")
+ REGBASE_PLLMIXED = MD_REG_BASE+0x140000
+ REGBASE_CLKSW = MD_REG_BASE+0x150000
+
+ # default md_srclken_ack settle time = 150T 32k
+ memory_write(REGBASE_PLLMIXED+0x4, 0x02021C55)
+ # change APBPLL_SETTLE_26M to 0x2f2 => 29us
+ memory_write(REGBASE_PLLMIXED+0x20, 0x17920803)
+
+ #REG_MDTOP_CLKSW_CLK_DUMMY = 0x00DFFFFF
+ memory_write(REGBASE_CLKSW+0xF00, 0x00DFFFFF)
+ #REG_MDTOP_PLLMIXED_PLL_SRC_SEL = 0x0
+ memory_write(REGBASE_PLLMIXED+0x140, 0x0)
+
+
+ memory_write(REGBASE_CLKSW+0x78, 0x10)# Set NRPLL1
+ memory_write(REGBASE_CLKSW+0x5C, 0x11)# Set BPIPLL
+ memory_write(REGBASE_CLKSW+0x8C, 0x30)# Set NRPLL4_1_CK to 800Mhz
+ memory_write(REGBASE_CLKSW+0xAC, 0x01)
+ memory_write(REGBASE_CLKSW+0x84, 0x00)
+ memory_write(REGBASE_CLKSW+0x88, 0x00)
+ memory_write(REGBASE_CLKSW+0xA8, 0x00)
+
+ memory_write(REGBASE_PLLMIXED+0x124, 0x2F020202)
+ memory_write(REGBASE_PLLMIXED+0x130, 0x00000003)
+
+ memory_write(REGBASE_PLLMIXED+0x58, 0x80114EC5) # Fixed Fvco = 1800Mhz
+ memory_write(REGBASE_PLLMIXED+0x50, 0x801FBB13) # Fvco = 3300Mhz. 3300/3 = 1100Mhz
+ memory_write(REGBASE_PLLMIXED+0x48, 0x801D2276) # Fvco = 3030Mhz. 3030/3 = 1010Mhz
+ memory_write(REGBASE_PLLMIXED+0x40, 0x801F189E) # Fvco = 3234Mhz. 3234/3 = 1078Mhz
+
+ memory_write(REGBASE_PLLMIXED+0x98, 0x80190000) # Fvco = 2600Mhz. 2600/4 = 650Mhz
+ memory_write(REGBASE_PLLMIXED+0x9C, 0x12)
+
+ memory_write(REGBASE_PLLMIXED+0x7C, 0x12)
+ memory_write(REGBASE_PLLMIXED+0x84, 0x12)
+
+ memory_write(REGBASE_PLLMIXED+0x68, 0x80133B13)#Fvco = 2000Mhz. 2000/2 = 1000Mhz
+ memory_write(REGBASE_PLLMIXED+0x70, 0x801713B1)#Fvco = 2400Mhz. 2400/2 = 1200Mhz
+ memory_write(REGBASE_PLLMIXED+0x78, 0x801AEC4E)#Fvco = 2800Mhz. 2800/4 = 700Mhz
+ memory_write(REGBASE_PLLMIXED+0x80, 0x80180000)#Fvco = 2496Mhz. 2496/4 = 624Mhz
+ memory_write(REGBASE_PLLMIXED+0x88, 0x800F6276)#Fvco = 1600Mhz. 1600/1 = 1600Mhz
+ memory_write(REGBASE_PLLMIXED+0x90, 0x801CD890)#Fvco = 3000Mhz. 3000/2 = 1500Mhz
+
+ memory_write(REGBASE_PLLMIXED+0x10, 0x0)
+ #----------------------------------------------------
+
+
+ time.sleep(0.01)#MO_Sync
+ # polling untill MDMCUPLL complete freq adjustment
+ time.sleep(0.01)
+ # wait MD bus clock ready
+ time.sleep(0.01)
+
+ #----------------------------------------------
+ #switch clock source to PLL
+ memory_write(REGBASE_CLKSW+0x24, memory_read(REGBASE_CLKSW+0x24) | 0x3) # switch MDMCU & MDBUS clock to PLL freq
+
+ memory_write(REGBASE_CLKSW+0x24, memory_read(REGBASE_CLKSW+0x24) | 0xfffffffc) # switch all clock to PLL freq
+ memory_write(REGBASE_CLKSW+0x28, memory_read(REGBASE_CLKSW+0x28) | 0x4)
+
+ memory_write(REGBASE_CLKSW+0x20, 0x3) # Turn off all SW clock request
+
+ memory_write(REGBASE_CLKSW+0x2c, memory_read(REGBASE_CLKSW+0x2c) | 0x1104011) # switch SDF clock to PLL freq
+
+ memory_write(REGBASE_PLLMIXED+0x314, 0xffff) # Clear PLL ADJ RDY IRQ fired by initial period adjustment
+ memory_write(REGBASE_PLLMIXED+0x318, 0xffff) # Mask all PLL ADJ RDY IRQ
+
+ memory_write(REGBASE_PLLMIXED+0xf00, 0x62970000) # Write PLL magic number
+ return
+
+def PMIC_Power_Latch_disable():
+ '''
+ Description:
+ Not neccesary in Power-on sequence flow.
+ It should cover by AP tinyBL and APCCCI.
+ This API is for md script only flow.
+ We pull high for WDTRST to stop PMIC Booting Watchdog timer(BWDT) counting.
+ Without this, AP and MD will shutdown and boot again.
+ Usage:
+ Must to set in md script only flow.
+ Nice to set in tinyBL for safe.
+ PIC:
+ PMIC owner (Wen Su/OSS1_SS10)
+ AP RGU Owner (Freddy Hsin/OSS1_SS9)
+ Review:
+ Margaux done
+ '''
+ AP_RGU = AP_REG_BASE + 0x7000
+ memory_write(AP_RGU + 0xA4, 0x66000001)
+ return
+
+def GPIO_Custom_Setting():
+ '''
+ Description:
+ Not neccesary in Power-on sequence flow. It should cover by AP tinyBL and APCCCI.
+ This API is for Issue support.
+ If GPIO setting of tinyBL or dummyAP is wrong, we can overwrite it.
+ It is requested by DIGRF owner to add.
+ Usage:
+ md script only flow need it.
+ tinyBL, dummyAP can also be used by user requested.
+ PIC:
+ GPIO owner
+ '''
+ print("UART GPIO setting ..")
+ BASE_ADDR_MDGPIO=AP_REG_BASE+0x5000
+ BASE_ADDR_IOCFG=AP_REG_BASE+0x1F20000
+
+ memory_write(BASE_ADDR_MDGPIO+0x348, 0x770000)
+ memory_write(BASE_ADDR_MDGPIO+0x344, 0x440000)
+
+ memory_write(BASE_ADDR_IOCFG+0x68, 0x60000)
+ memory_write(BASE_ADDR_IOCFG+0x84, 0x20000)
+ return
+
+def USB_Custom_Setting():
+ '''
+ Description:
+ Neccesary in Power-on sequence flow.
+ Covered by MD script in TinyBL
+ Covered by AP script in dummyAP
+
+ Usage:
+ tinyBL
+ PIC:
+ USB owner/AP CCCI
+ Zhiqiang Yu/Xin Huang, Yubing
+ Review:
+ Margaux done
+ '''
+ memory_write(0xC020A100, 0x40)
+
+if __name__ == "__main__":
+ #...Start
+ """
+ Description:
+ Coretracer_basic_init.py is MD script for Bringup.
+ It is basically consisted of two parts.
+ The first is power on sequence, which is based on SD10 released document.
+ The second part is pre-init, which is not related to basic power/clock flow but also important for MD to bringup.
+ Review:
+ Margaux done
+ """
+
+ # Pre-init
+ # access AXI w/o CPU
+ switch_to_axi_mode()
+ # PMIC power latch disable
+ PMIC_Power_Latch_disable()
+ # Re-config MD & AP WDT setting
+ WDT_Disable()
+
+ # Margaux_MD_Power_OnOff_Sequence.ppt
+
+ # Step 1: Configure&Power on Modem Related Buck
+ # No need for MD cmm
+ # Should be done by AP script (tinyBL or dummyAP)
+
+ # Step 2: Configure md_srclkena setting(on)
+ MD_SRCLKENA()
+
+ # Step 3: Power On MD MTCMOS
+ # No need for MD cmm
+ # Should be done by AP script (tinyBL or dummyAP)
+
+ # Step 4 : Configure PLL setting
+ Config_26M_Quality()
+
+
+ # Step 5: Trigger MD MCU to run
+ # MDAP address remapping
+ MD_Remap()
+ # Config address remapping for USB driver
+ USB_Custom_Setting()
+
+ print "All misc config done!"
+
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/coretracer_basic_init_bigram.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/coretracer_basic_init_bigram.py
new file mode 100755
index 0000000..40abc9e
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/coretracer_basic_init_bigram.py
@@ -0,0 +1,334 @@
+import sys
+import time
+import os
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+
+#MD Side
+AP_REG_BASE=0xC0000000
+MD_REG_BASE=0xA0000000
+
+#AP side
+#AP_REG_BASE=0x10000000
+#MD_REG_BASE=0x20000000
+
+def switch_to_axi_mode():
+ '''
+ Description:
+ Not Neccesary in Power-on sequence flow
+ To access AXI w/o CPU
+ It will speedup loading code by bypassing CPU.
+ Usage:
+ tinyBL, dummyAP. Do not use in FullLoad.
+ PIC:
+ Coretracer owner (Jessie Kuo / DP2_DM7)
+ '''
+ print("Switch to AXI port ..")
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ mem_value = mem_value[12:23]
+ hex_int = int(mem_value, 16)
+ return hex_int
+
+def WDT_Disable():
+ """diable WDT function
+ [in] thread, codescape thread object
+ MD WDT PIC: Yao Xue
+ AP WDT PIC: Freddy Hsin/OSS1_SS9
+ """
+ #MD WDT default off, but still disable again
+ #enable MD WDT: DRV_REG(0XB00F0100) = (0x55 <<24) | (DRV_REG(0XB00F0100) &0x3);
+ #disable MD WDT: DRV_REG(0XB00F0100) = (0x55 <<24) | (DRV_REG(0XB00F0100) & 0xFFFFFFFC);
+
+ print("WDT disable ..")
+ mdrgu = 0xA00F0000 + 0x0100
+ aprgu = 0xC0007000
+ memory_write(mdrgu, (memory_read(mdrgu) & 0xFFFFFFFC) | 0x55000000)
+ memory_write(aprgu, (memory_read(aprgu) & 0xFFFFFFFE) | 0x22000000)
+
+def MD_SRCLKENA():
+ print("MD_SRCLKENA config ..")
+ """
+ INFRA_MISC2 (0x10001F0C)
+ [3:0] : mdsrc_req_0_en = 4'b0001
+ [7:4] : mdsrc_req_1_en = 4'b0010
+ PIC: AP SPM(Fraser Chang)
+ """
+ infra_misc2_addr = AP_REG_BASE + 0x1f0c
+ memory_write(infra_misc2_addr, (memory_read(infra_misc2_addr) & 0xFFFFFF00) | 0x21)
+
+ """
+ SRCLKEN_O1 Force RF On
+ PIC: Clare Li/Fraser Chang
+ """
+ addr1 = AP_REG_BASE + 0x6000
+ addr2 = AP_REG_BASE + 0x6008
+ memory_write(addr1, 0x0B160001) # magic key
+ memory_write(addr2, memory_read(addr2) | (1<<21) ) #set bit[21]
+ """
+ Owner: Albert-ZL Huang
+ Make sure SPM setting HW mode timing.
+ """
+
+def Config_26M_Quality():
+ '''
+ Description:
+ Neccesary in Power-on sequence flow.
+ Cover by MD script in tinyBL.
+ Cover by AP script in dummyAP.
+
+ Usage:
+ tinyBL
+ PIC:
+ Jun-Ying.Huang/Hanna.Chiang
+ '''
+ print("Config 26M Quality ..")
+ addr = AP_REG_BASE + 0xC000
+ #Configure 0xC000C000(MD view AP sys) to 0x15
+ memory_write(addr, 0x15)
+ time.sleep(0.001)
+ #Configure 0xC000C000(MD view AP sys) to 0x15
+ memory_write(addr, 0x17)
+ time.sleep(0.001)
+
+def MD_Remap(adr=None):
+ print("MD EMI Remap ..")
+ """MD reamp config
+ [in] thread, codescape thread object
+ [in] adr, user specific remap address (ap infra memory map view, 32M alignment)
+ default: emi start address
+ """
+ '''
+ Description:
+ Neccesary in Power-on sequence flow.
+ Cover by MD script in tinyBL.
+ Cover by AP script in dummyAP and fullAP.
+ To set AP bus remap setting for MDAP address remapping.
+ It should be config before we load code into EMI.
+ Usage:
+ tinyBL
+ PIC:
+ AP Bus DE (Ryan-CR Yang/Justin Gu)
+ '''
+
+ bcrm_infra_ao = AP_REG_BASE + 0x43000
+
+ memory_write((AP_REG_BASE + 0x44F00),(memory_read(AP_REG_BASE + 0x44F00) & 0xFFFFFFFB))
+ memory_write((AP_REG_BASE + 0x44A00),(memory_read(AP_REG_BASE + 0x44A00) | 0x100))
+ # MD bank 0 -> AP bank 4
+ # MD bank 1 -> AP bank 5
+ # MD bank 4 -> AP bank 6
+ memory_write((bcrm_infra_ao + 0x00),( ((0x40000000)>>25)+(((0x42000000)>>25)<<10) + (((0x44000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x04,( ((0x46000000)>>25)+(((0x48000000)>>25)<<10) + (((0x4A000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x08,( ((0x4C000000)>>25)+(((0x4E000000)>>25)<<10) + (((0x50000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x0C,( ((0x52000000)>>25)+(((0x54000000)>>25)<<10) + (((0x56000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x10,( ((0x58000000)>>25)+(((0x5A000000)>>25)<<10) + (((0x5C000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x14,( ((0x5E000000)>>25)+(((0xFFFFFFFF)>>25)<<10) + (((0x60000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x18,( ((0x62000000)>>25)+(((0x64000000)>>25)<<10) + (((0x66000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x1C,( ((0x68000000)>>25)+(((0x6A000000)>>25)<<10) + (((0x6C000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x20,( ((0x6E000000)>>25)+(((0xFFFFFFFF)>>25)<<10) + (((0xFFFFFFFF)>>25)<<20) ) )
+
+
+def MO_Port_Enable():
+ print("MO port enable ..")
+ """
+ enable shaolin MO port
+ """
+ memory_write(0x1F000020, 0xF)
+ memory_write(0x1F000090, 0xA0000000)
+ memory_write(0x1F000098, 0xE0000002)
+ memory_write(0x1F0000A0, 0xC0000000)
+ memory_write(0x1F0000A8, 0xC0000002)
+
+def Petrus_MD_PLL_Init():
+ #http://mtkteams.mediatek.inc/sites/WCT/CD1/DE1_DE2/Shared%20Documents/U3G_U4G%20modemsys/Petrus/Clock/md_global_con_top/06_Sample_C_code/01_mdpll_init/Petrus_mdpll_init_20190606.c
+ '''
+ Description:
+ Not neccesary in Power-on sequence flow. It should cover by MD init flow
+ This API is for Issue support.
+ DSP team may need it to init PLL.
+ Usage:
+ tinyBL, dummyAP. Do not use in FullLoad.
+ PIC:
+ PLL owner(Jun-Ying Huang/SSE_SS3)
+ '''
+ print("MD PLL Init ..")
+ REGBASE_PLLMIXED = MD_REG_BASE+0x140000
+ REGBASE_CLKSW = MD_REG_BASE+0x150000
+
+ # default md_srclken_ack settle time = 150T 32k
+ memory_write(REGBASE_PLLMIXED+0x4, 0x02021C55)
+ # change APBPLL_SETTLE_26M to 0x2f2 => 29us
+ memory_write(REGBASE_PLLMIXED+0x20, 0x17920803)
+
+ #REG_MDTOP_CLKSW_CLK_DUMMY = 0x00DFFFFF
+ memory_write(REGBASE_CLKSW+0xF00, 0x00DFFFFF)
+ #REG_MDTOP_PLLMIXED_PLL_SRC_SEL = 0x0
+ memory_write(REGBASE_PLLMIXED+0x140, 0x0)
+
+
+ memory_write(REGBASE_CLKSW+0x78, 0x10)# Set NRPLL1
+ memory_write(REGBASE_CLKSW+0x5C, 0x11)# Set BPIPLL
+ memory_write(REGBASE_CLKSW+0x8C, 0x30)# Set NRPLL4_1_CK to 800Mhz
+ memory_write(REGBASE_CLKSW+0xAC, 0x01)
+ memory_write(REGBASE_CLKSW+0x84, 0x00)
+ memory_write(REGBASE_CLKSW+0x88, 0x00)
+ memory_write(REGBASE_CLKSW+0xA8, 0x00)
+
+ memory_write(REGBASE_PLLMIXED+0x124, 0x2F020202)
+ memory_write(REGBASE_PLLMIXED+0x130, 0x00000003)
+
+ memory_write(REGBASE_PLLMIXED+0x58, 0x80114EC5) # Fixed Fvco = 1800Mhz
+ memory_write(REGBASE_PLLMIXED+0x50, 0x801FBB13) # Fvco = 3300Mhz. 3300/3 = 1100Mhz
+ memory_write(REGBASE_PLLMIXED+0x48, 0x801D2276) # Fvco = 3030Mhz. 3030/3 = 1010Mhz
+ memory_write(REGBASE_PLLMIXED+0x40, 0x801F189E) # Fvco = 3234Mhz. 3234/3 = 1078Mhz
+
+ memory_write(REGBASE_PLLMIXED+0x98, 0x80190000) # Fvco = 2600Mhz. 2600/4 = 650Mhz
+ memory_write(REGBASE_PLLMIXED+0x9C, 0x12)
+
+ memory_write(REGBASE_PLLMIXED+0x7C, 0x12)
+ memory_write(REGBASE_PLLMIXED+0x84, 0x12)
+
+ memory_write(REGBASE_PLLMIXED+0x68, 0x80133B13)#Fvco = 2000Mhz. 2000/2 = 1000Mhz
+ memory_write(REGBASE_PLLMIXED+0x70, 0x801713B1)#Fvco = 2400Mhz. 2400/2 = 1200Mhz
+ memory_write(REGBASE_PLLMIXED+0x78, 0x801AEC4E)#Fvco = 2800Mhz. 2800/4 = 700Mhz
+ memory_write(REGBASE_PLLMIXED+0x80, 0x80180000)#Fvco = 2496Mhz. 2496/4 = 624Mhz
+ memory_write(REGBASE_PLLMIXED+0x88, 0x800F6276)#Fvco = 1600Mhz. 1600/1 = 1600Mhz
+ memory_write(REGBASE_PLLMIXED+0x90, 0x801CD890)#Fvco = 3000Mhz. 3000/2 = 1500Mhz
+
+ memory_write(REGBASE_PLLMIXED+0x10, 0x0)
+ #----------------------------------------------------
+
+
+ time.sleep(0.01)#MO_Sync
+ # polling untill MDMCUPLL complete freq adjustment
+ time.sleep(0.01)
+ # wait MD bus clock ready
+ time.sleep(0.01)
+
+ #----------------------------------------------
+ #switch clock source to PLL
+ memory_write(REGBASE_CLKSW+0x24, memory_read(REGBASE_CLKSW+0x24) | 0x3) # switch MDMCU & MDBUS clock to PLL freq
+
+ memory_write(REGBASE_CLKSW+0x24, memory_read(REGBASE_CLKSW+0x24) | 0xfffffffc) # switch all clock to PLL freq
+ memory_write(REGBASE_CLKSW+0x28, memory_read(REGBASE_CLKSW+0x28) | 0x4)
+
+ memory_write(REGBASE_CLKSW+0x20, 0x3) # Turn off all SW clock request
+
+ memory_write(REGBASE_CLKSW+0x2c, memory_read(REGBASE_CLKSW+0x2c) | 0x1104011) # switch SDF clock to PLL freq
+
+ memory_write(REGBASE_PLLMIXED+0x314, 0xffff) # Clear PLL ADJ RDY IRQ fired by initial period adjustment
+ memory_write(REGBASE_PLLMIXED+0x318, 0xffff) # Mask all PLL ADJ RDY IRQ
+
+ memory_write(REGBASE_PLLMIXED+0xf00, 0x62970000) # Write PLL magic number
+ return
+
+def PMIC_Power_Latch_disable():
+ '''
+ Description:
+ Not neccesary in Power-on sequence flow.
+ It should cover by AP tinyBL and APCCCI.
+ This API is for md script only flow.
+ We pull high for WDTRST to stop PMIC Booting Watchdog timer(BWDT) counting.
+ Without this, AP and MD will shutdown and boot again.
+ Usage:
+ Must to set in md script only flow.
+ Nice to set in tinyBL for safe.
+ PIC:
+ PMIC owner (Wen Su/OSS1_SS10)
+ AP RGU Owner (Freddy Hsin/OSS1_SS9)
+ '''
+ AP_RGU = AP_REG_BASE + 0x7000
+ memory_write(AP_RGU + 0xA4, 0x66000001)
+ return
+
+def GPIO_Custom_Setting():
+ '''
+ Description:
+ Not neccesary in Power-on sequence flow. It should cover by AP tinyBL and APCCCI.
+ This API is for Issue support.
+ If GPIO setting of tinyBL or dummyAP is wrong, we can overwrite it.
+ It is requested by DIGRF owner to add.
+ Usage:
+ md script only flow need it.
+ tinyBL, dummyAP can also be used by user requested.
+ PIC:
+ GPIO owner
+ '''
+ print "Setting GPIO"
+ memory_write(0xC0005378, 0x7077000)
+ memory_write(0xC0005374, 0x1011000)
+ return
+def Power_ON_BigRam():
+ """power on bigram
+ [in] thread, codescape thread object
+ """
+ # print("Enable MO port...")
+ # memory_write(0x1F000020, 0x0000000F)
+ # memory_write(0x1F000090, 0xA0000000)
+ # memory_write(0x1F000098, 0xE0000002)
+ # memory_write(0x1F0000A0, 0xC0000000)
+ # memory_write(0x1F0000A8, 0xC0000002)
+
+ print("BIGRAM Power ON ...")
+ memory_write(0xAB810008, 0x000007FF)
+ memory_write(0xAB830000, 0x00000001)
+
+ return
+if __name__ == "__main__":
+ #...Start
+
+ # Preinit
+ # access AXI w/o CPU
+ switch_to_axi_mode()
+ # PMIC power latch disable
+ PMIC_Power_Latch_disable()
+ # Re-config MD & AP WDT setting
+ WDT_Disable()
+
+ # Margaux_MD_Power_OnOff_Sequence.ppt
+
+ # Step 1: Configure&Power on Modem Related Buck
+ # No need for MD cmm
+ # Should be done by AP script (tinyBL or dummyAP)
+
+ # Step 2: Configure md_srclkena setting(on)
+ MD_SRCLKENA()
+
+ # Step 3: Power On MD MTCMOS
+ # No need for MD cmm
+ # Should be done by AP script (tinyBL or dummyAP)
+
+ # Step 4 : Configure PLL setting
+ Config_26M_Quality()
+
+
+ # Step 5: Trigger MD MCU to run
+ # MDAP address remapping
+ # NO NEED FOR BIGRAM ONLY lOAD since we won't access EMI.
+ # MD_Remap()
+ # Config address remapping for USB driver
+ # USB_Custom_Setting()
+
+ #No Need to do this part
+ #cover by AP tinyBL and APCCCI
+ GPIO_Custom_Setting()
+
+ #...power on Bigram for TCM only load
+ Power_ON_BigRam()
+ print "All misc config done!"
+
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/coretracer_init_emi.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/coretracer_init_emi.py
new file mode 100755
index 0000000..f44c884
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/coretracer_init_emi.py
@@ -0,0 +1,707 @@
+import sys
+import time
+import os
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+
+#MD Side
+AP_REG_BASE=0xC0000000
+MD_REG_BASE=0xA0000000
+
+#AP side
+#AP_REG_BASE=0x10000000
+#MD_REG_BASE=0x20000000
+
+def switch_to_axi_mode():
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ mem_value = mem_value[12:23]
+ hex_int = int(mem_value, 16)
+ return hex_int
+
+def DRAM_INIT():
+ print("DRAM_INIT ...")
+ tim = time.time()
+
+ # disable md to ap write secure world register protection
+ reg_bak_APC_CON = memory_read(0xC001DF00)
+ reg_bak_MAS_SEC_0 = memory_read(0xC001DB00)
+ memory_write(0xC001DF00, 0x00000000) # APC_CON[2] = DBG_MASK = 0
+ memory_write(0xC001DB00, 0x00010000) # MAS_SEC_0[16] = M16_SEC = 1
+
+ NR_RNKS=1
+ #EMI
+
+ #DRAMC0_NAO
+ #0x10234***
+ #DRAMC0
+ #0x10230***
+ #DRAMC1
+ #0x10240***
+ #DDRPHY0
+ #0x10238***
+ #DDRPHY1
+ #0x10248***
+
+ #EMI setting
+ memory_write(0xC0219000, 0x00001052) # ;0x00025052
+ memory_write(0xC0219060, 0xff000400)
+ memory_write(0xC0219020, 0x00008000)
+ memory_write(0xC0235000, 0x00001012) # ;0x00005053
+ memory_write(0xC0235010, 0x00000001)
+
+
+ #;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ memory_write(0xC0238274, 0xffffffff)
+ memory_write(0xC0248278, 0x00000000)
+ memory_write(0xC0248274, 0xffffffff)
+ memory_write(0xC023829c, 0x38030000)
+ #PLL sel
+
+ memory_write(0xC02381a0, 0x00000000)
+ memory_write(0xC02380a0, 0x00000000)
+ memory_write(0xC0238120, 0x00000000)
+ memory_write(0xC02382ac, 0x80000006)
+ memory_write(0xC02481a0, 0x00000000)
+ memory_write(0xC02480a0, 0x00000000)
+ memory_write(0xC0248120, 0x00000000)
+ memory_write(0xC02482ac, 0x80000006)
+ memory_write(0xC02382a0, 0x00000100) # ;PINMUX
+ memory_write(0xC02482a0, 0x00000100)
+ memory_write(0xC0238264, 0x00400000)
+ memory_write(0xC0238268, 0x00000040)
+ memory_write(0xC0248264, 0x00400000)
+ memory_write(0xC0248268, 0x00000040)
+ memory_write(0xC0238e18, 0x00000000)
+ memory_write(0xC0238f18, 0x01010000)
+ memory_write(0xC0239018, 0x02020000)
+ memory_write(0xC0238e68, 0x04040000)
+ memory_write(0xC0238f68, 0x05050000)
+ memory_write(0xC0239068, 0x06060000)
+ memory_write(0xC0238ec4, 0x00000c00)
+ memory_write(0xC0238fc4, 0x00000c00)
+ memory_write(0xC02393c4, 0x00000c00)
+ memory_write(0xC02394c4, 0x00000c00)
+ memory_write(0xC0238e50, 0x00000000)
+ memory_write(0xC0238f50, 0xbbbbbbbb)
+ memory_write(0xC0239050, 0xbbbbbbbb)
+ memory_write(0xC0238e54, 0x00000000)
+ memory_write(0xC0238f54, 0x0000bb00)
+ memory_write(0xC0239054, 0x0000bb00)
+ memory_write(0xC0248ea0, 0x00000000)
+ memory_write(0xC0248fa0, 0x00bbbbbb)
+ memory_write(0xC02490a0, 0x00bbbbbb)
+ memory_write(0xC0248ea4, 0x00000000)
+ memory_write(0xC0248fa4, 0x00000bbb)
+ memory_write(0xC02490a4, 0x00000bbb)
+ memory_write(0xC0248e00, 0x00000000)
+ memory_write(0xC0248f00, 0xbbbbbbbb)
+ memory_write(0xC0249000, 0xbbbbbbbb)
+ memory_write(0xC0248e04, 0x00000000)
+ memory_write(0xC0248f04, 0x0000bb00)
+ memory_write(0xC0249004, 0x0000bb00)
+ memory_write(0xC0248e50, 0x00000000)
+ memory_write(0xC0248f50, 0xbbbbbbbb)
+ memory_write(0xC0249050, 0xbbbbbbbb)
+ memory_write(0xC0248e54, 0x00000000)
+ memory_write(0xC0248f54, 0x0000bb00)
+ memory_write(0xC0249054, 0x0000bb00)
+ memory_write(0xC0238e1c, 0x00000c00)
+ memory_write(0xC0238f1c, 0x00000c00)
+ memory_write(0xC023901c, 0x00000c00)
+ memory_write(0xC0238e6c, 0x000f0f00)
+ memory_write(0xC0238f6c, 0x000f0f00)
+ memory_write(0xC023906c, 0x000f0f00)
+ memory_write(0xC0248ec4, 0x00000f0f)
+ memory_write(0xC0248fc4, 0x00000f0f)
+ memory_write(0xC02490c4, 0x00000f0f)
+ memory_write(0xC0248e1c, 0x000f0f00)
+ memory_write(0xC0248f1c, 0x000f0f00)
+ memory_write(0xC024901c, 0x000f0f00)
+ memory_write(0xC0248e6c, 0x000f0f00)
+ memory_write(0xC0248f6c, 0x000f0f00)
+ memory_write(0xC024906c, 0x000f0f00)
+ memory_write(0xC0238128, 0x00001010)
+ memory_write(0xC023812c, 0x01111010)
+ memory_write(0xC0238130, 0x010c10d0)
+ memory_write(0xC023812c, 0x03111010)
+ memory_write(0xC02381a4, 0x0000008c)
+ #TINFO="SHL ddrphy chA reset release"
+ memory_write(0xC02381b0, 0x00080010) # ;SER MODE
+ memory_write(0xC0238d04, 0x00000101)
+ memory_write(0xC0238d08, 0x00000101)
+ memory_write(0xC0239204, 0x00000101)
+ memory_write(0xC0239208, 0x00000101)
+ memory_write(0xC02380a4, 0x0000008c)
+ memory_write(0xC02380b0, 0x00080010) # ;SER MODE
+ memory_write(0xC0238c04, 0x00000101)
+ memory_write(0xC0238c08, 0x00000101)
+ memory_write(0xC0239104, 0x00000101)
+ memory_write(0xC0239108, 0x00000101)
+ memory_write(0xC02481a8, 0x00001010)
+ memory_write(0xC02481ac, 0x01111010)
+ memory_write(0xC02481b0, 0x010c10d0)
+ memory_write(0xC02481ac, 0x03111010)
+ memory_write(0xC02480a8, 0x00001010)
+ memory_write(0xC02480ac, 0x01111010)
+ memory_write(0xC02480b0, 0x010c10d0)
+ memory_write(0xC02480ac, 0x03111010)
+ memory_write(0xC0248128, 0x00001010)
+ memory_write(0xC024812c, 0x01111010)
+ memory_write(0xC0248130, 0x010c10d0)
+ memory_write(0xC024812c, 0x03111010)
+ #PLL
+
+ memory_write(0xC0238c18, 0x44000000)
+ memory_write(0xC0239118, 0x04000000)
+ memory_write(0xC0238c98, 0x44000000)
+ memory_write(0xC0239198, 0x04000000)
+ memory_write(0xC0238d18, 0x44000000)
+ memory_write(0xC0239218, 0x04000000)
+ memory_write(0xC0248c18, 0x44000000)
+ memory_write(0xC0249118, 0x04000000)
+ memory_write(0xC0248c98, 0x44000000)
+ memory_write(0xC0249198, 0x04000000)
+ memory_write(0xC0248d18, 0x44000000)
+ memory_write(0xC0249218, 0x04000000)
+ memory_write(0xC0238da0, 0x00000000)
+ memory_write(0xC02392a0, 0x00000000)
+ # DLL
+
+ memory_write(0xC0238124, 0x0000051e)
+ memory_write(0xC02481a4, 0x0000051e)
+ #TINFO="SHL ddrphy chB reset release"
+ memory_write(0xC02480a4, 0x0000051e)
+ memory_write(0xC0248124, 0x0000051e)
+ memory_write(0xC0238194, 0x00660600)
+ memory_write(0xC0238094, 0xc0660600)
+ memory_write(0xC0238114, 0xc0660600)
+ memory_write(0xC0248194, 0xc0660600)
+ memory_write(0xC0248094, 0xc0660600)
+ memory_write(0xC0248114, 0xc0660600)
+ memory_write(0xC02381b8, 0x00180101)
+ memory_write(0xC023826c, 0x00000000)
+ memory_write(0xC02481b8, 0x00180101)
+ memory_write(0xC024826c, 0x00000000)
+ memory_write(0xC0238d14, 0x00000000)
+ memory_write(0xC0239214, 0x00000000)
+ memory_write(0xC0239714, 0x00000000)
+ memory_write(0xC0239c14, 0x00000000)
+ memory_write(0xC0248d14, 0x00000000)
+ memory_write(0xC0249214, 0x00000000)
+ memory_write(0xC0249714, 0x00000000)
+ memory_write(0xC0249c14, 0x00000000)
+
+ time.sleep(0.001)
+
+ memory_write(0xC023800c, 0x006d0000)
+ memory_write(0xC0238180, 0x0000000c)
+ memory_write(0xC0238080, 0x00000009)
+ memory_write(0xC0238100, 0x00000009)
+ memory_write(0xC0248180, 0x00000009)
+ memory_write(0xC0248080, 0x00000009)
+ memory_write(0xC0248100, 0x00000009)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238000, 0x80000000)
+ memory_write(0xC0238004, 0x80000000)
+ memory_write(0xC0238004, 0x00000000)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238da4, 0x00019200)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238194, 0x00660e00)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238094, 0xc0660e00)
+ memory_write(0xC0238114, 0xc0660e00)
+ memory_write(0xC0248194, 0xc0660e00)
+ memory_write(0xC0248094, 0xc0660e00)
+ memory_write(0xC0248114, 0xc0660e00)
+ memory_write(0xC0238284, 0x0000001f)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238124, 0x0001051e)
+ memory_write(0xC02481a4, 0x0001051e)
+ memory_write(0xC02480a4, 0x0001051e)
+ memory_write(0xC0248124, 0x0001051e)
+ memory_write(0xC02382a0, 0x8100018c)
+ memory_write(0xC02482a0, 0x8100018c)
+ memory_write(0xC02381b8, 0x00040101)
+ memory_write(0xC02381b4, 0x00000000)
+ memory_write(0xC02380b4, 0x00000000)
+ memory_write(0xC0238134, 0x00000000)
+ memory_write(0xC0238c1c, 0x00200000) # ; WJ: LP3
+ memory_write(0xC02481b4, 0x00000000)
+ memory_write(0xC02480b4, 0x00000000)
+ memory_write(0xC0248134, 0x00000000)
+ memory_write(0xC0248c1c, 0x00200000) # ; WJ: LP3
+ memory_write(0xC02300dc, 0x00051008)
+ #;D.S EAXI:0x1024000dc %LE %LONG 0x00050008
+ memory_write(0xC0230000, 0x02101000) # ;[24]=LP2_EN , [25]=LP3_EN, [26]=LP4_EN
+ memory_write(0xC0230640, 0xa688049f)
+ memory_write(0xC0230660, 0x00030053)
+ memory_write(0xC023004c, 0x25712000)
+ memory_write(0xC0230680, 0x00000000)
+ memory_write(0xC0230684, 0x00000000)
+ memory_write(0xC0230688, 0x00000000)
+ memory_write(0xC023068c, 0x00000000)
+ memory_write(0xC0230690, 0x11111011)
+ memory_write(0xC0230694, 0x01101111)
+ memory_write(0xC0230698, 0x11111111)
+ memory_write(0xC023069c, 0x11111111)
+ memory_write(0xC02306a0, 0x11111111) # ;TXDLY DQS
+ memory_write(0xC02306a4, 0x66667777)
+ memory_write(0xC023082c, 0x11111111) # ;TXDLY DQ
+ memory_write(0xC0230830, 0x11111111) # ;TXDLY DQM
+ memory_write(0xC0230834, 0x66667777)
+ memory_write(0xC0230838, 0x66667777)
+ #D.S EAXI:0x1023092c %LE %LONG 0x22222222
+ #D.S EAXI:0x10230930 %LE %LONG 0x22222222
+ #D.S EAXI:0x10230934 %LE %LONG 0x66667777
+ #D.S EAXI:0x10230938 %LE %LONG 0x66667777
+ #D.S EAXI:0x10230a2c %LE %LONG 0x22222222
+ #D.S EAXI:0x10230a30 %LE %LONG 0x22222222
+ #D.S EAXI:0x10230a34 %LE %LONG 0x66667777
+ #D.S EAXI:0x10230a38 %LE %LONG 0x66667777
+ memory_write(0xC023081c, 0x00000000)
+ memory_write(0xC0230820, 0x00000000)
+ #D.S EAXI:0x1023091c %LE %LONG 0x00000000
+ #D.S EAXI:0x10230920 %LE %LONG 0x00000000
+ #D.S EAXI:0x10230a1c %LE %LONG 0x00000000
+ #D.S EAXI:0x10230a20 %LE %LONG 0x66666666
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ memory_write(0xC0230200, 0xf0100000) # ;[31]=DQSIEN MODE
+ memory_write(0xC0230048, 0x08000000)
+ memory_write(0xC0230678, 0xc0000000)
+ memory_write(0xC0230600, 0x09030b06)
+ memory_write(0xC0230604, 0x14090901)
+ memory_write(0xC0230608, 0x0c050201)
+ memory_write(0xC023060c, 0x00490019)
+ memory_write(0xC0230614, 0x01000606)
+ memory_write(0xC023061c, 0x02030408)
+ memory_write(0xC0230620, 0x02000400)
+ memory_write(0xC0230648, 0x9007320f)
+ memory_write(0xC0230644, 0x00000b0d) # ;DATLAT
+ memory_write(0xC0230000, 0x02111000) # ;[24]=LP2_EN , [25]=LP3_EN, [26]=LP4_EN
+ memory_write(0xC0230004, 0x20002000)
+ memory_write(0xC0230008, 0x81080000)
+ memory_write(0xC023000c, 0x0002cf13)
+ memory_write(0xC0230010, 0x00000080)
+ memory_write(0xC0230020, 0x00000009)
+ memory_write(0xC0230024, 0x80030000)
+ memory_write(0xC0230038, 0x80000106)
+ memory_write(0xC0230040, 0x3000000c)
+ memory_write(0xC023004c, 0x25714001)
+ memory_write(0xC0230064, 0x25b1f1cf) # ;REFRDIS=1
+ memory_write(0xC02300b0, 0x04300000)
+ memory_write(0xC0230200, 0xf0310000) # ;[31]=DQSIEN MODE
+ memory_write(0xC0230658, 0x21200001)
+ memory_write(0xC0230800, 0x00000002)
+ #D.S EAXI:0x10230900 %LE %LONG 0x00000002
+ #D.S EAXI:0x10230a00 %LE %LONG 0x00000002
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230824, 0x10101010) # ;GATE WINDOW unit:2T
+ memory_write(0xC0230828, 0x17171717)
+ #D.S EAXI:0x10230924 %LE %LONG 0x11111111
+ #D.S EAXI:0x10230928 %LE %LONG 0x42424242
+ #D.S EAXI:0x10230a24 %LE %LONG 0x32323232
+ #D.S EAXI:0x10230a28 %LE %LONG 0x06060606
+ #;D.S EAXI:0x10240a24 %LE %LONG 0x00000000; ;GATE WINDOW unit:2T
+ #;D.S EAXI:0x10240a28 %LE %LONG 0x53535353
+ #;D.S EAXI:0x10240b24 %LE %LONG 0x32323232
+ #;D.S EAXI:0x10240b28 %LE %LONG 0x06060606
+ #;D.S EAXI:0x10240c24 %LE %LONG 0x32323232
+ #;D.S EAXI:0x10240c28 %LE %LONG 0x06060606
+ # 33961 === over_write_setting_begin ===
+ # 33961 === over_write_setting_end ===
+ memory_write(0xC0230034, 0x00731010)
+ memory_write(0xC0230024, 0x80030050)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC023005c, 0x00003f00)
+ memory_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230060, 0x00000000)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC023005c, 0x00000aff)
+ memory_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230060, 0x00000000)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC023005c, 0x00000183)
+ memory_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230060, 0x00000000)
+ memory_write(0xC023005c, 0x00000206) # ;RL/WL
+ memory_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230060, 0x00000000)
+ memory_write(0xC0230028, 0x00000034)
+ memory_write(0xC023005c, 0x00000b03)
+ memory_write(0xC0230060, 0x00000001)
+
+ #=============================RANK1 MRW==================
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #D.S EAXI:0x1023005c %LE %LONG 0x01003f00
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000aff
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000183
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000206; ;RL/WL
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000b03
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #================== end RANK1 MRW =====================
+
+
+ memory_write(0xC0230060, 0x00000000)
+ memory_write(0xC0230024, 0x80030040)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ memory_write(0xC023005c, 0x00000400)
+
+
+
+ memory_write(0xC023064c, 0x00000005)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC023004c, 0x25774001)
+ memory_write(0xC0230034, 0x00731810)
+ memory_write(0xC0230024, 0x80030000)
+ memory_write(0xC0230004, 0x20082000)
+ memory_write(0xC0230058, 0x00000a56)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ memory_write(0xC023064c, 0x00ff0005)
+ memory_write(0xC0230064, 0x25b1f1cf) # ;REFRDIS=1
+ memory_write(0xC0230610, 0x22653055)
+ memory_write(0xC023004c, 0x45774001)
+ memory_write(0xC0230048, 0x48000000)
+ memory_write(0xC023005c, 0x80000400)
+ memory_write(0xC0230038, 0xc0000107)
+ memory_write(0xC023020c, 0x00010002)
+ memory_write(0xC0230204, 0x00014e00)
+ memory_write(0xC0230094, 0x00100000)
+ memory_write(0xC0230098, 0x00004000)
+ memory_write(0xC023009c, 0x12010480)
+ # 54377 === DE initial sequence done ===
+
+ #selftest
+ #D.S EAXI:0x1023009C %LE %LONG 0x02010080
+ #D.S EAXI:0x10230094 %LE %LONG 0x00100000
+ #D.S EAXI:0x10230098 %LE %LONG 0x00004000
+ #D.S EAXI:0x1023009C %LE %LONG 0x82010080
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ # restore md to ap write secure world register protection
+ memory_write(0xC001DB00, reg_bak_MAS_SEC_0) # MAS_SEC_0[16] = M16_SEC = 0
+ memory_write(0xC001DF00, reg_bak_APC_CON) # APC_CON[2] = DBG_MASK = 1
+
+ print("DRAM_INIT -> elapsed time: {:.3f}".format(time.time()-tim))
+
+def MD_Remap(adr=None):
+ """MD reamp config
+ [in] thread, codescape thread object
+ [in] adr, user specific remap address (ap infra memory map view, 32M alignment)
+ default: emi start address
+ """
+
+ inf_emi = 0x80000000 if memory_read(0xA000001C) < 0x08566094 else 0x40000000
+ print("MD_Remap(adr={:#x}) ...".format(inf_emi if adr == None else adr))
+ if adr == None:
+ inf_md = inf_emi
+ else:
+ assert (adr & 0x01FFFFFF) == 0
+ inf_md = adr
+ print("MD_Remap -> md:bank0=>ap:{:#x}, md:bank1=>ap:{:#x}, md:bank4=>ap:{:#x}".format(inf_md, inf_md+0x10000000, inf_emi))
+ # md remap bank 0
+ bnk = inf_md >> 25
+ memory_write(0xC0001300, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ memory_write(0xC0001304, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ memory_write(0xC0001308, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ memory_write(0xC000130c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+ # md remap bank 1
+ bnk = (inf_md+0x10000000) >> 25
+ memory_write(0xC0001310, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ memory_write(0xC0001314, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ memory_write(0xC0001318, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ memory_write(0xC000131c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+ # md remap bank 4
+ bnk = inf_emi >> 25
+ memory_write(0xC0001320, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ memory_write(0xC0001324, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ memory_write(0xC0001328, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ memory_write(0xC000132c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+
+def WDT_Disable():
+ """diable WDT function
+ [in] thread, codescape thread object
+ """
+ print("WDT disable ...")
+ mdrgu = 0xA00F0000 + 0x0100
+ aprgu = 0xC0007000
+ memory_write(mdrgu, (memory_read(mdrgu) & 0xFFFFFFFC) | 0x55000000)
+ memory_write(aprgu, (memory_read(aprgu) & 0xFFFFFFFE) | 0x22000000)
+
+if __name__ == "__main__":
+ switch_to_axi_mode()
+ WDT_Disable()
+ DRAM_INIT()
+ MD_Remap()
+ tEnd = time.time()
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/coretracer_load_dsp.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/coretracer_load_dsp.py
new file mode 100755
index 0000000..96ff456
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/coretracer_load_dsp.py
@@ -0,0 +1,147 @@
+#from imgtec import codescape
+import sys
+import time
+import os
+sys.path.append(os.path.dirname(os.path.realpath(__file__)))
+import gdb
+import binascii
+import Tkinter, tkFileDialog
+from TCF import Event, Result
+import TCF as client
+
+app = None
+dsp_header = 0x0
+dsp_magic = "4d4d4d01"
+
+TCF_HOST = 'localhost'
+TCF_PORT = 1534
+
+def get_tcf_port():
+ global TCF_PORT
+ gdb_cmd = 'show env tcfport'
+ res = gdb.execute(gdb_cmd, to_string=True)
+ TCF_PORT = int(res.split()[2], 0)
+ print "TCF_PORT = " + str(TCF_PORT)
+
+def switch_to_axi_mode():
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def switch_to_apb_mode():
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write off'
+ gdb.execute(gdb_cmd)
+
+def print_to_log(str):
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','log',str+'\n'])
+ tcf.close()
+
+# load dsp bin file
+def load_dsp_bin(dsp_path):
+ global dsp_header
+
+ time_str = time.time()
+ #print_to_log("=== Start to load dsp bin ===")
+ print_to_log("Dsp bin path: " + dsp_path)
+ if(os.path.exists(dsp_path) == False):
+ print_to_log( "DSP bin doesn't exist: %s" %(dsp_path))
+ print_to_log( "[Error] Load DSP bin failed")
+ return
+ else:
+ with open(dsp_path, "rb") as dsp_bin:
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print_to_log( "No header detected, continue")
+ else:
+ dsp_header = 0x200
+ dsp_bin.seek(dsp_header, os.SEEK_SET)
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print_to_log( "Header detected, skip first 512B")
+ else:
+ print_to_log( "DSP header detected at neither 0x0 nor 0x200")
+ print_to_log( "Please check the bin is legal!")
+ print_to_log( "[Error] Load DSP bin failed")
+ return
+ gdb_cmd='thread 1'
+ gdb.execute(gdb_cmd)
+ ## a) need parsing: 0x13a0000 <dsp_bin_ro>
+ ##symbol_name='&dsp_bin_ro'
+ ##dsp_addr = gdb.parse_and_eval(symbol_name)
+ ## b) need parsing: $3 = 0x13a0000
+ ##gdb_cmd='p/x &dsp_bin_ro'
+ ##dsp_addr = gdb.execute(gdb_cmd, False, True)
+ symbol_name='dsp_bin_ro'
+ dsp_addr = gdb.parse_and_eval(symbol_name)
+ dsp_addr = str(dsp_addr.address).split(" ")
+ dsp_addr = int(dsp_addr[0], 16) - dsp_header
+ #print_to_log( hex(dsp_addr) )
+ gdb_cmd = " ".join(['restore', dsp_path, 'binary', hex(dsp_addr), hex(dsp_header)])
+ #print_to_log( gdb_cmd)
+ switch_to_axi_mode()
+ print_to_log( "Load DSP bin ......................")
+ gdb.execute(gdb_cmd)
+ switch_to_apb_mode()
+ time_end = time.time()
+ print_to_log("loading dsp is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+
+class gui_tk(Tkinter.Tk):
+ def __init__(self, parent):
+ Tkinter.Tk.__init__(self, parent)
+ elf_path = ""
+ dsp_path = ""
+ dsp_addr = ""
+ self.file_opt = options = {}
+ options['title'] = 'Choose a file'
+ self.parent = parent
+ self.initialize()
+
+ def initialize(self):
+ self.grid()
+
+ dsp_button = Tkinter.Button(self, text=u"Load DSP bin =>", command=self.dsp_OnButtonClick)
+ dsp_button.grid(column=0, row=4, sticky='W')
+
+ def dsp_OnButtonClick(self):
+ dsp_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(dsp_path) > 0:
+ print_to_log( "You chose %s" % dsp_path)
+ load_dsp_bin(dsp_path)
+ self.quit()
+
+ def quit(self):
+ global app
+ print_to_log( "=== Close DSP Loader ===")
+ app.destroy()
+
+def load_dsp_gui():
+ print_to_log( "=== Start DSP Loader UI ===")
+ global app
+ app = gui_tk(None)
+ app.title('DSP Loader')
+ app.mainloop()
+
+def disable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','disable','["LoadDSP"]'])
+ tcf.close()
+
+def enable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','enable','["LoadDSP"]'])
+ tcf.close()
+
+if __name__ == "__main__":
+ get_tcf_port()
+ disable_button()
+ load_dsp_gui()
+ enable_button()
+
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/coretracer_misc.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/coretracer_misc.py
new file mode 100755
index 0000000..11b9be2
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/coretracer_misc.py
@@ -0,0 +1,70 @@
+import sys
+import time
+import os
+import gdb
+import ctypes
+
+dsp_bin_base = "0x0d500000"
+ramdisk_base = "0x0c500000"
+RAMDISK_SIZE = 0x1000
+EXCEPT_RET = 0xdeaddead
+
+def switch_to_axi_mode():
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def switch_to_apb_mode():
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write off'
+ gdb.execute(gdb_cmd)
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def get_symbol_addr(symbol_name):
+ res = -1
+ try:
+ res = gdb.parse_and_eval(symbol_name)
+ except:
+ return EXCEPT_RET
+
+ return str(res.address).split()[0]
+
+def clean_ram_disk_region():
+ global ramdisk_base
+
+ ram_disk_addr = get_symbol_addr('ram_disk')
+
+ if ram_disk_addr != EXCEPT_RET:
+ print("ram_disk = %s . clean 4K .." % ram_disk_addr)
+ switch_to_axi_mode()
+ for i in range(RAMDISK_SIZE/4):
+ memory_write(int(ram_disk_addr,0)+i*4,0)
+ switch_to_apb_mode()
+ ramdisk_base = ram_disk_addr
+ else:
+ print "There is no ram_disk symbol in this elf!"
+
+def clean_dsp_bin_magic():
+ global dsp_bin_base
+
+ magic_addr = get_symbol_addr('dsp_bin_ro')
+
+ if magic_addr != EXCEPT_RET:
+ print("dsp_bin_addr = %s . write the addr with 0 .." % magic_addr)
+ memory_write(magic_addr, 0)
+ dsp_bin_base = magic_addr
+ else:
+ print "There is no dsp_bin_ro symbol in this elf!"
+
+
+if __name__ == "__main__":
+ print "Check dsp bin magic .."
+ clean_dsp_bin_magic()
+ print "Check ramdisk 4k .."
+ clean_ram_disk_region()
+ print "=================== All process done. You can tigger cpu run or load DSP bin ==================="
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/coretracer_restore_callstack.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/coretracer_restore_callstack.py
new file mode 100755
index 0000000..ff9bcef
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/coretracer_restore_callstack.py
@@ -0,0 +1,188 @@
+import sys
+import time
+import os
+sys.path.append(os.path.dirname(os.path.realpath(__file__)))
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+import struct
+from TCF import Event, Result
+import TCF as client
+EXCEPT_RET = 0xdeaddead
+
+TCF_HOST = 'localhost'
+TCF_PORT = 1534
+
+CPU_CORE_NUM =4
+CPU_PER_CORE_VPE_NUM =3
+CPU_PER_CORE_TC_NUM =6
+
+CPUGPR_NAME = ['zero', 'at', 't4', 't5',
+ 'a0', 'a1', 'a2', 'a3',
+ 'a4', 'a5', 'a6', 'a7',
+ 't0', 't1', 't2', 't3',
+ 's0', 's1', 's2', 's3',
+ 's4', 's5', 's6', 's7',
+ 't8', 't9', 'k0', 'k1',
+ 'gp', 'sp', 'raw_fp', 'ra']
+
+OFFENDING_VPE_NONE = 0xffffffff
+
+def get_tcf_port():
+ global TCF_PORT
+ gdb_cmd = 'show env tcfport'
+ res = gdb.execute(gdb_cmd, to_string=True)
+ TCF_PORT = int(res.split()[2], 0)
+ print "TCF_PORT = " + str(TCF_PORT)
+
+def print_to_log(str):
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','log',str+'\n'])
+ tcf.close()
+
+def disable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','disable','["restoreCallStack"]'])
+ tcf.close()
+
+def enable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','enable','["restoreCallStack"]'])
+ tcf.close()
+
+def refresh_callstack_ui():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','refresh','debug'])
+ tcf.close()
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+
+ return int(mem_value.split()[2], 0)
+
+def register_read(reg):
+ gdb_cmd = 'info register '+ str(reg)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ return int(mem_value.split()[1], 0)
+
+def register_write(reg, set_value):
+ gdb_cmd = 'set $' + str(reg) + ' = ' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def get_symbol_addr(symbol_name):
+ res = -1
+ try:
+ res = gdb.parse_and_eval(symbol_name)
+ except:
+ return EXCEPT_RET
+
+ return str(res.address).split()[0]
+
+def get_variable_value(symbol_name):
+ mem_value = gdb.parse_and_eval(symbol_name)
+ return (mem_value)
+
+def find_offender():
+ print_to_log( "checking vpe status ..")
+ offending_core = OFFENDING_VPE_NONE
+ offending_vpe = OFFENDING_VPE_NONE
+ offending_tc = OFFENDING_VPE_NONE
+ try:
+ offending_core = get_variable_value('sst_offending_coreid')
+ offending_vpe = get_variable_value('sst_offending_vpeid')
+ offending_tc = get_variable_value('sst_offending_tcid')
+ except:
+ return [OFFENDING_VPE_NONE, OFFENDING_VPE_NONE, OFFENDING_VPE_NONE]
+
+ return [offending_core, offending_vpe, offending_tc]
+
+def find_thread_id(core_num, vpe_num, tc_num):
+ gdb_cmd = 'thread find Core {}/VPE {}/TC {}'.format(core_num, vpe_num, tc_num)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ print mem_value
+ return int(mem_value.split()[1], 0)
+
+def switch_thread(tid):
+ gdb_cmd = 'thread '+str(tid)
+ gdb.execute(gdb_cmd)
+
+def restore_thread_callstack(core, vpe, tc): # core0~3, vpe0~2, tc0~1
+ # switch thread
+ thread_id = find_thread_id(core, vpe, vpe*2 + tc)
+ switch_thread(thread_id)
+
+ #print_to_log( "CONT. VPE"+str(core*3+vpe) )
+ vpe_ex_tc = get_variable_value('ex_info[{}][0].tcid'.format(core*3+vpe)) # tc0~5
+
+ #print_to_log('CORE{}/vpe{}/tc{}'.format(core, vpe, tc))
+ if vpe_ex_tc%2 == tc :# offender tc will use ex_info to restore
+ #print_to_log("restore from ex_info_reg ..")
+ # restore GPR from variable ex_info_reg
+ base_addr = get_symbol_addr('ex_info[{}][0].SST_Exception_Regs.GPR'.format(core*3+vpe))
+ #print_to_log("ex_info.GPR base addr = {}".format(base_addr))
+ i=0
+ for reg_name in CPUGPR_NAME:
+ val = memory_read(int(base_addr,0) + i*4)
+ register_write(reg_name, val)
+ i+=1
+ else: # else we use interaptive_state
+ #print_to_log("restore from ex_interaptive_state ..")
+ # restore GPR from variable ex_interaptive_state
+ base_addr = get_symbol_addr('ex_interaptive_state.coreregs[{}].tcregs[{}].GPR'.format(core, tc))
+ i=0
+ for reg_name in CPUGPR_NAME:
+ val = memory_read(int(base_addr,0) + i*4)
+ register_write(reg_name, val)
+ i+=1
+
+ # restore EPC -> PC
+# epc_val = get_variable_value('ex_interaptive_state.coreregs[{}].vperegs[{}].EPC'.format(core, vpe))
+ epc_val = get_variable_value('ex_info[{}][0].SST_Exception_Regs.EPC'.format(core*3+vpe))
+ register_write("pc", epc_val)
+
+ # restore status -> status
+ status_val = get_variable_value('ex_info[{}][0].SST_Exception_Regs.status'.format(core*3+vpe))
+ register_write("status", epc_val)
+
+ return
+
+def restore_callstack(offender):
+ core_num = offender[0]
+ vpe_num = offender[1]%3 # VPE0~VPE2
+ tc_num = offender[2]%2 # TC0~TC1
+ print_to_log("============> Offender is CORE{} VPE{} TC{}".format(core_num, vpe_num, tc_num))
+
+ for core in range(CPU_CORE_NUM):
+ for vpe in range(CPU_PER_CORE_VPE_NUM):
+ print_to_log("Restore CORE{} VPE{} ..".format(core, vpe))
+ for tc in range(2):
+ #print_to_log("Restore CORE{} VPE{} TC{} ..".format(core, vpe, vpe*2 + tc))
+ restore_thread_callstack(core, vpe, tc)
+ refresh_callstack_ui()
+ print_to_log("=== restore call stack finish! ===")
+ return
+
+def main_func():
+ print_to_log("=== start to restore call stack! ===")
+ offender = find_offender()
+ if offender[0] == OFFENDING_VPE_NONE:
+ print_to_log( "This is no any exception happened. Restore abort!")
+ return
+ restore_callstack(offender)
+ return
+
+
+if __name__ == "__main__":
+ get_tcf_port()
+ disable_button()
+ main_func()
+ enable_button()
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/coretracer_swla.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/coretracer_swla.py
new file mode 100755
index 0000000..138ac69
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/coretracer_swla.py
@@ -0,0 +1,309 @@
+import sys
+import time
+import os
+sys.path.append(os.path.dirname(os.path.realpath(__file__)))
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+import struct
+from TCF import Event, Result
+import TCF as client
+
+CORE_NUM = 4
+CORE_TC_NUM = 6
+LAST_COUNT = 100
+
+EXCEPT_RET = 0xdeaddead
+
+TCF_HOST = 'localhost'
+TCF_PORT = 1534
+
+def get_tcf_port():
+ global TCF_PORT
+ gdb_cmd = 'show env tcfport'
+ res = gdb.execute(gdb_cmd, to_string=True)
+ TCF_PORT = int(res.split()[2], 0)
+ print "TCF_PORT = " + str(TCF_PORT)
+
+def print_to_log(str):
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','log',str+'\n'])
+ tcf.close()
+
+def dump_memory(start_addr, end_addr, filename):
+ gdb_cmd = 'dump binary memory '+str(filename)+' '+hex(start_addr)+' '+hex(end_addr)
+ gdb.execute(gdb_cmd)
+
+def switch_to_axi_mode():
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def switch_to_apb_mode():
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write off'
+ gdb.execute(gdb_cmd)
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ #print "[DBG] "+ mem_value
+ return int(mem_value.split()[2], 0)
+
+
+def get_symbol_addr(symbol_name):
+ res = -1
+ try:
+ res = gdb.parse_and_eval(symbol_name)
+ except:
+ return EXCEPT_RET
+
+ return str(res.address).split()[0]
+
+def get_variable_value(symbol_name):
+ mem_value = gdb.parse_and_eval(symbol_name)
+ #print "[DBG] " + str(mem_value)
+ return (mem_value)
+
+WRAP_PATTERN = 0x50415257 # WRAP
+def isBufferWrap(f, total_size, entry_size):
+ seek_offset = total_size - entry_size
+ f.seek(seek_offset)
+ raw_dword = f.read(8)
+ word1, word2 = struct.unpack('II', raw_dword)
+ if word1 == WRAP_PATTERN and word2 == WRAP_PATTERN:
+ return False
+ else:
+ print "WRAP!!"
+ return True
+
+def find_first_idx_cus(f, total_size, entry_size, next_avail_idx):
+ avail_buffer_size = total_size - entry_size
+ if next_avail_idx - LAST_COUNT >= 0:
+ return next_avail_idx - LAST_COUNT
+ else:
+ if not isBufferWrap(f, total_size, entry_size):
+ return 0
+ else:
+ return (avail_buffer_size/entry_size) + (next_avail_idx - LAST_COUNT)
+
+def parse_swla_dump(file_path, entry_size, bin_size, next_avail_idx):
+ f = open(file_path, "rb")
+ #first_idx = find_first_idx(f, bin_size, entry_size, next_avail_idx)
+ first_idx = find_first_idx_cus(f, bin_size, entry_size, next_avail_idx)
+ f.seek(first_idx*entry_size)
+
+ cnt, wrap = 0, 0
+ tmp_list = []
+ for i in range(0, CORE_TC_NUM):
+ tmp_list.append([])
+
+ while True:
+ word = f.read(entry_size)
+ tmp_hash = {}
+ context, frc, raw_coretc = struct.unpack('III', word) #################################### need to modify
+ tmp_hash['frc'], tc, core = hex(frc), raw_coretc >> 8, raw_coretc & 0xff
+
+ if context&0xf0==0xe0:
+ tmp_hash['context'] = "CUS"
+ elif context==0xAAAAAAAA:
+ #print "IRQEND!"
+ tmp_hash['context'] = "IRQEND"
+ tmp_list[tc].append(tmp_hash.copy())
+ elif context>>16==0xAAAA:
+ irq_id = int(context & 0xFFFF)
+ tmp_hash['context'] = "IRQ"+str(irq_id)
+ tmp_list[tc].append(tmp_hash.copy())
+ #print tmp_hash['context']
+ else:
+ char1, char2, char3, char4 = (context&0xff), (context>>8&0xff), (context>>16&0xff), (context>>24&0xff)
+ if char4==0:
+ if char3==0:
+ context_name = chr(char1) + chr(char2)
+ else:
+ context_name = chr(char1) + chr(char2) + chr(char3)
+ else:
+ context_name = chr(char1) + chr(char2) + chr(char3) + chr(char4)
+ tmp_hash['context'] = context_name
+ tmp_list[tc].append(tmp_hash.copy())
+
+ #print str(tc)+", "+tmp_hash['context']+", "+hex(frc)
+
+ cnt +=1
+
+ # WRAP condition
+ if f.tell()==bin_size and wrap==0 :
+ f.seek(0)
+ wrap=1
+ print "CORE"+str(file_idx)+" swla buffer WRAP"
+ #print "seek:" + hex(f.tell()) + " cnt*entry_size = "+hex(cnt*entry_size)
+
+ # check END
+ if f.tell()==next_avail_idx*entry_size:
+ #print "END! cnt="+str(cnt)
+ break
+
+ f.close()
+ return tmp_list
+
+def swla_parse(tc_lvl_list):
+ context_list = {}
+
+ irq_queue = []
+ pre_task, pre_frc = 0, 0
+ for context in tc_lvl_list:
+ context_name = context['context']
+ context_start_frc = context['frc']
+ target_context=""
+ if pre_task != 0:
+ # sys_exec case
+ if pre_task=="IRQEND" and len(irq_queue)==0:
+ target_context = "sys_exec"
+ if not target_context in context_list:
+ context_list[target_context] = []
+ context_list[target_context].append([pre_frc, context_start_frc])
+ # irqend case
+ elif pre_task=="IRQEND":
+ last_irq = irq_queue.pop()
+ target_context = last_irq
+ if not target_context in context_list:
+ context_list[target_context] = []
+ context_list[target_context].append([pre_frc, context_start_frc])
+ else:
+ if "IRQ" in context_name and context_name!="IRQEND": # irq
+ irq_queue.append(context_name)
+
+ target_context = pre_task
+ if not target_context in context_list:
+ context_list[target_context] = []
+ context_list[target_context].append([pre_frc, context_start_frc])
+ if target_context=="IRQEND":
+ print "????"
+ pre_task, pre_frc = context_name, context_start_frc
+
+ #print context_list
+ return context_list.copy()
+
+def main_func():
+ print_to_log("=== Start to parse SWLA information ===")
+ """
+ get swla buffer base address
+ """
+ res = get_symbol_addr('SysProfilerBufferAddress')
+ if res==EXCEPT_RET:
+ print_to_log( "[ERR] this elf does not support SWLA!")
+ return
+
+ swla_buffer_base_addr = int(get_symbol_addr('SysProfilerBufferAddress'), 16)
+ swla_buffer_addr_ary = []
+ for i in range(0, CORE_NUM):
+ swla_buffer_addr_ary.append(memory_read(swla_buffer_base_addr+i*4))
+
+ """
+ get swla entry size
+ """
+ swla_entry_size = get_variable_value("SA_LoggingNodeSize[0]") ##########################################
+ #print "SWLA Entry Size: "+str(swla_entry_size)+" B"
+
+ """
+ get swla next available entry index
+ """
+ swla_buffer_next_avail_index = []
+ for i in range(0, CORE_NUM):
+ swla_buffer_next_avail_index.append(get_variable_value("SA_LoggingOffset["+str(i)+"]"))
+
+ """
+ get swla buffer total size
+ """
+ tmp = get_variable_value("SA_LoggingStop[0]")
+ swla_size = int(str(tmp).split()[0], 0) - swla_buffer_addr_ary[0]
+ print_to_log( "SWLA Buffer Size: "+ hex(swla_size)+" B")
+
+ """
+ dump each core's swla raw buffer
+ """
+ swla_dump_file = []
+
+ switch_to_axi_mode() # switch to AXI mode to speed up (axi mode will not go through CPU -> MUST used in non-cache region)
+ for i in range(0, CORE_NUM):
+ print_to_log( "Dump core"+str(i)+" swla raw buffer ..")
+ s_t = time.time()
+ filename = "core"+str(i)+"_raw_swla.bin"
+ dump_memory(swla_buffer_addr_ary[i], swla_buffer_addr_ary[i]+swla_size, filename)
+ swla_dump_file.append(filename)
+ e_t = time.time()
+ print_to_log("Elapsed time: {:.3f} sec".format(e_t-s_t))
+ switch_to_apb_mode() # switch back
+
+ print "All swla raw dump finish!!"
+
+ #exit()
+ """
+ parse swla raw
+ """
+ output = open("final_swla.log", "w")
+ output.write('met-info [000] 0.0: ms_ud_timeline_header: {"resource": [{"entity-attr": ["Interrupt"], "name": "default"}], "name": "MCU Timeline"}'+"\n")
+ output.write('met-info [000] 0.0: ms_ud_timeline_description: MCU Timeline:HAS_CHILD_TRACE=Y;COPY_TO_TOP=Y'+"\n")
+
+ core_num=0
+ log_index=1
+ for file in swla_dump_file:
+ print_to_log( "Parsing "+file+" ...")
+ s_t = time.time()
+ tc_list = parse_swla_dump(file, swla_entry_size, swla_size, swla_buffer_next_avail_index[core_num])
+ #print tc_list
+ e_t = time.time()
+
+ print_to_log("Elapsed time: {:.3f} sec".format(e_t-s_t))
+ print_to_log( "start to write to final_swla ..")
+ tc_num = 0
+ for tc_content in tc_list:
+ #print tc_content
+ context_list = swla_parse(tc_content)
+ #print context_list
+ vpe_num = tc_num/2
+ for context_name, period_list in context_list.items():
+ isIRQ = "NO"
+ if "IRQ" in context_name:
+ isIRQ = "YES"
+ for period in period_list:
+ #print period
+ start_frc, end_frc = int(period[0],0)*1.0/1000000, int(period[1],0)*1.0/1000000
+ #print start_frc
+ out_str1 = "NULL-0 [000] {:.10f}: MCU Timeline: ".format(start_frc)
+ out_str2 = "'CORE{}%%VPE{}%%TC{}%%{}', 'e': [['{}']], 't': ['{:.10f}', '{:.10f}']".format(core_num, vpe_num, tc_num/2, context_name, isIRQ, start_frc, end_frc)
+ output.write(out_str1+"{'r': "+out_str2+"}\n")
+ log_index+=1
+ tc_num+=1
+
+ core_num+=1
+ #break
+ output.close()
+ print_to_log( '=== SWLA parse finish! Please use MET font-end to open final_swla.log for SWLA view ===')
+ print_to_log( '=== The output filename is "final_swla.log" in the same folder of your elf file ===')
+ return
+
+def disable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','disable','["SWLA"]'])
+ tcf.close()
+
+def enable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','enable','["SWLA"]'])
+ tcf.close()
+
+if __name__ == "__main__":
+ get_tcf_port()
+ disable_button()
+ main_func()
+ enable_button()
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/prepare_mode.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/prepare_mode.launch
new file mode 100755
index 0000000..2b67fdb
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6853/coretracer/prepare_mode.launch
@@ -0,0 +1,64 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
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+<stringAttribute key="com.mediatek.ide.dsf.mvpu.dbg_file" value=""/>
+<stringAttribute key="com.mediatek.ide.dsf.mvpu.pattern_file" value=""/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value=""/>
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+<stringAttribute key="com.mediatek.ide.util.cache.FilePath" value=""/>
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+<intAttribute key="com.mediatek.ide.util.debuggerPortNumber" value="3333"/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
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+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
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+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.substitute_path_no_translate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="Prepare"/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.args" value="-f board/mips/debug_port_swd.cfg -c "adapter_khz 3000""/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.cmds" value=""/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.widget.args" value="{"Clock_3000":"3000"}"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="attach"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
+<booleanAttribute key="org.eclipse.debug.core.capture_output" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_OUTPUT_ON" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+<stringAttribute key="saved_expressions<seperator>Unknown<seperator>APB" value="0xa0638000,0xa0310000"/>
+<stringAttribute key="saved_expressions<seperator>Unknown<seperator>AXI" value="0xa0020000,0xa0630000,0xa0638000,0xa0291e50"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/AP_UART_log_Checker/FullLoad_Checker/FullLoad_Checker.bat b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/AP_UART_log_Checker/FullLoad_Checker/FullLoad_Checker.bat
new file mode 100755
index 0000000..b606ecf
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/AP_UART_log_Checker/FullLoad_Checker/FullLoad_Checker.bat
@@ -0,0 +1,30 @@
+@echo off
+
+echo ...
+echo ...Finding "md1 load fail"...
+findstr /lin /c:"md1 load fail" %~dp0*.txt
+if NOT ERRORLEVEL 1 (
+ echo ...String Found...
+ echo ...load MD img FAILED...
+) else (
+ echo ...String Not Found...
+ echo ...Load MD img SUCCESS...
+)
+
+echo ...
+echo ...Finding "<6>[ 9.419579] .(2)[237:ccci_ctrl][ccci1/fsm]control message 0x0,0x0".....
+findstr /lin /c:"[ccci1/fsm]control message 0x0,0x0" %~dp0*.txt
+if NOT ERRORLEVEL 1 (
+ echo ...String Found...
+) else (
+ echo ...String Not Found...
+)
+
+echo ...
+echo ...Finding "<6>[ 9.426288] .(2)[228:ccci_fsm1][ccci1/fsm]command 1 is completed 1 by fsm_main_thread".....
+findstr /lin /c:"[ccci1/fsm]command 1 is completed 1 by fsm_main_thread" %~dp0*.txt
+if NOT ERRORLEVEL 1 (
+ echo ...String Found...
+) else (
+ echo ...String Not Found...
+)
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/AP_UART_log_Checker/dummyAP_Checker/dummyAP_Checker.bat b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/AP_UART_log_Checker/dummyAP_Checker/dummyAP_Checker.bat
new file mode 100755
index 0000000..c03cdb5
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/AP_UART_log_Checker/dummyAP_Checker/dummyAP_Checker.bat
@@ -0,0 +1,21 @@
+@echo off
+
+echo ...
+echo ...Finding "md1 load fail"...
+findstr /lin /c:"md1 load fail" %~dp0*.txt
+if NOT ERRORLEVEL 1 (
+ echo ...String Found...
+ echo ...load MD img FAILED...
+) else (
+ echo ...String Not Found...
+ echo ...Load MD img SUCCESS...
+)
+
+echo ...
+echo ...Finding "while(1)".....
+findstr /lin /c:"while(1)" %~dp0*.txt
+if NOT ERRORLEVEL 1 (
+ echo ...String Found...
+) else (
+ echo ...String Not Found...
+)
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/CVD/APview_MT6873_Frequency_Meter.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/CVD/APview_MT6873_Frequency_Meter.cmm
new file mode 100644
index 0000000..590bee9
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/CVD/APview_MT6873_Frequency_Meter.cmm
@@ -0,0 +1,764 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; MARGAUX MD Frequency Meter
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;;Select PLL
+LOCAL &key_in
+&key_in=0
+
+LOCAL &opt_cvd_connect
+&opt_cvd_connect="debug"
+
+;;;;;;;;;;;;;;;;;;;;;;;Below you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+LOCAL &mclass ;; Memory Class
+&mclass="axi"
+;&mclass="pm"
+
+LOCAL &clksw_base ;; MD CLKSW base address
+;&clksw_base=0xA0150000 ;; MD view APB
+;&clksw_base=0xA0616000 ;; MD view debug APB
+&clksw_base=0x20150000 ;; AP view MD system bus
+;&clksw_base=0x0D116000 ;; AP view MD debug sys
+
+LOCAL &pll_base ;; MD PLLMIXED base address
+;&pll_base=0xA0140000 ;; MD view APB
+;&pll_base=0xA0614000 ;; MD view debug APB
+&pll_base=0x20140000 ;; AP view MD system bus
+;&pll_base=0x0D114000 ;; AP view MD debug sys
+
+&fqmtr_fcksel_32k_index=0x17
+;;;;;;;;;;;;;;;;;;;;;;;Above you should change for each project;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+LOCAL &fqmtr_winset ;; Frequency Meter Windoiw Setting (= Number of FIXED clock cycle)
+&fqmtr_winset=0x1ff
+&fqmtr_winset_for_32k=0x1E000
+
+LOCAL &fqmtr_fcksel_val ;; Frequency Meter FIXED clock selection
+&fqmtr_fcksel_val=0x1a ;; Select 26Mhz by default
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;All the PLL you could select;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+&SRC_STR_0="AD_MDNRPLL5"
+&SRC_STR_1="AD_MDNRPLL4_1"
+&SRC_STR_2="AD_MDNRPLL4_0"
+&SRC_STR_3="AD_MDNRPLL3"
+&SRC_STR_4="AD_MDNRPLL2"
+&SRC_STR_5="AD_MDNRPLL1"
+&SRC_STR_6="AD_MDNRPLL0"
+&SRC_STR_7="MDSYS_NRL2_CLOCK"
+&SRC_STR_8="MDRXSYS_DFESYNC_CLOCK"
+&SRC_STR_9="MDTOP_F216P7M_CLOCK"
+&SRC_STR_10="TRACE_MON_CLOCK"
+&SRC_STR_11="MDSYS_216P7M_CLOCK"
+&SRC_STR_12="MDRXSYS_RAKE_CLOCK"
+&SRC_STR_13="MDRXSYS_BRP_CLOCK"
+&SRC_STR_14="MDRXSYS_VDSP_CLOCK"
+&SRC_STR_15="MDTOP_LOG_ATB_CLOCK"
+&SRC_STR_16="FESYS_CSYS_CLOCK"
+&SRC_STR_17="MDSYS_SHAOLIN_CLOCK"
+&SRC_STR_18="FESYS_BSI_CLOCK"
+&SRC_STR_19="MDSYS_MDCORE_CLOCK"
+&SRC_STR_20="MDSYS_BUS2X_NODCM_CLOCK"
+&SRC_STR_21="MDSYS_BUS4X_CLOCK"
+&SRC_STR_22="MDTOP_DBG_CLOCK"
+&SRC_STR_23="MDTOP_F32K_CLOCK"
+&SRC_STR_24="AD_MDBPI_PLL_D7"
+&SRC_STR_25="AD_MDBPI_PLL_D5"
+&SRC_STR_26="AD_MDBPI_PLL_D4"
+&SRC_STR_27="AD_MDBPI_PLL_D3"
+&SRC_STR_28="AD_MDBPI_PLL_D2"
+&SRC_STR_29="AD_MDBRP_PLL"
+&SRC_STR_30="AD_MDVDSP_PLL"
+&SRC_STR_31="AD_MDMCU_PLL"
+&SRC_STR_32="null_32"
+&SRC_STR_33="null_33"
+&SRC_STR_34="null_34"
+&SRC_STR_35="null_35"
+&SRC_STR_36="null_36"
+&SRC_STR_37="null_37"
+&SRC_STR_38="null_38"
+&SRC_STR_39="null_39"
+&SRC_STR_40="null_40"
+&SRC_STR_41="null_41"
+&SRC_STR_42="null_42"
+&SRC_STR_43="null_43"
+&SRC_STR_44="null_44"
+&SRC_STR_45="null_45"
+&SRC_STR_46="DFESYS_RXDFE_BB_CORE_CLOCK"
+&SRC_STR_47="AD_MDNRPLL4_2"
+&SRC_STR_48="MDTOP_BUS4X_FIXED_CLOCK"
+&SRC_STR_49="DA_DRF_26M_CLOCK"
+&SRC_STR_50="MDTOP_BUS4X_CLOCK"
+&SRC_STR_51="RXCPC_CPC_CLOCK"
+&SRC_STR_52="null_52"
+&SRC_STR_53="RXDDMBRP_RXDBRP_CLOCK"
+&SRC_STR_54="RXDDMBRP_RXDDM_CLOCK"
+&SRC_STR_55="MCORE_MCORE_CLOCK"
+&SRC_STR_56="VCOREHRAM_VCORE_CLOCK"
+&SRC_STR_57="VCOREHRAM_HRAM_CLOCK"
+&SRC_STR_58="FESYS_TXBSRP_CLOCK"
+&SRC_STR_59="FESYS_MDPLL_CLOCK"
+&SRC_STR_60="TX_CS_NR_RXT2F_NR_CLOCK"
+&SRC_STR_61="TX_CS_NR_TXBSRP_NR_CLOCK"
+&SRC_STR_62="TX_CS_NR_CM_NR_CLOCK"
+&SRC_STR_63="TX_CS_NR_CS_NR_CLOCK"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+DIALOG
+(&
+ HEADER "PLL Frequency Meter"
+ ICON ":chip"
+
+ POS 0. 0. 45. 1.
+ LINE "----------------------------FQMTR Selection(Error Rate: +/- 1Mhz)----------------------------"
+ ; x y w h
+ POS 0. 1. 20. 1.
+ SEL.NONE: CHOOSEBOX "None"
+ (
+ &key_in=0xF00
+ )
+ SEL.0: CHOOSEBOX "&SRC_STR_0"
+ (
+ &key_in=0x0
+ &key_str="&SRC_STR_0"
+ )
+ SEL.1: CHOOSEBOX "&SRC_STR_1"
+ (
+ &key_in=0x1
+ &key_str="&SRC_STR_1"
+ )
+ SEL.2: CHOOSEBOX "&SRC_STR_2"
+ (
+ &key_in=0x2
+ &key_str="&SRC_STR_2"
+ )
+ SEL.3: CHOOSEBOX "&SRC_STR_3"
+ (
+ &key_in=0x3
+ &key_str="&SRC_STR_3"
+ )
+ SEL.4: CHOOSEBOX "&SRC_STR_4"
+ (
+ &key_in=0x4
+ &key_str="&SRC_STR_4"
+ )
+ SEL.5: CHOOSEBOX "&SRC_STR_5"
+ (
+ &key_in=0x5
+ &key_str="&SRC_STR_5"
+ )
+ SEL.6: CHOOSEBOX "&SRC_STR_6"
+ (
+ &key_in=0x6
+ &key_str="&SRC_STR_6"
+ )
+ SEL.7: CHOOSEBOX "&SRC_STR_7"
+ (
+ &key_in=0x7
+ &key_str="&SRC_STR_7"
+ )
+ SEL.8: CHOOSEBOX "&SRC_STR_8"
+ (
+ &key_in=0x8
+ &key_str="&SRC_STR_8"
+ )
+ SEL.9: CHOOSEBOX "&SRC_STR_9"
+ (
+ &key_in=0x9
+ &key_str="&SRC_STR_9"
+ )
+ SEL.10: CHOOSEBOX "&SRC_STR_10"
+ (
+ &key_in=0xA
+ &key_str="&SRC_STR_10"
+ )
+ SEL.11: CHOOSEBOX "&SRC_STR_11"
+ (
+ &key_in=0xB
+ &key_str="&SRC_STR_11"
+ )
+ SEL.12: CHOOSEBOX "&SRC_STR_12"
+ (
+ &key_in=0xC
+ &key_str="&SRC_STR_12"
+ )
+ SEL.13: CHOOSEBOX "&SRC_STR_13"
+ (
+ &key_in=0xD
+ &key_str="&SRC_STR_13"
+ )
+ SEL.14: CHOOSEBOX "&SRC_STR_14"
+ (
+ &key_in=0xE
+ &key_str="&SRC_STR_14"
+ )
+ SEL.15: CHOOSEBOX "&SRC_STR_15"
+ (
+ &key_in=0xF
+ &key_str="&SRC_STR_15"
+ )
+ SEL.16: CHOOSEBOX "&SRC_STR_16"
+ (
+ &key_in=0x10
+ &key_str="&SRC_STR_16"
+ )
+ SEL.17: CHOOSEBOX "&SRC_STR_17"
+ (
+ &key_in=0x11
+ &key_str="&SRC_STR_17"
+ )
+ SEL.18: CHOOSEBOX "&SRC_STR_18"
+ (
+ &key_in=0x12
+ &key_str="&SRC_STR_18"
+ )
+ SEL.19: CHOOSEBOX "&SRC_STR_19"
+ (
+ &key_in=0x13
+ &key_str="&SRC_STR_19"
+ )
+ SEL.20: CHOOSEBOX "&SRC_STR_20"
+ (
+ &key_in=0x14
+ &key_str="&SRC_STR_20"
+ )
+ SEL.21: CHOOSEBOX "&SRC_STR_21"
+ (
+ &key_in=0x15
+ &key_str="&SRC_STR_21"
+ )
+ SEL.22: CHOOSEBOX "&SRC_STR_22"
+ (
+ &key_in=0x16
+ &key_str="&SRC_STR_22"
+ )
+ SEL.23: CHOOSEBOX "&SRC_STR_23"
+ (
+ &key_in=0x17
+ &key_str="&SRC_STR_23"
+ )
+ SEL.24: CHOOSEBOX "&SRC_STR_24"
+ (
+ &key_in=0x18
+ &key_str="&SRC_STR_24"
+ )
+ SEL.25: CHOOSEBOX "&SRC_STR_25"
+ (
+ &key_in=0x19
+ &key_str="&SRC_STR_25"
+ )
+ SEL.26: CHOOSEBOX "&SRC_STR_26"
+ (
+ &key_in=0x1A
+ &key_str="&SRC_STR_26"
+ )
+ SEL.27: CHOOSEBOX "&SRC_STR_27"
+ (
+ &key_in=0x1B
+ &key_str="&SRC_STR_27"
+ )
+ SEL.28: CHOOSEBOX "&SRC_STR_28"
+ (
+ &key_in=0x1C
+ &key_str="&SRC_STR_28"
+ )
+ SEL.29: CHOOSEBOX "&SRC_STR_29"
+ (
+ &key_in=0x1D
+ &key_str="&SRC_STR_29"
+ )
+ SEL.30: CHOOSEBOX "&SRC_STR_30"
+ (
+ &key_in=0x1E
+ &key_str="&SRC_STR_30"
+ )
+ SEL.31: CHOOSEBOX "&SRC_STR_31"
+ (
+ &key_in=0x1F
+ &key_str="&SRC_STR_31"
+ )
+
+ POS 21. 1. 25. 1.
+;; SEL.32: CHOOSEBOX "&SRC_STR_32"
+;; (
+;; &key_in=0x20
+;; &key_str="&SRC_STR_32"
+;; )
+;; SEL.33: CHOOSEBOX "&SRC_STR_33"
+;; (
+;; &key_in=0x21
+;; &key_str="&SRC_STR_33"
+;; )
+ SEL.46: CHOOSEBOX "&SRC_STR_46"
+ (
+ &key_in=0x2E
+ &key_str="&SRC_STR_46"
+ )
+ SEL.47: CHOOSEBOX "&SRC_STR_47"
+ (
+ &key_in=0x2F
+ &key_str="&SRC_STR_47"
+ )
+ SEL.48: CHOOSEBOX "&SRC_STR_48"
+ (
+ &key_in=0x30
+ &key_str="&SRC_STR_48"
+ )
+ SEL.49: CHOOSEBOX "&SRC_STR_49"
+ (
+ &key_in=0x31
+ &key_str="&SRC_STR_49"
+ )
+ SEL.50: CHOOSEBOX "&SRC_STR_50"
+ (
+ &key_in=0x32
+ &key_str="&SRC_STR_50"
+ )
+ SEL.51: CHOOSEBOX "&SRC_STR_51"
+ (
+ &key_in=0x33
+ &key_str="&SRC_STR_51"
+ )
+;; SEL.52: CHOOSEBOX "&SRC_STR_52"
+;; (
+;; &key_in=0x34
+;; &key_str="&SRC_STR_52"
+;; )
+ SEL.53: CHOOSEBOX "&SRC_STR_53"
+ (
+ &key_in=0x35
+ &key_str="&SRC_STR_53"
+ )
+ SEL.54: CHOOSEBOX "&SRC_STR_54"
+ (
+ &key_in=0x36
+ &key_str="&SRC_STR_54"
+ )
+ SEL.55: CHOOSEBOX "&SRC_STR_55"
+ (
+ &key_in=0x37
+ &key_str="&SRC_STR_55"
+ )
+ SEL.56: CHOOSEBOX "&SRC_STR_56"
+ (
+ &key_in=0x38
+ &key_str="&SRC_STR_56"
+ )
+ SEL.57: CHOOSEBOX "&SRC_STR_57"
+ (
+ &key_in=0x39
+ &key_str="&SRC_STR_57"
+ )
+ SEL.58: CHOOSEBOX "&SRC_STR_58"
+ (
+ &key_in=0x3A
+ &key_str="&SRC_STR_58"
+ )
+ SEL.59: CHOOSEBOX "&SRC_STR_59"
+ (
+ &key_in=0x3B
+ &key_str="&SRC_STR_59"
+ )
+ SEL.60: CHOOSEBOX "&SRC_STR_60"
+ (
+ &key_in=0x3C
+ &key_str="&SRC_STR_60"
+ )
+ SEL.61: CHOOSEBOX "&SRC_STR_61"
+ (
+ &key_in=0x3D
+ &key_str="&SRC_STR_61"
+ )
+ SEL.62: CHOOSEBOX "&SRC_STR_62"
+ (
+ &key_in=0x3E
+ &key_str="&SRC_STR_62"
+ )
+ SEL.63: CHOOSEBOX "&SRC_STR_63"
+ (
+ &key_in=0x3F
+ &key_str="&SRC_STR_63"
+ )
+
+ POS 46. 0. 20. 1.
+ LINE "FQMTR Information"
+ INFO1: EDIT "Window Seting: &fqmtr_winset" ""
+ INFO2: EDIT "Fixed Clock: &fqmtr_fcksel_val" ""
+ INFO3: EDIT "32K measure support" ""
+
+ POSY 1. 20. 1.
+ LINE "FQMTR Result"
+ LINE "(Error Rate: +/- 1Mhz)"
+ RESULT: EDIT "" ""
+
+ POSY 1. 20. 1.
+ DEFBUTTON "OK"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ IF &key_in!=0xF00
+ (
+ GOSUB fqmtr_query &key_in &key_str 1
+ )
+ )
+
+ DEFBUTTON "LIST ALL"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ GOSUB fqmtr_list_all
+ )
+
+ DEFBUTTON "Force LIST main clk"
+ (
+ ;; Clear Result
+ DIALOG.Set RESULT ""
+ GOSUB fqmtr_force_list_all
+ )
+
+ CLOSE
+ (
+ PRINT "bye~"
+ DIALOG.END
+ )
+)
+
+ ;; Disable EDIT of showing information
+ DIALOG.Disable INFO1
+ DIALOG.Disable INFO2
+ DIALOG.Disable INFO3
+ ;DIALOG.Disable RESULT
+STOP
+ENDDO
+
+;;;;;The main function to get the Frequency. &idx==> the clock you select, &str==> clock name, &info==>list more info and wait 5ms in the function
+;; &info=1 ==> for printing many PLLs at one time
+fqmtr_query:
+ENTRY &idx &str &info
+(
+ IF &info!=0
+ (
+ PRINT "&str: &idx"
+ PRINT "fqmtrsrc: 0x" FORMAT.HEX(2,&idx)
+ PRINT "opt_cvd_connect: &opt_cvd_connect"
+ )
+
+ LOCAL &unit
+ LOCAL &fqmtr_winset_26M
+ LOCAL &fqmtr_result
+ LOCAL &fqmtr_result_raw
+ LOCAL &fqmtr_result_str
+ LOCAL &safe_wait_cnt
+ LOCAL &safe_wait_cnt_max
+ LOCAL &fqmtr_busy
+
+ &safe_wait_cnt=0
+
+ IF &fqmtr_fcksel_val==0x1a ;; base on 26M, unit:MHz
+ (
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &unit="Khz"
+ &fqmtr_winset_26M=&fqmtr_winset_for_32k
+ &safe_wait_cnt_max=500 ;;5000 ms = 5s ==> in real test, longer than 5s, so reduce it
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &unit="Mhz"
+ &fqmtr_winset_26M=&fqmtr_winset
+ &safe_wait_cnt_max=32 ;;32 ms
+ )
+ )
+ ELSE
+ (
+ &unit=""
+ )
+
+ IF "&opt_cvd_connect"=="none"
+ (
+ sys.m prepare
+ )
+ ELSE IF "&opt_cvd_connect"=="debug"
+ (
+ ; do nothing
+ )
+ ELSE
+ (
+ IF &info!=0
+ (
+ PRINT "No explicit CVD connection, use current status"
+ )
+ )
+
+;; IF &idx==0
+;; (
+ ;; This is used for connect CVD only, no FQMTR test
+;; RETURN
+;; )
+
+ ;;select source to a valid clock to let reset success.
+ Data.Set &mclass:(&clksw_base+0x0400) %LE %LONG 0x13
+ Data.Set &mclass:(&clksw_base+0x0404) %LE %LONG 0x0 ;reset frequency meter
+ WAIT 1ms
+
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ ;;For accurate, don't div 8 for 32K
+ Data.Set &mclass:(&clksw_base+0x0400) %LE %LONG (&idx)
+ )
+ ELSE ;; measure PLL and other module
+ (
+ ;;div 8 and select src
+ Data.Set &mclass:(&clksw_base+0x0400) %LE %LONG (0x0300)|(&idx)
+ )
+
+ Data.Set &mclass:(&clksw_base+0x0408) %LE %LONG &fqmtr_winset_26M
+ Data.Set &mclass:(&clksw_base+0x0404) %LE %LONG 0x1 ;enable frequency meter
+
+ ;; read status, to check polling done or not
+ &fqmtr_busy=DATA.LONG(&mclass:(&clksw_base+0x0404))&(1<<1)
+ WHILE &fqmtr_busy==0
+ (
+ ;PRINT ". &fqmtr_busy"
+ &fqmtr_busy=DATA.LONG(&mclass:(&clksw_base+0x0404))&(1<<1)
+ &safe_wait_cnt=&safe_wait_cnt+1
+ IF &safe_wait_cnt==&safe_wait_cnt_max
+ (
+ PRINT "[&str] Wait Fail, exit"
+ DIALOG.Set RESULT "Wait Fail(No clock), exit"
+ RETURN
+ )
+ ELSE
+ (
+;; PRINT "Waiting result. safe_wait_cnt=" "&safe_wait_cnt"
+ )
+ WAIT 1ms
+ )
+
+ ;; Calculate the result
+ &fqmtr_result_raw=DATA.LONG(&mclass:(&clksw_base+0x40c))
+
+ IF &idx==&fqmtr_fcksel_32k_index ;; measure 32K
+ (
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*(0x3E8)/(&fqmtr_winset_26M+3)
+ )
+ ELSE ;; measure PLL and other module
+ (
+ &fqmtr_result=&fqmtr_result_raw*&fqmtr_fcksel_val*8/(&fqmtr_winset_26M+3)
+ )
+
+ &fqmtr_result_dec=FORMAT.DECIMAL(0,&fqmtr_result)
+ &fqmtr_result_str=""+FORMAT.DECIMAL(0,&fqmtr_result)+" &unit"
+ IF &info==0
+ (
+ PRINT "0x" FORMAT.HEX(2,&idx) ",&fqmtr_result_dec,&unit,&str,&fqmtr_result_raw,"
+ )
+ ELSE
+ (
+ PRINT "Frequency Meter Result: &fqmtr_result_str (&fqmtr_result_raw)"
+ PRINT ""
+ )
+ DIALOG.Set RESULT "&fqmtr_result_str"
+
+ IF &info==0
+ (
+ WAIT 5ms
+ )
+
+ RETURN
+)
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+fqmtr_create_win:
+(
+ AREA.RESet
+ AREA.Create PLL_FMETER
+ AREA.Select PLL_FMETER
+ WinPOS 10.,0.,70.,35.,,, FMETER
+ AREA.view PLL_FMETER
+ AREA.Clear PLL_FMETER
+ RETURN
+)
+
+fqmtr_list_all:
+(
+ GOSUB fqmtr_create_win
+
+ PRINT "Note: The Error Rate of Frequency Meter is +/-1 MHz!!"
+ PRINT ""
+ GOSUB fqmtr_query 0x0 &SRC_STR_0 0
+ GOSUB fqmtr_query 0x1 &SRC_STR_1 0
+ GOSUB fqmtr_query 0x2 &SRC_STR_2 0
+ GOSUB fqmtr_query 0x3 &SRC_STR_3 0
+ GOSUB fqmtr_query 0x4 &SRC_STR_4 0
+ GOSUB fqmtr_query 0x5 &SRC_STR_5 0
+ GOSUB fqmtr_query 0x6 &SRC_STR_6 0
+ GOSUB fqmtr_query 0x7 &SRC_STR_7 0
+ GOSUB fqmtr_query 0x8 &SRC_STR_8 0
+ GOSUB fqmtr_query 0x9 &SRC_STR_9 0
+ GOSUB fqmtr_query 0xA &SRC_STR_10 0
+ GOSUB fqmtr_query 0xB &SRC_STR_11 0
+ GOSUB fqmtr_query 0xC &SRC_STR_12 0
+ GOSUB fqmtr_query 0xD &SRC_STR_13 0
+ GOSUB fqmtr_query 0xE &SRC_STR_14 0
+ GOSUB fqmtr_query 0xF &SRC_STR_15 0
+ GOSUB fqmtr_query 0x10 &SRC_STR_16 0
+ GOSUB fqmtr_query 0x11 &SRC_STR_17 0
+ GOSUB fqmtr_query 0x12 &SRC_STR_18 0
+ GOSUB fqmtr_query 0x13 &SRC_STR_19 0
+ GOSUB fqmtr_query 0x14 &SRC_STR_20 0
+ GOSUB fqmtr_query 0x15 &SRC_STR_21 0
+ GOSUB fqmtr_query 0x16 &SRC_STR_22 0
+ GOSUB fqmtr_query 0x17 &SRC_STR_23 0
+ GOSUB fqmtr_query 0x18 &SRC_STR_24 0
+ GOSUB fqmtr_query 0x19 &SRC_STR_25 0
+ GOSUB fqmtr_query 0x1A &SRC_STR_26 0
+ GOSUB fqmtr_query 0x1B &SRC_STR_27 0
+ GOSUB fqmtr_query 0x1C &SRC_STR_28 0
+ GOSUB fqmtr_query 0x1D &SRC_STR_29 0
+ GOSUB fqmtr_query 0x1E &SRC_STR_30 0
+ GOSUB fqmtr_query 0x1F &SRC_STR_31 0
+; GOSUB fqmtr_query 0x20 &SRC_STR_32 0
+; GOSUB fqmtr_query 0x21 &SRC_STR_33 0
+; GOSUB fqmtr_query 0x22 &SRC_STR_34 0
+; GOSUB fqmtr_query 0x23 &SRC_STR_35 0
+; GOSUB fqmtr_query 0x24 &SRC_STR_36 0
+; GOSUB fqmtr_query 0x25 &SRC_STR_37 0
+; GOSUB fqmtr_query 0x26 &SRC_STR_38 0
+; GOSUB fqmtr_query 0x27 &SRC_STR_39 0
+; GOSUB fqmtr_query 0x28 &SRC_STR_40 0
+; GOSUB fqmtr_query 0x29 &SRC_STR_41 0
+; GOSUB fqmtr_query 0x2A &SRC_STR_42 0
+; GOSUB fqmtr_query 0x2B &SRC_STR_43 0
+; GOSUB fqmtr_query 0x2C &SRC_STR_44 0
+; GOSUB fqmtr_query 0x2D &SRC_STR_45 0
+ GOSUB fqmtr_query 0x2E &SRC_STR_46 0
+ GOSUB fqmtr_query 0x2F &SRC_STR_47 0
+ GOSUB fqmtr_query 0x30 &SRC_STR_48 0
+ GOSUB fqmtr_query 0x31 &SRC_STR_49 0
+ GOSUB fqmtr_query 0x32 &SRC_STR_50 0
+ GOSUB fqmtr_query 0x33 &SRC_STR_51 0
+; GOSUB fqmtr_query 0x34 &SRC_STR_52 0
+ GOSUB fqmtr_query 0x35 &SRC_STR_53 0
+ GOSUB fqmtr_query 0x36 &SRC_STR_54 0
+ GOSUB fqmtr_query 0x37 &SRC_STR_55 0
+ GOSUB fqmtr_query 0x38 &SRC_STR_56 0
+ GOSUB fqmtr_query 0x39 &SRC_STR_57 0
+ GOSUB fqmtr_query 0x3A &SRC_STR_58 0
+ GOSUB fqmtr_query 0x3B &SRC_STR_59 0
+ GOSUB fqmtr_query 0x3C &SRC_STR_60 0
+ GOSUB fqmtr_query 0x3D &SRC_STR_61 0
+ GOSUB fqmtr_query 0x3E &SRC_STR_62 0
+ GOSUB fqmtr_query 0x3F &SRC_STR_63 0
+ RETURN
+)
+
+fqmtr_force_list_all:
+(
+ GOSUB fqmtr_create_win
+
+ PRINT "Note: The Error Rate of Frequency Meter is +/-1 MHz!!"
+ PRINT ""
+
+ LOCAL &original_reg
+ LOCAL &original_reg_clksw_10
+ LOCAL &original_reg_clksw_14
+ LOCAL &original_reg_clksw_18
+ LOCAL &original_reg_clksw_20
+ LOCAL &tmp
+
+ &original_reg=DATA.LONG(&mclass:(&pll_base+0x10))
+
+ ; S/W force on all PLL
+ Data.Set &mclass:(&pll_base+0x10) %LE %LONG 0xFFFFFFFF
+
+ &original_reg_clksw_10=DATA.LONG(&mclass:(&clksw_base+0x10))
+ &original_reg_clksw_14=DATA.LONG(&mclass:(&clksw_base+0x14))
+ &original_reg_clksw_18=DATA.LONG(&mclass:(&clksw_base+0x18))
+ &original_reg_clksw_20=DATA.LONG(&mclass:(&clksw_base+0x20))
+
+ ; S/W force request all module clock
+ Data.Set &mclass:(&clksw_base+0x10) %long %le 0xFFFFFFFF
+ Data.Set &mclass:(&clksw_base+0x14) %long %le 0xFFFFFFFF
+ Data.Set &mclass:(&clksw_base+0x18) %long %le 0xFFFFFFFF
+ &tmp = data.long(&clksw_base+0x20)|(0x10077)
+ Data.Set &mclass:(&clksw_base+0x20) %long %le &tmp
+
+ WAIT 1.s
+
+ GOSUB fqmtr_query 0x0 &SRC_STR_0 0
+ GOSUB fqmtr_query 0x1 &SRC_STR_1 0
+ GOSUB fqmtr_query 0x2 &SRC_STR_2 0
+ GOSUB fqmtr_query 0x3 &SRC_STR_3 0
+ GOSUB fqmtr_query 0x4 &SRC_STR_4 0
+ GOSUB fqmtr_query 0x5 &SRC_STR_5 0
+ GOSUB fqmtr_query 0x6 &SRC_STR_6 0
+ GOSUB fqmtr_query 0x7 &SRC_STR_7 0
+ GOSUB fqmtr_query 0x8 &SRC_STR_8 0
+ GOSUB fqmtr_query 0x9 &SRC_STR_9 0
+ GOSUB fqmtr_query 0xA &SRC_STR_10 0
+ GOSUB fqmtr_query 0xB &SRC_STR_11 0
+ GOSUB fqmtr_query 0xC &SRC_STR_12 0
+ GOSUB fqmtr_query 0xD &SRC_STR_13 0
+ GOSUB fqmtr_query 0xE &SRC_STR_14 0
+ GOSUB fqmtr_query 0xF &SRC_STR_15 0
+ GOSUB fqmtr_query 0x10 &SRC_STR_16 0
+ GOSUB fqmtr_query 0x11 &SRC_STR_17 0
+ GOSUB fqmtr_query 0x12 &SRC_STR_18 0
+ GOSUB fqmtr_query 0x13 &SRC_STR_19 0
+ GOSUB fqmtr_query 0x14 &SRC_STR_20 0
+ GOSUB fqmtr_query 0x15 &SRC_STR_21 0
+ GOSUB fqmtr_query 0x16 &SRC_STR_22 0
+ GOSUB fqmtr_query 0x17 &SRC_STR_23 0
+ GOSUB fqmtr_query 0x18 &SRC_STR_24 0
+ GOSUB fqmtr_query 0x19 &SRC_STR_25 0
+ GOSUB fqmtr_query 0x1A &SRC_STR_26 0
+ GOSUB fqmtr_query 0x1B &SRC_STR_27 0
+ GOSUB fqmtr_query 0x1C &SRC_STR_28 0
+ GOSUB fqmtr_query 0x1D &SRC_STR_29 0
+ GOSUB fqmtr_query 0x1E &SRC_STR_30 0
+ GOSUB fqmtr_query 0x1F &SRC_STR_31 0
+; GOSUB fqmtr_query 0x20 &SRC_STR_32 0
+; GOSUB fqmtr_query 0x21 &SRC_STR_33 0
+; GOSUB fqmtr_query 0x22 &SRC_STR_34 0
+; GOSUB fqmtr_query 0x23 &SRC_STR_35 0
+; GOSUB fqmtr_query 0x24 &SRC_STR_36 0
+; GOSUB fqmtr_query 0x25 &SRC_STR_37 0
+; GOSUB fqmtr_query 0x26 &SRC_STR_38 0
+; GOSUB fqmtr_query 0x27 &SRC_STR_39 0
+; GOSUB fqmtr_query 0x28 &SRC_STR_40 0
+; GOSUB fqmtr_query 0x29 &SRC_STR_41 0
+; GOSUB fqmtr_query 0x2A &SRC_STR_42 0
+; GOSUB fqmtr_query 0x2B &SRC_STR_43 0
+; GOSUB fqmtr_query 0x2C &SRC_STR_44 0
+; GOSUB fqmtr_query 0x2D &SRC_STR_45 0
+ GOSUB fqmtr_query 0x2E &SRC_STR_46 0
+ GOSUB fqmtr_query 0x2F &SRC_STR_47 0
+ GOSUB fqmtr_query 0x30 &SRC_STR_48 0
+ GOSUB fqmtr_query 0x31 &SRC_STR_49 0
+ GOSUB fqmtr_query 0x32 &SRC_STR_50 0
+ GOSUB fqmtr_query 0x33 &SRC_STR_51 0
+; GOSUB fqmtr_query 0x34 &SRC_STR_52 0
+ GOSUB fqmtr_query 0x35 &SRC_STR_53 0
+ GOSUB fqmtr_query 0x36 &SRC_STR_54 0
+ GOSUB fqmtr_query 0x37 &SRC_STR_55 0
+ GOSUB fqmtr_query 0x38 &SRC_STR_56 0
+ GOSUB fqmtr_query 0x39 &SRC_STR_57 0
+ GOSUB fqmtr_query 0x3A &SRC_STR_58 0
+ GOSUB fqmtr_query 0x3B &SRC_STR_59 0
+ GOSUB fqmtr_query 0x3C &SRC_STR_60 0
+ GOSUB fqmtr_query 0x3D &SRC_STR_61 0
+ GOSUB fqmtr_query 0x3E &SRC_STR_62 0
+ GOSUB fqmtr_query 0x3F &SRC_STR_63 0
+
+ ; Revert to original value
+ Data.Set &mclass:(&pll_base+0x10) %LE %LONG &original_reg
+
+ Data.Set &mclass:(&clksw_base+0x10) %LE %LONG &original_reg_clksw_10
+ Data.Set &mclass:(&clksw_base+0x14) %LE %LONG &original_reg_clksw_14
+ Data.Set &mclass:(&clksw_base+0x18) %LE %LONG &original_reg_clksw_18
+ Data.Set &mclass:(&clksw_base+0x20) %LE %LONG &original_reg_clksw_20
+
+ WAIT 1.s
+
+ RETURN
+)
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/CVD/MT6873_MD_Only.cmm b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/CVD/MT6873_MD_Only.cmm
new file mode 100644
index 0000000..39fd916
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/CVD/MT6873_MD_Only.cmm
@@ -0,0 +1,294 @@
+sys.m prepare
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Common Macro
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+&MEM_CLASS="AXI"
+;;; MD DAP ;;;
+;&AP_REG_BASE=0xC0000000
+;&MD_REG_BASE=0xA0000000
+;;; AP DAP ;;;
+&AP_REG_BASE=0x10000000
+&MD_REG_BASE=0x20000000
+;;; Control PLL init ;;;
+&ENABLE_PLL_INIT=0x1
+
+wait 1.ms
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; [Note]:
+;; 1. If AP touching MD, Request DAPC(Neal Liu)/PMS(Hanna Chiang) for access right
+;; Margaux Review On-going
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+&ADDR_A=(&AP_REG_BASE+0x00030F00)
+&ADDR_B=(&AP_REG_BASE+0x00030A00)
+Data.Set &MEM_CLASS:&ADDR_A %LE %LONG (Data.Long(&MEM_CLASS:&ADDR_A) & 0xFFFFFFFB)
+Data.Set &MEM_CLASS:&ADDR_B %LE %LONG (Data.Long(&MEM_CLASS:&ADDR_B) | 0x1)
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Step 0: Disable MD/AP WDT
+; Margaux Review Done
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+PRINT "Step 0: Disable MD/AP WDT"
+&BASE_ADDR_MDRGU=(&MD_REG_BASE+0x000F0100)
+&BASE_ADDR_APRGU=(&AP_REG_BASE+0x00007000)
+Data.Set &MEM_CLASS:(&BASE_ADDR_MDRGU) %LE %LONG ((Data.Long(&MEM_CLASS:&BASE_ADDR_MDRGU)&0xFFFFFFFC)|0x55000000)
+Data.Set &MEM_CLASS:(&BASE_ADDR_APRGU) %LE %LONG ((Data.Long(&MEM_CLASS:&BASE_ADDR_APRGU)&0xFFFFFFFE)|0x22000000)
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Step 0.1: Disable PMIC power latch (Jeter Chen/Brian-py Chen)
+; Margaux Review Done
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+PRINT "Step 0.1: Disable PMIC power latch (Jeter Chen/Brian-py Chen)"
+&BASE_ADDR_APRGU_PMIC_PWR_LATCH=(&AP_REG_BASE+0x00007000+0x000000A4)
+Data.Set &MEM_CLASS:&BASE_ADDR_APRGU_PMIC_PWR_LATCH %LE %LONG 0x66000001
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Step 1: Config MD related Buck (Chao-Kai/Wen Su)
+;; Margaux Review Done
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; AP preloader should set Modem related buck, i.e., void vmd1_pmic_setting_on(void)
+; Settings should be:
+; - VMODEM: 0.8V,
+; - VSRAM_MD: 0.8V,
+; - VNR: 0.8V,
+; - VDIGRF:0.7V
+; Check with preloader/PMIC owner if not set
+; skip
+PRINT "Step 1: Config MD related Buck (Chao-Kai/Wen Su)"
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Step 2: Configure md_srclkena setting (Yuyang/Hank Wang)
+; - Configure md_srclkena strategy to turn on 26M/RF
+; Margaux Review Done
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+PRINT "Step 2: Configure md_srclkena setting (Yuyang/Hank Wang)"
+&INFRA_MISC2=(&AP_REG_BASE+0x00001F0C)
+&BASE_ADDR_APSPM=(&AP_REG_BASE+0x00006000)
+&POWERON_CONFIG_EN=(&BASE_ADDR_APSPM+0x00000000)
+&SPM_POWER_ON_VAL1=(&BASE_ADDR_APSPM+0x00000008)
+
+; [3:0] : mdsrc_req_0_en = 4'b0001, [7:4] : mdsrc_req_1_en = 4'b0010
+Data.Set (&MEM_CLASS:&INFRA_MISC2) %LE %LONG ((Data.Long(&MEM_CLASS:&INFRA_MISC2)&0xFFFFFF00)|0x21)
+
+; set SPM register for clkenal force on
+Data.Set (&MEM_CLASS:&POWERON_CONFIG_EN) %LE %LONG 0x0B160001
+; Set src clkena1 force on, 0x10006008|= 0x1 << 21
+Data.Set (&MEM_CLASS:&SPM_POWER_ON_VAL1) %LE %LONG (Data.Long(&MEM_CLASS:&SPM_POWER_ON_VAL1)|0x200000)
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Step 3: Power on MD MTCMOS (AP PLL: YY Huang/AP SPM: Hank Wang/MD TOPSM: Andy.Chiang)
+; Margaux Review Done
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; AP SPM owner gen code to AP PLL owner, and provide the API, i.e., clk_prepare_enable
+; to CCCI for execution
+; skip
+PRINT "Step 3: Power on MD MTCMOS (AP PLL: YY Huang/AP SPM: Hank Wang/MD TOPSM: Andy.Chiang)"
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Step 4 Enable MDMCU clock (Jun-Ying Huang/ Hanna Chiang)
+; - PLL init step has been removed here and implemented by BootROM
+; Margaux Review Done
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+PRINT "Step 4 Enable MDMCU clock (Jun-Ying Huang/ Hanna Chiang)"
+&QUALITY_26M_ADDR=(&AP_REG_BASE+0x0000C000)
+Data.Set (&MEM_CLASS:&QUALITY_26M_ADDR) %LE %LONG 0x15
+wait 1.s
+Data.Set (&MEM_CLASS:&QUALITY_26M_ADDR) %LE %LONG 0x17
+wait 1.s
+
+IF &ENABLE_PLL_INIT==0x1
+(
+ &BASE_MADDR_MDTOP_PLLMIXED=(&MD_REG_BASE+0x00140000)
+ &BASE_MADDR_MDTOP_CLKSW=(&MD_REG_BASE+0x00150000)
+ ®_MDTOP_PLLMIXED_PLL_ON_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x10)
+ ®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x4)
+ ®_MDTOP_PLLMIXED_PLL_SETTLE_26M_CTL=(&BASE_MADDR_MDTOP_PLLMIXED+0x20)
+ ®_MDTOP_PLLMIXED_MDMCUPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x40)
+ ;;®_MDTOP_PLLMIXED_MDMCUPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x44)
+ ®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x48)
+ ;;®_MDTOP_PLLMIXED_MDVDSPPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x4C)
+ ®_MDTOP_PLLMIXED_MDBRPPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x50)
+ ;;®_MDTOP_PLLMIXED_MDBRPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x54)
+ ®_MDTOP_PLLMIXED_MDBPIPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x58)
+ ®_MDTOP_PLLMIXED_MDNRPLL0_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x68)
+ ;;®_MDTOP_PLLMIXED_MDNRPLL0_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x6C)
+ ®_MDTOP_PLLMIXED_MDNRPLL1_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x70)
+ ;;®_MDTOP_PLLMIXED_MDNRPLL1_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x74)
+ ®_MDTOP_PLLMIXED_MDNRPLL2_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x78)
+ ®_MDTOP_PLLMIXED_MDNRPLL2_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x7C)
+ ®_MDTOP_PLLMIXED_MDNRPLL3_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x80)
+ ®_MDTOP_PLLMIXED_MDNRPLL3_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x84)
+ ®_MDTOP_PLLMIXED_MDNRPLL4_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x88)
+ ;;®_MDTOP_PLLMIXED_MDNRPLL4_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x8C)
+ ®_MDTOP_PLLMIXED_MDNRPLL5_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x90)
+ ;;®_MDTOP_PLLMIXED_MDNRPLL5_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x94)
+ ®_MDTOP_PLLMIXED_MDPLL_CTL0=(&BASE_MADDR_MDTOP_PLLMIXED+0x98)
+ ®_MDTOP_PLLMIXED_MDPLL_CTL1=(&BASE_MADDR_MDTOP_PLLMIXED+0x9C)
+
+ ®_MDTOP_PLLMIXED_PLL_DIV_EN0=(&BASE_MADDR_MDTOP_PLLMIXED+0x124)
+ ®_MDTOP_PLLMIXED_PLL_DIV_EN3=(&BASE_MADDR_MDTOP_PLLMIXED+0x130)
+ ®_MDTOP_PLLMIXED_PLL_SRC_SEL=(&BASE_MADDR_MDTOP_PLLMIXED+0x140)
+
+ ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ=(&BASE_MADDR_MDTOP_PLLMIXED+0x314)
+ ®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK=(&BASE_MADDR_MDTOP_PLLMIXED+0x318)
+
+ ®_MDTOP_PLLMIXED_MDMCUPLL_STS=(&BASE_MADDR_MDTOP_PLLMIXED+0x800)
+ ®_MDTOP_PLLMIXED_PLL_DUMMY=(&BASE_MADDR_MDTOP_PLLMIXED+0xF00)
+
+ ®_MDTOP_CLKSW_CLKON_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x20)
+ ®_MDTOP_CLKSW_CLKSEL_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x24)
+ ®_MDTOP_CLKSW_CLKSEL_CTL_2=(&BASE_MADDR_MDTOP_CLKSW+0x28)
+ ®_MDTOP_CLKSW_SDF_ATB_CK_CTL=(&BASE_MADDR_MDTOP_CLKSW+0x2C)
+ ®_MDTOP_CLKSW_CLK_DUMMY=(&BASE_MADDR_MDTOP_CLKSW+0xF00)
+
+ ®_MDTOP_CLKSW_DFESYNC_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x5C)
+ ®_MDTOP_CLKSW_HRAM_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x8C)
+ ;;®_MDTOP_CLKSW_BUS2X_NODCM_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0xBC)
+ ®_MDTOP_CLKSW_SHAOLIN_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x78)
+ ;;®_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x70)
+ ;;®_MDTOP_CLKSW_MCORE_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x94)
+ ;;®_MDTOP_CLKSW_VCORE_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x90)
+
+ ®_MDTOP_CLKSW_NR_CS_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x84)
+ ®_MDTOP_CLKSW_NR_CM_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0x88)
+ ®_MDTOP_CLKSW_NR_RXT2F_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0xAC)
+ ®_MDTOP_CLKSW_NR_TXBSRP_DFS_FLEXCKGEN_SEL=(&BASE_MADDR_MDTOP_CLKSW+0xA8)
+
+ ®_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS=(&BASE_MADDR_MDTOP_CLKSW+0xCC)
+
+ &MD_PLL_MAGIC_NUM=0x62970000
+
+ ;; Default md_srclkena_ack settle time = 81+4T 32K
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL) %LE %LONG 0x02021C53
+
+ ;;Change ABBPLL_SETTLE_26M to 0x2F2==>29us
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_PLL_SETTLE_26M_CTL) %LE %LONG 0x17920803
+
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_CLK_DUMMY) %LE %LONG 0x00DFFFFF
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_PLL_SRC_SEL) %LE %LONG 0x0
+
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_SHAOLIN_DFS_FLEXCKGEN_SEL) %LE %LONG 0x10 ;; to NRPLL1
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_DFESYNC_FLEXCKGEN_SEL) %LE %LONG 0x11 ;; to BPIPLL
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_HRAM_DFS_FLEXCKGEN_SEL) %LE %LONG 0x30 ;; to NRPLL4_1_CK 800Mhz
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_NR_RXT2F_DFS_FLEXCKGEN_SEL) %LE %LONG 0x01
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_NR_CS_DFS_FLEXCKGEN_SEL) %LE %LONG 0x00
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_NR_CM_DFS_FLEXCKGEN_SEL) %LE %LONG 0x00
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_NR_TXBSRP_DFS_FLEXCKGEN_SEL) %LE %LONG 0x00
+
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_PLL_DIV_EN0) %LE %LONG 0x2F020202
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_PLL_DIV_EN3) %LE %LONG 0x00000003
+
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDBPIPLL_CTL0) %LE %LONG 0x80114EC5 ;; Fixed Fvco = 1800Mhz
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDBRPPLL_CTL0) %LE %LONG 0x801FBB13 ;; Fvco = 3300Mhz. 3300/3 = 1100Mhz more setting in PLL_SEC_SW_VERSION_ENHANCE()
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDVDSPPLL_CTL0) %LE %LONG 0x801D2276 ;; Fvco = 3030Mhz. 3030/3 = 1010Mhz
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDMCUPLL_CTL0) %LE %LONG 0x801FBB13 ;; Fvco = 3300Mhz. 3300/3 = 1100Mhz
+
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDPLL_CTL0) %LE %LONG 0x80190000 ;; Fvco = 2600Mhz. 2600/4 = 650Mhz
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDPLL_CTL1) %LE %LONG 0x12
+
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDNRPLL2_CTL1) %LE %LONG 0x12
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDNRPLL3_CTL1) %LE %LONG 0x12
+
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDNRPLL0_CTL0) %LE %LONG 0x80133B13 ;; Fvco = 2000Mhz. 2000/2 = 1000Mhz
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDNRPLL1_CTL0) %LE %LONG 0x801713B1 ;; Fvco = 2400Mhz. 2400/2 = 1200Mhz
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDNRPLL2_CTL0) %LE %LONG 0x801AEC4E ;; Fvco = 2800Mhz. 2800/4 = 700Mhz
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDNRPLL3_CTL0) %LE %LONG 0x80180000 ;; Fvco = 2496Mhz. 2496/4 = 624Mhz
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDNRPLL4_CTL0) %LE %LONG 0x800F6276 ;; Fvco = 1600Mhz. 1600/1 = 1600Mhz
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_MDNRPLL5_CTL0) %LE %LONG 0x801CD890 ;; Fvco = 3000Mhz. 3000/2 = 1500Mhz
+
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_PLL_ON_CTL) %LE %LONG 0x0;
+
+ wait 1.ms ;;MO_Sync()
+
+ ;; Polling until MDMCUPLL complete frequency adjustment
+ ;; Once MDMCUPLL complete, other PLL should complete too
+ ;;while ((*REG_MDTOP_PLLMIXED_MDMCUPLL_STS >> 14)&0x1);
+ wait 1.ms
+
+ ;; Wait MD bus clock ready
+ ;; Once MD bus ready, other clock should be ready too
+ ;;while ((*REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS & 0x8000) != 0x8000);
+ wait 1.ms
+
+ ;; Switch clock source to PLL
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL) %LE %LONG (Data.Long(&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL)|0x3) ;; switch MDMCU & MD BUS clock to PLL frequency
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL) %LE %LONG (Data.Long(&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL)|0xFFFFFFFC) ;; switch all clock to PLL frequency
+
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL_2) %LE %LONG (Data.Long(&MEM_CLASS:®_MDTOP_CLKSW_CLKSEL_CTL_2)|0x4)
+
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_CLKON_CTL) %LE %LONG 0x3; ;; Turn off all SW clock request
+
+ Data.Set (&MEM_CLASS:®_MDTOP_CLKSW_SDF_ATB_CK_CTL) %LE %LONG (Data.Long(&MEM_CLASS:®_MDTOP_CLKSW_SDF_ATB_CK_CTL)|0x1104011) ;; switch SDF clock to PLL frequency
+ wait 1.ms ;;MO_Sync();
+
+ ;; Clear PLL ADJ RDY IRQ fired by initial period adjustment
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ) %LE %LONG 0xFFFF;
+
+ ;; Mask all PLL ADJ RDY IRQ
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK) %LE %LONG 0xFFFF;
+ wait 1.ms ;;MO_Sync();
+
+ ;; Make a record that means MD pll has been initialized.
+ Data.Set (&MEM_CLASS:®_MDTOP_PLLMIXED_PLL_DUMMY) %LE %LONG &MD_PLL_MAGIC_NUM;
+ wait 1.ms ;;MO_Sync();
+)
+
+
+;; ==== Supplement ====
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Step 5: Custom GPIO settings
+; Margaux Bypass
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+PRINT "Step 5: Custom GPIO settings"
+; DIGRF settings
+&BASE_ADDR_GPIO=(&AP_REG_BASE+0x00005000)
+&GPIO_MODE5_ADDR=(&BASE_ADDR_GPIO+0x350)
+&GPIO_MODE6_ADDR=(&BASE_ADDR_GPIO+0x360)
+&GPIO_MODE7_ADDR=(&BASE_ADDR_GPIO+0x370)
+&GPIO_MODE7_SET_ADDR=(&BASE_ADDR_GPIO+0x374)
+&GPIO_MODE7_CLR_ADDR=(&BASE_ADDR_GPIO+0x378)
+
+; Clear GPIO62(DIGRF_IRQ), GPIO60(MIPI_M_SDATA), GPIO59(MIPI_M_SCLK)
+;;;Data.Set (&MEM_CLASS:&GPIO_MODE7_CLR_ADDR) %LE %LONG 0x07077000
+; Set GPIO62(DIGRF_IRQ), GPIO60(MIPI_M_SDATA), GPIO59(MIPI_M_SCLK)
+;;;Data.Set (&MEM_CLASS:&GPIO_MODE7_SET_ADDR) %LE %LONG 0x01011000
+
+; Check GPIO43~GPIO50 all default value = 4b'0001
+;;;&tmp=Data.Long(&MEM_CLASS:&GPIO_MODE5_ADDR)
+;;;PRINT "[GPIO_MODE5 0x" &GPIO_MODE5_ADDR "].[31:12] = " %HEX &tmp " == 0x1111_1xxx?"
+;;;&tmp=Data.Long(&MEM_CLASS:&GPIO_MODE6_ADDR)
+;;;PRINT "[GPIO_MODE6 0x" &GPIO_MODE6_ADDR "].[31:12] = " %HEX &tmp " == 0xxxx_x111?"
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Step 6: EMI Remap MD<->AP Banks (Rich Chen/Neal Liu for SEC world)
+; Margaux Review Done
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+PRINT "Step 6: EMI Remap MD<->AP Banks (Rich Chen/Neal Liu for SEC world)"
+&BCRM_INFRA_AO=(&AP_REG_BASE+0x00043000)
+
+&ADDR_A=(&AP_REG_BASE+0x00030F00)
+&ADDR_B=(&AP_REG_BASE+0x00030A00)
+Data.Set &MEM_CLASS:&ADDR_A %LE %LONG (Data.Long(&MEM_CLASS:&ADDR_A) & 0xFFFFFFFB)
+Data.Set &MEM_CLASS:&ADDR_B %LE %LONG (Data.Long(&MEM_CLASS:&ADDR_B) | 0x1)
+
+;MD Bank0<->AP Bank4,MD Bank1->AP Bank5,MD Bank4->AP Bank6
+Data.Set &MEM_CLASS:(&BCRM_INFRA_AO+0x00) %LE %LONG 0x02208420 ; MD bank0 1st~3rd 32MB
+Data.Set &MEM_CLASS:(&BCRM_INFRA_AO+0x04) %LE %LONG 0x02509023 ; MD bank0 4th~6th 32MB
+Data.Set &MEM_CLASS:(&BCRM_INFRA_AO+0x08) %LE %LONG 0x02809C26 ; MD bank0 7th~8th 32MB and bank1 1st 32MB
+Data.Set &MEM_CLASS:(&BCRM_INFRA_AO+0x0C) %LE %LONG 0x02B0A829 ; MD bank1 2nd~4th 32MB
+Data.Set &MEM_CLASS:(&BCRM_INFRA_AO+0x10) %LE %LONG 0x02E0B42C ; MD bank1 5th~7th 32MB
+Data.Set &MEM_CLASS:(&BCRM_INFRA_AO+0x14) %LE %LONG 0x0300002F ; MD bank1 8th 32MB and reserved and bank4 1st 32MB
+Data.Set &MEM_CLASS:(&BCRM_INFRA_AO+0x18) %LE %LONG 0x0330C831 ; MD bank4 2nd~4th 32MB
+Data.Set &MEM_CLASS:(&BCRM_INFRA_AO+0x1C) %LE %LONG 0x0360D434 ; MD bank4 5th~7th 32MB
+Data.Set &MEM_CLASS:(&BCRM_INFRA_AO+0x20) %LE %LONG 0x00000037 ; MD bank4 8th 32MB
+
+&USB_CUSTOM_SETTING=(&AP_REG_BASE+0x0020A100)
+Data.Set &MEM_CLASS:&USB_CUSTOM_SETTING %LE %LONG 0x40
+
+PRINT "Settings done..."
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/Coretracer_MT6873_Frequency_Meter.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/Coretracer_MT6873_Frequency_Meter.py
new file mode 100644
index 0000000..98cb7db
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/Coretracer_MT6873_Frequency_Meter.py
@@ -0,0 +1,115 @@
+#;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+## MARGAUX MD Frequency Meter
+#;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+#source D:\Coretracer_MT6885_Frequency_Meter.py
+import sys
+import time
+import os
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+
+#MD Side
+REG_CLKSW_BASE=0xA0150000
+
+#==============Below you should change for each project;====================
+fqmtr_fcksel_32k_index=0x17 #32K clock index
+valid_clk_index=0x13 # Use 0x13==>mdsys_mdcore_ck as a valid clock to reset Frequency Meter
+
+Clock_List=(
+ (0, "AD_MDNRPLL5"), (1, "AD_MDNRPLL4_1"), (2, "AD_MDNRPLL4_0"), (3, "AD_MDNRPLL3"), (4, "AD_MDNRPLL2"),
+ (5, "AD_MDNRPLL1"), (6, "AD_MDNRPLL0"), (7, "MDSYS_NRL2_CLOCK"), (8, "MDRXSYS_DFESYNC_CLOCK"), (9, "MDTOP_F216P7M_CLOCK"),
+ (10, "TRACE_MON_CLOCK"), (11, "MDSYS_216P7M_CLOCK"), (12, "MDRXSYS_RAKE_CLOCK"), (13, "MDRXSYS_BRP_CLOCK"), (14, "MDRXSYS_VDSP_CLOCK"),
+ (15, "MDTOP_LOG_ATB_CLOCK"), (16, "FESYS_CSYS_CLOCK"), (17, "MDSYS_SHAOLIN_CLOCK"), (18, "FESYS_BSI_CLOCK"), (19, "MDSYS_MDCORE_CLOCK"),
+ (20, "MDSYS_BUS2X_NODCM_CLOCK"), (21, "MDSYS_BUS4X_CLOCK"), (22, "MDTOP_DBG_CLOCK"), (23, "MDTOP_F32K_CLOCK"), (24, "AD_MDBPI_PLL_D7"),
+ (25, "AD_MDBPI_PLL_D5"), (26, "AD_MDBPI_PLL_D4"), (27, "AD_MDBPI_PLL_D3"), (28, "AD_MDBPI_PLL_D2"), (29, "AD_MDBRP_PLL"),
+ (30, "AD_MDVDSP_PLL"), (31, "AD_MDMCU_PLL"), (32, "null"), (33, "null"), (34, "null"),
+ (35, "null"), (36, "null"), (37, "null"), (38, "null"), (39, "null"),
+ (40, "null"), (41, "null"), (42, "null"), (43, "null"), (44, "null"),
+ (45, "null"), (46, "DFESYS_RXDFE_BB_CORE_CLOCK"), (47, "AD_MDNRPLL4_2"), (48, "MDTOP_BUS4X_FIXED_CLOCK"), (49, "DA_DRF_26M_CLOCK"),
+ (50, "MDTOP_BUS4X_CLOCK"), (51, "RXCPC_CPC_CLOCK"), (52, "null"), (53, "RXDDMBRP_RXDBRP_CLOCK"), (54, "RXDDMBRP_RXDDM_CLOCK"),
+ (55, "MCORE_MCORE_CLOCK"), (56, "VCOREHRAM_VCORE_CLOCK"), (57, "VCOREHRAM_HRAM_CLOCK"), (58, "FESYS_TXBSRP_CLOCK"), (59, "FESYS_MDPLL_CLOCK"),
+ (60, "TX_CS_NR_RXT2F_NR_CLOCK"), (61, "TX_CS_NR_TXBSRP_NR_CLOCK"), (62, "TX_CS_NR_CM_NR_CLOCK"), (63, "TX_CS_NR_CS_NR_CLOCK") )
+#==============Above you should change for each project;====================
+
+REG_CKMON_CTL=REG_CLKSW_BASE+0x400
+REG_FREQ_METER_CTL=REG_CLKSW_BASE+0x404
+REG_FREQ_METER_XTAL_CNT=REG_CLKSW_BASE+0x408
+REG_FREQ_METER_CKMON_CNT=REG_CLKSW_BASE+0x40C
+
+fqmtr_winset=0x1ff #Frequency Meter Windoiw Setting (= Number of FIXED clock cycle)
+fqmtr_winset_for_32k=0x1E000
+
+#Frequency Meter FIXED clock selection
+fqmtr_fcksel_val=26 #Select 26Mhz by default
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ mem_value = mem_value[12:23]
+ hex_int = int(mem_value, 16)
+ return hex_int
+
+def fqmtr_query(idx, clock_name):
+ #print("Running fqmtr_query() %s idx=%d"%(clock_name, idx))
+ if idx>=64 or idx<0 or clock_name=="null":
+ return
+ else:
+ #select source to a valid clock to let reset success.
+ memory_write(REG_CKMON_CTL, valid_clk_index)
+ memory_write(REG_FREQ_METER_CTL, 0x0) #reset frequency meter
+ time.sleep(1)
+
+ if idx==fqmtr_fcksel_32k_index: #measure 32K
+ unit="Khz"
+ fqmtr_winset_26M=fqmtr_winset_for_32k
+ safe_wait_cnt_max=50 #50 * 0.1 =5 sec
+ memory_write(REG_CKMON_CTL, idx) #For accurate, don't div 8 for 32K
+ else: #measure PLL and other module
+ unit="Mhz"
+ fqmtr_winset_26M=fqmtr_winset
+ safe_wait_cnt_max=1 #1 * 0.1 = 0.1 sec
+ memory_write(REG_CKMON_CTL, idx|0x300) #div 8 and select src
+
+ memory_write(REG_FREQ_METER_XTAL_CNT, fqmtr_winset_26M)
+ memory_write(REG_FREQ_METER_CTL, 1) #enable frequency meter
+ safe_wait_cnt=0
+
+ while memory_read(REG_FREQ_METER_CTL)&0x2==0:
+ safe_wait_cnt+=1
+ if safe_wait_cnt==safe_wait_cnt_max:
+ print("%2d.(0x%-2X) %-26s Wait Fail"%(idx , idx, clock_name))
+ return
+ time.sleep(0.1)
+
+ #Calculate the result
+ fqmtr_result_raw=memory_read(REG_FREQ_METER_CKMON_CNT)
+
+ if idx==fqmtr_fcksel_32k_index: #measure 32K
+ fqmtr_result=fqmtr_result_raw*fqmtr_fcksel_val*(0x3E8)/(fqmtr_winset_26M+3)
+ else: #measure PLL and other module
+ fqmtr_result=fqmtr_result_raw*fqmtr_fcksel_val*(8)/(fqmtr_winset_26M+3)
+
+ print("%2d.(0x%-2X) %-25s %4d%s"%(idx, idx, clock_name, fqmtr_result, unit))
+
+if __name__ == "__main__":
+ print("Note: The Error Rate of Frequency Meter is +/-1 MHz!!")
+ #print("sys.argv=%s, len(sys.argv)=%d"%(sys.argv, len(sys.argv)))
+ input=64
+
+ if 0<=input<64:#Only measure specified clock
+ fqmtr_query(Clock_List[input][0], Clock_List[input][1])
+ else:#measure all
+ for index, name in Clock_List:
+ #print("Running main() %s index=%d"%(name, index))
+ fqmtr_query(index, name)
+
+ print("===========Done=============\n\n")
+
+
+
+
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/MT6873.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/MT6873.launch
new file mode 100644
index 0000000..deccc8e
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/MT6873.launch
@@ -0,0 +1,58 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.ui.focus_threads" value=""/>
+<stringAttribute key="com.mediatek.ide.dsf.mvpu.dbg_file" value=""/>
+<stringAttribute key="com.mediatek.ide.dsf.mvpu.imageloader.pattern_file" value=""/>
+<stringAttribute key="com.mediatek.ide.dsf.mvpu.pattern_file" value=""/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value="D:\Downloads\Margaux_Bringup\pre_bringup\Regression\VMOLY.MT6873.BRINGUP.SMT.DEV.W19.49.p1\BASIC_TCM_NO_AP\MT6873_EVB_PCB01_MT6873_S00.elf"/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.cache.FilePath" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.cache.gdbIndexElf" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.clearBreakpoint" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.clearExpression" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.LocalTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.debuggerIpAddress" value="localhost"/>
+<intAttribute key="com.mediatek.ide.util.debuggerPortNumber" value="3333"/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value="source \\PC16120265\pre_bringup\Margaux_script\coretracer_basic_init.py"/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value="hb general_ex_handler hb INT_TEMP_general_ex_vector"/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.substitute_path_no_translate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="MT6297_Chip"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="localclock" value="5000"/>
+<booleanAttribute key="org.eclipse.debug.core.capture_output" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_OUTPUT_ON" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="com.mediatek.ide.dsf.gdb.core.launching.MtkGdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/Prepare_Mode_remote.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/Prepare_Mode_remote.launch
new file mode 100644
index 0000000..b574245
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/Prepare_Mode_remote.launch
@@ -0,0 +1,58 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.ui.focus_threads" value=""/>
+<stringAttribute key="com.mediatek.ide.dsf.mvpu.dbg_file" value=""/>
+<stringAttribute key="com.mediatek.ide.dsf.mvpu.imageloader.pattern_file" value=""/>
+<stringAttribute key="com.mediatek.ide.dsf.mvpu.pattern_file" value=""/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value=""/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.cache.FilePath" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.cache.gdbIndexElf" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.RemoteTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.debuggerIpAddress" value="localhost"/>
+<intAttribute key="com.mediatek.ide.util.debuggerPortNumber" value="3667"/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.original.location" value="C:\Users\mtk11711\Downloads\Prepare_Mode_remote.launch"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.substitute_path_no_translate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="Prepare"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="localclock" value="10000"/>
+<booleanAttribute key="org.eclipse.debug.core.capture_output" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_OUTPUT_ON" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="com.mediatek.ide.dsf.gdb.core.launching.MtkGdbProcessFactory"/>
+<stringAttribute key="saved_expressions<seperator>Unknown<seperator>AXI" value="0xa0000000,0xc0022000,0xc0030f00,0xc0030a00,0xc0007000,0xa0310004,0xc0030F00,0xc0030A00,0xc0001f0c,0xc00700a4,0xc00070a4"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/SSButton.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/SSButton.act
new file mode 100644
index 0000000..12d8920
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/SSButton.act
@@ -0,0 +1,14 @@
+<Customize>
+ <Action name="LoadDSP">
+ <GDBSource>coretracer_load_dsp.py</GDBSource>
+ </Action>
+ <Action name="SWLA">
+ <GDBSource>coretracer_swla.py</GDBSource>
+ </Action>
+ <Action name="restoreCallStack">
+ <GDBSource>coretracer_restore_callstack.py</GDBSource>
+ </Action>
+ <Action name="DspExceptionInfo">
+ <GDBSource>../../../dsp_debug_info_CoreTracer.py</GDBSource>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/TCF.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/TCF.py
new file mode 100644
index 0000000..bb8c771
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/TCF.py
@@ -0,0 +1,172 @@
+import getopt
+from multiprocessing import Queue
+import socket
+import sys
+from threading import Thread
+import time
+
+SPLITTER = '\x00'
+EOL = '\x03\x01'
+HEADER = '\x03\x03'
+LEN_EOL = len((SPLITTER + EOL))
+
+class Event():
+ def __init__(self, args):
+ b = bytearray(args).split(SPLITTER.encode('utf_8'))
+ self.servicename = b[1]
+ self.eventname = b[2]
+ self.data = b[3]
+ self.elements = b[3:]
+
+ def getServiceName(self):
+ return self.servicename.decode('utf_8')
+
+ def getEventName(self):
+ return self.eventname.decode('utf_8')
+
+ def getData(self):
+ return self.data.decode('utf_8')
+
+ def getElement(self, index):
+ if len(self.elements) == 0:
+ return ''
+ return self.elements[index]
+
+ def toString(self):
+ datastr = ''
+ for b in self.elements:
+ if not b == EOL:
+ datastr = datastr + ' ' + b.decode('utf_8')
+ return 'Event ' + self.getServiceName() + ' ' + self.getEventName() + ' ' + datastr
+
+class Result():
+ def __init__(self, args):
+ b = bytearray(args).split(SPLITTER.encode('utf_8'))
+ self.type = b[0]
+ self.token = b[1]
+ self.data = b[2]
+ self.elements = b[2:]
+
+ def getType(self):
+ return self.type.decode('utf_8')
+
+ def getToken(self):
+ return self.token.decode('utf_8')
+
+ def getData(self):
+ return self.data.decode('utf_8')
+
+ def getElement(self, index):
+ if len(self.elements) == 0:
+ return ''
+ return self.elements[index]
+
+ def toString(self):
+ datastr = ''
+ for b in self.elements:
+ if not b == EOL:
+ datastr = datastr + ' ' + b.decode('utf_8')
+ return self.getType() + ' ' + self.getToken() + ' ' + datastr
+
+class TCFThread(Thread):
+ def __init__(self, host='localhost', port='1534'):
+ Thread.__init__(self)
+ try:
+ opts, args = getopt.getopt(sys.argv[1:],"h:p:",["host=","port="])
+ for opt, arg in opts:
+ if opt in ("-h", "--host"):
+ host = arg
+ elif opt in ("-p", "--port"):
+ port = int(arg)
+ except getopt.GetoptError:
+ pass
+ self.tcf_terminator = (SPLITTER + EOL).encode('utf_8')
+ self.tcf = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+ self.tcf.connect((host, int(port)))
+ self.queue = Queue()
+ self.send(['E','Locator','Hello','["ZeroCopy"]'])
+
+ def run(self):
+ remain = None
+ while 1:
+ try:
+ data = self.tcf.recv(1024)
+ if remain == None:
+ remain = data
+ else:
+ remain = remain + data
+
+ if bytearray(data).endswith(self.tcf_terminator):
+ res, rem = getData(remain)
+ if bytearray(res).startswith('E'.encode('utf_8')):
+ self.queue.put(Event(res))
+ elif bytearray(res).startswith('R'.encode('utf_8')):
+ self.queue.put(Result(res))
+ remain = rem
+ except:
+ break
+ time.sleep(0.1)
+ self.tcf.close()
+
+ def get(self):
+ if not self.queue.empty():
+ return self.queue.get()
+ else:
+ return None
+
+ def send(self, args):
+ for arg in args:
+ self.tcf.send(str(arg + SPLITTER).encode('utf_8'))
+ self.tcf.send(EOL.encode('utf_8'))
+
+ def rawsend(self, rawarg):
+ self.tcf.send(rawarg)
+
+ def close(self):
+ self.tcf.shutdown(1)
+ self.tcf.close()
+
+def getData(arg):
+ data = bytearray(arg)
+ result = None
+ remain = None
+ if data.startswith(HEADER.encode('utf_8')):
+ ind = data.index(HEADER.encode('utf_8'))+2
+ leng, cnt = getDataLength(data, ind, 0)
+ ind = ind + cnt + 1
+ result = data[ind:ind+leng-1]
+ remain = data[ind+leng-1:]
+ else:
+ ind = data.index((SPLITTER + EOL).encode('utf_8'))
+ if not ind == -1:
+ result = data[:ind]
+ remain = data[ind:]
+ else:
+ result = None
+ remain = data
+
+ if not remain == None and bytearray(remain).startswith((SPLITTER + EOL).encode('utf_8')):
+ remain = remain[LEN_EOL:]
+
+# print('result: \'' + str(result) + '\'')
+# print('remain: \'' + str(remain) + '\'')
+# sys.stdout.flush()
+ return result, remain
+
+def getDataLength(_rec, ind, count):
+ rec_bytes = bytearray(_rec);
+ leng = rec_bytes[ind]
+ mulp = 0
+ if count == 0:
+ mulp = 1
+ else:
+ mulp = 128 * count
+
+ if leng & 0x80 == 0:
+ return leng * mulp, count
+ else:
+ num, cnt = getDataLength(rec_bytes, ind + 1, count + 1)
+ return ((leng & 0x7f) * mulp) + num, cnt
+
+def doEcaspe(arg):
+ return str(arg).replace('\\', '\\\\').replace('\"', '\\\"')
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/TCF.pyc b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/TCF.pyc
new file mode 100644
index 0000000..f47f3c8
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/TCF.pyc
Binary files differ
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/coretracer_PMIC_Golden_Setting_Dump_MT6873.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/coretracer_PMIC_Golden_Setting_Dump_MT6873.py
new file mode 100644
index 0000000..0e134f1
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/coretracer_PMIC_Golden_Setting_Dump_MT6873.py
@@ -0,0 +1,109 @@
+#;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+## MARGAUX PMIC Golden Setting Dump
+#;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+import sys
+import time
+import os
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+
+#MD Side
+AP_REG_BASE=0xC0000000
+MD_REG_BASE=0xA0000000
+
+
+# (Name, Reg, Mask, checkvalue)
+PMIC_List=(
+#"=== SRCLKEN_O1 Check ==="
+("PRINT_TITLE", "=== SRCLKEN_O1 Check ==="),
+("RC_MISC_0", 0xC00065B4, 0x1, 0x3),
+
+#"=== CLOCK & RESET ==="
+("PRINT_TITLE", "=== CLOCK & RESET ==="),
+("MODULE_SW_CG_0_STA", 0xC0001090, 0x970F, 0x0),
+("PMICW_CLOCK_CTRL", 0xC0001108, 0xF, 0x0),
+("ULPOSC_CON", 0xC0006420, 0x8, 0x0),
+("INFRA_GLOBALCON_RST2_STA", 0xC0001148, 0x4001, 0x0),
+
+#"=== GPIO ==="
+("PRINT_TITLE", "=== GPIO ==="),
+("GPIO_GPIO_MODE26", 0xC00054A0, 0x77770, 0x11110),
+("IOCFG_LM_DRV_CFG1", 0xC1E20010, 0x7, 0x0),
+
+#"=== PMIC_WRAP ==="
+("PRINT_TITLE", "=== PMIC_WRAP ==="),
+("PMIF_SPI_PMIF_INF_EN", 0xC0026024, 0x3FEF, 0x376F),
+("PMIF_SPI_PMIF_ARB_EN", 0xC0026150, 0x7FEF, 0x776F),
+("PMIF_SPI_PMIF_CMDISSUE_EN", 0xC00263B4, 0xFFFFFFFF, 0x1),
+("PMIF_SPI_PMIF_INIT_DONE", 0xC0026000, 0xFFFFFFFF, 0x1),
+("PMIF_SPMI_PMIF_INF_EN", 0xC0027024, 0xFFFFFFFF, 0x2F7),
+("PMIF_SPMI_PMIF_ARB_EN", 0xC0027150, 0xFFFFFFFF, 0x2F7),
+("PMIF_SPMI_PMIF_CMDISSUE_EN", 0xC00273B4, 0xFFFFFFFF, 0x1),
+("PMIF_SPMI_PMIF_INIT_DONE", 0xC0027000, 0xFFFFFFFF, 0x1),
+
+#"=== PMICSPI_MST ==="
+("PRINT_TITLE", "=== PMICSPI_MST ==="),
+("PMICSPI_MST_SPIWRAP_EN", 0xC0028014, 0xFFFFFFFF, 0x1),
+("PMICSPI_MST_SPIMUX_SEL", 0xC0028034, 0xFFFFFFFF, 0x0),
+("PMICSPI_MST_EXT_CK_WRITE", 0xC002805C, 0xFFFFFFFF, 0x1),
+("PMICSPI_MST_EXT_CK_READ", 0xC0028060, 0xFFFFFFFF, 0x0),
+("PMICSPI_MST_CSHEXT_WRITE", 0xC0028054, 0xFFFFFFFF, 0x0),
+("PMICSPI_MST_CSHEXT_READ", 0xC0028058, 0xFFFFFFFF, 0x0),
+("PMICSPI_MST_CSLEXT_WRITE", 0xC002804C, 0xFFFFFFFF, 0x0),
+("PMICSPI_MST_CSLEXT_WRITE", 0xC0028050, 0xFFFFFFFF, 0x100),
+("PMICSPI_MST_RDDMY", 0xC0028048, 0xFFFFFFFF, 0x8),
+("PMICSPI_MST_DIO_EN", 0xC0028044, 0xFFFFFFFF, 0x1) )
+
+
+#==============Above you should change for each project;====================
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ mem_value = mem_value[12:23]
+ hex_int = int(mem_value, 16)
+ return hex_int
+
+def MO_Port_Enable():
+ print("MO port enable ..")
+ """
+ enable shaolin MO port
+ """
+ memory_write(0x1F000020, 0xF)
+ memory_write(0x1F000090, 0xA0000000)
+ memory_write(0x1F000098, 0xE0000002)
+ memory_write(0x1F0000A0, 0xC0000000)
+ memory_write(0x1F0000A8, 0xC0000002)
+
+
+def golden_setting_query(name_str, reg_addr, reg_mask, match_value):
+ temp_val = memory_read(reg_addr)
+ if((temp_val & reg_mask) != match_value):
+ print("FAIL!! " + name_str + " " + str(hex(reg_addr)) + " = " + str(hex(temp_val)))
+ else:
+ print("PASS!! " + name_str + " " + str(hex(reg_addr)) + " = " + str(hex(temp_val)))
+
+
+if __name__ == "__main__":
+ print("Start PMIC Golden Setting Dump")
+
+ # If you need to dump before MD init, please enable this.
+ #MO_Port_Enable()
+
+ for i in range(len(PMIC_List)):
+ if(PMIC_List[i][0] == "PRINT_TITLE"):
+ print(PMIC_List[i][1])
+ else:
+ golden_setting_query(PMIC_List[i][0], PMIC_List[i][1], PMIC_List[i][2], PMIC_List[i][3])
+
+ print("===========Done=============\n\n")
+
+
+
+
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/coretracer_basic_init.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/coretracer_basic_init.py
new file mode 100644
index 0000000..e89434d
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/coretracer_basic_init.py
@@ -0,0 +1,362 @@
+import sys
+import time
+import os
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+
+#MD Side
+AP_REG_BASE=0xC0000000
+MD_REG_BASE=0xA0000000
+
+#AP side
+#AP_REG_BASE=0x10000000
+#MD_REG_BASE=0x20000000
+
+def switch_to_axi_mode():
+ '''
+ Description:
+ Not Neccesary in Power-on sequence flow
+ To access AXI w/o CPU
+ It will speedup loading code by bypassing CPU.
+ Usage:
+ tinyBL, dummyAP. Do not use in FullLoad.
+ PIC:
+ Coretracer owner (Jessie Kuo / DP2_DM7)
+ Review:
+ Margaux done
+ '''
+ print("Switch to AXI port ..")
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ mem_value = mem_value[12:23]
+ hex_int = int(mem_value, 16)
+ return hex_int
+
+def WDT_Disable():
+ """
+ Description:
+ diable WDT function
+ [in] thread, codescape thread object
+ PIC:
+ MD WDT PIC: Yao Xue
+ AP WDT PIC: Freddy Hsin/OSS1_SS9
+ Review:
+ Margaux done
+ """
+ #MD WDT default off, but still disable again
+ #enable MD WDT: DRV_REG(0XB00F0100) = (0x55 <<24) | (DRV_REG(0XB00F0100) &0x3);
+ #disable MD WDT: DRV_REG(0XB00F0100) = (0x55 <<24) | (DRV_REG(0XB00F0100) & 0xFFFFFFFC);
+
+ print("WDT disable ..")
+ mdrgu = 0xA00F0000 + 0x0100
+ aprgu = 0xC0007000
+ memory_write(mdrgu, (memory_read(mdrgu) & 0xFFFFFFFC) | 0x55000000)
+ memory_write(aprgu, (memory_read(aprgu) & 0xFFFFFFFE) | 0x22000000)
+
+def MD_SRCLKENA():
+ print("MD_SRCLKENA config ..")
+ """
+ Description:
+ INFRA_MISC2 (0x10001F0C)
+ [3:0] : mdsrc_req_0_en = 4'b0001
+ [7:4] : mdsrc_req_1_en = 4'b0010
+ PIC:
+ AP SPM(Fraser Chang)
+ Review:
+ Margaux done
+ """
+ infra_misc2_addr = AP_REG_BASE + 0x1f0c
+ memory_write(infra_misc2_addr, (memory_read(infra_misc2_addr) & 0xFFFFFF00) | 0x21)
+
+ """
+ SRCLKEN_O1 Force RF On
+ PIC: Clare Li/Fraser Chang
+ """
+ addr1 = AP_REG_BASE + 0x6000
+ addr2 = AP_REG_BASE + 0x6008
+ memory_write(addr1, 0x0B160001) # magic key
+ memory_write(addr2, memory_read(addr2) | (1<<21) ) #set bit[21]
+ """
+ Owner: Albert-ZL Huang
+ Make sure SPM setting HW mode timing.
+ """
+
+def Config_26M_Quality():
+ '''
+ Description:
+ Neccesary in Power-on sequence flow.
+ Cover by MD script in tinyBL.
+ Cover by AP script in dummyAP.
+ Usage:
+ tinyBL
+ PIC:
+ Jun-Ying.Huang/Hanna.Chiang
+ Review:
+ Margaux done
+ '''
+ print("Config 26M Quality ..")
+ addr = AP_REG_BASE + 0xC000
+ #Configure 0xC000C000(MD view AP sys) to 0x15
+ memory_write(addr, 0x15)
+ time.sleep(0.001)
+ #Configure 0xC000C000(MD view AP sys) to 0x15
+ memory_write(addr, 0x17)
+ time.sleep(0.001)
+
+def MD_Remap(adr=None):
+ print("MD EMI Remap ..")
+ """MD reamp config
+ [in] thread, codescape thread object
+ [in] adr, user specific remap address (ap infra memory map view, 32M alignment)
+ default: emi start address
+ """
+ '''
+ Description:
+ Neccesary in Power-on sequence flow.
+ Cover by MD script in tinyBL.
+ Cover by AP script in dummyAP and fullAP.
+ To set AP bus remap setting for MDAP address remapping.
+ It should be config before we load code into EMI.
+ Usage:
+ tinyBL
+ PIC:
+ AP Bus DE (Ryan-CR Yang/Justin Gu)
+ Review:
+ Margaux done
+ '''
+
+ bcrm_infra_ao = AP_REG_BASE + 0x43000
+
+ memory_write((AP_REG_BASE + 0x44F00),(memory_read(AP_REG_BASE + 0x44F00) & 0xFFFFFFFB))
+ memory_write((AP_REG_BASE + 0x44A00),(memory_read(AP_REG_BASE + 0x44A00) | 0x100))
+ # MD bank 0 -> AP bank 4
+ # MD bank 1 -> AP bank 5
+ # MD bank 4 -> AP bank 6
+ memory_write((bcrm_infra_ao + 0x00),( ((0x40000000)>>25)+(((0x42000000)>>25)<<10) + (((0x44000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x04,( ((0x46000000)>>25)+(((0x48000000)>>25)<<10) + (((0x4A000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x08,( ((0x4C000000)>>25)+(((0x4E000000)>>25)<<10) + (((0x50000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x0C,( ((0x52000000)>>25)+(((0x54000000)>>25)<<10) + (((0x56000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x10,( ((0x58000000)>>25)+(((0x5A000000)>>25)<<10) + (((0x5C000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x14,( ((0x5E000000)>>25)+(((0xFFFFFFFF)>>25)<<10) + (((0x60000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x18,( ((0x62000000)>>25)+(((0x64000000)>>25)<<10) + (((0x66000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x1C,( ((0x68000000)>>25)+(((0x6A000000)>>25)<<10) + (((0x6C000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x20,( ((0x6E000000)>>25)+(((0xFFFFFFFF)>>25)<<10) + (((0xFFFFFFFF)>>25)<<20) ) )
+
+
+def MO_Port_Enable():
+ print("MO port enable ..")
+ """
+ enable shaolin MO port
+ """
+ memory_write(0x1F000020, 0xF)
+ memory_write(0x1F000090, 0xA0000000)
+ memory_write(0x1F000098, 0xE0000002)
+ memory_write(0x1F0000A0, 0xC0000000)
+ memory_write(0x1F0000A8, 0xC0000002)
+
+def Petrus_MD_PLL_Init():
+ #http://mtkteams.mediatek.inc/sites/WCT/CD1/DE1_DE2/Shared%20Documents/U3G_U4G%20modemsys/Petrus/Clock/md_global_con_top/06_Sample_C_code/01_mdpll_init/Petrus_mdpll_init_20190606.c
+ '''
+ Description:
+ Not neccesary in Power-on sequence flow. It should cover by MD init flow
+ This API is for Issue support.
+ DSP team may need it to init PLL.
+ Usage:
+ tinyBL, dummyAP. Do not use in FullLoad.
+ PIC:
+ PLL owner(Jun-Ying Huang/SSE_SS3)
+ Review:
+ Margaux noneed to use, no change
+ '''
+ print("MD PLL Init ..")
+ REGBASE_PLLMIXED = MD_REG_BASE+0x140000
+ REGBASE_CLKSW = MD_REG_BASE+0x150000
+
+ # default md_srclken_ack settle time = 150T 32k
+ memory_write(REGBASE_PLLMIXED+0x4, 0x02021C55)
+ # change APBPLL_SETTLE_26M to 0x2f2 => 29us
+ memory_write(REGBASE_PLLMIXED+0x20, 0x17920803)
+
+ #REG_MDTOP_CLKSW_CLK_DUMMY = 0x00DFFFFF
+ memory_write(REGBASE_CLKSW+0xF00, 0x00DFFFFF)
+ #REG_MDTOP_PLLMIXED_PLL_SRC_SEL = 0x0
+ memory_write(REGBASE_PLLMIXED+0x140, 0x0)
+
+
+ memory_write(REGBASE_CLKSW+0x78, 0x10)# Set NRPLL1
+ memory_write(REGBASE_CLKSW+0x5C, 0x11)# Set BPIPLL
+ memory_write(REGBASE_CLKSW+0x8C, 0x30)# Set NRPLL4_1_CK to 800Mhz
+ memory_write(REGBASE_CLKSW+0xAC, 0x01)
+ memory_write(REGBASE_CLKSW+0x84, 0x00)
+ memory_write(REGBASE_CLKSW+0x88, 0x00)
+ memory_write(REGBASE_CLKSW+0xA8, 0x00)
+
+ memory_write(REGBASE_PLLMIXED+0x124, 0x2F020202)
+ memory_write(REGBASE_PLLMIXED+0x130, 0x00000003)
+
+ memory_write(REGBASE_PLLMIXED+0x58, 0x80114EC5) # Fixed Fvco = 1800Mhz
+ memory_write(REGBASE_PLLMIXED+0x50, 0x801FBB13) # Fvco = 3300Mhz. 3300/3 = 1100Mhz
+ memory_write(REGBASE_PLLMIXED+0x48, 0x801D2276) # Fvco = 3030Mhz. 3030/3 = 1010Mhz
+ memory_write(REGBASE_PLLMIXED+0x40, 0x801F189E) # Fvco = 3234Mhz. 3234/3 = 1078Mhz
+
+ memory_write(REGBASE_PLLMIXED+0x98, 0x80190000) # Fvco = 2600Mhz. 2600/4 = 650Mhz
+ memory_write(REGBASE_PLLMIXED+0x9C, 0x12)
+
+ memory_write(REGBASE_PLLMIXED+0x7C, 0x12)
+ memory_write(REGBASE_PLLMIXED+0x84, 0x12)
+
+ memory_write(REGBASE_PLLMIXED+0x68, 0x80133B13)#Fvco = 2000Mhz. 2000/2 = 1000Mhz
+ memory_write(REGBASE_PLLMIXED+0x70, 0x801713B1)#Fvco = 2400Mhz. 2400/2 = 1200Mhz
+ memory_write(REGBASE_PLLMIXED+0x78, 0x801AEC4E)#Fvco = 2800Mhz. 2800/4 = 700Mhz
+ memory_write(REGBASE_PLLMIXED+0x80, 0x80180000)#Fvco = 2496Mhz. 2496/4 = 624Mhz
+ memory_write(REGBASE_PLLMIXED+0x88, 0x800F6276)#Fvco = 1600Mhz. 1600/1 = 1600Mhz
+ memory_write(REGBASE_PLLMIXED+0x90, 0x801CD890)#Fvco = 3000Mhz. 3000/2 = 1500Mhz
+
+ memory_write(REGBASE_PLLMIXED+0x10, 0x0)
+ #----------------------------------------------------
+
+
+ time.sleep(0.01)#MO_Sync
+ # polling untill MDMCUPLL complete freq adjustment
+ time.sleep(0.01)
+ # wait MD bus clock ready
+ time.sleep(0.01)
+
+ #----------------------------------------------
+ #switch clock source to PLL
+ memory_write(REGBASE_CLKSW+0x24, memory_read(REGBASE_CLKSW+0x24) | 0x3) # switch MDMCU & MDBUS clock to PLL freq
+
+ memory_write(REGBASE_CLKSW+0x24, memory_read(REGBASE_CLKSW+0x24) | 0xfffffffc) # switch all clock to PLL freq
+ memory_write(REGBASE_CLKSW+0x28, memory_read(REGBASE_CLKSW+0x28) | 0x4)
+
+ memory_write(REGBASE_CLKSW+0x20, 0x3) # Turn off all SW clock request
+
+ memory_write(REGBASE_CLKSW+0x2c, memory_read(REGBASE_CLKSW+0x2c) | 0x1104011) # switch SDF clock to PLL freq
+
+ memory_write(REGBASE_PLLMIXED+0x314, 0xffff) # Clear PLL ADJ RDY IRQ fired by initial period adjustment
+ memory_write(REGBASE_PLLMIXED+0x318, 0xffff) # Mask all PLL ADJ RDY IRQ
+
+ memory_write(REGBASE_PLLMIXED+0xf00, 0x62970000) # Write PLL magic number
+ return
+
+def PMIC_Power_Latch_disable():
+ '''
+ Description:
+ Not neccesary in Power-on sequence flow.
+ It should cover by AP tinyBL and APCCCI.
+ This API is for md script only flow.
+ We pull high for WDTRST to stop PMIC Booting Watchdog timer(BWDT) counting.
+ Without this, AP and MD will shutdown and boot again.
+ Usage:
+ Must to set in md script only flow.
+ Nice to set in tinyBL for safe.
+ PIC:
+ PMIC owner (Wen Su/OSS1_SS10)
+ AP RGU Owner (Freddy Hsin/OSS1_SS9)
+ Review:
+ Margaux done
+ '''
+ AP_RGU = AP_REG_BASE + 0x7000
+ memory_write(AP_RGU + 0xA4, 0x66000001)
+ return
+
+def GPIO_Custom_Setting():
+ '''
+ Description:
+ Not neccesary in Power-on sequence flow. It should cover by AP tinyBL and APCCCI.
+ This API is for Issue support.
+ If GPIO setting of tinyBL or dummyAP is wrong, we can overwrite it.
+ It is requested by DIGRF owner to add.
+ Usage:
+ md script only flow need it.
+ tinyBL, dummyAP can also be used by user requested.
+ PIC:
+ GPIO owner
+ '''
+ print("UART GPIO setting ..")
+ BASE_ADDR_MDGPIO=AP_REG_BASE+0x5000
+ BASE_ADDR_IOCFG=AP_REG_BASE+0x1F20000
+
+ memory_write(BASE_ADDR_MDGPIO+0x348, 0x770000)
+ memory_write(BASE_ADDR_MDGPIO+0x344, 0x440000)
+
+ memory_write(BASE_ADDR_IOCFG+0x68, 0x60000)
+ memory_write(BASE_ADDR_IOCFG+0x84, 0x20000)
+ return
+
+def USB_Custom_Setting():
+ '''
+ Description:
+ Neccesary in Power-on sequence flow.
+ Covered by MD script in TinyBL
+ Covered by AP script in dummyAP
+
+ Usage:
+ tinyBL
+ PIC:
+ USB owner/AP CCCI
+ Zhiqiang Yu/Xin Huang, Yubing
+ Review:
+ Margaux done
+ '''
+ memory_write(0xC020A100, 0x40)
+
+if __name__ == "__main__":
+ #...Start
+ """
+ Description:
+ Coretracer_basic_init.py is MD script for Bringup.
+ It is basically consisted of two parts.
+ The first is power on sequence, which is based on SD10 released document.
+ The second part is pre-init, which is not related to basic power/clock flow but also important for MD to bringup.
+ Review:
+ Margaux done
+ """
+
+ # Pre-init
+ # access AXI w/o CPU
+ switch_to_axi_mode()
+ # PMIC power latch disable
+ PMIC_Power_Latch_disable()
+ # Re-config MD & AP WDT setting
+ WDT_Disable()
+
+ # Margaux_MD_Power_OnOff_Sequence.ppt
+
+ # Step 1: Configure&Power on Modem Related Buck
+ # No need for MD cmm
+ # Should be done by AP script (tinyBL or dummyAP)
+
+ # Step 2: Configure md_srclkena setting(on)
+ MD_SRCLKENA()
+
+ # Step 3: Power On MD MTCMOS
+ # No need for MD cmm
+ # Should be done by AP script (tinyBL or dummyAP)
+
+ # Step 4 : Configure PLL setting
+ Config_26M_Quality()
+
+
+ # Step 5: Trigger MD MCU to run
+ # MDAP address remapping
+ MD_Remap()
+ # Config address remapping for USB driver
+ USB_Custom_Setting()
+
+ print "All misc config done!"
+
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/coretracer_basic_init_bigram.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/coretracer_basic_init_bigram.py
new file mode 100644
index 0000000..40abc9e
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/coretracer_basic_init_bigram.py
@@ -0,0 +1,334 @@
+import sys
+import time
+import os
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+
+#MD Side
+AP_REG_BASE=0xC0000000
+MD_REG_BASE=0xA0000000
+
+#AP side
+#AP_REG_BASE=0x10000000
+#MD_REG_BASE=0x20000000
+
+def switch_to_axi_mode():
+ '''
+ Description:
+ Not Neccesary in Power-on sequence flow
+ To access AXI w/o CPU
+ It will speedup loading code by bypassing CPU.
+ Usage:
+ tinyBL, dummyAP. Do not use in FullLoad.
+ PIC:
+ Coretracer owner (Jessie Kuo / DP2_DM7)
+ '''
+ print("Switch to AXI port ..")
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ mem_value = mem_value[12:23]
+ hex_int = int(mem_value, 16)
+ return hex_int
+
+def WDT_Disable():
+ """diable WDT function
+ [in] thread, codescape thread object
+ MD WDT PIC: Yao Xue
+ AP WDT PIC: Freddy Hsin/OSS1_SS9
+ """
+ #MD WDT default off, but still disable again
+ #enable MD WDT: DRV_REG(0XB00F0100) = (0x55 <<24) | (DRV_REG(0XB00F0100) &0x3);
+ #disable MD WDT: DRV_REG(0XB00F0100) = (0x55 <<24) | (DRV_REG(0XB00F0100) & 0xFFFFFFFC);
+
+ print("WDT disable ..")
+ mdrgu = 0xA00F0000 + 0x0100
+ aprgu = 0xC0007000
+ memory_write(mdrgu, (memory_read(mdrgu) & 0xFFFFFFFC) | 0x55000000)
+ memory_write(aprgu, (memory_read(aprgu) & 0xFFFFFFFE) | 0x22000000)
+
+def MD_SRCLKENA():
+ print("MD_SRCLKENA config ..")
+ """
+ INFRA_MISC2 (0x10001F0C)
+ [3:0] : mdsrc_req_0_en = 4'b0001
+ [7:4] : mdsrc_req_1_en = 4'b0010
+ PIC: AP SPM(Fraser Chang)
+ """
+ infra_misc2_addr = AP_REG_BASE + 0x1f0c
+ memory_write(infra_misc2_addr, (memory_read(infra_misc2_addr) & 0xFFFFFF00) | 0x21)
+
+ """
+ SRCLKEN_O1 Force RF On
+ PIC: Clare Li/Fraser Chang
+ """
+ addr1 = AP_REG_BASE + 0x6000
+ addr2 = AP_REG_BASE + 0x6008
+ memory_write(addr1, 0x0B160001) # magic key
+ memory_write(addr2, memory_read(addr2) | (1<<21) ) #set bit[21]
+ """
+ Owner: Albert-ZL Huang
+ Make sure SPM setting HW mode timing.
+ """
+
+def Config_26M_Quality():
+ '''
+ Description:
+ Neccesary in Power-on sequence flow.
+ Cover by MD script in tinyBL.
+ Cover by AP script in dummyAP.
+
+ Usage:
+ tinyBL
+ PIC:
+ Jun-Ying.Huang/Hanna.Chiang
+ '''
+ print("Config 26M Quality ..")
+ addr = AP_REG_BASE + 0xC000
+ #Configure 0xC000C000(MD view AP sys) to 0x15
+ memory_write(addr, 0x15)
+ time.sleep(0.001)
+ #Configure 0xC000C000(MD view AP sys) to 0x15
+ memory_write(addr, 0x17)
+ time.sleep(0.001)
+
+def MD_Remap(adr=None):
+ print("MD EMI Remap ..")
+ """MD reamp config
+ [in] thread, codescape thread object
+ [in] adr, user specific remap address (ap infra memory map view, 32M alignment)
+ default: emi start address
+ """
+ '''
+ Description:
+ Neccesary in Power-on sequence flow.
+ Cover by MD script in tinyBL.
+ Cover by AP script in dummyAP and fullAP.
+ To set AP bus remap setting for MDAP address remapping.
+ It should be config before we load code into EMI.
+ Usage:
+ tinyBL
+ PIC:
+ AP Bus DE (Ryan-CR Yang/Justin Gu)
+ '''
+
+ bcrm_infra_ao = AP_REG_BASE + 0x43000
+
+ memory_write((AP_REG_BASE + 0x44F00),(memory_read(AP_REG_BASE + 0x44F00) & 0xFFFFFFFB))
+ memory_write((AP_REG_BASE + 0x44A00),(memory_read(AP_REG_BASE + 0x44A00) | 0x100))
+ # MD bank 0 -> AP bank 4
+ # MD bank 1 -> AP bank 5
+ # MD bank 4 -> AP bank 6
+ memory_write((bcrm_infra_ao + 0x00),( ((0x40000000)>>25)+(((0x42000000)>>25)<<10) + (((0x44000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x04,( ((0x46000000)>>25)+(((0x48000000)>>25)<<10) + (((0x4A000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x08,( ((0x4C000000)>>25)+(((0x4E000000)>>25)<<10) + (((0x50000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x0C,( ((0x52000000)>>25)+(((0x54000000)>>25)<<10) + (((0x56000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x10,( ((0x58000000)>>25)+(((0x5A000000)>>25)<<10) + (((0x5C000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x14,( ((0x5E000000)>>25)+(((0xFFFFFFFF)>>25)<<10) + (((0x60000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x18,( ((0x62000000)>>25)+(((0x64000000)>>25)<<10) + (((0x66000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x1C,( ((0x68000000)>>25)+(((0x6A000000)>>25)<<10) + (((0x6C000000)>>25)<<20) ) )
+ memory_write(bcrm_infra_ao + 0x20,( ((0x6E000000)>>25)+(((0xFFFFFFFF)>>25)<<10) + (((0xFFFFFFFF)>>25)<<20) ) )
+
+
+def MO_Port_Enable():
+ print("MO port enable ..")
+ """
+ enable shaolin MO port
+ """
+ memory_write(0x1F000020, 0xF)
+ memory_write(0x1F000090, 0xA0000000)
+ memory_write(0x1F000098, 0xE0000002)
+ memory_write(0x1F0000A0, 0xC0000000)
+ memory_write(0x1F0000A8, 0xC0000002)
+
+def Petrus_MD_PLL_Init():
+ #http://mtkteams.mediatek.inc/sites/WCT/CD1/DE1_DE2/Shared%20Documents/U3G_U4G%20modemsys/Petrus/Clock/md_global_con_top/06_Sample_C_code/01_mdpll_init/Petrus_mdpll_init_20190606.c
+ '''
+ Description:
+ Not neccesary in Power-on sequence flow. It should cover by MD init flow
+ This API is for Issue support.
+ DSP team may need it to init PLL.
+ Usage:
+ tinyBL, dummyAP. Do not use in FullLoad.
+ PIC:
+ PLL owner(Jun-Ying Huang/SSE_SS3)
+ '''
+ print("MD PLL Init ..")
+ REGBASE_PLLMIXED = MD_REG_BASE+0x140000
+ REGBASE_CLKSW = MD_REG_BASE+0x150000
+
+ # default md_srclken_ack settle time = 150T 32k
+ memory_write(REGBASE_PLLMIXED+0x4, 0x02021C55)
+ # change APBPLL_SETTLE_26M to 0x2f2 => 29us
+ memory_write(REGBASE_PLLMIXED+0x20, 0x17920803)
+
+ #REG_MDTOP_CLKSW_CLK_DUMMY = 0x00DFFFFF
+ memory_write(REGBASE_CLKSW+0xF00, 0x00DFFFFF)
+ #REG_MDTOP_PLLMIXED_PLL_SRC_SEL = 0x0
+ memory_write(REGBASE_PLLMIXED+0x140, 0x0)
+
+
+ memory_write(REGBASE_CLKSW+0x78, 0x10)# Set NRPLL1
+ memory_write(REGBASE_CLKSW+0x5C, 0x11)# Set BPIPLL
+ memory_write(REGBASE_CLKSW+0x8C, 0x30)# Set NRPLL4_1_CK to 800Mhz
+ memory_write(REGBASE_CLKSW+0xAC, 0x01)
+ memory_write(REGBASE_CLKSW+0x84, 0x00)
+ memory_write(REGBASE_CLKSW+0x88, 0x00)
+ memory_write(REGBASE_CLKSW+0xA8, 0x00)
+
+ memory_write(REGBASE_PLLMIXED+0x124, 0x2F020202)
+ memory_write(REGBASE_PLLMIXED+0x130, 0x00000003)
+
+ memory_write(REGBASE_PLLMIXED+0x58, 0x80114EC5) # Fixed Fvco = 1800Mhz
+ memory_write(REGBASE_PLLMIXED+0x50, 0x801FBB13) # Fvco = 3300Mhz. 3300/3 = 1100Mhz
+ memory_write(REGBASE_PLLMIXED+0x48, 0x801D2276) # Fvco = 3030Mhz. 3030/3 = 1010Mhz
+ memory_write(REGBASE_PLLMIXED+0x40, 0x801F189E) # Fvco = 3234Mhz. 3234/3 = 1078Mhz
+
+ memory_write(REGBASE_PLLMIXED+0x98, 0x80190000) # Fvco = 2600Mhz. 2600/4 = 650Mhz
+ memory_write(REGBASE_PLLMIXED+0x9C, 0x12)
+
+ memory_write(REGBASE_PLLMIXED+0x7C, 0x12)
+ memory_write(REGBASE_PLLMIXED+0x84, 0x12)
+
+ memory_write(REGBASE_PLLMIXED+0x68, 0x80133B13)#Fvco = 2000Mhz. 2000/2 = 1000Mhz
+ memory_write(REGBASE_PLLMIXED+0x70, 0x801713B1)#Fvco = 2400Mhz. 2400/2 = 1200Mhz
+ memory_write(REGBASE_PLLMIXED+0x78, 0x801AEC4E)#Fvco = 2800Mhz. 2800/4 = 700Mhz
+ memory_write(REGBASE_PLLMIXED+0x80, 0x80180000)#Fvco = 2496Mhz. 2496/4 = 624Mhz
+ memory_write(REGBASE_PLLMIXED+0x88, 0x800F6276)#Fvco = 1600Mhz. 1600/1 = 1600Mhz
+ memory_write(REGBASE_PLLMIXED+0x90, 0x801CD890)#Fvco = 3000Mhz. 3000/2 = 1500Mhz
+
+ memory_write(REGBASE_PLLMIXED+0x10, 0x0)
+ #----------------------------------------------------
+
+
+ time.sleep(0.01)#MO_Sync
+ # polling untill MDMCUPLL complete freq adjustment
+ time.sleep(0.01)
+ # wait MD bus clock ready
+ time.sleep(0.01)
+
+ #----------------------------------------------
+ #switch clock source to PLL
+ memory_write(REGBASE_CLKSW+0x24, memory_read(REGBASE_CLKSW+0x24) | 0x3) # switch MDMCU & MDBUS clock to PLL freq
+
+ memory_write(REGBASE_CLKSW+0x24, memory_read(REGBASE_CLKSW+0x24) | 0xfffffffc) # switch all clock to PLL freq
+ memory_write(REGBASE_CLKSW+0x28, memory_read(REGBASE_CLKSW+0x28) | 0x4)
+
+ memory_write(REGBASE_CLKSW+0x20, 0x3) # Turn off all SW clock request
+
+ memory_write(REGBASE_CLKSW+0x2c, memory_read(REGBASE_CLKSW+0x2c) | 0x1104011) # switch SDF clock to PLL freq
+
+ memory_write(REGBASE_PLLMIXED+0x314, 0xffff) # Clear PLL ADJ RDY IRQ fired by initial period adjustment
+ memory_write(REGBASE_PLLMIXED+0x318, 0xffff) # Mask all PLL ADJ RDY IRQ
+
+ memory_write(REGBASE_PLLMIXED+0xf00, 0x62970000) # Write PLL magic number
+ return
+
+def PMIC_Power_Latch_disable():
+ '''
+ Description:
+ Not neccesary in Power-on sequence flow.
+ It should cover by AP tinyBL and APCCCI.
+ This API is for md script only flow.
+ We pull high for WDTRST to stop PMIC Booting Watchdog timer(BWDT) counting.
+ Without this, AP and MD will shutdown and boot again.
+ Usage:
+ Must to set in md script only flow.
+ Nice to set in tinyBL for safe.
+ PIC:
+ PMIC owner (Wen Su/OSS1_SS10)
+ AP RGU Owner (Freddy Hsin/OSS1_SS9)
+ '''
+ AP_RGU = AP_REG_BASE + 0x7000
+ memory_write(AP_RGU + 0xA4, 0x66000001)
+ return
+
+def GPIO_Custom_Setting():
+ '''
+ Description:
+ Not neccesary in Power-on sequence flow. It should cover by AP tinyBL and APCCCI.
+ This API is for Issue support.
+ If GPIO setting of tinyBL or dummyAP is wrong, we can overwrite it.
+ It is requested by DIGRF owner to add.
+ Usage:
+ md script only flow need it.
+ tinyBL, dummyAP can also be used by user requested.
+ PIC:
+ GPIO owner
+ '''
+ print "Setting GPIO"
+ memory_write(0xC0005378, 0x7077000)
+ memory_write(0xC0005374, 0x1011000)
+ return
+def Power_ON_BigRam():
+ """power on bigram
+ [in] thread, codescape thread object
+ """
+ # print("Enable MO port...")
+ # memory_write(0x1F000020, 0x0000000F)
+ # memory_write(0x1F000090, 0xA0000000)
+ # memory_write(0x1F000098, 0xE0000002)
+ # memory_write(0x1F0000A0, 0xC0000000)
+ # memory_write(0x1F0000A8, 0xC0000002)
+
+ print("BIGRAM Power ON ...")
+ memory_write(0xAB810008, 0x000007FF)
+ memory_write(0xAB830000, 0x00000001)
+
+ return
+if __name__ == "__main__":
+ #...Start
+
+ # Preinit
+ # access AXI w/o CPU
+ switch_to_axi_mode()
+ # PMIC power latch disable
+ PMIC_Power_Latch_disable()
+ # Re-config MD & AP WDT setting
+ WDT_Disable()
+
+ # Margaux_MD_Power_OnOff_Sequence.ppt
+
+ # Step 1: Configure&Power on Modem Related Buck
+ # No need for MD cmm
+ # Should be done by AP script (tinyBL or dummyAP)
+
+ # Step 2: Configure md_srclkena setting(on)
+ MD_SRCLKENA()
+
+ # Step 3: Power On MD MTCMOS
+ # No need for MD cmm
+ # Should be done by AP script (tinyBL or dummyAP)
+
+ # Step 4 : Configure PLL setting
+ Config_26M_Quality()
+
+
+ # Step 5: Trigger MD MCU to run
+ # MDAP address remapping
+ # NO NEED FOR BIGRAM ONLY lOAD since we won't access EMI.
+ # MD_Remap()
+ # Config address remapping for USB driver
+ # USB_Custom_Setting()
+
+ #No Need to do this part
+ #cover by AP tinyBL and APCCCI
+ GPIO_Custom_Setting()
+
+ #...power on Bigram for TCM only load
+ Power_ON_BigRam()
+ print "All misc config done!"
+
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/coretracer_init_emi.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/coretracer_init_emi.py
new file mode 100644
index 0000000..f44c884
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/coretracer_init_emi.py
@@ -0,0 +1,707 @@
+import sys
+import time
+import os
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+
+#MD Side
+AP_REG_BASE=0xC0000000
+MD_REG_BASE=0xA0000000
+
+#AP side
+#AP_REG_BASE=0x10000000
+#MD_REG_BASE=0x20000000
+
+def switch_to_axi_mode():
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ mem_value = mem_value[12:23]
+ hex_int = int(mem_value, 16)
+ return hex_int
+
+def DRAM_INIT():
+ print("DRAM_INIT ...")
+ tim = time.time()
+
+ # disable md to ap write secure world register protection
+ reg_bak_APC_CON = memory_read(0xC001DF00)
+ reg_bak_MAS_SEC_0 = memory_read(0xC001DB00)
+ memory_write(0xC001DF00, 0x00000000) # APC_CON[2] = DBG_MASK = 0
+ memory_write(0xC001DB00, 0x00010000) # MAS_SEC_0[16] = M16_SEC = 1
+
+ NR_RNKS=1
+ #EMI
+
+ #DRAMC0_NAO
+ #0x10234***
+ #DRAMC0
+ #0x10230***
+ #DRAMC1
+ #0x10240***
+ #DDRPHY0
+ #0x10238***
+ #DDRPHY1
+ #0x10248***
+
+ #EMI setting
+ memory_write(0xC0219000, 0x00001052) # ;0x00025052
+ memory_write(0xC0219060, 0xff000400)
+ memory_write(0xC0219020, 0x00008000)
+ memory_write(0xC0235000, 0x00001012) # ;0x00005053
+ memory_write(0xC0235010, 0x00000001)
+
+
+ #;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ memory_write(0xC0238274, 0xffffffff)
+ memory_write(0xC0248278, 0x00000000)
+ memory_write(0xC0248274, 0xffffffff)
+ memory_write(0xC023829c, 0x38030000)
+ #PLL sel
+
+ memory_write(0xC02381a0, 0x00000000)
+ memory_write(0xC02380a0, 0x00000000)
+ memory_write(0xC0238120, 0x00000000)
+ memory_write(0xC02382ac, 0x80000006)
+ memory_write(0xC02481a0, 0x00000000)
+ memory_write(0xC02480a0, 0x00000000)
+ memory_write(0xC0248120, 0x00000000)
+ memory_write(0xC02482ac, 0x80000006)
+ memory_write(0xC02382a0, 0x00000100) # ;PINMUX
+ memory_write(0xC02482a0, 0x00000100)
+ memory_write(0xC0238264, 0x00400000)
+ memory_write(0xC0238268, 0x00000040)
+ memory_write(0xC0248264, 0x00400000)
+ memory_write(0xC0248268, 0x00000040)
+ memory_write(0xC0238e18, 0x00000000)
+ memory_write(0xC0238f18, 0x01010000)
+ memory_write(0xC0239018, 0x02020000)
+ memory_write(0xC0238e68, 0x04040000)
+ memory_write(0xC0238f68, 0x05050000)
+ memory_write(0xC0239068, 0x06060000)
+ memory_write(0xC0238ec4, 0x00000c00)
+ memory_write(0xC0238fc4, 0x00000c00)
+ memory_write(0xC02393c4, 0x00000c00)
+ memory_write(0xC02394c4, 0x00000c00)
+ memory_write(0xC0238e50, 0x00000000)
+ memory_write(0xC0238f50, 0xbbbbbbbb)
+ memory_write(0xC0239050, 0xbbbbbbbb)
+ memory_write(0xC0238e54, 0x00000000)
+ memory_write(0xC0238f54, 0x0000bb00)
+ memory_write(0xC0239054, 0x0000bb00)
+ memory_write(0xC0248ea0, 0x00000000)
+ memory_write(0xC0248fa0, 0x00bbbbbb)
+ memory_write(0xC02490a0, 0x00bbbbbb)
+ memory_write(0xC0248ea4, 0x00000000)
+ memory_write(0xC0248fa4, 0x00000bbb)
+ memory_write(0xC02490a4, 0x00000bbb)
+ memory_write(0xC0248e00, 0x00000000)
+ memory_write(0xC0248f00, 0xbbbbbbbb)
+ memory_write(0xC0249000, 0xbbbbbbbb)
+ memory_write(0xC0248e04, 0x00000000)
+ memory_write(0xC0248f04, 0x0000bb00)
+ memory_write(0xC0249004, 0x0000bb00)
+ memory_write(0xC0248e50, 0x00000000)
+ memory_write(0xC0248f50, 0xbbbbbbbb)
+ memory_write(0xC0249050, 0xbbbbbbbb)
+ memory_write(0xC0248e54, 0x00000000)
+ memory_write(0xC0248f54, 0x0000bb00)
+ memory_write(0xC0249054, 0x0000bb00)
+ memory_write(0xC0238e1c, 0x00000c00)
+ memory_write(0xC0238f1c, 0x00000c00)
+ memory_write(0xC023901c, 0x00000c00)
+ memory_write(0xC0238e6c, 0x000f0f00)
+ memory_write(0xC0238f6c, 0x000f0f00)
+ memory_write(0xC023906c, 0x000f0f00)
+ memory_write(0xC0248ec4, 0x00000f0f)
+ memory_write(0xC0248fc4, 0x00000f0f)
+ memory_write(0xC02490c4, 0x00000f0f)
+ memory_write(0xC0248e1c, 0x000f0f00)
+ memory_write(0xC0248f1c, 0x000f0f00)
+ memory_write(0xC024901c, 0x000f0f00)
+ memory_write(0xC0248e6c, 0x000f0f00)
+ memory_write(0xC0248f6c, 0x000f0f00)
+ memory_write(0xC024906c, 0x000f0f00)
+ memory_write(0xC0238128, 0x00001010)
+ memory_write(0xC023812c, 0x01111010)
+ memory_write(0xC0238130, 0x010c10d0)
+ memory_write(0xC023812c, 0x03111010)
+ memory_write(0xC02381a4, 0x0000008c)
+ #TINFO="SHL ddrphy chA reset release"
+ memory_write(0xC02381b0, 0x00080010) # ;SER MODE
+ memory_write(0xC0238d04, 0x00000101)
+ memory_write(0xC0238d08, 0x00000101)
+ memory_write(0xC0239204, 0x00000101)
+ memory_write(0xC0239208, 0x00000101)
+ memory_write(0xC02380a4, 0x0000008c)
+ memory_write(0xC02380b0, 0x00080010) # ;SER MODE
+ memory_write(0xC0238c04, 0x00000101)
+ memory_write(0xC0238c08, 0x00000101)
+ memory_write(0xC0239104, 0x00000101)
+ memory_write(0xC0239108, 0x00000101)
+ memory_write(0xC02481a8, 0x00001010)
+ memory_write(0xC02481ac, 0x01111010)
+ memory_write(0xC02481b0, 0x010c10d0)
+ memory_write(0xC02481ac, 0x03111010)
+ memory_write(0xC02480a8, 0x00001010)
+ memory_write(0xC02480ac, 0x01111010)
+ memory_write(0xC02480b0, 0x010c10d0)
+ memory_write(0xC02480ac, 0x03111010)
+ memory_write(0xC0248128, 0x00001010)
+ memory_write(0xC024812c, 0x01111010)
+ memory_write(0xC0248130, 0x010c10d0)
+ memory_write(0xC024812c, 0x03111010)
+ #PLL
+
+ memory_write(0xC0238c18, 0x44000000)
+ memory_write(0xC0239118, 0x04000000)
+ memory_write(0xC0238c98, 0x44000000)
+ memory_write(0xC0239198, 0x04000000)
+ memory_write(0xC0238d18, 0x44000000)
+ memory_write(0xC0239218, 0x04000000)
+ memory_write(0xC0248c18, 0x44000000)
+ memory_write(0xC0249118, 0x04000000)
+ memory_write(0xC0248c98, 0x44000000)
+ memory_write(0xC0249198, 0x04000000)
+ memory_write(0xC0248d18, 0x44000000)
+ memory_write(0xC0249218, 0x04000000)
+ memory_write(0xC0238da0, 0x00000000)
+ memory_write(0xC02392a0, 0x00000000)
+ # DLL
+
+ memory_write(0xC0238124, 0x0000051e)
+ memory_write(0xC02481a4, 0x0000051e)
+ #TINFO="SHL ddrphy chB reset release"
+ memory_write(0xC02480a4, 0x0000051e)
+ memory_write(0xC0248124, 0x0000051e)
+ memory_write(0xC0238194, 0x00660600)
+ memory_write(0xC0238094, 0xc0660600)
+ memory_write(0xC0238114, 0xc0660600)
+ memory_write(0xC0248194, 0xc0660600)
+ memory_write(0xC0248094, 0xc0660600)
+ memory_write(0xC0248114, 0xc0660600)
+ memory_write(0xC02381b8, 0x00180101)
+ memory_write(0xC023826c, 0x00000000)
+ memory_write(0xC02481b8, 0x00180101)
+ memory_write(0xC024826c, 0x00000000)
+ memory_write(0xC0238d14, 0x00000000)
+ memory_write(0xC0239214, 0x00000000)
+ memory_write(0xC0239714, 0x00000000)
+ memory_write(0xC0239c14, 0x00000000)
+ memory_write(0xC0248d14, 0x00000000)
+ memory_write(0xC0249214, 0x00000000)
+ memory_write(0xC0249714, 0x00000000)
+ memory_write(0xC0249c14, 0x00000000)
+
+ time.sleep(0.001)
+
+ memory_write(0xC023800c, 0x006d0000)
+ memory_write(0xC0238180, 0x0000000c)
+ memory_write(0xC0238080, 0x00000009)
+ memory_write(0xC0238100, 0x00000009)
+ memory_write(0xC0248180, 0x00000009)
+ memory_write(0xC0248080, 0x00000009)
+ memory_write(0xC0248100, 0x00000009)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238000, 0x80000000)
+ memory_write(0xC0238004, 0x80000000)
+ memory_write(0xC0238004, 0x00000000)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238da4, 0x00019200)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238194, 0x00660e00)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238094, 0xc0660e00)
+ memory_write(0xC0238114, 0xc0660e00)
+ memory_write(0xC0248194, 0xc0660e00)
+ memory_write(0xC0248094, 0xc0660e00)
+ memory_write(0xC0248114, 0xc0660e00)
+ memory_write(0xC0238284, 0x0000001f)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238124, 0x0001051e)
+ memory_write(0xC02481a4, 0x0001051e)
+ memory_write(0xC02480a4, 0x0001051e)
+ memory_write(0xC0248124, 0x0001051e)
+ memory_write(0xC02382a0, 0x8100018c)
+ memory_write(0xC02482a0, 0x8100018c)
+ memory_write(0xC02381b8, 0x00040101)
+ memory_write(0xC02381b4, 0x00000000)
+ memory_write(0xC02380b4, 0x00000000)
+ memory_write(0xC0238134, 0x00000000)
+ memory_write(0xC0238c1c, 0x00200000) # ; WJ: LP3
+ memory_write(0xC02481b4, 0x00000000)
+ memory_write(0xC02480b4, 0x00000000)
+ memory_write(0xC0248134, 0x00000000)
+ memory_write(0xC0248c1c, 0x00200000) # ; WJ: LP3
+ memory_write(0xC02300dc, 0x00051008)
+ #;D.S EAXI:0x1024000dc %LE %LONG 0x00050008
+ memory_write(0xC0230000, 0x02101000) # ;[24]=LP2_EN , [25]=LP3_EN, [26]=LP4_EN
+ memory_write(0xC0230640, 0xa688049f)
+ memory_write(0xC0230660, 0x00030053)
+ memory_write(0xC023004c, 0x25712000)
+ memory_write(0xC0230680, 0x00000000)
+ memory_write(0xC0230684, 0x00000000)
+ memory_write(0xC0230688, 0x00000000)
+ memory_write(0xC023068c, 0x00000000)
+ memory_write(0xC0230690, 0x11111011)
+ memory_write(0xC0230694, 0x01101111)
+ memory_write(0xC0230698, 0x11111111)
+ memory_write(0xC023069c, 0x11111111)
+ memory_write(0xC02306a0, 0x11111111) # ;TXDLY DQS
+ memory_write(0xC02306a4, 0x66667777)
+ memory_write(0xC023082c, 0x11111111) # ;TXDLY DQ
+ memory_write(0xC0230830, 0x11111111) # ;TXDLY DQM
+ memory_write(0xC0230834, 0x66667777)
+ memory_write(0xC0230838, 0x66667777)
+ #D.S EAXI:0x1023092c %LE %LONG 0x22222222
+ #D.S EAXI:0x10230930 %LE %LONG 0x22222222
+ #D.S EAXI:0x10230934 %LE %LONG 0x66667777
+ #D.S EAXI:0x10230938 %LE %LONG 0x66667777
+ #D.S EAXI:0x10230a2c %LE %LONG 0x22222222
+ #D.S EAXI:0x10230a30 %LE %LONG 0x22222222
+ #D.S EAXI:0x10230a34 %LE %LONG 0x66667777
+ #D.S EAXI:0x10230a38 %LE %LONG 0x66667777
+ memory_write(0xC023081c, 0x00000000)
+ memory_write(0xC0230820, 0x00000000)
+ #D.S EAXI:0x1023091c %LE %LONG 0x00000000
+ #D.S EAXI:0x10230920 %LE %LONG 0x00000000
+ #D.S EAXI:0x10230a1c %LE %LONG 0x00000000
+ #D.S EAXI:0x10230a20 %LE %LONG 0x66666666
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ memory_write(0xC0230200, 0xf0100000) # ;[31]=DQSIEN MODE
+ memory_write(0xC0230048, 0x08000000)
+ memory_write(0xC0230678, 0xc0000000)
+ memory_write(0xC0230600, 0x09030b06)
+ memory_write(0xC0230604, 0x14090901)
+ memory_write(0xC0230608, 0x0c050201)
+ memory_write(0xC023060c, 0x00490019)
+ memory_write(0xC0230614, 0x01000606)
+ memory_write(0xC023061c, 0x02030408)
+ memory_write(0xC0230620, 0x02000400)
+ memory_write(0xC0230648, 0x9007320f)
+ memory_write(0xC0230644, 0x00000b0d) # ;DATLAT
+ memory_write(0xC0230000, 0x02111000) # ;[24]=LP2_EN , [25]=LP3_EN, [26]=LP4_EN
+ memory_write(0xC0230004, 0x20002000)
+ memory_write(0xC0230008, 0x81080000)
+ memory_write(0xC023000c, 0x0002cf13)
+ memory_write(0xC0230010, 0x00000080)
+ memory_write(0xC0230020, 0x00000009)
+ memory_write(0xC0230024, 0x80030000)
+ memory_write(0xC0230038, 0x80000106)
+ memory_write(0xC0230040, 0x3000000c)
+ memory_write(0xC023004c, 0x25714001)
+ memory_write(0xC0230064, 0x25b1f1cf) # ;REFRDIS=1
+ memory_write(0xC02300b0, 0x04300000)
+ memory_write(0xC0230200, 0xf0310000) # ;[31]=DQSIEN MODE
+ memory_write(0xC0230658, 0x21200001)
+ memory_write(0xC0230800, 0x00000002)
+ #D.S EAXI:0x10230900 %LE %LONG 0x00000002
+ #D.S EAXI:0x10230a00 %LE %LONG 0x00000002
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230824, 0x10101010) # ;GATE WINDOW unit:2T
+ memory_write(0xC0230828, 0x17171717)
+ #D.S EAXI:0x10230924 %LE %LONG 0x11111111
+ #D.S EAXI:0x10230928 %LE %LONG 0x42424242
+ #D.S EAXI:0x10230a24 %LE %LONG 0x32323232
+ #D.S EAXI:0x10230a28 %LE %LONG 0x06060606
+ #;D.S EAXI:0x10240a24 %LE %LONG 0x00000000; ;GATE WINDOW unit:2T
+ #;D.S EAXI:0x10240a28 %LE %LONG 0x53535353
+ #;D.S EAXI:0x10240b24 %LE %LONG 0x32323232
+ #;D.S EAXI:0x10240b28 %LE %LONG 0x06060606
+ #;D.S EAXI:0x10240c24 %LE %LONG 0x32323232
+ #;D.S EAXI:0x10240c28 %LE %LONG 0x06060606
+ # 33961 === over_write_setting_begin ===
+ # 33961 === over_write_setting_end ===
+ memory_write(0xC0230034, 0x00731010)
+ memory_write(0xC0230024, 0x80030050)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC023005c, 0x00003f00)
+ memory_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230060, 0x00000000)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC023005c, 0x00000aff)
+ memory_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230060, 0x00000000)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC023005c, 0x00000183)
+ memory_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230060, 0x00000000)
+ memory_write(0xC023005c, 0x00000206) # ;RL/WL
+ memory_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230060, 0x00000000)
+ memory_write(0xC0230028, 0x00000034)
+ memory_write(0xC023005c, 0x00000b03)
+ memory_write(0xC0230060, 0x00000001)
+
+ #=============================RANK1 MRW==================
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #D.S EAXI:0x1023005c %LE %LONG 0x01003f00
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000aff
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000183
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000206; ;RL/WL
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000b03
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #================== end RANK1 MRW =====================
+
+
+ memory_write(0xC0230060, 0x00000000)
+ memory_write(0xC0230024, 0x80030040)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ memory_write(0xC023005c, 0x00000400)
+
+
+
+ memory_write(0xC023064c, 0x00000005)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC023004c, 0x25774001)
+ memory_write(0xC0230034, 0x00731810)
+ memory_write(0xC0230024, 0x80030000)
+ memory_write(0xC0230004, 0x20082000)
+ memory_write(0xC0230058, 0x00000a56)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ memory_write(0xC023064c, 0x00ff0005)
+ memory_write(0xC0230064, 0x25b1f1cf) # ;REFRDIS=1
+ memory_write(0xC0230610, 0x22653055)
+ memory_write(0xC023004c, 0x45774001)
+ memory_write(0xC0230048, 0x48000000)
+ memory_write(0xC023005c, 0x80000400)
+ memory_write(0xC0230038, 0xc0000107)
+ memory_write(0xC023020c, 0x00010002)
+ memory_write(0xC0230204, 0x00014e00)
+ memory_write(0xC0230094, 0x00100000)
+ memory_write(0xC0230098, 0x00004000)
+ memory_write(0xC023009c, 0x12010480)
+ # 54377 === DE initial sequence done ===
+
+ #selftest
+ #D.S EAXI:0x1023009C %LE %LONG 0x02010080
+ #D.S EAXI:0x10230094 %LE %LONG 0x00100000
+ #D.S EAXI:0x10230098 %LE %LONG 0x00004000
+ #D.S EAXI:0x1023009C %LE %LONG 0x82010080
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ # restore md to ap write secure world register protection
+ memory_write(0xC001DB00, reg_bak_MAS_SEC_0) # MAS_SEC_0[16] = M16_SEC = 0
+ memory_write(0xC001DF00, reg_bak_APC_CON) # APC_CON[2] = DBG_MASK = 1
+
+ print("DRAM_INIT -> elapsed time: {:.3f}".format(time.time()-tim))
+
+def MD_Remap(adr=None):
+ """MD reamp config
+ [in] thread, codescape thread object
+ [in] adr, user specific remap address (ap infra memory map view, 32M alignment)
+ default: emi start address
+ """
+
+ inf_emi = 0x80000000 if memory_read(0xA000001C) < 0x08566094 else 0x40000000
+ print("MD_Remap(adr={:#x}) ...".format(inf_emi if adr == None else adr))
+ if adr == None:
+ inf_md = inf_emi
+ else:
+ assert (adr & 0x01FFFFFF) == 0
+ inf_md = adr
+ print("MD_Remap -> md:bank0=>ap:{:#x}, md:bank1=>ap:{:#x}, md:bank4=>ap:{:#x}".format(inf_md, inf_md+0x10000000, inf_emi))
+ # md remap bank 0
+ bnk = inf_md >> 25
+ memory_write(0xC0001300, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ memory_write(0xC0001304, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ memory_write(0xC0001308, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ memory_write(0xC000130c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+ # md remap bank 1
+ bnk = (inf_md+0x10000000) >> 25
+ memory_write(0xC0001310, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ memory_write(0xC0001314, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ memory_write(0xC0001318, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ memory_write(0xC000131c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+ # md remap bank 4
+ bnk = inf_emi >> 25
+ memory_write(0xC0001320, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ memory_write(0xC0001324, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ memory_write(0xC0001328, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ memory_write(0xC000132c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+
+def WDT_Disable():
+ """diable WDT function
+ [in] thread, codescape thread object
+ """
+ print("WDT disable ...")
+ mdrgu = 0xA00F0000 + 0x0100
+ aprgu = 0xC0007000
+ memory_write(mdrgu, (memory_read(mdrgu) & 0xFFFFFFFC) | 0x55000000)
+ memory_write(aprgu, (memory_read(aprgu) & 0xFFFFFFFE) | 0x22000000)
+
+if __name__ == "__main__":
+ switch_to_axi_mode()
+ WDT_Disable()
+ DRAM_INIT()
+ MD_Remap()
+ tEnd = time.time()
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/coretracer_load_dsp.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/coretracer_load_dsp.py
new file mode 100644
index 0000000..96ff456
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/coretracer_load_dsp.py
@@ -0,0 +1,147 @@
+#from imgtec import codescape
+import sys
+import time
+import os
+sys.path.append(os.path.dirname(os.path.realpath(__file__)))
+import gdb
+import binascii
+import Tkinter, tkFileDialog
+from TCF import Event, Result
+import TCF as client
+
+app = None
+dsp_header = 0x0
+dsp_magic = "4d4d4d01"
+
+TCF_HOST = 'localhost'
+TCF_PORT = 1534
+
+def get_tcf_port():
+ global TCF_PORT
+ gdb_cmd = 'show env tcfport'
+ res = gdb.execute(gdb_cmd, to_string=True)
+ TCF_PORT = int(res.split()[2], 0)
+ print "TCF_PORT = " + str(TCF_PORT)
+
+def switch_to_axi_mode():
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def switch_to_apb_mode():
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write off'
+ gdb.execute(gdb_cmd)
+
+def print_to_log(str):
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','log',str+'\n'])
+ tcf.close()
+
+# load dsp bin file
+def load_dsp_bin(dsp_path):
+ global dsp_header
+
+ time_str = time.time()
+ #print_to_log("=== Start to load dsp bin ===")
+ print_to_log("Dsp bin path: " + dsp_path)
+ if(os.path.exists(dsp_path) == False):
+ print_to_log( "DSP bin doesn't exist: %s" %(dsp_path))
+ print_to_log( "[Error] Load DSP bin failed")
+ return
+ else:
+ with open(dsp_path, "rb") as dsp_bin:
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print_to_log( "No header detected, continue")
+ else:
+ dsp_header = 0x200
+ dsp_bin.seek(dsp_header, os.SEEK_SET)
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print_to_log( "Header detected, skip first 512B")
+ else:
+ print_to_log( "DSP header detected at neither 0x0 nor 0x200")
+ print_to_log( "Please check the bin is legal!")
+ print_to_log( "[Error] Load DSP bin failed")
+ return
+ gdb_cmd='thread 1'
+ gdb.execute(gdb_cmd)
+ ## a) need parsing: 0x13a0000 <dsp_bin_ro>
+ ##symbol_name='&dsp_bin_ro'
+ ##dsp_addr = gdb.parse_and_eval(symbol_name)
+ ## b) need parsing: $3 = 0x13a0000
+ ##gdb_cmd='p/x &dsp_bin_ro'
+ ##dsp_addr = gdb.execute(gdb_cmd, False, True)
+ symbol_name='dsp_bin_ro'
+ dsp_addr = gdb.parse_and_eval(symbol_name)
+ dsp_addr = str(dsp_addr.address).split(" ")
+ dsp_addr = int(dsp_addr[0], 16) - dsp_header
+ #print_to_log( hex(dsp_addr) )
+ gdb_cmd = " ".join(['restore', dsp_path, 'binary', hex(dsp_addr), hex(dsp_header)])
+ #print_to_log( gdb_cmd)
+ switch_to_axi_mode()
+ print_to_log( "Load DSP bin ......................")
+ gdb.execute(gdb_cmd)
+ switch_to_apb_mode()
+ time_end = time.time()
+ print_to_log("loading dsp is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+
+class gui_tk(Tkinter.Tk):
+ def __init__(self, parent):
+ Tkinter.Tk.__init__(self, parent)
+ elf_path = ""
+ dsp_path = ""
+ dsp_addr = ""
+ self.file_opt = options = {}
+ options['title'] = 'Choose a file'
+ self.parent = parent
+ self.initialize()
+
+ def initialize(self):
+ self.grid()
+
+ dsp_button = Tkinter.Button(self, text=u"Load DSP bin =>", command=self.dsp_OnButtonClick)
+ dsp_button.grid(column=0, row=4, sticky='W')
+
+ def dsp_OnButtonClick(self):
+ dsp_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(dsp_path) > 0:
+ print_to_log( "You chose %s" % dsp_path)
+ load_dsp_bin(dsp_path)
+ self.quit()
+
+ def quit(self):
+ global app
+ print_to_log( "=== Close DSP Loader ===")
+ app.destroy()
+
+def load_dsp_gui():
+ print_to_log( "=== Start DSP Loader UI ===")
+ global app
+ app = gui_tk(None)
+ app.title('DSP Loader')
+ app.mainloop()
+
+def disable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','disable','["LoadDSP"]'])
+ tcf.close()
+
+def enable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','enable','["LoadDSP"]'])
+ tcf.close()
+
+if __name__ == "__main__":
+ get_tcf_port()
+ disable_button()
+ load_dsp_gui()
+ enable_button()
+
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/coretracer_misc.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/coretracer_misc.py
new file mode 100644
index 0000000..11b9be2
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/coretracer_misc.py
@@ -0,0 +1,70 @@
+import sys
+import time
+import os
+import gdb
+import ctypes
+
+dsp_bin_base = "0x0d500000"
+ramdisk_base = "0x0c500000"
+RAMDISK_SIZE = 0x1000
+EXCEPT_RET = 0xdeaddead
+
+def switch_to_axi_mode():
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def switch_to_apb_mode():
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write off'
+ gdb.execute(gdb_cmd)
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def get_symbol_addr(symbol_name):
+ res = -1
+ try:
+ res = gdb.parse_and_eval(symbol_name)
+ except:
+ return EXCEPT_RET
+
+ return str(res.address).split()[0]
+
+def clean_ram_disk_region():
+ global ramdisk_base
+
+ ram_disk_addr = get_symbol_addr('ram_disk')
+
+ if ram_disk_addr != EXCEPT_RET:
+ print("ram_disk = %s . clean 4K .." % ram_disk_addr)
+ switch_to_axi_mode()
+ for i in range(RAMDISK_SIZE/4):
+ memory_write(int(ram_disk_addr,0)+i*4,0)
+ switch_to_apb_mode()
+ ramdisk_base = ram_disk_addr
+ else:
+ print "There is no ram_disk symbol in this elf!"
+
+def clean_dsp_bin_magic():
+ global dsp_bin_base
+
+ magic_addr = get_symbol_addr('dsp_bin_ro')
+
+ if magic_addr != EXCEPT_RET:
+ print("dsp_bin_addr = %s . write the addr with 0 .." % magic_addr)
+ memory_write(magic_addr, 0)
+ dsp_bin_base = magic_addr
+ else:
+ print "There is no dsp_bin_ro symbol in this elf!"
+
+
+if __name__ == "__main__":
+ print "Check dsp bin magic .."
+ clean_dsp_bin_magic()
+ print "Check ramdisk 4k .."
+ clean_ram_disk_region()
+ print "=================== All process done. You can tigger cpu run or load DSP bin ==================="
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/coretracer_restore_callstack.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/coretracer_restore_callstack.py
new file mode 100644
index 0000000..ff9bcef
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/coretracer_restore_callstack.py
@@ -0,0 +1,188 @@
+import sys
+import time
+import os
+sys.path.append(os.path.dirname(os.path.realpath(__file__)))
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+import struct
+from TCF import Event, Result
+import TCF as client
+EXCEPT_RET = 0xdeaddead
+
+TCF_HOST = 'localhost'
+TCF_PORT = 1534
+
+CPU_CORE_NUM =4
+CPU_PER_CORE_VPE_NUM =3
+CPU_PER_CORE_TC_NUM =6
+
+CPUGPR_NAME = ['zero', 'at', 't4', 't5',
+ 'a0', 'a1', 'a2', 'a3',
+ 'a4', 'a5', 'a6', 'a7',
+ 't0', 't1', 't2', 't3',
+ 's0', 's1', 's2', 's3',
+ 's4', 's5', 's6', 's7',
+ 't8', 't9', 'k0', 'k1',
+ 'gp', 'sp', 'raw_fp', 'ra']
+
+OFFENDING_VPE_NONE = 0xffffffff
+
+def get_tcf_port():
+ global TCF_PORT
+ gdb_cmd = 'show env tcfport'
+ res = gdb.execute(gdb_cmd, to_string=True)
+ TCF_PORT = int(res.split()[2], 0)
+ print "TCF_PORT = " + str(TCF_PORT)
+
+def print_to_log(str):
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','log',str+'\n'])
+ tcf.close()
+
+def disable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','disable','["restoreCallStack"]'])
+ tcf.close()
+
+def enable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','enable','["restoreCallStack"]'])
+ tcf.close()
+
+def refresh_callstack_ui():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','refresh','debug'])
+ tcf.close()
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+
+ return int(mem_value.split()[2], 0)
+
+def register_read(reg):
+ gdb_cmd = 'info register '+ str(reg)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ return int(mem_value.split()[1], 0)
+
+def register_write(reg, set_value):
+ gdb_cmd = 'set $' + str(reg) + ' = ' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def get_symbol_addr(symbol_name):
+ res = -1
+ try:
+ res = gdb.parse_and_eval(symbol_name)
+ except:
+ return EXCEPT_RET
+
+ return str(res.address).split()[0]
+
+def get_variable_value(symbol_name):
+ mem_value = gdb.parse_and_eval(symbol_name)
+ return (mem_value)
+
+def find_offender():
+ print_to_log( "checking vpe status ..")
+ offending_core = OFFENDING_VPE_NONE
+ offending_vpe = OFFENDING_VPE_NONE
+ offending_tc = OFFENDING_VPE_NONE
+ try:
+ offending_core = get_variable_value('sst_offending_coreid')
+ offending_vpe = get_variable_value('sst_offending_vpeid')
+ offending_tc = get_variable_value('sst_offending_tcid')
+ except:
+ return [OFFENDING_VPE_NONE, OFFENDING_VPE_NONE, OFFENDING_VPE_NONE]
+
+ return [offending_core, offending_vpe, offending_tc]
+
+def find_thread_id(core_num, vpe_num, tc_num):
+ gdb_cmd = 'thread find Core {}/VPE {}/TC {}'.format(core_num, vpe_num, tc_num)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ print mem_value
+ return int(mem_value.split()[1], 0)
+
+def switch_thread(tid):
+ gdb_cmd = 'thread '+str(tid)
+ gdb.execute(gdb_cmd)
+
+def restore_thread_callstack(core, vpe, tc): # core0~3, vpe0~2, tc0~1
+ # switch thread
+ thread_id = find_thread_id(core, vpe, vpe*2 + tc)
+ switch_thread(thread_id)
+
+ #print_to_log( "CONT. VPE"+str(core*3+vpe) )
+ vpe_ex_tc = get_variable_value('ex_info[{}][0].tcid'.format(core*3+vpe)) # tc0~5
+
+ #print_to_log('CORE{}/vpe{}/tc{}'.format(core, vpe, tc))
+ if vpe_ex_tc%2 == tc :# offender tc will use ex_info to restore
+ #print_to_log("restore from ex_info_reg ..")
+ # restore GPR from variable ex_info_reg
+ base_addr = get_symbol_addr('ex_info[{}][0].SST_Exception_Regs.GPR'.format(core*3+vpe))
+ #print_to_log("ex_info.GPR base addr = {}".format(base_addr))
+ i=0
+ for reg_name in CPUGPR_NAME:
+ val = memory_read(int(base_addr,0) + i*4)
+ register_write(reg_name, val)
+ i+=1
+ else: # else we use interaptive_state
+ #print_to_log("restore from ex_interaptive_state ..")
+ # restore GPR from variable ex_interaptive_state
+ base_addr = get_symbol_addr('ex_interaptive_state.coreregs[{}].tcregs[{}].GPR'.format(core, tc))
+ i=0
+ for reg_name in CPUGPR_NAME:
+ val = memory_read(int(base_addr,0) + i*4)
+ register_write(reg_name, val)
+ i+=1
+
+ # restore EPC -> PC
+# epc_val = get_variable_value('ex_interaptive_state.coreregs[{}].vperegs[{}].EPC'.format(core, vpe))
+ epc_val = get_variable_value('ex_info[{}][0].SST_Exception_Regs.EPC'.format(core*3+vpe))
+ register_write("pc", epc_val)
+
+ # restore status -> status
+ status_val = get_variable_value('ex_info[{}][0].SST_Exception_Regs.status'.format(core*3+vpe))
+ register_write("status", epc_val)
+
+ return
+
+def restore_callstack(offender):
+ core_num = offender[0]
+ vpe_num = offender[1]%3 # VPE0~VPE2
+ tc_num = offender[2]%2 # TC0~TC1
+ print_to_log("============> Offender is CORE{} VPE{} TC{}".format(core_num, vpe_num, tc_num))
+
+ for core in range(CPU_CORE_NUM):
+ for vpe in range(CPU_PER_CORE_VPE_NUM):
+ print_to_log("Restore CORE{} VPE{} ..".format(core, vpe))
+ for tc in range(2):
+ #print_to_log("Restore CORE{} VPE{} TC{} ..".format(core, vpe, vpe*2 + tc))
+ restore_thread_callstack(core, vpe, tc)
+ refresh_callstack_ui()
+ print_to_log("=== restore call stack finish! ===")
+ return
+
+def main_func():
+ print_to_log("=== start to restore call stack! ===")
+ offender = find_offender()
+ if offender[0] == OFFENDING_VPE_NONE:
+ print_to_log( "This is no any exception happened. Restore abort!")
+ return
+ restore_callstack(offender)
+ return
+
+
+if __name__ == "__main__":
+ get_tcf_port()
+ disable_button()
+ main_func()
+ enable_button()
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/coretracer_swla.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/coretracer_swla.py
new file mode 100644
index 0000000..138ac69
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/coretracer_swla.py
@@ -0,0 +1,309 @@
+import sys
+import time
+import os
+sys.path.append(os.path.dirname(os.path.realpath(__file__)))
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+import struct
+from TCF import Event, Result
+import TCF as client
+
+CORE_NUM = 4
+CORE_TC_NUM = 6
+LAST_COUNT = 100
+
+EXCEPT_RET = 0xdeaddead
+
+TCF_HOST = 'localhost'
+TCF_PORT = 1534
+
+def get_tcf_port():
+ global TCF_PORT
+ gdb_cmd = 'show env tcfport'
+ res = gdb.execute(gdb_cmd, to_string=True)
+ TCF_PORT = int(res.split()[2], 0)
+ print "TCF_PORT = " + str(TCF_PORT)
+
+def print_to_log(str):
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','log',str+'\n'])
+ tcf.close()
+
+def dump_memory(start_addr, end_addr, filename):
+ gdb_cmd = 'dump binary memory '+str(filename)+' '+hex(start_addr)+' '+hex(end_addr)
+ gdb.execute(gdb_cmd)
+
+def switch_to_axi_mode():
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def switch_to_apb_mode():
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write off'
+ gdb.execute(gdb_cmd)
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ #print "[DBG] "+ mem_value
+ return int(mem_value.split()[2], 0)
+
+
+def get_symbol_addr(symbol_name):
+ res = -1
+ try:
+ res = gdb.parse_and_eval(symbol_name)
+ except:
+ return EXCEPT_RET
+
+ return str(res.address).split()[0]
+
+def get_variable_value(symbol_name):
+ mem_value = gdb.parse_and_eval(symbol_name)
+ #print "[DBG] " + str(mem_value)
+ return (mem_value)
+
+WRAP_PATTERN = 0x50415257 # WRAP
+def isBufferWrap(f, total_size, entry_size):
+ seek_offset = total_size - entry_size
+ f.seek(seek_offset)
+ raw_dword = f.read(8)
+ word1, word2 = struct.unpack('II', raw_dword)
+ if word1 == WRAP_PATTERN and word2 == WRAP_PATTERN:
+ return False
+ else:
+ print "WRAP!!"
+ return True
+
+def find_first_idx_cus(f, total_size, entry_size, next_avail_idx):
+ avail_buffer_size = total_size - entry_size
+ if next_avail_idx - LAST_COUNT >= 0:
+ return next_avail_idx - LAST_COUNT
+ else:
+ if not isBufferWrap(f, total_size, entry_size):
+ return 0
+ else:
+ return (avail_buffer_size/entry_size) + (next_avail_idx - LAST_COUNT)
+
+def parse_swla_dump(file_path, entry_size, bin_size, next_avail_idx):
+ f = open(file_path, "rb")
+ #first_idx = find_first_idx(f, bin_size, entry_size, next_avail_idx)
+ first_idx = find_first_idx_cus(f, bin_size, entry_size, next_avail_idx)
+ f.seek(first_idx*entry_size)
+
+ cnt, wrap = 0, 0
+ tmp_list = []
+ for i in range(0, CORE_TC_NUM):
+ tmp_list.append([])
+
+ while True:
+ word = f.read(entry_size)
+ tmp_hash = {}
+ context, frc, raw_coretc = struct.unpack('III', word) #################################### need to modify
+ tmp_hash['frc'], tc, core = hex(frc), raw_coretc >> 8, raw_coretc & 0xff
+
+ if context&0xf0==0xe0:
+ tmp_hash['context'] = "CUS"
+ elif context==0xAAAAAAAA:
+ #print "IRQEND!"
+ tmp_hash['context'] = "IRQEND"
+ tmp_list[tc].append(tmp_hash.copy())
+ elif context>>16==0xAAAA:
+ irq_id = int(context & 0xFFFF)
+ tmp_hash['context'] = "IRQ"+str(irq_id)
+ tmp_list[tc].append(tmp_hash.copy())
+ #print tmp_hash['context']
+ else:
+ char1, char2, char3, char4 = (context&0xff), (context>>8&0xff), (context>>16&0xff), (context>>24&0xff)
+ if char4==0:
+ if char3==0:
+ context_name = chr(char1) + chr(char2)
+ else:
+ context_name = chr(char1) + chr(char2) + chr(char3)
+ else:
+ context_name = chr(char1) + chr(char2) + chr(char3) + chr(char4)
+ tmp_hash['context'] = context_name
+ tmp_list[tc].append(tmp_hash.copy())
+
+ #print str(tc)+", "+tmp_hash['context']+", "+hex(frc)
+
+ cnt +=1
+
+ # WRAP condition
+ if f.tell()==bin_size and wrap==0 :
+ f.seek(0)
+ wrap=1
+ print "CORE"+str(file_idx)+" swla buffer WRAP"
+ #print "seek:" + hex(f.tell()) + " cnt*entry_size = "+hex(cnt*entry_size)
+
+ # check END
+ if f.tell()==next_avail_idx*entry_size:
+ #print "END! cnt="+str(cnt)
+ break
+
+ f.close()
+ return tmp_list
+
+def swla_parse(tc_lvl_list):
+ context_list = {}
+
+ irq_queue = []
+ pre_task, pre_frc = 0, 0
+ for context in tc_lvl_list:
+ context_name = context['context']
+ context_start_frc = context['frc']
+ target_context=""
+ if pre_task != 0:
+ # sys_exec case
+ if pre_task=="IRQEND" and len(irq_queue)==0:
+ target_context = "sys_exec"
+ if not target_context in context_list:
+ context_list[target_context] = []
+ context_list[target_context].append([pre_frc, context_start_frc])
+ # irqend case
+ elif pre_task=="IRQEND":
+ last_irq = irq_queue.pop()
+ target_context = last_irq
+ if not target_context in context_list:
+ context_list[target_context] = []
+ context_list[target_context].append([pre_frc, context_start_frc])
+ else:
+ if "IRQ" in context_name and context_name!="IRQEND": # irq
+ irq_queue.append(context_name)
+
+ target_context = pre_task
+ if not target_context in context_list:
+ context_list[target_context] = []
+ context_list[target_context].append([pre_frc, context_start_frc])
+ if target_context=="IRQEND":
+ print "????"
+ pre_task, pre_frc = context_name, context_start_frc
+
+ #print context_list
+ return context_list.copy()
+
+def main_func():
+ print_to_log("=== Start to parse SWLA information ===")
+ """
+ get swla buffer base address
+ """
+ res = get_symbol_addr('SysProfilerBufferAddress')
+ if res==EXCEPT_RET:
+ print_to_log( "[ERR] this elf does not support SWLA!")
+ return
+
+ swla_buffer_base_addr = int(get_symbol_addr('SysProfilerBufferAddress'), 16)
+ swla_buffer_addr_ary = []
+ for i in range(0, CORE_NUM):
+ swla_buffer_addr_ary.append(memory_read(swla_buffer_base_addr+i*4))
+
+ """
+ get swla entry size
+ """
+ swla_entry_size = get_variable_value("SA_LoggingNodeSize[0]") ##########################################
+ #print "SWLA Entry Size: "+str(swla_entry_size)+" B"
+
+ """
+ get swla next available entry index
+ """
+ swla_buffer_next_avail_index = []
+ for i in range(0, CORE_NUM):
+ swla_buffer_next_avail_index.append(get_variable_value("SA_LoggingOffset["+str(i)+"]"))
+
+ """
+ get swla buffer total size
+ """
+ tmp = get_variable_value("SA_LoggingStop[0]")
+ swla_size = int(str(tmp).split()[0], 0) - swla_buffer_addr_ary[0]
+ print_to_log( "SWLA Buffer Size: "+ hex(swla_size)+" B")
+
+ """
+ dump each core's swla raw buffer
+ """
+ swla_dump_file = []
+
+ switch_to_axi_mode() # switch to AXI mode to speed up (axi mode will not go through CPU -> MUST used in non-cache region)
+ for i in range(0, CORE_NUM):
+ print_to_log( "Dump core"+str(i)+" swla raw buffer ..")
+ s_t = time.time()
+ filename = "core"+str(i)+"_raw_swla.bin"
+ dump_memory(swla_buffer_addr_ary[i], swla_buffer_addr_ary[i]+swla_size, filename)
+ swla_dump_file.append(filename)
+ e_t = time.time()
+ print_to_log("Elapsed time: {:.3f} sec".format(e_t-s_t))
+ switch_to_apb_mode() # switch back
+
+ print "All swla raw dump finish!!"
+
+ #exit()
+ """
+ parse swla raw
+ """
+ output = open("final_swla.log", "w")
+ output.write('met-info [000] 0.0: ms_ud_timeline_header: {"resource": [{"entity-attr": ["Interrupt"], "name": "default"}], "name": "MCU Timeline"}'+"\n")
+ output.write('met-info [000] 0.0: ms_ud_timeline_description: MCU Timeline:HAS_CHILD_TRACE=Y;COPY_TO_TOP=Y'+"\n")
+
+ core_num=0
+ log_index=1
+ for file in swla_dump_file:
+ print_to_log( "Parsing "+file+" ...")
+ s_t = time.time()
+ tc_list = parse_swla_dump(file, swla_entry_size, swla_size, swla_buffer_next_avail_index[core_num])
+ #print tc_list
+ e_t = time.time()
+
+ print_to_log("Elapsed time: {:.3f} sec".format(e_t-s_t))
+ print_to_log( "start to write to final_swla ..")
+ tc_num = 0
+ for tc_content in tc_list:
+ #print tc_content
+ context_list = swla_parse(tc_content)
+ #print context_list
+ vpe_num = tc_num/2
+ for context_name, period_list in context_list.items():
+ isIRQ = "NO"
+ if "IRQ" in context_name:
+ isIRQ = "YES"
+ for period in period_list:
+ #print period
+ start_frc, end_frc = int(period[0],0)*1.0/1000000, int(period[1],0)*1.0/1000000
+ #print start_frc
+ out_str1 = "NULL-0 [000] {:.10f}: MCU Timeline: ".format(start_frc)
+ out_str2 = "'CORE{}%%VPE{}%%TC{}%%{}', 'e': [['{}']], 't': ['{:.10f}', '{:.10f}']".format(core_num, vpe_num, tc_num/2, context_name, isIRQ, start_frc, end_frc)
+ output.write(out_str1+"{'r': "+out_str2+"}\n")
+ log_index+=1
+ tc_num+=1
+
+ core_num+=1
+ #break
+ output.close()
+ print_to_log( '=== SWLA parse finish! Please use MET font-end to open final_swla.log for SWLA view ===')
+ print_to_log( '=== The output filename is "final_swla.log" in the same folder of your elf file ===')
+ return
+
+def disable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','disable','["SWLA"]'])
+ tcf.close()
+
+def enable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','enable','["SWLA"]'])
+ tcf.close()
+
+if __name__ == "__main__":
+ get_tcf_port()
+ disable_button()
+ main_func()
+ enable_button()
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/prepare_mode.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/prepare_mode.launch
new file mode 100644
index 0000000..2b67fdb
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6873/coretracer/prepare_mode.launch
@@ -0,0 +1,64 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.ui.focus_threads" value=""/>
+<stringAttribute key="com.mediatek.ide.dsf.mvpu.dbg_file" value=""/>
+<stringAttribute key="com.mediatek.ide.dsf.mvpu.pattern_file" value=""/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value=""/>
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+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
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+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.substitute_path_no_translate" value="false"/>
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+<stringAttribute key="com.mediatek.ide.util.targetopt.args" value="-f board/mips/debug_port_swd.cfg -c "adapter_khz 3000""/>
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+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+<stringAttribute key="saved_expressions<seperator>Unknown<seperator>APB" value="0xa0638000,0xa0310000"/>
+<stringAttribute key="saved_expressions<seperator>Unknown<seperator>AXI" value="0xa0020000,0xa0630000,0xa0638000,0xa0291e50"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/codescape_fpga_emi_init.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/codescape_fpga_emi_init.py
new file mode 100755
index 0000000..fef2f8e
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/codescape_fpga_emi_init.py
@@ -0,0 +1,1200 @@
+from imgtec import codescape
+from imgtec.console import *
+import os
+import random
+import sys
+import time
+
+dsp_bin_base = "0x0d500000"
+ramdisk_base = "0x0c500000"
+RAMDISK_SIZE = 0x1000
+CPUREG_NAME = ['zero', 'at', 't4', 't5',
+ 'a0', 'a1', 'a2', 'a3',
+ 'a4', 'a5', 'a6', 'a7',
+ 't0', 't1', 't2', 't3',
+ 's0', 's1', 's2', 's3',
+ 's4', 's5', 's6', 's7',
+ 't8', 't9', 'k0', 'k1',
+ 'gp', 'sp', 'fp', 'ra']
+
+reg_backup = []
+
+def restore_callstack(da, ex_vpe):
+ core_num = ex_vpe/3
+ vpe_num = ex_vpe%3
+ print "restore CORE"+str(core_num)+" VPE"+str(vpe_num)
+ thread = da.cores[core_num].hwthreads[vpe_num]
+ try:
+ sym_addr = thread.GetSymbol('ex_info_reg').location
+ except:
+ print "There is no exception info symbol ex_info_reg. restore abort!"
+ return
+
+ print "&ex_info_reg=",format(sym_addr)
+ target_reg_info_addr = int(sym_addr, 0) + 0x178*int(ex_vpe)
+ var_status_addr = int(sym_addr, 0) + 0x88
+ var_epc_addr = int(sym_addr, 0) + 0x88 + 0x4*2
+ tmp_addr = target_reg_info_addr
+
+ print "regs restore start .."
+ for cpu_reg in CPUREG_NAME:
+ #reg_backup = thread.ReadRegister(cpu_reg) #regs(cpu_reg)
+ reg_val = thread.memory.Read(tmp_addr)
+ time.sleep(0.1)
+ thread.WriteRegister(cpu_reg, reg_val)#regs(cpu_reg, word(tmp_addr))
+ #print cpu_reg + " : " + hex(reg_val)
+ tmp_addr += 4
+ #time.sleep(0.1)
+ thread.WriteRegister('pc', thread.memory.Read(var_epc_addr))#regs('pc', regs('epc'))
+ thread.WriteRegister('status', thread.memory.Read(var_status_addr))
+ print "regs restore done. callstack restore finish!!!"
+ print "Please open call stack region in VPE"+str(ex_vpe)
+
+def find_excep_vpe(da):
+ print "checking vpe status .."
+ thread = da.cores[0].hwthreads[0]
+ try:
+ sst_off_vpeid_addr = thread.GetSymbol('sst_offending_vpeid').location
+ #sst_off_coreid_addr = thread.GetSymbol('sst_offending_coreid').location
+ #sst_offending_vpeid
+ #sst_offending_coreid
+ #sst_offending_tcid
+ except:
+ return -1
+
+ vpe_val = thread.memory.Read(sst_off_vpeid_addr)
+ #core_val = thread.memory.Read(sst_off_coreid_addr)
+ #print "Offending vpeid = "+hex(vpe_val)
+ if vpe_val==0xffffffff: #or core_val==0xffffffff:
+ return -1
+ else:
+ return vpe_val
+
+def enable_fast_write(da):
+ # To accelerate load elf
+ # Configure C0_CDMMBASE = 0x01FC1407 to enable access
+ thread.WriteRegister('CDMMBase', 0x01FC1407)
+ # Default all segments are NC, then configure VA Bank8 to WB for speed up load elf
+ thread.memory.Write(0x1FC100D4, 0x02030202)
+ da.SetDASettingValue("Fast Monitor Address", 0x6F800000)
+ da.SetDASettingValue("Fast Writes", True)
+
+
+def disable_fast_write(da):
+ thread = da.cores[0].hwthreads[0]
+ # Restore Default all segments to NC
+ thread.memory.Write(0x1FC100D4, 0x02020202)
+ # Restore C0_CDMMBASE = 0x01FC1007
+ thread.WriteRegister('CDMMBase', 0x01FC1007)
+ da.SetDASettingValue("Fast Writes", False)
+
+
+def load_all_elf(da, thread, elf_path):
+ if(os.path.exists(elf_path) == False):
+ print "[Error] UMOLY ELF doesn't exist %s" %(elf_path)
+ return 0
+
+ print elf_path
+ time_str = time.time()
+ core_num = (thread.memory.Read(0x1F000000) & 0xFF)+1
+ print "=== Get Core Number ===: %d" %(core_num)
+ print "=== Start Loading .elf ==="
+ print "Image path: " + elf_path
+
+ for core_idx in range(core_num):
+ if(core_idx == 0):
+ # load binary only on VPE0 of 0 core
+ thread = da.cores[core_idx].hwthreads[0]
+ thread.Stop()
+ enable_fast_write(da)
+ thread.LoadProgramFile(elf_path, False, 0x83, True, "")
+ #probe('sp536')
+ #print load(elf_path,verbose=True, physical=False)
+ print "[Core%d,VPE0] Load ELF successfully" %(core_idx)
+ thread = da.cores[core_idx].hwthreads[1]
+ thread.Stop()
+ thread.LoadProgramFile(elf_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE1] Load ELF successfully" %(core_idx)
+ thread = da.cores[core_idx].hwthreads[2]
+ thread.Stop()
+ thread.LoadProgramFile(elf_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE2] Load ELF successfully" %(core_idx)
+ else:
+ thread = da.cores[core_idx].hwthreads[0]
+ thread.Stop()
+ thread.LoadProgramFile(elf_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE0] Load ELF successfully" %(core_idx)
+ thread = da.cores[core_idx].hwthreads[1]
+ thread.Stop()
+ thread.LoadProgramFile(elf_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE1] Load ELF successfully" %(core_idx)
+ thread = da.cores[core_idx].hwthreads[2]
+ thread.Stop()
+ thread.LoadProgramFile(elf_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE2] Load ELF successfully" %(core_idx)
+
+ clean_ram_disk_region(thread)
+ clean_dsp_bin_magic(thread)
+ time_end = time.time()
+ print("All loading is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+ disable_fast_write(da)
+ return 1
+
+def clean_ram_disk_region(thread):
+ global ramdisk_base
+ ram_disk_addr = 0
+ try:
+ ram_disk_addr = thread.GetSymbol('ram_disk').location
+ except:
+ ram_disk_addr = 0
+
+ if ram_disk_addr!=0:
+ print("ram_disk = %s . clean 4K .." % ram_disk_addr)
+ word(ram_disk_addr,0,RAMDISK_SIZE)
+ ramdisk_base = ram_disk_addr
+ else:
+ print "There is no ram_disk symbol in this elf!"
+
+def clean_dsp_bin_magic(thread):
+ global dsp_bin_base
+ magic_addr = 0
+ try:
+ magic_addr = thread.GetSymbol('dsp_bin_ro').location
+ except:
+ magic_addr = 0
+
+ if magic_addr!=0:
+ print("dsp_bin_addr = %s . write the addr with 0 .." % magic_addr)
+ word(magic_addr, 0)
+ dsp_bin_base = magic_addr
+ else:
+ print "There is no dsp_bin_ro symbol in this elf!"
+
+
+def load_dsp_bin(da, thread, dsp_path, dsp_addr):
+ if(os.path.exists(dsp_path) == False):
+ print "[Error] DSP BIN doesn't exist %s" %(dsp_path)
+ return
+
+ enable_fast_write(da)
+ time_str = time.time()
+ print "=== Start load dsp bin ==="
+ print "Dsp bin path: " + dsp_path
+ print "Dsp bin load address: " + dsp_addr
+
+ dsp_file = open(dsp_path, "rb")
+ dsp_hdr = dsp_file.read(4)
+ dsp_file.close()
+
+ thread = da.cores[0].hwthreads[0]
+ if dsp_hdr == b'\x4d\x4d\x4d\x01':
+ dsp_bin_size = os.path.getsize(dsp_path)
+ print "Dsp bin file size: " + str(dsp_bin_size) + " bytes"
+ print "Loading DSP bin ..."
+ thread.memory.LoadBinaryFile(dsp_path, dsp_addr, start_offset = 0, length = None)
+ else:
+ dsp_bin_size = os.path.getsize(dsp_path) - 0x200
+ print "Dsp bin file size: " + str(dsp_bin_size) + " bytes"
+ print "Loading DSP bin ..."
+ thread.memory.LoadBinaryFile(dsp_path, dsp_addr, start_offset = 0x200, length = dsp_bin_size)
+
+ time_end = time.time()
+ print("loading dsp is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+ disable_fast_write(da)
+
+
+def WDT_Disable(thread):
+ """diable WDT function
+ [in] thread, codescape thread object
+ """
+ print("WDT disable ...")
+ mdrgu = 0xA00F0000 + 0x0100
+ aprgu = 0xC0007000
+ thread.memory.Write(mdrgu, (thread.memory.Read(mdrgu) & 0xFFFFFFFC) | 0x55000000)
+ thread.memory.Write(aprgu, (thread.memory.Read(aprgu) & 0xFFFFFFFE) | 0x22000000)
+
+
+def MD_Remap(thread, adr=None):
+ """MD reamp config
+ [in] thread, codescape thread object
+ [in] adr, user specific remap address (ap infra memory map view, 32M alignment)
+ default: emi start address
+ """
+
+ inf_emi = 0x80000000 if thread.memory.Read(0xA000001C) < 0x08566094 else 0x40000000
+ print("MD_Remap(adr={:#x}) ...".format(inf_emi if adr == None else adr))
+ if adr == None:
+ inf_md = inf_emi
+ else:
+ assert (adr & 0x01FFFFFF) == 0
+ inf_md = adr
+ print("MD_Remap -> md:bank0=>ap:{:#x}, md:bank1=>ap:{:#x}, md:bank4=>ap:{:#x}".format(inf_md, inf_md+0x10000000, inf_emi))
+ # md remap bank 0
+ bnk = inf_md >> 25
+ thread.memory.Write(0xC0001300, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ thread.memory.Write(0xC0001304, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ thread.memory.Write(0xC0001308, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ thread.memory.Write(0xC000130c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+ # md remap bank 1
+ bnk = (inf_md+0x10000000) >> 25
+ thread.memory.Write(0xC0001310, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ thread.memory.Write(0xC0001314, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ thread.memory.Write(0xC0001318, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ thread.memory.Write(0xC000131c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+ # md remap bank 4
+ bnk = inf_emi >> 25
+ thread.memory.Write(0xC0001320, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ thread.memory.Write(0xC0001324, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ thread.memory.Write(0xC0001328, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ thread.memory.Write(0xC000132c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+
+
+def DRAM_INIT(thread):
+ """initialize DRAM, include emi/dramc init
+ [in] thread, codescape thread object
+ """
+
+ def reg_write(adr, val):
+ thread.memory.Write(adr, val)
+
+ print("DRAM_INIT ...")
+ tim = time.time()
+
+ # disable md to ap write secure world register protection
+ reg_bak_APC_CON = thread.memory.Read(0xC001DF00)
+ reg_bak_MAS_SEC_0 = thread.memory.Read(0xC001DB00)
+ reg_write(0xC001DF00, 0x00000000) # APC_CON[2] = DBG_MASK = 0
+ reg_write(0xC001DB00, 0x00010000) # MAS_SEC_0[16] = M16_SEC = 1
+
+ NR_RNKS=1
+ #EMI
+
+ #DRAMC0_NAO
+ #0x10234***
+ #DRAMC0
+ #0x10230***
+ #DRAMC1
+ #0x10240***
+ #DDRPHY0
+ #0x10238***
+ #DDRPHY1
+ #0x10248***
+
+ #EMI setting
+ reg_write(0xC0219000, 0x00001052) # ;0x00025052
+ reg_write(0xC0219060, 0xff000400)
+ reg_write(0xC0219020, 0x00008000)
+ reg_write(0xC0235000, 0x00001012) # ;0x00005053
+ reg_write(0xC0235010, 0x00000001)
+
+
+ #;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ reg_write(0xC0238274, 0xffffffff)
+ reg_write(0xC0248278, 0x00000000)
+ reg_write(0xC0248274, 0xffffffff)
+ reg_write(0xC023829c, 0x38030000)
+ #PLL sel
+
+ reg_write(0xC02381a0, 0x00000000)
+ reg_write(0xC02380a0, 0x00000000)
+ reg_write(0xC0238120, 0x00000000)
+ reg_write(0xC02382ac, 0x80000006)
+ reg_write(0xC02481a0, 0x00000000)
+ reg_write(0xC02480a0, 0x00000000)
+ reg_write(0xC0248120, 0x00000000)
+ reg_write(0xC02482ac, 0x80000006)
+ reg_write(0xC02382a0, 0x00000100) # ;PINMUX
+ reg_write(0xC02482a0, 0x00000100)
+ reg_write(0xC0238264, 0x00400000)
+ reg_write(0xC0238268, 0x00000040)
+ reg_write(0xC0248264, 0x00400000)
+ reg_write(0xC0248268, 0x00000040)
+ reg_write(0xC0238e18, 0x00000000)
+ reg_write(0xC0238f18, 0x01010000)
+ reg_write(0xC0239018, 0x02020000)
+ reg_write(0xC0238e68, 0x04040000)
+ reg_write(0xC0238f68, 0x05050000)
+ reg_write(0xC0239068, 0x06060000)
+ reg_write(0xC0238ec4, 0x00000c00)
+ reg_write(0xC0238fc4, 0x00000c00)
+ reg_write(0xC02393c4, 0x00000c00)
+ reg_write(0xC02394c4, 0x00000c00)
+ reg_write(0xC0238e50, 0x00000000)
+ reg_write(0xC0238f50, 0xbbbbbbbb)
+ reg_write(0xC0239050, 0xbbbbbbbb)
+ reg_write(0xC0238e54, 0x00000000)
+ reg_write(0xC0238f54, 0x0000bb00)
+ reg_write(0xC0239054, 0x0000bb00)
+ reg_write(0xC0248ea0, 0x00000000)
+ reg_write(0xC0248fa0, 0x00bbbbbb)
+ reg_write(0xC02490a0, 0x00bbbbbb)
+ reg_write(0xC0248ea4, 0x00000000)
+ reg_write(0xC0248fa4, 0x00000bbb)
+ reg_write(0xC02490a4, 0x00000bbb)
+ reg_write(0xC0248e00, 0x00000000)
+ reg_write(0xC0248f00, 0xbbbbbbbb)
+ reg_write(0xC0249000, 0xbbbbbbbb)
+ reg_write(0xC0248e04, 0x00000000)
+ reg_write(0xC0248f04, 0x0000bb00)
+ reg_write(0xC0249004, 0x0000bb00)
+ reg_write(0xC0248e50, 0x00000000)
+ reg_write(0xC0248f50, 0xbbbbbbbb)
+ reg_write(0xC0249050, 0xbbbbbbbb)
+ reg_write(0xC0248e54, 0x00000000)
+ reg_write(0xC0248f54, 0x0000bb00)
+ reg_write(0xC0249054, 0x0000bb00)
+ reg_write(0xC0238e1c, 0x00000c00)
+ reg_write(0xC0238f1c, 0x00000c00)
+ reg_write(0xC023901c, 0x00000c00)
+ reg_write(0xC0238e6c, 0x000f0f00)
+ reg_write(0xC0238f6c, 0x000f0f00)
+ reg_write(0xC023906c, 0x000f0f00)
+ reg_write(0xC0248ec4, 0x00000f0f)
+ reg_write(0xC0248fc4, 0x00000f0f)
+ reg_write(0xC02490c4, 0x00000f0f)
+ reg_write(0xC0248e1c, 0x000f0f00)
+ reg_write(0xC0248f1c, 0x000f0f00)
+ reg_write(0xC024901c, 0x000f0f00)
+ reg_write(0xC0248e6c, 0x000f0f00)
+ reg_write(0xC0248f6c, 0x000f0f00)
+ reg_write(0xC024906c, 0x000f0f00)
+ reg_write(0xC0238128, 0x00001010)
+ reg_write(0xC023812c, 0x01111010)
+ reg_write(0xC0238130, 0x010c10d0)
+ reg_write(0xC023812c, 0x03111010)
+ reg_write(0xC02381a4, 0x0000008c)
+ #TINFO="SHL ddrphy chA reset release"
+ reg_write(0xC02381b0, 0x00080010) # ;SER MODE
+ reg_write(0xC0238d04, 0x00000101)
+ reg_write(0xC0238d08, 0x00000101)
+ reg_write(0xC0239204, 0x00000101)
+ reg_write(0xC0239208, 0x00000101)
+ reg_write(0xC02380a4, 0x0000008c)
+ reg_write(0xC02380b0, 0x00080010) # ;SER MODE
+ reg_write(0xC0238c04, 0x00000101)
+ reg_write(0xC0238c08, 0x00000101)
+ reg_write(0xC0239104, 0x00000101)
+ reg_write(0xC0239108, 0x00000101)
+ reg_write(0xC02481a8, 0x00001010)
+ reg_write(0xC02481ac, 0x01111010)
+ reg_write(0xC02481b0, 0x010c10d0)
+ reg_write(0xC02481ac, 0x03111010)
+ reg_write(0xC02480a8, 0x00001010)
+ reg_write(0xC02480ac, 0x01111010)
+ reg_write(0xC02480b0, 0x010c10d0)
+ reg_write(0xC02480ac, 0x03111010)
+ reg_write(0xC0248128, 0x00001010)
+ reg_write(0xC024812c, 0x01111010)
+ reg_write(0xC0248130, 0x010c10d0)
+ reg_write(0xC024812c, 0x03111010)
+ #PLL
+
+ reg_write(0xC0238c18, 0x44000000)
+ reg_write(0xC0239118, 0x04000000)
+ reg_write(0xC0238c98, 0x44000000)
+ reg_write(0xC0239198, 0x04000000)
+ reg_write(0xC0238d18, 0x44000000)
+ reg_write(0xC0239218, 0x04000000)
+ reg_write(0xC0248c18, 0x44000000)
+ reg_write(0xC0249118, 0x04000000)
+ reg_write(0xC0248c98, 0x44000000)
+ reg_write(0xC0249198, 0x04000000)
+ reg_write(0xC0248d18, 0x44000000)
+ reg_write(0xC0249218, 0x04000000)
+ reg_write(0xC0238da0, 0x00000000)
+ reg_write(0xC02392a0, 0x00000000)
+ # DLL
+
+ reg_write(0xC0238124, 0x0000051e)
+ reg_write(0xC02481a4, 0x0000051e)
+ #TINFO="SHL ddrphy chB reset release"
+ reg_write(0xC02480a4, 0x0000051e)
+ reg_write(0xC0248124, 0x0000051e)
+ reg_write(0xC0238194, 0x00660600)
+ reg_write(0xC0238094, 0xc0660600)
+ reg_write(0xC0238114, 0xc0660600)
+ reg_write(0xC0248194, 0xc0660600)
+ reg_write(0xC0248094, 0xc0660600)
+ reg_write(0xC0248114, 0xc0660600)
+ reg_write(0xC02381b8, 0x00180101)
+ reg_write(0xC023826c, 0x00000000)
+ reg_write(0xC02481b8, 0x00180101)
+ reg_write(0xC024826c, 0x00000000)
+ reg_write(0xC0238d14, 0x00000000)
+ reg_write(0xC0239214, 0x00000000)
+ reg_write(0xC0239714, 0x00000000)
+ reg_write(0xC0239c14, 0x00000000)
+ reg_write(0xC0248d14, 0x00000000)
+ reg_write(0xC0249214, 0x00000000)
+ reg_write(0xC0249714, 0x00000000)
+ reg_write(0xC0249c14, 0x00000000)
+
+ time.sleep(0.001)
+
+ reg_write(0xC023800c, 0x006d0000)
+ reg_write(0xC0238180, 0x0000000c)
+ reg_write(0xC0238080, 0x00000009)
+ reg_write(0xC0238100, 0x00000009)
+ reg_write(0xC0248180, 0x00000009)
+ reg_write(0xC0248080, 0x00000009)
+ reg_write(0xC0248100, 0x00000009)
+
+ time.sleep(0.001)
+
+ reg_write(0xC0238000, 0x80000000)
+ reg_write(0xC0238004, 0x80000000)
+ reg_write(0xC0238004, 0x00000000)
+
+ time.sleep(0.001)
+
+ reg_write(0xC0238da4, 0x00019200)
+
+ time.sleep(0.001)
+
+ reg_write(0xC0238194, 0x00660e00)
+
+ time.sleep(0.001)
+
+ reg_write(0xC0238094, 0xc0660e00)
+ reg_write(0xC0238114, 0xc0660e00)
+ reg_write(0xC0248194, 0xc0660e00)
+ reg_write(0xC0248094, 0xc0660e00)
+ reg_write(0xC0248114, 0xc0660e00)
+ reg_write(0xC0238284, 0x0000001f)
+
+ time.sleep(0.001)
+
+ reg_write(0xC0238124, 0x0001051e)
+ reg_write(0xC02481a4, 0x0001051e)
+ reg_write(0xC02480a4, 0x0001051e)
+ reg_write(0xC0248124, 0x0001051e)
+ reg_write(0xC02382a0, 0x8100018c)
+ reg_write(0xC02482a0, 0x8100018c)
+ reg_write(0xC02381b8, 0x00040101)
+ reg_write(0xC02381b4, 0x00000000)
+ reg_write(0xC02380b4, 0x00000000)
+ reg_write(0xC0238134, 0x00000000)
+ reg_write(0xC0238c1c, 0x00200000) # ; WJ: LP3
+ reg_write(0xC02481b4, 0x00000000)
+ reg_write(0xC02480b4, 0x00000000)
+ reg_write(0xC0248134, 0x00000000)
+ reg_write(0xC0248c1c, 0x00200000) # ; WJ: LP3
+ reg_write(0xC02300dc, 0x00051008)
+ #;D.S EAXI:0x1024000dc %LE %LONG 0x00050008
+ reg_write(0xC0230000, 0x02101000) # ;[24]=LP2_EN , [25]=LP3_EN, [26]=LP4_EN
+ reg_write(0xC0230640, 0xa688049f)
+ reg_write(0xC0230660, 0x00030053)
+ reg_write(0xC023004c, 0x25712000)
+ reg_write(0xC0230680, 0x00000000)
+ reg_write(0xC0230684, 0x00000000)
+ reg_write(0xC0230688, 0x00000000)
+ reg_write(0xC023068c, 0x00000000)
+ reg_write(0xC0230690, 0x11111011)
+ reg_write(0xC0230694, 0x01101111)
+ reg_write(0xC0230698, 0x11111111)
+ reg_write(0xC023069c, 0x11111111)
+ reg_write(0xC02306a0, 0x11111111) # ;TXDLY DQS
+ reg_write(0xC02306a4, 0x66667777)
+ reg_write(0xC023082c, 0x11111111) # ;TXDLY DQ
+ reg_write(0xC0230830, 0x11111111) # ;TXDLY DQM
+ reg_write(0xC0230834, 0x66667777)
+ reg_write(0xC0230838, 0x66667777)
+ #D.S EAXI:0x1023092c %LE %LONG 0x22222222
+ #D.S EAXI:0x10230930 %LE %LONG 0x22222222
+ #D.S EAXI:0x10230934 %LE %LONG 0x66667777
+ #D.S EAXI:0x10230938 %LE %LONG 0x66667777
+ #D.S EAXI:0x10230a2c %LE %LONG 0x22222222
+ #D.S EAXI:0x10230a30 %LE %LONG 0x22222222
+ #D.S EAXI:0x10230a34 %LE %LONG 0x66667777
+ #D.S EAXI:0x10230a38 %LE %LONG 0x66667777
+ reg_write(0xC023081c, 0x00000000)
+ reg_write(0xC0230820, 0x00000000)
+ #D.S EAXI:0x1023091c %LE %LONG 0x00000000
+ #D.S EAXI:0x10230920 %LE %LONG 0x00000000
+ #D.S EAXI:0x10230a1c %LE %LONG 0x00000000
+ #D.S EAXI:0x10230a20 %LE %LONG 0x66666666
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ reg_write(0xC0230200, 0xf0100000) # ;[31]=DQSIEN MODE
+ reg_write(0xC0230048, 0x08000000)
+ reg_write(0xC0230678, 0xc0000000)
+ reg_write(0xC0230600, 0x09030b06)
+ reg_write(0xC0230604, 0x14090901)
+ reg_write(0xC0230608, 0x0c050201)
+ reg_write(0xC023060c, 0x00490019)
+ reg_write(0xC0230614, 0x01000606)
+ reg_write(0xC023061c, 0x02030408)
+ reg_write(0xC0230620, 0x02000400)
+ reg_write(0xC0230648, 0x9007320f)
+ reg_write(0xC0230644, 0x00000b0d) # ;DATLAT
+ reg_write(0xC0230000, 0x02111000) # ;[24]=LP2_EN , [25]=LP3_EN, [26]=LP4_EN
+ reg_write(0xC0230004, 0x20002000)
+ reg_write(0xC0230008, 0x81080000)
+ reg_write(0xC023000c, 0x0002cf13)
+ reg_write(0xC0230010, 0x00000080)
+ reg_write(0xC0230020, 0x00000009)
+ reg_write(0xC0230024, 0x80030000)
+ reg_write(0xC0230038, 0x80000106)
+ reg_write(0xC0230040, 0x3000000c)
+ reg_write(0xC023004c, 0x25714001)
+ reg_write(0xC0230064, 0x25b1f1cf) # ;REFRDIS=1
+ reg_write(0xC02300b0, 0x04300000)
+ reg_write(0xC0230200, 0xf0310000) # ;[31]=DQSIEN MODE
+ reg_write(0xC0230658, 0x21200001)
+ reg_write(0xC0230800, 0x00000002)
+ #D.S EAXI:0x10230900 %LE %LONG 0x00000002
+ #D.S EAXI:0x10230a00 %LE %LONG 0x00000002
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC0230824, 0x10101010) # ;GATE WINDOW unit:2T
+ reg_write(0xC0230828, 0x17171717)
+ #D.S EAXI:0x10230924 %LE %LONG 0x11111111
+ #D.S EAXI:0x10230928 %LE %LONG 0x42424242
+ #D.S EAXI:0x10230a24 %LE %LONG 0x32323232
+ #D.S EAXI:0x10230a28 %LE %LONG 0x06060606
+ #;D.S EAXI:0x10240a24 %LE %LONG 0x00000000; ;GATE WINDOW unit:2T
+ #;D.S EAXI:0x10240a28 %LE %LONG 0x53535353
+ #;D.S EAXI:0x10240b24 %LE %LONG 0x32323232
+ #;D.S EAXI:0x10240b28 %LE %LONG 0x06060606
+ #;D.S EAXI:0x10240c24 %LE %LONG 0x32323232
+ #;D.S EAXI:0x10240c28 %LE %LONG 0x06060606
+ # 33961 === over_write_setting_begin ===
+ # 33961 === over_write_setting_end ===
+ reg_write(0xC0230034, 0x00731010)
+ reg_write(0xC0230024, 0x80030050)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC023005c, 0x00003f00)
+ reg_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC0230060, 0x00000000)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC023005c, 0x00000aff)
+ reg_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC0230060, 0x00000000)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC023005c, 0x00000183)
+ reg_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC0230060, 0x00000000)
+ reg_write(0xC023005c, 0x00000206) # ;RL/WL
+ reg_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC0230060, 0x00000000)
+ reg_write(0xC0230028, 0x00000034)
+ reg_write(0xC023005c, 0x00000b03)
+ reg_write(0xC0230060, 0x00000001)
+
+ #=============================RANK1 MRW==================
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #D.S EAXI:0x1023005c %LE %LONG 0x01003f00
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000aff
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000183
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000206; ;RL/WL
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000b03
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #================== end RANK1 MRW =====================
+
+
+ reg_write(0xC0230060, 0x00000000)
+ reg_write(0xC0230024, 0x80030040)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ reg_write(0xC023005c, 0x00000400)
+
+
+
+ reg_write(0xC023064c, 0x00000005)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC023004c, 0x25774001)
+ reg_write(0xC0230034, 0x00731810)
+ reg_write(0xC0230024, 0x80030000)
+ reg_write(0xC0230004, 0x20082000)
+ reg_write(0xC0230058, 0x00000a56)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ reg_write(0xC023064c, 0x00ff0005)
+ reg_write(0xC0230064, 0x25b1f1cf) # ;REFRDIS=1
+ reg_write(0xC0230610, 0x22653055)
+ reg_write(0xC023004c, 0x45774001)
+ reg_write(0xC0230048, 0x48000000)
+ reg_write(0xC023005c, 0x80000400)
+ reg_write(0xC0230038, 0xc0000107)
+ reg_write(0xC023020c, 0x00010002)
+ reg_write(0xC0230204, 0x00014e00)
+ reg_write(0xC0230094, 0x00100000)
+ reg_write(0xC0230098, 0x00004000)
+ reg_write(0xC023009c, 0x12010480)
+ # 54377 === DE initial sequence done ===
+
+ #selftest
+ #D.S EAXI:0x1023009C %LE %LONG 0x02010080
+ #D.S EAXI:0x10230094 %LE %LONG 0x00100000
+ #D.S EAXI:0x10230098 %LE %LONG 0x00004000
+ #D.S EAXI:0x1023009C %LE %LONG 0x82010080
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ # restore md to ap write secure world register protection
+ reg_write(0xC001DB00, reg_bak_MAS_SEC_0) # MAS_SEC_0[16] = M16_SEC = 0
+ reg_write(0xC001DF00, reg_bak_APC_CON) # APC_CON[2] = DBG_MASK = 1
+
+ print("DRAM_INIT -> elapsed time: {:.3f}".format(time.time()-tim))
+
+
+def DRAM_TEST(thread):
+ """dram test
+ [in] thread, codescape thread object
+ """
+ def _dram_test_by_ice(thread):
+ """simple dram test by ice
+ [in] thread, codescape thread object
+ """
+ adr, siz, omx = 0x0, 0x1000, 0x1000
+ print("_dram_test_by_ice(adr={:#x}, siz={:#x}) ...".format(adr, siz))
+
+ # fix pattern
+ tim = time.time()
+ ptn, inc = 0x55AAAA55, 0
+ print("fix pattern test, {:#010x} ...".format(ptn))
+ idx, rem, err = adr, siz, 0
+ while rem:
+ one = omx if rem > omx else rem
+ thread.memory.Fill(idx, element_size=4, element_count=one>>2, initial_value=ptn, increment=inc)
+ idx += one
+ rem -= one
+ idx, rem = adr, siz
+ while rem:
+ one = omx if rem > omx else rem
+ if not thread.memory.Check(idx, element_size=4, element_count=one>>2, initial_value=ptn, increment=inc):
+ print("-> {:#x}~{:#x} fail ...>\"<".format(idx, idx+one-1))
+ err += 1
+ idx += one
+ rem -= one
+ print("-> elapsed {:.3f} sec, {}".format(time.time()-tim, "fail ...>\"<" if err else "pass"))
+
+ # random pattern
+ print("random pattern test")
+ tim = time.time()
+ ptn = [random.randint(0x0, 0xFFFFFFFF) for _ in range(siz>>2)]
+ idx, rem, err = adr, siz, 0
+ while rem:
+ one = omx if rem > omx else rem
+ thread.memory.Write(idx, ptn[(idx-adr)>>2:(idx-adr+one)>>2])
+ idx += one
+ rem -= one
+ idx, rem, dat = adr, siz, []
+ while rem:
+ one = omx if rem > omx else rem
+ dat.extend(thread.memory.Read(idx, count=one>>2))
+ idx += one
+ rem -= one
+ for idx in range(siz>>2):
+ if ptn[idx] != dat[idx]:
+ print("{:#010x}: {:#010x} -> {:#010x} mismatch".format(idx*4, ptn[idx], dat[idx]))
+ err += 1
+ print("-> elapsed {:.3f} sec, {}".format(time.time()-tim, "fail ...>\"<" if err else "pass"))
+
+ def _dram_test_by_trfg(thread, ctrl=0, loop=2):
+ """use traffic-gen (TRFG) *4 to test DRAM
+ [in] thread, codescape thread object
+ [in] ctrl, all-0: config and start
+ bit-0: start
+ bit-1: pause
+ bit-2: resume
+ [in] loop, test loop, 0:infinite, others:N-times
+ [out] 0:success, 1:fail
+ """
+ TRFG_BASE = 0xC0215000 # TRFG 0~3 offset 0x100
+
+ if ctrl != 0:
+ thread.memory.Write(TRFG_BASE+0x000, ctrl)
+ thread.memory.Write(TRFG_BASE+0x100, ctrl)
+ thread.memory.Write(TRFG_BASE+0x200, ctrl)
+ thread.memory.Write(TRFG_BASE+0x300, ctrl)
+ print("TRFG control done ...")
+ return 0
+
+ print("TRFG config and start ...")
+ for idx in range(4):
+ base = TRFG_BASE + 0x100 * idx
+ start_addr = 0x01000000 * idx
+ pat_ctl = 0x07FF0017 + ((loop & 0xF) << 8)
+ # TRFG_STRAT_CTL, [0]:start, [1]:pause, [2]:resume
+ thread.memory.Write(base+0x00, 0x00000000)
+ # TRFG_INIT_PAT_W3
+ thread.memory.Write(base+0x04, 0x5A5A5A5A)
+ # TRFG_INIT_PAT_W2
+ thread.memory.Write(base+0x08, 0xA5A5A5A5)
+ # TRFG_INIT_PAT_W1
+ thread.memory.Write(base+0x0C, 0x5A5A5A5A)
+ # TRFG_INIT_PAT_W0
+ thread.memory.Write(base+0x10, 0xA5A5A5A5)
+ # TRFG_START_ADDR
+ thread.memory.Write(base+0x14, start_addr)
+ # TRFG_TEST_LEN * 16 byte
+ thread.memory.Write(base+0x18, 0x00040000)
+ # TRFG_PAT_CTL, [11:8]:test_loop, [5:4]:pat_mode
+ thread.memory.Write(base+0x1C, pat_ctl)
+ # TRFG_BUS_CTL, [13:10]:domain, [3:0]:burst_len
+ thread.memory.Write(base+0x20, 0x00000003)
+ # TRFG_STRAT_CTL, [0]:start, [1]:pause, [2]:resume
+ thread.memory.Write(base+0x00, 0x00000001)
+
+ # Wait done
+ print("Wait done")
+ trfg = [None] * 4
+ while None in trfg:
+ print(".")
+ time.sleep(1)
+ for idx in range(4):
+ base = TRFG_BASE + 0x100 * idx
+ if trfg[idx] != None:
+ continue
+ if (thread.memory.Read(base+0x24) & 0x1) == 0x1:
+ continue
+ if (thread.memory.Read(base+0x24) & 0x4) == 0x0:
+ print("-> TRFG {} test fail:".format(idx))
+ print("FAIL_ADDR = {:#010x}".format(thread.memory.Read(base+0x28)))
+ print("EXP_DATA_W3~0 = " + \
+ ", ".join(["{:#010x}".format(thread.memory.Read(base+0x2C+_*4)) for _ in range(4)]))
+ print("FAIL_DATA_W3~0 = " +\
+ ", ".join(["{:#010x}".format(thread.memory.Read(base+0x3C+_*4)) for _ in range(4)]))
+ trfg[idx] = 1
+ else:
+ trfg[idx] = 0
+
+ if trfg == [0,0,0,0]:
+ print("-> TRFG dram test pass ...^_^")
+ return 0
+ else:
+ print("-> TRFG dram test fail ...>'<")
+ return 1
+
+ print("DRAM_TEST() ...")
+ if thread.memory.Read(0xA000001C) < 0x08623511:
+ _dram_test_by_ice(thread)
+ else:
+ _dram_test_by_trfg(thread)
+
+
+def Head8478120_workaround(thread):
+
+ print("Workaround for bitfile(Head8478120) bootslave bug ...")
+ thread.memory.Write(0xA0061118, 0x5500)
+ thread.memory.Write(0xA0061110, 0x9fb40000)
+ thread.memory.Write(0xA0061114, 0x1)
+
+ thread.memory.Write(0xA0061124, 0x5500)
+ thread.memory.Write(0xA006111c, 0x9fb80000)
+ thread.memory.Write(0xA0061120, 0x1)
+
+ thread.memory.Write(0xA0061130, 0x5500)
+ thread.memory.Write(0xA0061128, 0x9fbc0000)
+ thread.memory.Write(0xA006112c, 0x1)
+
+
+if __name__ == "__main__":
+ print "=== Start Initializing ==="
+ umolya_path = ""
+ dsp_path = ""
+ da = codescape.GetFirstProbe()
+ print "Get probe name = %s" %(da.name)
+ probe(da.name)
+ #reset(probe(da.name))
+ #autodetect()
+
+ #config('lazy Freeze',0)
+ #cmdall(halt)
+
+ #print "Enlarge timeout for stability..."
+ #da.SetDASettingValue("Disable MMU Checking", True)
+ #da.SetDASettingValue("apb timeout",500000)
+ #da.SetDASettingValue("Enter Debug Timeout",50000)
+ #da.SetDASettingValue("reset ack timeout",50000)
+ #da.SetDASettingValue("mdh valid retry step",100000)
+ #da.SetDASettingValue("Fast Writes", False)
+
+ thread = da.cores[0].hwthreads[0]
+ core_num = (thread.memory.Read(0x1F000000) & 0xFF)+1
+ print "Get Core Number = %d" %(core_num)
+ #thread = da.cores[0].hwthreads[0]
+ #thread.Stop()
+
+ print "Stop all cores ..."
+ for idx in reversed(range(core_num)):
+ #thread = da.cores[idx].hwthreads[0]
+ #thread.Stop()
+ da.cores[idx].StopAll(False)
+
+ #da.SetDASettingValue("Lock Monitor in Cache", False)
+
+ print "Enable CPU MO port ..."
+ thread.memory.Write(0x1F000020, 0xF)
+ thread.memory.Write(0x1F000090, 0xA0000000)
+ thread.memory.Write(0x1F000098, 0xE0000002)
+ thread.memory.Write(0x1F0000A0, 0xC0000000)
+ thread.memory.Write(0x1F0000A8, 0xC0000002)
+
+ da.SetDASettingValue("Fast Monitor Address", 0x6F800000)
+ da.SetDASettingValue("Fast Writes", False)
+ da.SetDASettingValue("Fast Reads", False)
+
+ time_str = time.time()
+ WDT_Disable(thread)
+ DRAM_INIT(thread)
+ MD_Remap(thread)
+ #Head8478120_workaround(thread)
+ #DRAM_TEST(thread)
+
+ #clear dsp header
+ #print("Clear DSP Header...")
+ #thread.memory.Write(0x0D500000, 0)
+ #thread.memory.Write(0x00080000, 0)
+
+ #print("Clear NVRAM Header...")
+ #Only for BIANCO
+ #thread.memory.Write(0x0D8001FC, 0)
+
+ time_end = time.time()
+ print("Total elapsed time: {:.3f} sec".format(time_end-time_str))
+
+ if codescape.environment == "codescape":
+
+ if codescape.is_script_region:
+ region_thread = codescape.GetRegionThread()
+ # This is a script region, set up events to wait for thread halted
+ import wx
+ class Frame(wx.Frame):
+
+ dsp_bin_addr = dsp_bin_base
+ textctrl = 0
+ restore_callstack_btn = 0
+ def __init__(self, parent, thread):
+ wx.Frame.__init__(self, parent, title="[ModemOnly]LoadBin&Symbol")
+
+ # Initialize UI
+ button_width = 80
+ border_size = 6
+
+ load_all_elf_btn = wx.Button(self, pos=(0, 0), label='Load elf', size=(button_width,-1))
+ load_all_elf_btn.Bind(wx.EVT_BUTTON, self.on_load_all_elf_button)
+
+ button_width = 100
+ border_size = 6
+ load_dsp_btn = wx.Button(self, pos=(0, 35), label='Load DSP Bin', size=(button_width,-1))
+ load_dsp_btn.Bind(wx.EVT_BUTTON, self.on_load_dsp_button)
+
+ statictext = wx.StaticText(self, pos=(110, 40), label="dsp address:")
+
+ button_width = 120
+ border_size = 6
+ Frame.restore_callstack_btn = wx.Button(self, pos=(0, 70), label='Restore CallStack', size=(button_width,-1))
+ Frame.restore_callstack_btn.Bind(wx.EVT_BUTTON, self.on_restore_callstack_button)
+ statictext2 = wx.StaticText(self, pos=(125, 75), label="// use when exception")
+ Frame.restore_callstack_btn.Disable()
+
+ Frame.textctrl = wx.TextCtrl(self,pos=(190, 37), value = self.dsp_bin_addr)
+ Frame.textctrl.Bind(wx.EVT_TEXT, self.OnTextChanged)
+
+
+ # load all elf
+ def on_load_all_elf_button(self, event):
+ #myobject = event.GetEventObject()
+ #myobject.Disable()
+ da.SetDASettingValue("Fast Reads", True)
+ global dsp_bin_base
+ fileDialog = wx.FileDialog(self)
+ fileDialog.ShowModal()
+ umolya_path = fileDialog.GetPath()
+ fileDialog.Destroy()
+ thread = da.cores[0].hwthreads[0]
+ if load_all_elf(da, thread, umolya_path)==1:
+ Frame.restore_callstack_btn.Enable()
+ Frame.dsp_bin_addr = dsp_bin_base
+ Frame.textctrl.SetValue(Frame.dsp_bin_addr)
+ da.SetDASettingValue("Fast Reads", False)
+ #config('lazy Freeze',1)
+ #myobject.Enable()
+
+ # load dsp bin
+ def on_load_dsp_button(self, event):
+ myobject = event.GetEventObject()
+ myobject.Disable()
+ da.SetDASettingValue("Fast Reads", True)
+ print "Select dsp bin...."
+ fileDialog = wx.FileDialog(self)
+ fileDialog.ShowModal()
+ dsp_path = fileDialog.GetPath()
+
+ thread = da.cores[0].hwthreads[0]
+ load_dsp_bin(da, thread, dsp_path,self.dsp_bin_addr)
+ da.SetDASettingValue("Fast Reads", False)
+ myobject.Enable()
+
+ def OnTextChanged(self, event):
+ Frame.dsp_bin_addr = event.String
+ #print "Dsp address set to " + self.dsp_bin_addr
+
+ def on_restore_callstack_button(self, event):
+ myobject = event.GetEventObject()
+ myobject.Disable()
+ da.SetDASettingValue("Fast Reads", True)
+ cmdall(halt)
+ ex_vpe = find_excep_vpe(da)
+ if ex_vpe==-1:
+ print "There is no vpe enter exception!"
+ else:
+ restore_callstack(da, ex_vpe)
+ da.SetDASettingValue("Fast Reads", False)
+ myobject.Enable()
+
+ app = wx.App()
+ frame = Frame(None, region_thread);
+ frame.Show()
+ app.MainLoop()
+ sys.exit()
+ else:
+ if (len(sys.argv) == 2):
+ umolya_path = sys.argv[1]
+ load_all_elf(da, thread, umolya_path)
+ else:
+ # WDT_Disable and DRAM_INIT done
+ sys.exit("[Reminder] Remember to load .elf")
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/APOLLO_EVB.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/APOLLO_EVB.launch
new file mode 100755
index 0000000..aa3527d
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/APOLLO_EVB.launch
@@ -0,0 +1,62 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="["SPV_memset_size_profile[0]","SPV_memset_profile_cnt","SPV_memset_lr_profile[0]"]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.ui.focus_threads" value=""/>
+<stringAttribute key="com.mediatek.ide.dsf.mvpu.dbg_file" value=""/>
+<stringAttribute key="com.mediatek.ide.dsf.mvpu.pattern_file" value=""/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value=""/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.cache.FilePath" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.cache.gdbIndexElf" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.LocalTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.debuggerIpAddress" value="localhost"/>
+<intAttribute key="com.mediatek.ide.util.debuggerPortNumber" value="3333"/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.substitute_path_no_translate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="MT6297_Chip"/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.args" value="-f board/mips/mt6297_mips_chip.cfg -c "adapter_khz 10000""/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.cmds" value=""/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.widget.args" value="{"Clock_10000":"10000"}"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="attach"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
+<booleanAttribute key="org.eclipse.debug.core.capture_output" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_OUTPUT_ON" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/SSButton.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/SSButton.act
new file mode 100755
index 0000000..12d8920
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/SSButton.act
@@ -0,0 +1,14 @@
+<Customize>
+ <Action name="LoadDSP">
+ <GDBSource>coretracer_load_dsp.py</GDBSource>
+ </Action>
+ <Action name="SWLA">
+ <GDBSource>coretracer_swla.py</GDBSource>
+ </Action>
+ <Action name="restoreCallStack">
+ <GDBSource>coretracer_restore_callstack.py</GDBSource>
+ </Action>
+ <Action name="DspExceptionInfo">
+ <GDBSource>../../../dsp_debug_info_CoreTracer.py</GDBSource>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/TCF.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/TCF.py
new file mode 100755
index 0000000..bb8c771
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/TCF.py
@@ -0,0 +1,172 @@
+import getopt
+from multiprocessing import Queue
+import socket
+import sys
+from threading import Thread
+import time
+
+SPLITTER = '\x00'
+EOL = '\x03\x01'
+HEADER = '\x03\x03'
+LEN_EOL = len((SPLITTER + EOL))
+
+class Event():
+ def __init__(self, args):
+ b = bytearray(args).split(SPLITTER.encode('utf_8'))
+ self.servicename = b[1]
+ self.eventname = b[2]
+ self.data = b[3]
+ self.elements = b[3:]
+
+ def getServiceName(self):
+ return self.servicename.decode('utf_8')
+
+ def getEventName(self):
+ return self.eventname.decode('utf_8')
+
+ def getData(self):
+ return self.data.decode('utf_8')
+
+ def getElement(self, index):
+ if len(self.elements) == 0:
+ return ''
+ return self.elements[index]
+
+ def toString(self):
+ datastr = ''
+ for b in self.elements:
+ if not b == EOL:
+ datastr = datastr + ' ' + b.decode('utf_8')
+ return 'Event ' + self.getServiceName() + ' ' + self.getEventName() + ' ' + datastr
+
+class Result():
+ def __init__(self, args):
+ b = bytearray(args).split(SPLITTER.encode('utf_8'))
+ self.type = b[0]
+ self.token = b[1]
+ self.data = b[2]
+ self.elements = b[2:]
+
+ def getType(self):
+ return self.type.decode('utf_8')
+
+ def getToken(self):
+ return self.token.decode('utf_8')
+
+ def getData(self):
+ return self.data.decode('utf_8')
+
+ def getElement(self, index):
+ if len(self.elements) == 0:
+ return ''
+ return self.elements[index]
+
+ def toString(self):
+ datastr = ''
+ for b in self.elements:
+ if not b == EOL:
+ datastr = datastr + ' ' + b.decode('utf_8')
+ return self.getType() + ' ' + self.getToken() + ' ' + datastr
+
+class TCFThread(Thread):
+ def __init__(self, host='localhost', port='1534'):
+ Thread.__init__(self)
+ try:
+ opts, args = getopt.getopt(sys.argv[1:],"h:p:",["host=","port="])
+ for opt, arg in opts:
+ if opt in ("-h", "--host"):
+ host = arg
+ elif opt in ("-p", "--port"):
+ port = int(arg)
+ except getopt.GetoptError:
+ pass
+ self.tcf_terminator = (SPLITTER + EOL).encode('utf_8')
+ self.tcf = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+ self.tcf.connect((host, int(port)))
+ self.queue = Queue()
+ self.send(['E','Locator','Hello','["ZeroCopy"]'])
+
+ def run(self):
+ remain = None
+ while 1:
+ try:
+ data = self.tcf.recv(1024)
+ if remain == None:
+ remain = data
+ else:
+ remain = remain + data
+
+ if bytearray(data).endswith(self.tcf_terminator):
+ res, rem = getData(remain)
+ if bytearray(res).startswith('E'.encode('utf_8')):
+ self.queue.put(Event(res))
+ elif bytearray(res).startswith('R'.encode('utf_8')):
+ self.queue.put(Result(res))
+ remain = rem
+ except:
+ break
+ time.sleep(0.1)
+ self.tcf.close()
+
+ def get(self):
+ if not self.queue.empty():
+ return self.queue.get()
+ else:
+ return None
+
+ def send(self, args):
+ for arg in args:
+ self.tcf.send(str(arg + SPLITTER).encode('utf_8'))
+ self.tcf.send(EOL.encode('utf_8'))
+
+ def rawsend(self, rawarg):
+ self.tcf.send(rawarg)
+
+ def close(self):
+ self.tcf.shutdown(1)
+ self.tcf.close()
+
+def getData(arg):
+ data = bytearray(arg)
+ result = None
+ remain = None
+ if data.startswith(HEADER.encode('utf_8')):
+ ind = data.index(HEADER.encode('utf_8'))+2
+ leng, cnt = getDataLength(data, ind, 0)
+ ind = ind + cnt + 1
+ result = data[ind:ind+leng-1]
+ remain = data[ind+leng-1:]
+ else:
+ ind = data.index((SPLITTER + EOL).encode('utf_8'))
+ if not ind == -1:
+ result = data[:ind]
+ remain = data[ind:]
+ else:
+ result = None
+ remain = data
+
+ if not remain == None and bytearray(remain).startswith((SPLITTER + EOL).encode('utf_8')):
+ remain = remain[LEN_EOL:]
+
+# print('result: \'' + str(result) + '\'')
+# print('remain: \'' + str(remain) + '\'')
+# sys.stdout.flush()
+ return result, remain
+
+def getDataLength(_rec, ind, count):
+ rec_bytes = bytearray(_rec);
+ leng = rec_bytes[ind]
+ mulp = 0
+ if count == 0:
+ mulp = 1
+ else:
+ mulp = 128 * count
+
+ if leng & 0x80 == 0:
+ return leng * mulp, count
+ else:
+ num, cnt = getDataLength(rec_bytes, ind + 1, count + 1)
+ return ((leng & 0x7f) * mulp) + num, cnt
+
+def doEcaspe(arg):
+ return str(arg).replace('\\', '\\\\').replace('\"', '\\\"')
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/TCF.pyc b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/TCF.pyc
new file mode 100755
index 0000000..f47f3c8
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/TCF.pyc
Binary files differ
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/coretracer_basic_init.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/coretracer_basic_init.py
new file mode 100755
index 0000000..12d261d
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/coretracer_basic_init.py
@@ -0,0 +1,213 @@
+import sys
+import time
+import os
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+
+#MD Side
+AP_REG_BASE=0xC0000000
+MD_REG_BASE=0xA0000000
+
+#AP side
+#AP_REG_BASE=0x10000000
+#MD_REG_BASE=0x20000000
+
+def switch_to_axi_mode():
+ print("Switch to AXI port ..")
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ mem_value = mem_value[12:23]
+ hex_int = int(mem_value, 16)
+ return hex_int
+
+def WDT_Disable():
+ """diable WDT function
+ [in] thread, codescape thread object
+ """
+ print("WDT disable ..")
+ mdrgu = 0xA00F0000 + 0x0100
+ aprgu = 0xC0007000
+ memory_write(mdrgu, (memory_read(mdrgu) & 0xFFFFFFFC) | 0x55000000)
+ memory_write(aprgu, (memory_read(aprgu) & 0xFFFFFFFE) | 0x22000000)
+
+def MD_SRCLKENA():
+ print("MD_SRCLKENA config ..")
+ """
+ INFRA_MISC2
+ [3:0] : mdsrc_req_0_en = 4'b0001
+ [7:4] : mdsrc_req_1_en = 4'b0010
+ """
+ infra_misc2_addr = 0x10001f0c
+ memory_write(infra_misc2_addr, (memory_read(infra_misc2_addr) & 0xFFFFFF00) | 0x21)
+
+ """
+ SRCLKEN_O1 Force RF On
+ """
+ addr1 = 0xC0006000
+ addr2 = 0xC0006008
+ memory_write(addr1, 0x0B160001) # magic key
+ memory_write(addr2, memory_read(addr2) | (1<<21) ) #set bit[21]
+
+def Config_26M_Quality():
+ print("Config 26M Quality ..")
+ addr = 0xC000C018
+ memory_write(addr, memory_read(addr) | 0x3 ) # set bit[1:0] = 2'b11
+ addr = 0xC000C00C
+ memory_write(addr, memory_read(addr) | 0x3 ) # set bit[1:0] = 2'b11
+ addr = 0xC000C000
+ memory_write(addr, memory_read(addr) | 0x3 ) # set bit[1:0] = 2'b11
+
+def MD_Remap(adr=None):
+ print("MD EMI Remap ..")
+ """MD reamp config
+ [in] thread, codescape thread object
+ [in] adr, user specific remap address (ap infra memory map view, 32M alignment)
+ default: emi start address
+ """
+
+ inf_emi = 0x40000000
+ print("MD_Remap(adr={:#x}) ...".format(inf_emi if adr == None else adr))
+ if adr == None:
+ inf_md = inf_emi
+ else:
+ assert (adr & 0x01FFFFFF) == 0
+ inf_md = adr
+ print("MD_Remap -> md:bank0=>ap:{:#x}, md:bank1=>ap:{:#x}, md:bank4=>ap:{:#x}".format(inf_md, inf_md+0x10000000, inf_emi))
+ # md remap bank 0
+ bnk = inf_md >> 25
+ memory_write(0xC0001300, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ memory_write(0xC0001304, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ memory_write(0xC0001308, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ memory_write(0xC000130c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+ # md remap bank 1
+ bnk = (inf_md+0x10000000) >> 25
+ memory_write(0xC0001310, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ memory_write(0xC0001314, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ memory_write(0xC0001318, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ memory_write(0xC000131c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+ # md remap bank 4
+ bnk = inf_emi >> 25
+ memory_write(0xC0001320, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ memory_write(0xC0001324, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ memory_write(0xC0001328, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ memory_write(0xC000132c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+
+def MO_Port_Enable():
+ print("MO port enable ..")
+ """
+ enable shaolin MO port
+ """
+ memory_write(0x1F000020, 0xF)
+ memory_write(0x1F000090, 0xA0000000)
+ memory_write(0x1F000098, 0xE0000002)
+ memory_write(0x1F0000A0, 0xC0000000)
+ memory_write(0x1F0000A8, 0xC0000002)
+
+def Switch_MDJtag_to_ShaolinDAP():
+ print("Switch MDJtag to ShaolinDAP ..")
+ """
+ switch MD JTAG to shaolinDAP (the jtag is defaultly for codescape. We want to let coretracer can use it.)
+ dbgsys addr = 0x0d101100
+ """
+ memory_write(0xA0601100, 0x3)
+ return
+
+def MD_PLL_Init():
+ print("MD PLL Init ..")
+ REGBASE_PLLMIXED = 0xA0140000
+ REGBASE_CLKSW = 0xA0150000
+
+ # default md_srclken_ack settle time = 150T 32k
+ memory_write(REGBASE_PLLMIXED+0x4, 0x02021c96)
+ # change APBPLL_SETTLE_26M to 0x2f2 => 29us
+ memory_write(REGBASE_PLLMIXED+0x20, 0x17920803)
+
+
+ memory_write(REGBASE_CLKSW+0xB8, 0x0) # Set HRAM to 800Mhz
+ memory_write(REGBASE_CLKSW+0x8c, 0x30)# Set NRPLL4_1_CK to 800Mhz
+ memory_write(REGBASE_CLKSW+0x5c, 0x11)# Set BPIPLL
+ memory_write(REGBASE_CLKSW+0x78, 0x10)# Set NRPLL1
+ memory_write(REGBASE_CLKSW+0x70, 0x21)# Set NRL2 spec to 450Mhz
+ memory_write(REGBASE_CLKSW+0x94, 0x10)# Set MCORE spec to 900MHz
+ memory_write(REGBASE_CLKSW+0x90, 0x10)# Set VCORE spec to 900MHz
+
+
+ memory_write(REGBASE_CLKSW+0xF00, 0x00D7FFFF) # NR0/1/2/4 PLL turn on
+
+ memory_write(REGBASE_PLLMIXED+0x84, memory_read(REGBASE_PLLMIXED+0x84) & 0xfffeffff) # Set FBKSEL = 0
+ memory_write(REGBASE_PLLMIXED+0x8c, memory_read(REGBASE_PLLMIXED+0x8c) & 0xfffeffff) # Set FBKSEL = 0
+
+ memory_write(REGBASE_PLLMIXED+0x58, 0x80117b13) # Fixed Fvco = 1818Mhz
+ memory_write(REGBASE_PLLMIXED+0x50, 0x8023d800) # Fvco = 3728Mhz. 3728/4 = 932Mhz
+ memory_write(REGBASE_PLLMIXED+0x48, 0x80229e00) # Fvco = 3600Mhz. 3600/4 = 900Mhz
+ memory_write(REGBASE_PLLMIXED+0x40, 0x8019f626) # Fvco = 2700Mhz. 2700/3 = 900Mhz
+
+ memory_write(REGBASE_PLLMIXED+0x98, 0x80180000) # Fvco = 2496Mhz. 2496/4 = 624Mhz
+ memory_write(REGBASE_PLLMIXED+0x9c, 0x12)
+
+ memory_write(REGBASE_PLLMIXED+0x68, 0x80133c00) # Fvco = 2000Mhz. 2000/2 = 1000Mhz
+ memory_write(REGBASE_PLLMIXED+0x70, 0x80171400) # Fvco = 2400Mhz. 2400/2 = 1000Mhz
+ memory_write(REGBASE_PLLMIXED+0x78, 0x801aec00) # Fvco = 2800Mhz. 2800/2 = 1400Mhz
+ memory_write(REGBASE_PLLMIXED+0x80, 0x80180000) # Fvco = 2496Mhz. 2496/4 = 624Mhz
+ memory_write(REGBASE_PLLMIXED+0x88, 0x800f6200) # Fvco = 1600Mhz. 1600/1 = 1600Mhz
+ memory_write(REGBASE_PLLMIXED+0x90, 0x801cd800) # Fvco = 3000Mhz. 3000/2 = 1500Mhz
+
+ memory_write(REGBASE_PLLMIXED+0x10, 0x0)
+
+ # polling untill MDMCUPLL complete freq adjustment
+ dummy_x = 0
+ while (memory_read(REGBASE_PLLMIXED+0x800) >> 14) & 0x1 == 0x1 :
+ dummy_x+=1
+
+ # wait MD bus clock ready
+ dummy_y = 0
+ while memory_read(REGBASE_CLKSW+0xcc) & 0x8000 != 0x8000 :
+ dummy_y+=1
+
+ #switch clock source to PLL
+ memory_write(REGBASE_CLKSW+0x24, memory_read(REGBASE_CLKSW+0x24) | 0x3) # switch MDMCU & MDBUS clock to PLL freq
+
+ memory_write(REGBASE_CLKSW+0x24, memory_read(REGBASE_CLKSW+0x24) | 0xfffffffc) # switch all clock to PLL freq
+ memory_write(REGBASE_CLKSW+0x28, memory_read(REGBASE_CLKSW+0x28) | 0x4)
+
+ memory_write(REGBASE_CLKSW+0x20, 0x3) # Turn off all SW clock request
+
+ memory_write(REGBASE_CLKSW+0x2c, memory_read(REGBASE_CLKSW+0x2c) | 0x1100011) # switch SDF clock to PLL freq
+
+ memory_write(REGBASE_PLLMIXED+0x314, 0xffff) # Clear PLL ADJ RDY IRQ fired by initial period adjustment
+ memory_write(REGBASE_PLLMIXED+0x318, 0xffff) # Mask all PLL ADJ RDY IRQ
+
+ memory_write(REGBASE_PLLMIXED+0xf00, 0x62970000) # Write PLL magic number
+ return
+
+if __name__ == "__main__":
+ #MO_Port_Enable()
+ switch_to_axi_mode()
+
+ #Switch_MDJtag_to_ShaolinDAP()
+
+ WDT_Disable()
+
+ #MD_SRCLKENA()
+
+ Config_26M_Quality()
+
+ #MD_Remap()
+
+ #MD_PLL_Init()
+ print "All misc config done!"
+
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/coretracer_init_emi.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/coretracer_init_emi.py
new file mode 100755
index 0000000..f44c884
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/coretracer_init_emi.py
@@ -0,0 +1,707 @@
+import sys
+import time
+import os
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+
+#MD Side
+AP_REG_BASE=0xC0000000
+MD_REG_BASE=0xA0000000
+
+#AP side
+#AP_REG_BASE=0x10000000
+#MD_REG_BASE=0x20000000
+
+def switch_to_axi_mode():
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ mem_value = mem_value[12:23]
+ hex_int = int(mem_value, 16)
+ return hex_int
+
+def DRAM_INIT():
+ print("DRAM_INIT ...")
+ tim = time.time()
+
+ # disable md to ap write secure world register protection
+ reg_bak_APC_CON = memory_read(0xC001DF00)
+ reg_bak_MAS_SEC_0 = memory_read(0xC001DB00)
+ memory_write(0xC001DF00, 0x00000000) # APC_CON[2] = DBG_MASK = 0
+ memory_write(0xC001DB00, 0x00010000) # MAS_SEC_0[16] = M16_SEC = 1
+
+ NR_RNKS=1
+ #EMI
+
+ #DRAMC0_NAO
+ #0x10234***
+ #DRAMC0
+ #0x10230***
+ #DRAMC1
+ #0x10240***
+ #DDRPHY0
+ #0x10238***
+ #DDRPHY1
+ #0x10248***
+
+ #EMI setting
+ memory_write(0xC0219000, 0x00001052) # ;0x00025052
+ memory_write(0xC0219060, 0xff000400)
+ memory_write(0xC0219020, 0x00008000)
+ memory_write(0xC0235000, 0x00001012) # ;0x00005053
+ memory_write(0xC0235010, 0x00000001)
+
+
+ #;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ memory_write(0xC0238274, 0xffffffff)
+ memory_write(0xC0248278, 0x00000000)
+ memory_write(0xC0248274, 0xffffffff)
+ memory_write(0xC023829c, 0x38030000)
+ #PLL sel
+
+ memory_write(0xC02381a0, 0x00000000)
+ memory_write(0xC02380a0, 0x00000000)
+ memory_write(0xC0238120, 0x00000000)
+ memory_write(0xC02382ac, 0x80000006)
+ memory_write(0xC02481a0, 0x00000000)
+ memory_write(0xC02480a0, 0x00000000)
+ memory_write(0xC0248120, 0x00000000)
+ memory_write(0xC02482ac, 0x80000006)
+ memory_write(0xC02382a0, 0x00000100) # ;PINMUX
+ memory_write(0xC02482a0, 0x00000100)
+ memory_write(0xC0238264, 0x00400000)
+ memory_write(0xC0238268, 0x00000040)
+ memory_write(0xC0248264, 0x00400000)
+ memory_write(0xC0248268, 0x00000040)
+ memory_write(0xC0238e18, 0x00000000)
+ memory_write(0xC0238f18, 0x01010000)
+ memory_write(0xC0239018, 0x02020000)
+ memory_write(0xC0238e68, 0x04040000)
+ memory_write(0xC0238f68, 0x05050000)
+ memory_write(0xC0239068, 0x06060000)
+ memory_write(0xC0238ec4, 0x00000c00)
+ memory_write(0xC0238fc4, 0x00000c00)
+ memory_write(0xC02393c4, 0x00000c00)
+ memory_write(0xC02394c4, 0x00000c00)
+ memory_write(0xC0238e50, 0x00000000)
+ memory_write(0xC0238f50, 0xbbbbbbbb)
+ memory_write(0xC0239050, 0xbbbbbbbb)
+ memory_write(0xC0238e54, 0x00000000)
+ memory_write(0xC0238f54, 0x0000bb00)
+ memory_write(0xC0239054, 0x0000bb00)
+ memory_write(0xC0248ea0, 0x00000000)
+ memory_write(0xC0248fa0, 0x00bbbbbb)
+ memory_write(0xC02490a0, 0x00bbbbbb)
+ memory_write(0xC0248ea4, 0x00000000)
+ memory_write(0xC0248fa4, 0x00000bbb)
+ memory_write(0xC02490a4, 0x00000bbb)
+ memory_write(0xC0248e00, 0x00000000)
+ memory_write(0xC0248f00, 0xbbbbbbbb)
+ memory_write(0xC0249000, 0xbbbbbbbb)
+ memory_write(0xC0248e04, 0x00000000)
+ memory_write(0xC0248f04, 0x0000bb00)
+ memory_write(0xC0249004, 0x0000bb00)
+ memory_write(0xC0248e50, 0x00000000)
+ memory_write(0xC0248f50, 0xbbbbbbbb)
+ memory_write(0xC0249050, 0xbbbbbbbb)
+ memory_write(0xC0248e54, 0x00000000)
+ memory_write(0xC0248f54, 0x0000bb00)
+ memory_write(0xC0249054, 0x0000bb00)
+ memory_write(0xC0238e1c, 0x00000c00)
+ memory_write(0xC0238f1c, 0x00000c00)
+ memory_write(0xC023901c, 0x00000c00)
+ memory_write(0xC0238e6c, 0x000f0f00)
+ memory_write(0xC0238f6c, 0x000f0f00)
+ memory_write(0xC023906c, 0x000f0f00)
+ memory_write(0xC0248ec4, 0x00000f0f)
+ memory_write(0xC0248fc4, 0x00000f0f)
+ memory_write(0xC02490c4, 0x00000f0f)
+ memory_write(0xC0248e1c, 0x000f0f00)
+ memory_write(0xC0248f1c, 0x000f0f00)
+ memory_write(0xC024901c, 0x000f0f00)
+ memory_write(0xC0248e6c, 0x000f0f00)
+ memory_write(0xC0248f6c, 0x000f0f00)
+ memory_write(0xC024906c, 0x000f0f00)
+ memory_write(0xC0238128, 0x00001010)
+ memory_write(0xC023812c, 0x01111010)
+ memory_write(0xC0238130, 0x010c10d0)
+ memory_write(0xC023812c, 0x03111010)
+ memory_write(0xC02381a4, 0x0000008c)
+ #TINFO="SHL ddrphy chA reset release"
+ memory_write(0xC02381b0, 0x00080010) # ;SER MODE
+ memory_write(0xC0238d04, 0x00000101)
+ memory_write(0xC0238d08, 0x00000101)
+ memory_write(0xC0239204, 0x00000101)
+ memory_write(0xC0239208, 0x00000101)
+ memory_write(0xC02380a4, 0x0000008c)
+ memory_write(0xC02380b0, 0x00080010) # ;SER MODE
+ memory_write(0xC0238c04, 0x00000101)
+ memory_write(0xC0238c08, 0x00000101)
+ memory_write(0xC0239104, 0x00000101)
+ memory_write(0xC0239108, 0x00000101)
+ memory_write(0xC02481a8, 0x00001010)
+ memory_write(0xC02481ac, 0x01111010)
+ memory_write(0xC02481b0, 0x010c10d0)
+ memory_write(0xC02481ac, 0x03111010)
+ memory_write(0xC02480a8, 0x00001010)
+ memory_write(0xC02480ac, 0x01111010)
+ memory_write(0xC02480b0, 0x010c10d0)
+ memory_write(0xC02480ac, 0x03111010)
+ memory_write(0xC0248128, 0x00001010)
+ memory_write(0xC024812c, 0x01111010)
+ memory_write(0xC0248130, 0x010c10d0)
+ memory_write(0xC024812c, 0x03111010)
+ #PLL
+
+ memory_write(0xC0238c18, 0x44000000)
+ memory_write(0xC0239118, 0x04000000)
+ memory_write(0xC0238c98, 0x44000000)
+ memory_write(0xC0239198, 0x04000000)
+ memory_write(0xC0238d18, 0x44000000)
+ memory_write(0xC0239218, 0x04000000)
+ memory_write(0xC0248c18, 0x44000000)
+ memory_write(0xC0249118, 0x04000000)
+ memory_write(0xC0248c98, 0x44000000)
+ memory_write(0xC0249198, 0x04000000)
+ memory_write(0xC0248d18, 0x44000000)
+ memory_write(0xC0249218, 0x04000000)
+ memory_write(0xC0238da0, 0x00000000)
+ memory_write(0xC02392a0, 0x00000000)
+ # DLL
+
+ memory_write(0xC0238124, 0x0000051e)
+ memory_write(0xC02481a4, 0x0000051e)
+ #TINFO="SHL ddrphy chB reset release"
+ memory_write(0xC02480a4, 0x0000051e)
+ memory_write(0xC0248124, 0x0000051e)
+ memory_write(0xC0238194, 0x00660600)
+ memory_write(0xC0238094, 0xc0660600)
+ memory_write(0xC0238114, 0xc0660600)
+ memory_write(0xC0248194, 0xc0660600)
+ memory_write(0xC0248094, 0xc0660600)
+ memory_write(0xC0248114, 0xc0660600)
+ memory_write(0xC02381b8, 0x00180101)
+ memory_write(0xC023826c, 0x00000000)
+ memory_write(0xC02481b8, 0x00180101)
+ memory_write(0xC024826c, 0x00000000)
+ memory_write(0xC0238d14, 0x00000000)
+ memory_write(0xC0239214, 0x00000000)
+ memory_write(0xC0239714, 0x00000000)
+ memory_write(0xC0239c14, 0x00000000)
+ memory_write(0xC0248d14, 0x00000000)
+ memory_write(0xC0249214, 0x00000000)
+ memory_write(0xC0249714, 0x00000000)
+ memory_write(0xC0249c14, 0x00000000)
+
+ time.sleep(0.001)
+
+ memory_write(0xC023800c, 0x006d0000)
+ memory_write(0xC0238180, 0x0000000c)
+ memory_write(0xC0238080, 0x00000009)
+ memory_write(0xC0238100, 0x00000009)
+ memory_write(0xC0248180, 0x00000009)
+ memory_write(0xC0248080, 0x00000009)
+ memory_write(0xC0248100, 0x00000009)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238000, 0x80000000)
+ memory_write(0xC0238004, 0x80000000)
+ memory_write(0xC0238004, 0x00000000)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238da4, 0x00019200)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238194, 0x00660e00)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238094, 0xc0660e00)
+ memory_write(0xC0238114, 0xc0660e00)
+ memory_write(0xC0248194, 0xc0660e00)
+ memory_write(0xC0248094, 0xc0660e00)
+ memory_write(0xC0248114, 0xc0660e00)
+ memory_write(0xC0238284, 0x0000001f)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238124, 0x0001051e)
+ memory_write(0xC02481a4, 0x0001051e)
+ memory_write(0xC02480a4, 0x0001051e)
+ memory_write(0xC0248124, 0x0001051e)
+ memory_write(0xC02382a0, 0x8100018c)
+ memory_write(0xC02482a0, 0x8100018c)
+ memory_write(0xC02381b8, 0x00040101)
+ memory_write(0xC02381b4, 0x00000000)
+ memory_write(0xC02380b4, 0x00000000)
+ memory_write(0xC0238134, 0x00000000)
+ memory_write(0xC0238c1c, 0x00200000) # ; WJ: LP3
+ memory_write(0xC02481b4, 0x00000000)
+ memory_write(0xC02480b4, 0x00000000)
+ memory_write(0xC0248134, 0x00000000)
+ memory_write(0xC0248c1c, 0x00200000) # ; WJ: LP3
+ memory_write(0xC02300dc, 0x00051008)
+ #;D.S EAXI:0x1024000dc %LE %LONG 0x00050008
+ memory_write(0xC0230000, 0x02101000) # ;[24]=LP2_EN , [25]=LP3_EN, [26]=LP4_EN
+ memory_write(0xC0230640, 0xa688049f)
+ memory_write(0xC0230660, 0x00030053)
+ memory_write(0xC023004c, 0x25712000)
+ memory_write(0xC0230680, 0x00000000)
+ memory_write(0xC0230684, 0x00000000)
+ memory_write(0xC0230688, 0x00000000)
+ memory_write(0xC023068c, 0x00000000)
+ memory_write(0xC0230690, 0x11111011)
+ memory_write(0xC0230694, 0x01101111)
+ memory_write(0xC0230698, 0x11111111)
+ memory_write(0xC023069c, 0x11111111)
+ memory_write(0xC02306a0, 0x11111111) # ;TXDLY DQS
+ memory_write(0xC02306a4, 0x66667777)
+ memory_write(0xC023082c, 0x11111111) # ;TXDLY DQ
+ memory_write(0xC0230830, 0x11111111) # ;TXDLY DQM
+ memory_write(0xC0230834, 0x66667777)
+ memory_write(0xC0230838, 0x66667777)
+ #D.S EAXI:0x1023092c %LE %LONG 0x22222222
+ #D.S EAXI:0x10230930 %LE %LONG 0x22222222
+ #D.S EAXI:0x10230934 %LE %LONG 0x66667777
+ #D.S EAXI:0x10230938 %LE %LONG 0x66667777
+ #D.S EAXI:0x10230a2c %LE %LONG 0x22222222
+ #D.S EAXI:0x10230a30 %LE %LONG 0x22222222
+ #D.S EAXI:0x10230a34 %LE %LONG 0x66667777
+ #D.S EAXI:0x10230a38 %LE %LONG 0x66667777
+ memory_write(0xC023081c, 0x00000000)
+ memory_write(0xC0230820, 0x00000000)
+ #D.S EAXI:0x1023091c %LE %LONG 0x00000000
+ #D.S EAXI:0x10230920 %LE %LONG 0x00000000
+ #D.S EAXI:0x10230a1c %LE %LONG 0x00000000
+ #D.S EAXI:0x10230a20 %LE %LONG 0x66666666
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ memory_write(0xC0230200, 0xf0100000) # ;[31]=DQSIEN MODE
+ memory_write(0xC0230048, 0x08000000)
+ memory_write(0xC0230678, 0xc0000000)
+ memory_write(0xC0230600, 0x09030b06)
+ memory_write(0xC0230604, 0x14090901)
+ memory_write(0xC0230608, 0x0c050201)
+ memory_write(0xC023060c, 0x00490019)
+ memory_write(0xC0230614, 0x01000606)
+ memory_write(0xC023061c, 0x02030408)
+ memory_write(0xC0230620, 0x02000400)
+ memory_write(0xC0230648, 0x9007320f)
+ memory_write(0xC0230644, 0x00000b0d) # ;DATLAT
+ memory_write(0xC0230000, 0x02111000) # ;[24]=LP2_EN , [25]=LP3_EN, [26]=LP4_EN
+ memory_write(0xC0230004, 0x20002000)
+ memory_write(0xC0230008, 0x81080000)
+ memory_write(0xC023000c, 0x0002cf13)
+ memory_write(0xC0230010, 0x00000080)
+ memory_write(0xC0230020, 0x00000009)
+ memory_write(0xC0230024, 0x80030000)
+ memory_write(0xC0230038, 0x80000106)
+ memory_write(0xC0230040, 0x3000000c)
+ memory_write(0xC023004c, 0x25714001)
+ memory_write(0xC0230064, 0x25b1f1cf) # ;REFRDIS=1
+ memory_write(0xC02300b0, 0x04300000)
+ memory_write(0xC0230200, 0xf0310000) # ;[31]=DQSIEN MODE
+ memory_write(0xC0230658, 0x21200001)
+ memory_write(0xC0230800, 0x00000002)
+ #D.S EAXI:0x10230900 %LE %LONG 0x00000002
+ #D.S EAXI:0x10230a00 %LE %LONG 0x00000002
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230824, 0x10101010) # ;GATE WINDOW unit:2T
+ memory_write(0xC0230828, 0x17171717)
+ #D.S EAXI:0x10230924 %LE %LONG 0x11111111
+ #D.S EAXI:0x10230928 %LE %LONG 0x42424242
+ #D.S EAXI:0x10230a24 %LE %LONG 0x32323232
+ #D.S EAXI:0x10230a28 %LE %LONG 0x06060606
+ #;D.S EAXI:0x10240a24 %LE %LONG 0x00000000; ;GATE WINDOW unit:2T
+ #;D.S EAXI:0x10240a28 %LE %LONG 0x53535353
+ #;D.S EAXI:0x10240b24 %LE %LONG 0x32323232
+ #;D.S EAXI:0x10240b28 %LE %LONG 0x06060606
+ #;D.S EAXI:0x10240c24 %LE %LONG 0x32323232
+ #;D.S EAXI:0x10240c28 %LE %LONG 0x06060606
+ # 33961 === over_write_setting_begin ===
+ # 33961 === over_write_setting_end ===
+ memory_write(0xC0230034, 0x00731010)
+ memory_write(0xC0230024, 0x80030050)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC023005c, 0x00003f00)
+ memory_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230060, 0x00000000)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC023005c, 0x00000aff)
+ memory_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230060, 0x00000000)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC023005c, 0x00000183)
+ memory_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230060, 0x00000000)
+ memory_write(0xC023005c, 0x00000206) # ;RL/WL
+ memory_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230060, 0x00000000)
+ memory_write(0xC0230028, 0x00000034)
+ memory_write(0xC023005c, 0x00000b03)
+ memory_write(0xC0230060, 0x00000001)
+
+ #=============================RANK1 MRW==================
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #D.S EAXI:0x1023005c %LE %LONG 0x01003f00
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000aff
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000183
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000206; ;RL/WL
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000b03
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #================== end RANK1 MRW =====================
+
+
+ memory_write(0xC0230060, 0x00000000)
+ memory_write(0xC0230024, 0x80030040)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ memory_write(0xC023005c, 0x00000400)
+
+
+
+ memory_write(0xC023064c, 0x00000005)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC023004c, 0x25774001)
+ memory_write(0xC0230034, 0x00731810)
+ memory_write(0xC0230024, 0x80030000)
+ memory_write(0xC0230004, 0x20082000)
+ memory_write(0xC0230058, 0x00000a56)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ memory_write(0xC023064c, 0x00ff0005)
+ memory_write(0xC0230064, 0x25b1f1cf) # ;REFRDIS=1
+ memory_write(0xC0230610, 0x22653055)
+ memory_write(0xC023004c, 0x45774001)
+ memory_write(0xC0230048, 0x48000000)
+ memory_write(0xC023005c, 0x80000400)
+ memory_write(0xC0230038, 0xc0000107)
+ memory_write(0xC023020c, 0x00010002)
+ memory_write(0xC0230204, 0x00014e00)
+ memory_write(0xC0230094, 0x00100000)
+ memory_write(0xC0230098, 0x00004000)
+ memory_write(0xC023009c, 0x12010480)
+ # 54377 === DE initial sequence done ===
+
+ #selftest
+ #D.S EAXI:0x1023009C %LE %LONG 0x02010080
+ #D.S EAXI:0x10230094 %LE %LONG 0x00100000
+ #D.S EAXI:0x10230098 %LE %LONG 0x00004000
+ #D.S EAXI:0x1023009C %LE %LONG 0x82010080
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ # restore md to ap write secure world register protection
+ memory_write(0xC001DB00, reg_bak_MAS_SEC_0) # MAS_SEC_0[16] = M16_SEC = 0
+ memory_write(0xC001DF00, reg_bak_APC_CON) # APC_CON[2] = DBG_MASK = 1
+
+ print("DRAM_INIT -> elapsed time: {:.3f}".format(time.time()-tim))
+
+def MD_Remap(adr=None):
+ """MD reamp config
+ [in] thread, codescape thread object
+ [in] adr, user specific remap address (ap infra memory map view, 32M alignment)
+ default: emi start address
+ """
+
+ inf_emi = 0x80000000 if memory_read(0xA000001C) < 0x08566094 else 0x40000000
+ print("MD_Remap(adr={:#x}) ...".format(inf_emi if adr == None else adr))
+ if adr == None:
+ inf_md = inf_emi
+ else:
+ assert (adr & 0x01FFFFFF) == 0
+ inf_md = adr
+ print("MD_Remap -> md:bank0=>ap:{:#x}, md:bank1=>ap:{:#x}, md:bank4=>ap:{:#x}".format(inf_md, inf_md+0x10000000, inf_emi))
+ # md remap bank 0
+ bnk = inf_md >> 25
+ memory_write(0xC0001300, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ memory_write(0xC0001304, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ memory_write(0xC0001308, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ memory_write(0xC000130c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+ # md remap bank 1
+ bnk = (inf_md+0x10000000) >> 25
+ memory_write(0xC0001310, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ memory_write(0xC0001314, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ memory_write(0xC0001318, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ memory_write(0xC000131c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+ # md remap bank 4
+ bnk = inf_emi >> 25
+ memory_write(0xC0001320, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ memory_write(0xC0001324, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ memory_write(0xC0001328, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ memory_write(0xC000132c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+
+def WDT_Disable():
+ """diable WDT function
+ [in] thread, codescape thread object
+ """
+ print("WDT disable ...")
+ mdrgu = 0xA00F0000 + 0x0100
+ aprgu = 0xC0007000
+ memory_write(mdrgu, (memory_read(mdrgu) & 0xFFFFFFFC) | 0x55000000)
+ memory_write(aprgu, (memory_read(aprgu) & 0xFFFFFFFE) | 0x22000000)
+
+if __name__ == "__main__":
+ switch_to_axi_mode()
+ WDT_Disable()
+ DRAM_INIT()
+ MD_Remap()
+ tEnd = time.time()
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/coretracer_load_dsp.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/coretracer_load_dsp.py
new file mode 100755
index 0000000..96ff456
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/coretracer_load_dsp.py
@@ -0,0 +1,147 @@
+#from imgtec import codescape
+import sys
+import time
+import os
+sys.path.append(os.path.dirname(os.path.realpath(__file__)))
+import gdb
+import binascii
+import Tkinter, tkFileDialog
+from TCF import Event, Result
+import TCF as client
+
+app = None
+dsp_header = 0x0
+dsp_magic = "4d4d4d01"
+
+TCF_HOST = 'localhost'
+TCF_PORT = 1534
+
+def get_tcf_port():
+ global TCF_PORT
+ gdb_cmd = 'show env tcfport'
+ res = gdb.execute(gdb_cmd, to_string=True)
+ TCF_PORT = int(res.split()[2], 0)
+ print "TCF_PORT = " + str(TCF_PORT)
+
+def switch_to_axi_mode():
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def switch_to_apb_mode():
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write off'
+ gdb.execute(gdb_cmd)
+
+def print_to_log(str):
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','log',str+'\n'])
+ tcf.close()
+
+# load dsp bin file
+def load_dsp_bin(dsp_path):
+ global dsp_header
+
+ time_str = time.time()
+ #print_to_log("=== Start to load dsp bin ===")
+ print_to_log("Dsp bin path: " + dsp_path)
+ if(os.path.exists(dsp_path) == False):
+ print_to_log( "DSP bin doesn't exist: %s" %(dsp_path))
+ print_to_log( "[Error] Load DSP bin failed")
+ return
+ else:
+ with open(dsp_path, "rb") as dsp_bin:
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print_to_log( "No header detected, continue")
+ else:
+ dsp_header = 0x200
+ dsp_bin.seek(dsp_header, os.SEEK_SET)
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print_to_log( "Header detected, skip first 512B")
+ else:
+ print_to_log( "DSP header detected at neither 0x0 nor 0x200")
+ print_to_log( "Please check the bin is legal!")
+ print_to_log( "[Error] Load DSP bin failed")
+ return
+ gdb_cmd='thread 1'
+ gdb.execute(gdb_cmd)
+ ## a) need parsing: 0x13a0000 <dsp_bin_ro>
+ ##symbol_name='&dsp_bin_ro'
+ ##dsp_addr = gdb.parse_and_eval(symbol_name)
+ ## b) need parsing: $3 = 0x13a0000
+ ##gdb_cmd='p/x &dsp_bin_ro'
+ ##dsp_addr = gdb.execute(gdb_cmd, False, True)
+ symbol_name='dsp_bin_ro'
+ dsp_addr = gdb.parse_and_eval(symbol_name)
+ dsp_addr = str(dsp_addr.address).split(" ")
+ dsp_addr = int(dsp_addr[0], 16) - dsp_header
+ #print_to_log( hex(dsp_addr) )
+ gdb_cmd = " ".join(['restore', dsp_path, 'binary', hex(dsp_addr), hex(dsp_header)])
+ #print_to_log( gdb_cmd)
+ switch_to_axi_mode()
+ print_to_log( "Load DSP bin ......................")
+ gdb.execute(gdb_cmd)
+ switch_to_apb_mode()
+ time_end = time.time()
+ print_to_log("loading dsp is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+
+class gui_tk(Tkinter.Tk):
+ def __init__(self, parent):
+ Tkinter.Tk.__init__(self, parent)
+ elf_path = ""
+ dsp_path = ""
+ dsp_addr = ""
+ self.file_opt = options = {}
+ options['title'] = 'Choose a file'
+ self.parent = parent
+ self.initialize()
+
+ def initialize(self):
+ self.grid()
+
+ dsp_button = Tkinter.Button(self, text=u"Load DSP bin =>", command=self.dsp_OnButtonClick)
+ dsp_button.grid(column=0, row=4, sticky='W')
+
+ def dsp_OnButtonClick(self):
+ dsp_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(dsp_path) > 0:
+ print_to_log( "You chose %s" % dsp_path)
+ load_dsp_bin(dsp_path)
+ self.quit()
+
+ def quit(self):
+ global app
+ print_to_log( "=== Close DSP Loader ===")
+ app.destroy()
+
+def load_dsp_gui():
+ print_to_log( "=== Start DSP Loader UI ===")
+ global app
+ app = gui_tk(None)
+ app.title('DSP Loader')
+ app.mainloop()
+
+def disable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','disable','["LoadDSP"]'])
+ tcf.close()
+
+def enable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','enable','["LoadDSP"]'])
+ tcf.close()
+
+if __name__ == "__main__":
+ get_tcf_port()
+ disable_button()
+ load_dsp_gui()
+ enable_button()
+
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/coretracer_misc.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/coretracer_misc.py
new file mode 100755
index 0000000..11b9be2
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/coretracer_misc.py
@@ -0,0 +1,70 @@
+import sys
+import time
+import os
+import gdb
+import ctypes
+
+dsp_bin_base = "0x0d500000"
+ramdisk_base = "0x0c500000"
+RAMDISK_SIZE = 0x1000
+EXCEPT_RET = 0xdeaddead
+
+def switch_to_axi_mode():
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def switch_to_apb_mode():
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write off'
+ gdb.execute(gdb_cmd)
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def get_symbol_addr(symbol_name):
+ res = -1
+ try:
+ res = gdb.parse_and_eval(symbol_name)
+ except:
+ return EXCEPT_RET
+
+ return str(res.address).split()[0]
+
+def clean_ram_disk_region():
+ global ramdisk_base
+
+ ram_disk_addr = get_symbol_addr('ram_disk')
+
+ if ram_disk_addr != EXCEPT_RET:
+ print("ram_disk = %s . clean 4K .." % ram_disk_addr)
+ switch_to_axi_mode()
+ for i in range(RAMDISK_SIZE/4):
+ memory_write(int(ram_disk_addr,0)+i*4,0)
+ switch_to_apb_mode()
+ ramdisk_base = ram_disk_addr
+ else:
+ print "There is no ram_disk symbol in this elf!"
+
+def clean_dsp_bin_magic():
+ global dsp_bin_base
+
+ magic_addr = get_symbol_addr('dsp_bin_ro')
+
+ if magic_addr != EXCEPT_RET:
+ print("dsp_bin_addr = %s . write the addr with 0 .." % magic_addr)
+ memory_write(magic_addr, 0)
+ dsp_bin_base = magic_addr
+ else:
+ print "There is no dsp_bin_ro symbol in this elf!"
+
+
+if __name__ == "__main__":
+ print "Check dsp bin magic .."
+ clean_dsp_bin_magic()
+ print "Check ramdisk 4k .."
+ clean_ram_disk_region()
+ print "=================== All process done. You can tigger cpu run or load DSP bin ==================="
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/coretracer_restore_callstack.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/coretracer_restore_callstack.py
new file mode 100755
index 0000000..ff9bcef
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/coretracer_restore_callstack.py
@@ -0,0 +1,188 @@
+import sys
+import time
+import os
+sys.path.append(os.path.dirname(os.path.realpath(__file__)))
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+import struct
+from TCF import Event, Result
+import TCF as client
+EXCEPT_RET = 0xdeaddead
+
+TCF_HOST = 'localhost'
+TCF_PORT = 1534
+
+CPU_CORE_NUM =4
+CPU_PER_CORE_VPE_NUM =3
+CPU_PER_CORE_TC_NUM =6
+
+CPUGPR_NAME = ['zero', 'at', 't4', 't5',
+ 'a0', 'a1', 'a2', 'a3',
+ 'a4', 'a5', 'a6', 'a7',
+ 't0', 't1', 't2', 't3',
+ 's0', 's1', 's2', 's3',
+ 's4', 's5', 's6', 's7',
+ 't8', 't9', 'k0', 'k1',
+ 'gp', 'sp', 'raw_fp', 'ra']
+
+OFFENDING_VPE_NONE = 0xffffffff
+
+def get_tcf_port():
+ global TCF_PORT
+ gdb_cmd = 'show env tcfport'
+ res = gdb.execute(gdb_cmd, to_string=True)
+ TCF_PORT = int(res.split()[2], 0)
+ print "TCF_PORT = " + str(TCF_PORT)
+
+def print_to_log(str):
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','log',str+'\n'])
+ tcf.close()
+
+def disable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','disable','["restoreCallStack"]'])
+ tcf.close()
+
+def enable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','enable','["restoreCallStack"]'])
+ tcf.close()
+
+def refresh_callstack_ui():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','refresh','debug'])
+ tcf.close()
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+
+ return int(mem_value.split()[2], 0)
+
+def register_read(reg):
+ gdb_cmd = 'info register '+ str(reg)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ return int(mem_value.split()[1], 0)
+
+def register_write(reg, set_value):
+ gdb_cmd = 'set $' + str(reg) + ' = ' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def get_symbol_addr(symbol_name):
+ res = -1
+ try:
+ res = gdb.parse_and_eval(symbol_name)
+ except:
+ return EXCEPT_RET
+
+ return str(res.address).split()[0]
+
+def get_variable_value(symbol_name):
+ mem_value = gdb.parse_and_eval(symbol_name)
+ return (mem_value)
+
+def find_offender():
+ print_to_log( "checking vpe status ..")
+ offending_core = OFFENDING_VPE_NONE
+ offending_vpe = OFFENDING_VPE_NONE
+ offending_tc = OFFENDING_VPE_NONE
+ try:
+ offending_core = get_variable_value('sst_offending_coreid')
+ offending_vpe = get_variable_value('sst_offending_vpeid')
+ offending_tc = get_variable_value('sst_offending_tcid')
+ except:
+ return [OFFENDING_VPE_NONE, OFFENDING_VPE_NONE, OFFENDING_VPE_NONE]
+
+ return [offending_core, offending_vpe, offending_tc]
+
+def find_thread_id(core_num, vpe_num, tc_num):
+ gdb_cmd = 'thread find Core {}/VPE {}/TC {}'.format(core_num, vpe_num, tc_num)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ print mem_value
+ return int(mem_value.split()[1], 0)
+
+def switch_thread(tid):
+ gdb_cmd = 'thread '+str(tid)
+ gdb.execute(gdb_cmd)
+
+def restore_thread_callstack(core, vpe, tc): # core0~3, vpe0~2, tc0~1
+ # switch thread
+ thread_id = find_thread_id(core, vpe, vpe*2 + tc)
+ switch_thread(thread_id)
+
+ #print_to_log( "CONT. VPE"+str(core*3+vpe) )
+ vpe_ex_tc = get_variable_value('ex_info[{}][0].tcid'.format(core*3+vpe)) # tc0~5
+
+ #print_to_log('CORE{}/vpe{}/tc{}'.format(core, vpe, tc))
+ if vpe_ex_tc%2 == tc :# offender tc will use ex_info to restore
+ #print_to_log("restore from ex_info_reg ..")
+ # restore GPR from variable ex_info_reg
+ base_addr = get_symbol_addr('ex_info[{}][0].SST_Exception_Regs.GPR'.format(core*3+vpe))
+ #print_to_log("ex_info.GPR base addr = {}".format(base_addr))
+ i=0
+ for reg_name in CPUGPR_NAME:
+ val = memory_read(int(base_addr,0) + i*4)
+ register_write(reg_name, val)
+ i+=1
+ else: # else we use interaptive_state
+ #print_to_log("restore from ex_interaptive_state ..")
+ # restore GPR from variable ex_interaptive_state
+ base_addr = get_symbol_addr('ex_interaptive_state.coreregs[{}].tcregs[{}].GPR'.format(core, tc))
+ i=0
+ for reg_name in CPUGPR_NAME:
+ val = memory_read(int(base_addr,0) + i*4)
+ register_write(reg_name, val)
+ i+=1
+
+ # restore EPC -> PC
+# epc_val = get_variable_value('ex_interaptive_state.coreregs[{}].vperegs[{}].EPC'.format(core, vpe))
+ epc_val = get_variable_value('ex_info[{}][0].SST_Exception_Regs.EPC'.format(core*3+vpe))
+ register_write("pc", epc_val)
+
+ # restore status -> status
+ status_val = get_variable_value('ex_info[{}][0].SST_Exception_Regs.status'.format(core*3+vpe))
+ register_write("status", epc_val)
+
+ return
+
+def restore_callstack(offender):
+ core_num = offender[0]
+ vpe_num = offender[1]%3 # VPE0~VPE2
+ tc_num = offender[2]%2 # TC0~TC1
+ print_to_log("============> Offender is CORE{} VPE{} TC{}".format(core_num, vpe_num, tc_num))
+
+ for core in range(CPU_CORE_NUM):
+ for vpe in range(CPU_PER_CORE_VPE_NUM):
+ print_to_log("Restore CORE{} VPE{} ..".format(core, vpe))
+ for tc in range(2):
+ #print_to_log("Restore CORE{} VPE{} TC{} ..".format(core, vpe, vpe*2 + tc))
+ restore_thread_callstack(core, vpe, tc)
+ refresh_callstack_ui()
+ print_to_log("=== restore call stack finish! ===")
+ return
+
+def main_func():
+ print_to_log("=== start to restore call stack! ===")
+ offender = find_offender()
+ if offender[0] == OFFENDING_VPE_NONE:
+ print_to_log( "This is no any exception happened. Restore abort!")
+ return
+ restore_callstack(offender)
+ return
+
+
+if __name__ == "__main__":
+ get_tcf_port()
+ disable_button()
+ main_func()
+ enable_button()
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/coretracer_swla.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/coretracer_swla.py
new file mode 100755
index 0000000..138ac69
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/coretracer_swla.py
@@ -0,0 +1,309 @@
+import sys
+import time
+import os
+sys.path.append(os.path.dirname(os.path.realpath(__file__)))
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+import struct
+from TCF import Event, Result
+import TCF as client
+
+CORE_NUM = 4
+CORE_TC_NUM = 6
+LAST_COUNT = 100
+
+EXCEPT_RET = 0xdeaddead
+
+TCF_HOST = 'localhost'
+TCF_PORT = 1534
+
+def get_tcf_port():
+ global TCF_PORT
+ gdb_cmd = 'show env tcfport'
+ res = gdb.execute(gdb_cmd, to_string=True)
+ TCF_PORT = int(res.split()[2], 0)
+ print "TCF_PORT = " + str(TCF_PORT)
+
+def print_to_log(str):
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','log',str+'\n'])
+ tcf.close()
+
+def dump_memory(start_addr, end_addr, filename):
+ gdb_cmd = 'dump binary memory '+str(filename)+' '+hex(start_addr)+' '+hex(end_addr)
+ gdb.execute(gdb_cmd)
+
+def switch_to_axi_mode():
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def switch_to_apb_mode():
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write off'
+ gdb.execute(gdb_cmd)
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ #print "[DBG] "+ mem_value
+ return int(mem_value.split()[2], 0)
+
+
+def get_symbol_addr(symbol_name):
+ res = -1
+ try:
+ res = gdb.parse_and_eval(symbol_name)
+ except:
+ return EXCEPT_RET
+
+ return str(res.address).split()[0]
+
+def get_variable_value(symbol_name):
+ mem_value = gdb.parse_and_eval(symbol_name)
+ #print "[DBG] " + str(mem_value)
+ return (mem_value)
+
+WRAP_PATTERN = 0x50415257 # WRAP
+def isBufferWrap(f, total_size, entry_size):
+ seek_offset = total_size - entry_size
+ f.seek(seek_offset)
+ raw_dword = f.read(8)
+ word1, word2 = struct.unpack('II', raw_dword)
+ if word1 == WRAP_PATTERN and word2 == WRAP_PATTERN:
+ return False
+ else:
+ print "WRAP!!"
+ return True
+
+def find_first_idx_cus(f, total_size, entry_size, next_avail_idx):
+ avail_buffer_size = total_size - entry_size
+ if next_avail_idx - LAST_COUNT >= 0:
+ return next_avail_idx - LAST_COUNT
+ else:
+ if not isBufferWrap(f, total_size, entry_size):
+ return 0
+ else:
+ return (avail_buffer_size/entry_size) + (next_avail_idx - LAST_COUNT)
+
+def parse_swla_dump(file_path, entry_size, bin_size, next_avail_idx):
+ f = open(file_path, "rb")
+ #first_idx = find_first_idx(f, bin_size, entry_size, next_avail_idx)
+ first_idx = find_first_idx_cus(f, bin_size, entry_size, next_avail_idx)
+ f.seek(first_idx*entry_size)
+
+ cnt, wrap = 0, 0
+ tmp_list = []
+ for i in range(0, CORE_TC_NUM):
+ tmp_list.append([])
+
+ while True:
+ word = f.read(entry_size)
+ tmp_hash = {}
+ context, frc, raw_coretc = struct.unpack('III', word) #################################### need to modify
+ tmp_hash['frc'], tc, core = hex(frc), raw_coretc >> 8, raw_coretc & 0xff
+
+ if context&0xf0==0xe0:
+ tmp_hash['context'] = "CUS"
+ elif context==0xAAAAAAAA:
+ #print "IRQEND!"
+ tmp_hash['context'] = "IRQEND"
+ tmp_list[tc].append(tmp_hash.copy())
+ elif context>>16==0xAAAA:
+ irq_id = int(context & 0xFFFF)
+ tmp_hash['context'] = "IRQ"+str(irq_id)
+ tmp_list[tc].append(tmp_hash.copy())
+ #print tmp_hash['context']
+ else:
+ char1, char2, char3, char4 = (context&0xff), (context>>8&0xff), (context>>16&0xff), (context>>24&0xff)
+ if char4==0:
+ if char3==0:
+ context_name = chr(char1) + chr(char2)
+ else:
+ context_name = chr(char1) + chr(char2) + chr(char3)
+ else:
+ context_name = chr(char1) + chr(char2) + chr(char3) + chr(char4)
+ tmp_hash['context'] = context_name
+ tmp_list[tc].append(tmp_hash.copy())
+
+ #print str(tc)+", "+tmp_hash['context']+", "+hex(frc)
+
+ cnt +=1
+
+ # WRAP condition
+ if f.tell()==bin_size and wrap==0 :
+ f.seek(0)
+ wrap=1
+ print "CORE"+str(file_idx)+" swla buffer WRAP"
+ #print "seek:" + hex(f.tell()) + " cnt*entry_size = "+hex(cnt*entry_size)
+
+ # check END
+ if f.tell()==next_avail_idx*entry_size:
+ #print "END! cnt="+str(cnt)
+ break
+
+ f.close()
+ return tmp_list
+
+def swla_parse(tc_lvl_list):
+ context_list = {}
+
+ irq_queue = []
+ pre_task, pre_frc = 0, 0
+ for context in tc_lvl_list:
+ context_name = context['context']
+ context_start_frc = context['frc']
+ target_context=""
+ if pre_task != 0:
+ # sys_exec case
+ if pre_task=="IRQEND" and len(irq_queue)==0:
+ target_context = "sys_exec"
+ if not target_context in context_list:
+ context_list[target_context] = []
+ context_list[target_context].append([pre_frc, context_start_frc])
+ # irqend case
+ elif pre_task=="IRQEND":
+ last_irq = irq_queue.pop()
+ target_context = last_irq
+ if not target_context in context_list:
+ context_list[target_context] = []
+ context_list[target_context].append([pre_frc, context_start_frc])
+ else:
+ if "IRQ" in context_name and context_name!="IRQEND": # irq
+ irq_queue.append(context_name)
+
+ target_context = pre_task
+ if not target_context in context_list:
+ context_list[target_context] = []
+ context_list[target_context].append([pre_frc, context_start_frc])
+ if target_context=="IRQEND":
+ print "????"
+ pre_task, pre_frc = context_name, context_start_frc
+
+ #print context_list
+ return context_list.copy()
+
+def main_func():
+ print_to_log("=== Start to parse SWLA information ===")
+ """
+ get swla buffer base address
+ """
+ res = get_symbol_addr('SysProfilerBufferAddress')
+ if res==EXCEPT_RET:
+ print_to_log( "[ERR] this elf does not support SWLA!")
+ return
+
+ swla_buffer_base_addr = int(get_symbol_addr('SysProfilerBufferAddress'), 16)
+ swla_buffer_addr_ary = []
+ for i in range(0, CORE_NUM):
+ swla_buffer_addr_ary.append(memory_read(swla_buffer_base_addr+i*4))
+
+ """
+ get swla entry size
+ """
+ swla_entry_size = get_variable_value("SA_LoggingNodeSize[0]") ##########################################
+ #print "SWLA Entry Size: "+str(swla_entry_size)+" B"
+
+ """
+ get swla next available entry index
+ """
+ swla_buffer_next_avail_index = []
+ for i in range(0, CORE_NUM):
+ swla_buffer_next_avail_index.append(get_variable_value("SA_LoggingOffset["+str(i)+"]"))
+
+ """
+ get swla buffer total size
+ """
+ tmp = get_variable_value("SA_LoggingStop[0]")
+ swla_size = int(str(tmp).split()[0], 0) - swla_buffer_addr_ary[0]
+ print_to_log( "SWLA Buffer Size: "+ hex(swla_size)+" B")
+
+ """
+ dump each core's swla raw buffer
+ """
+ swla_dump_file = []
+
+ switch_to_axi_mode() # switch to AXI mode to speed up (axi mode will not go through CPU -> MUST used in non-cache region)
+ for i in range(0, CORE_NUM):
+ print_to_log( "Dump core"+str(i)+" swla raw buffer ..")
+ s_t = time.time()
+ filename = "core"+str(i)+"_raw_swla.bin"
+ dump_memory(swla_buffer_addr_ary[i], swla_buffer_addr_ary[i]+swla_size, filename)
+ swla_dump_file.append(filename)
+ e_t = time.time()
+ print_to_log("Elapsed time: {:.3f} sec".format(e_t-s_t))
+ switch_to_apb_mode() # switch back
+
+ print "All swla raw dump finish!!"
+
+ #exit()
+ """
+ parse swla raw
+ """
+ output = open("final_swla.log", "w")
+ output.write('met-info [000] 0.0: ms_ud_timeline_header: {"resource": [{"entity-attr": ["Interrupt"], "name": "default"}], "name": "MCU Timeline"}'+"\n")
+ output.write('met-info [000] 0.0: ms_ud_timeline_description: MCU Timeline:HAS_CHILD_TRACE=Y;COPY_TO_TOP=Y'+"\n")
+
+ core_num=0
+ log_index=1
+ for file in swla_dump_file:
+ print_to_log( "Parsing "+file+" ...")
+ s_t = time.time()
+ tc_list = parse_swla_dump(file, swla_entry_size, swla_size, swla_buffer_next_avail_index[core_num])
+ #print tc_list
+ e_t = time.time()
+
+ print_to_log("Elapsed time: {:.3f} sec".format(e_t-s_t))
+ print_to_log( "start to write to final_swla ..")
+ tc_num = 0
+ for tc_content in tc_list:
+ #print tc_content
+ context_list = swla_parse(tc_content)
+ #print context_list
+ vpe_num = tc_num/2
+ for context_name, period_list in context_list.items():
+ isIRQ = "NO"
+ if "IRQ" in context_name:
+ isIRQ = "YES"
+ for period in period_list:
+ #print period
+ start_frc, end_frc = int(period[0],0)*1.0/1000000, int(period[1],0)*1.0/1000000
+ #print start_frc
+ out_str1 = "NULL-0 [000] {:.10f}: MCU Timeline: ".format(start_frc)
+ out_str2 = "'CORE{}%%VPE{}%%TC{}%%{}', 'e': [['{}']], 't': ['{:.10f}', '{:.10f}']".format(core_num, vpe_num, tc_num/2, context_name, isIRQ, start_frc, end_frc)
+ output.write(out_str1+"{'r': "+out_str2+"}\n")
+ log_index+=1
+ tc_num+=1
+
+ core_num+=1
+ #break
+ output.close()
+ print_to_log( '=== SWLA parse finish! Please use MET font-end to open final_swla.log for SWLA view ===')
+ print_to_log( '=== The output filename is "final_swla.log" in the same folder of your elf file ===')
+ return
+
+def disable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','disable','["SWLA"]'])
+ tcf.close()
+
+def enable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','enable','["SWLA"]'])
+ tcf.close()
+
+if __name__ == "__main__":
+ get_tcf_port()
+ disable_button()
+ main_func()
+ enable_button()
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/prepare_mode.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/prepare_mode.launch
new file mode 100755
index 0000000..2b67fdb
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/MT6885/coretracer/prepare_mode.launch
@@ -0,0 +1,64 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.ui.focus_threads" value=""/>
+<stringAttribute key="com.mediatek.ide.dsf.mvpu.dbg_file" value=""/>
+<stringAttribute key="com.mediatek.ide.dsf.mvpu.pattern_file" value=""/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value=""/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.cache.FilePath" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.cache.gdbIndexElf" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.LocalTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.debuggerIpAddress" value="localhost"/>
+<intAttribute key="com.mediatek.ide.util.debuggerPortNumber" value="3333"/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.substitute_path_no_translate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="Prepare"/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.args" value="-f board/mips/debug_port_swd.cfg -c "adapter_khz 3000""/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.cmds" value=""/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.widget.args" value="{"Clock_3000":"3000"}"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="attach"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
+<booleanAttribute key="org.eclipse.debug.core.capture_output" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_OUTPUT_ON" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+<stringAttribute key="saved_expressions<seperator>Unknown<seperator>APB" value="0xa0638000,0xa0310000"/>
+<stringAttribute key="saved_expressions<seperator>Unknown<seperator>AXI" value="0xa0020000,0xa0630000,0xa0638000,0xa0291e50"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/codescape_fpga_emi_init.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/codescape_fpga_emi_init.py
new file mode 100755
index 0000000..fef2f8e
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/codescape_fpga_emi_init.py
@@ -0,0 +1,1200 @@
+from imgtec import codescape
+from imgtec.console import *
+import os
+import random
+import sys
+import time
+
+dsp_bin_base = "0x0d500000"
+ramdisk_base = "0x0c500000"
+RAMDISK_SIZE = 0x1000
+CPUREG_NAME = ['zero', 'at', 't4', 't5',
+ 'a0', 'a1', 'a2', 'a3',
+ 'a4', 'a5', 'a6', 'a7',
+ 't0', 't1', 't2', 't3',
+ 's0', 's1', 's2', 's3',
+ 's4', 's5', 's6', 's7',
+ 't8', 't9', 'k0', 'k1',
+ 'gp', 'sp', 'fp', 'ra']
+
+reg_backup = []
+
+def restore_callstack(da, ex_vpe):
+ core_num = ex_vpe/3
+ vpe_num = ex_vpe%3
+ print "restore CORE"+str(core_num)+" VPE"+str(vpe_num)
+ thread = da.cores[core_num].hwthreads[vpe_num]
+ try:
+ sym_addr = thread.GetSymbol('ex_info_reg').location
+ except:
+ print "There is no exception info symbol ex_info_reg. restore abort!"
+ return
+
+ print "&ex_info_reg=",format(sym_addr)
+ target_reg_info_addr = int(sym_addr, 0) + 0x178*int(ex_vpe)
+ var_status_addr = int(sym_addr, 0) + 0x88
+ var_epc_addr = int(sym_addr, 0) + 0x88 + 0x4*2
+ tmp_addr = target_reg_info_addr
+
+ print "regs restore start .."
+ for cpu_reg in CPUREG_NAME:
+ #reg_backup = thread.ReadRegister(cpu_reg) #regs(cpu_reg)
+ reg_val = thread.memory.Read(tmp_addr)
+ time.sleep(0.1)
+ thread.WriteRegister(cpu_reg, reg_val)#regs(cpu_reg, word(tmp_addr))
+ #print cpu_reg + " : " + hex(reg_val)
+ tmp_addr += 4
+ #time.sleep(0.1)
+ thread.WriteRegister('pc', thread.memory.Read(var_epc_addr))#regs('pc', regs('epc'))
+ thread.WriteRegister('status', thread.memory.Read(var_status_addr))
+ print "regs restore done. callstack restore finish!!!"
+ print "Please open call stack region in VPE"+str(ex_vpe)
+
+def find_excep_vpe(da):
+ print "checking vpe status .."
+ thread = da.cores[0].hwthreads[0]
+ try:
+ sst_off_vpeid_addr = thread.GetSymbol('sst_offending_vpeid').location
+ #sst_off_coreid_addr = thread.GetSymbol('sst_offending_coreid').location
+ #sst_offending_vpeid
+ #sst_offending_coreid
+ #sst_offending_tcid
+ except:
+ return -1
+
+ vpe_val = thread.memory.Read(sst_off_vpeid_addr)
+ #core_val = thread.memory.Read(sst_off_coreid_addr)
+ #print "Offending vpeid = "+hex(vpe_val)
+ if vpe_val==0xffffffff: #or core_val==0xffffffff:
+ return -1
+ else:
+ return vpe_val
+
+def enable_fast_write(da):
+ # To accelerate load elf
+ # Configure C0_CDMMBASE = 0x01FC1407 to enable access
+ thread.WriteRegister('CDMMBase', 0x01FC1407)
+ # Default all segments are NC, then configure VA Bank8 to WB for speed up load elf
+ thread.memory.Write(0x1FC100D4, 0x02030202)
+ da.SetDASettingValue("Fast Monitor Address", 0x6F800000)
+ da.SetDASettingValue("Fast Writes", True)
+
+
+def disable_fast_write(da):
+ thread = da.cores[0].hwthreads[0]
+ # Restore Default all segments to NC
+ thread.memory.Write(0x1FC100D4, 0x02020202)
+ # Restore C0_CDMMBASE = 0x01FC1007
+ thread.WriteRegister('CDMMBase', 0x01FC1007)
+ da.SetDASettingValue("Fast Writes", False)
+
+
+def load_all_elf(da, thread, elf_path):
+ if(os.path.exists(elf_path) == False):
+ print "[Error] UMOLY ELF doesn't exist %s" %(elf_path)
+ return 0
+
+ print elf_path
+ time_str = time.time()
+ core_num = (thread.memory.Read(0x1F000000) & 0xFF)+1
+ print "=== Get Core Number ===: %d" %(core_num)
+ print "=== Start Loading .elf ==="
+ print "Image path: " + elf_path
+
+ for core_idx in range(core_num):
+ if(core_idx == 0):
+ # load binary only on VPE0 of 0 core
+ thread = da.cores[core_idx].hwthreads[0]
+ thread.Stop()
+ enable_fast_write(da)
+ thread.LoadProgramFile(elf_path, False, 0x83, True, "")
+ #probe('sp536')
+ #print load(elf_path,verbose=True, physical=False)
+ print "[Core%d,VPE0] Load ELF successfully" %(core_idx)
+ thread = da.cores[core_idx].hwthreads[1]
+ thread.Stop()
+ thread.LoadProgramFile(elf_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE1] Load ELF successfully" %(core_idx)
+ thread = da.cores[core_idx].hwthreads[2]
+ thread.Stop()
+ thread.LoadProgramFile(elf_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE2] Load ELF successfully" %(core_idx)
+ else:
+ thread = da.cores[core_idx].hwthreads[0]
+ thread.Stop()
+ thread.LoadProgramFile(elf_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE0] Load ELF successfully" %(core_idx)
+ thread = da.cores[core_idx].hwthreads[1]
+ thread.Stop()
+ thread.LoadProgramFile(elf_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE1] Load ELF successfully" %(core_idx)
+ thread = da.cores[core_idx].hwthreads[2]
+ thread.Stop()
+ thread.LoadProgramFile(elf_path, False, codescape.da_types.LoadType.symbols, False, "")
+ print "[Core%d,VPE2] Load ELF successfully" %(core_idx)
+
+ clean_ram_disk_region(thread)
+ clean_dsp_bin_magic(thread)
+ time_end = time.time()
+ print("All loading is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+ disable_fast_write(da)
+ return 1
+
+def clean_ram_disk_region(thread):
+ global ramdisk_base
+ ram_disk_addr = 0
+ try:
+ ram_disk_addr = thread.GetSymbol('ram_disk').location
+ except:
+ ram_disk_addr = 0
+
+ if ram_disk_addr!=0:
+ print("ram_disk = %s . clean 4K .." % ram_disk_addr)
+ word(ram_disk_addr,0,RAMDISK_SIZE)
+ ramdisk_base = ram_disk_addr
+ else:
+ print "There is no ram_disk symbol in this elf!"
+
+def clean_dsp_bin_magic(thread):
+ global dsp_bin_base
+ magic_addr = 0
+ try:
+ magic_addr = thread.GetSymbol('dsp_bin_ro').location
+ except:
+ magic_addr = 0
+
+ if magic_addr!=0:
+ print("dsp_bin_addr = %s . write the addr with 0 .." % magic_addr)
+ word(magic_addr, 0)
+ dsp_bin_base = magic_addr
+ else:
+ print "There is no dsp_bin_ro symbol in this elf!"
+
+
+def load_dsp_bin(da, thread, dsp_path, dsp_addr):
+ if(os.path.exists(dsp_path) == False):
+ print "[Error] DSP BIN doesn't exist %s" %(dsp_path)
+ return
+
+ enable_fast_write(da)
+ time_str = time.time()
+ print "=== Start load dsp bin ==="
+ print "Dsp bin path: " + dsp_path
+ print "Dsp bin load address: " + dsp_addr
+
+ dsp_file = open(dsp_path, "rb")
+ dsp_hdr = dsp_file.read(4)
+ dsp_file.close()
+
+ thread = da.cores[0].hwthreads[0]
+ if dsp_hdr == b'\x4d\x4d\x4d\x01':
+ dsp_bin_size = os.path.getsize(dsp_path)
+ print "Dsp bin file size: " + str(dsp_bin_size) + " bytes"
+ print "Loading DSP bin ..."
+ thread.memory.LoadBinaryFile(dsp_path, dsp_addr, start_offset = 0, length = None)
+ else:
+ dsp_bin_size = os.path.getsize(dsp_path) - 0x200
+ print "Dsp bin file size: " + str(dsp_bin_size) + " bytes"
+ print "Loading DSP bin ..."
+ thread.memory.LoadBinaryFile(dsp_path, dsp_addr, start_offset = 0x200, length = dsp_bin_size)
+
+ time_end = time.time()
+ print("loading dsp is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+ disable_fast_write(da)
+
+
+def WDT_Disable(thread):
+ """diable WDT function
+ [in] thread, codescape thread object
+ """
+ print("WDT disable ...")
+ mdrgu = 0xA00F0000 + 0x0100
+ aprgu = 0xC0007000
+ thread.memory.Write(mdrgu, (thread.memory.Read(mdrgu) & 0xFFFFFFFC) | 0x55000000)
+ thread.memory.Write(aprgu, (thread.memory.Read(aprgu) & 0xFFFFFFFE) | 0x22000000)
+
+
+def MD_Remap(thread, adr=None):
+ """MD reamp config
+ [in] thread, codescape thread object
+ [in] adr, user specific remap address (ap infra memory map view, 32M alignment)
+ default: emi start address
+ """
+
+ inf_emi = 0x80000000 if thread.memory.Read(0xA000001C) < 0x08566094 else 0x40000000
+ print("MD_Remap(adr={:#x}) ...".format(inf_emi if adr == None else adr))
+ if adr == None:
+ inf_md = inf_emi
+ else:
+ assert (adr & 0x01FFFFFF) == 0
+ inf_md = adr
+ print("MD_Remap -> md:bank0=>ap:{:#x}, md:bank1=>ap:{:#x}, md:bank4=>ap:{:#x}".format(inf_md, inf_md+0x10000000, inf_emi))
+ # md remap bank 0
+ bnk = inf_md >> 25
+ thread.memory.Write(0xC0001300, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ thread.memory.Write(0xC0001304, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ thread.memory.Write(0xC0001308, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ thread.memory.Write(0xC000130c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+ # md remap bank 1
+ bnk = (inf_md+0x10000000) >> 25
+ thread.memory.Write(0xC0001310, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ thread.memory.Write(0xC0001314, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ thread.memory.Write(0xC0001318, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ thread.memory.Write(0xC000131c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+ # md remap bank 4
+ bnk = inf_emi >> 25
+ thread.memory.Write(0xC0001320, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ thread.memory.Write(0xC0001324, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ thread.memory.Write(0xC0001328, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ thread.memory.Write(0xC000132c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+
+
+def DRAM_INIT(thread):
+ """initialize DRAM, include emi/dramc init
+ [in] thread, codescape thread object
+ """
+
+ def reg_write(adr, val):
+ thread.memory.Write(adr, val)
+
+ print("DRAM_INIT ...")
+ tim = time.time()
+
+ # disable md to ap write secure world register protection
+ reg_bak_APC_CON = thread.memory.Read(0xC001DF00)
+ reg_bak_MAS_SEC_0 = thread.memory.Read(0xC001DB00)
+ reg_write(0xC001DF00, 0x00000000) # APC_CON[2] = DBG_MASK = 0
+ reg_write(0xC001DB00, 0x00010000) # MAS_SEC_0[16] = M16_SEC = 1
+
+ NR_RNKS=1
+ #EMI
+
+ #DRAMC0_NAO
+ #0x10234***
+ #DRAMC0
+ #0x10230***
+ #DRAMC1
+ #0x10240***
+ #DDRPHY0
+ #0x10238***
+ #DDRPHY1
+ #0x10248***
+
+ #EMI setting
+ reg_write(0xC0219000, 0x00001052) # ;0x00025052
+ reg_write(0xC0219060, 0xff000400)
+ reg_write(0xC0219020, 0x00008000)
+ reg_write(0xC0235000, 0x00001012) # ;0x00005053
+ reg_write(0xC0235010, 0x00000001)
+
+
+ #;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ reg_write(0xC0238274, 0xffffffff)
+ reg_write(0xC0248278, 0x00000000)
+ reg_write(0xC0248274, 0xffffffff)
+ reg_write(0xC023829c, 0x38030000)
+ #PLL sel
+
+ reg_write(0xC02381a0, 0x00000000)
+ reg_write(0xC02380a0, 0x00000000)
+ reg_write(0xC0238120, 0x00000000)
+ reg_write(0xC02382ac, 0x80000006)
+ reg_write(0xC02481a0, 0x00000000)
+ reg_write(0xC02480a0, 0x00000000)
+ reg_write(0xC0248120, 0x00000000)
+ reg_write(0xC02482ac, 0x80000006)
+ reg_write(0xC02382a0, 0x00000100) # ;PINMUX
+ reg_write(0xC02482a0, 0x00000100)
+ reg_write(0xC0238264, 0x00400000)
+ reg_write(0xC0238268, 0x00000040)
+ reg_write(0xC0248264, 0x00400000)
+ reg_write(0xC0248268, 0x00000040)
+ reg_write(0xC0238e18, 0x00000000)
+ reg_write(0xC0238f18, 0x01010000)
+ reg_write(0xC0239018, 0x02020000)
+ reg_write(0xC0238e68, 0x04040000)
+ reg_write(0xC0238f68, 0x05050000)
+ reg_write(0xC0239068, 0x06060000)
+ reg_write(0xC0238ec4, 0x00000c00)
+ reg_write(0xC0238fc4, 0x00000c00)
+ reg_write(0xC02393c4, 0x00000c00)
+ reg_write(0xC02394c4, 0x00000c00)
+ reg_write(0xC0238e50, 0x00000000)
+ reg_write(0xC0238f50, 0xbbbbbbbb)
+ reg_write(0xC0239050, 0xbbbbbbbb)
+ reg_write(0xC0238e54, 0x00000000)
+ reg_write(0xC0238f54, 0x0000bb00)
+ reg_write(0xC0239054, 0x0000bb00)
+ reg_write(0xC0248ea0, 0x00000000)
+ reg_write(0xC0248fa0, 0x00bbbbbb)
+ reg_write(0xC02490a0, 0x00bbbbbb)
+ reg_write(0xC0248ea4, 0x00000000)
+ reg_write(0xC0248fa4, 0x00000bbb)
+ reg_write(0xC02490a4, 0x00000bbb)
+ reg_write(0xC0248e00, 0x00000000)
+ reg_write(0xC0248f00, 0xbbbbbbbb)
+ reg_write(0xC0249000, 0xbbbbbbbb)
+ reg_write(0xC0248e04, 0x00000000)
+ reg_write(0xC0248f04, 0x0000bb00)
+ reg_write(0xC0249004, 0x0000bb00)
+ reg_write(0xC0248e50, 0x00000000)
+ reg_write(0xC0248f50, 0xbbbbbbbb)
+ reg_write(0xC0249050, 0xbbbbbbbb)
+ reg_write(0xC0248e54, 0x00000000)
+ reg_write(0xC0248f54, 0x0000bb00)
+ reg_write(0xC0249054, 0x0000bb00)
+ reg_write(0xC0238e1c, 0x00000c00)
+ reg_write(0xC0238f1c, 0x00000c00)
+ reg_write(0xC023901c, 0x00000c00)
+ reg_write(0xC0238e6c, 0x000f0f00)
+ reg_write(0xC0238f6c, 0x000f0f00)
+ reg_write(0xC023906c, 0x000f0f00)
+ reg_write(0xC0248ec4, 0x00000f0f)
+ reg_write(0xC0248fc4, 0x00000f0f)
+ reg_write(0xC02490c4, 0x00000f0f)
+ reg_write(0xC0248e1c, 0x000f0f00)
+ reg_write(0xC0248f1c, 0x000f0f00)
+ reg_write(0xC024901c, 0x000f0f00)
+ reg_write(0xC0248e6c, 0x000f0f00)
+ reg_write(0xC0248f6c, 0x000f0f00)
+ reg_write(0xC024906c, 0x000f0f00)
+ reg_write(0xC0238128, 0x00001010)
+ reg_write(0xC023812c, 0x01111010)
+ reg_write(0xC0238130, 0x010c10d0)
+ reg_write(0xC023812c, 0x03111010)
+ reg_write(0xC02381a4, 0x0000008c)
+ #TINFO="SHL ddrphy chA reset release"
+ reg_write(0xC02381b0, 0x00080010) # ;SER MODE
+ reg_write(0xC0238d04, 0x00000101)
+ reg_write(0xC0238d08, 0x00000101)
+ reg_write(0xC0239204, 0x00000101)
+ reg_write(0xC0239208, 0x00000101)
+ reg_write(0xC02380a4, 0x0000008c)
+ reg_write(0xC02380b0, 0x00080010) # ;SER MODE
+ reg_write(0xC0238c04, 0x00000101)
+ reg_write(0xC0238c08, 0x00000101)
+ reg_write(0xC0239104, 0x00000101)
+ reg_write(0xC0239108, 0x00000101)
+ reg_write(0xC02481a8, 0x00001010)
+ reg_write(0xC02481ac, 0x01111010)
+ reg_write(0xC02481b0, 0x010c10d0)
+ reg_write(0xC02481ac, 0x03111010)
+ reg_write(0xC02480a8, 0x00001010)
+ reg_write(0xC02480ac, 0x01111010)
+ reg_write(0xC02480b0, 0x010c10d0)
+ reg_write(0xC02480ac, 0x03111010)
+ reg_write(0xC0248128, 0x00001010)
+ reg_write(0xC024812c, 0x01111010)
+ reg_write(0xC0248130, 0x010c10d0)
+ reg_write(0xC024812c, 0x03111010)
+ #PLL
+
+ reg_write(0xC0238c18, 0x44000000)
+ reg_write(0xC0239118, 0x04000000)
+ reg_write(0xC0238c98, 0x44000000)
+ reg_write(0xC0239198, 0x04000000)
+ reg_write(0xC0238d18, 0x44000000)
+ reg_write(0xC0239218, 0x04000000)
+ reg_write(0xC0248c18, 0x44000000)
+ reg_write(0xC0249118, 0x04000000)
+ reg_write(0xC0248c98, 0x44000000)
+ reg_write(0xC0249198, 0x04000000)
+ reg_write(0xC0248d18, 0x44000000)
+ reg_write(0xC0249218, 0x04000000)
+ reg_write(0xC0238da0, 0x00000000)
+ reg_write(0xC02392a0, 0x00000000)
+ # DLL
+
+ reg_write(0xC0238124, 0x0000051e)
+ reg_write(0xC02481a4, 0x0000051e)
+ #TINFO="SHL ddrphy chB reset release"
+ reg_write(0xC02480a4, 0x0000051e)
+ reg_write(0xC0248124, 0x0000051e)
+ reg_write(0xC0238194, 0x00660600)
+ reg_write(0xC0238094, 0xc0660600)
+ reg_write(0xC0238114, 0xc0660600)
+ reg_write(0xC0248194, 0xc0660600)
+ reg_write(0xC0248094, 0xc0660600)
+ reg_write(0xC0248114, 0xc0660600)
+ reg_write(0xC02381b8, 0x00180101)
+ reg_write(0xC023826c, 0x00000000)
+ reg_write(0xC02481b8, 0x00180101)
+ reg_write(0xC024826c, 0x00000000)
+ reg_write(0xC0238d14, 0x00000000)
+ reg_write(0xC0239214, 0x00000000)
+ reg_write(0xC0239714, 0x00000000)
+ reg_write(0xC0239c14, 0x00000000)
+ reg_write(0xC0248d14, 0x00000000)
+ reg_write(0xC0249214, 0x00000000)
+ reg_write(0xC0249714, 0x00000000)
+ reg_write(0xC0249c14, 0x00000000)
+
+ time.sleep(0.001)
+
+ reg_write(0xC023800c, 0x006d0000)
+ reg_write(0xC0238180, 0x0000000c)
+ reg_write(0xC0238080, 0x00000009)
+ reg_write(0xC0238100, 0x00000009)
+ reg_write(0xC0248180, 0x00000009)
+ reg_write(0xC0248080, 0x00000009)
+ reg_write(0xC0248100, 0x00000009)
+
+ time.sleep(0.001)
+
+ reg_write(0xC0238000, 0x80000000)
+ reg_write(0xC0238004, 0x80000000)
+ reg_write(0xC0238004, 0x00000000)
+
+ time.sleep(0.001)
+
+ reg_write(0xC0238da4, 0x00019200)
+
+ time.sleep(0.001)
+
+ reg_write(0xC0238194, 0x00660e00)
+
+ time.sleep(0.001)
+
+ reg_write(0xC0238094, 0xc0660e00)
+ reg_write(0xC0238114, 0xc0660e00)
+ reg_write(0xC0248194, 0xc0660e00)
+ reg_write(0xC0248094, 0xc0660e00)
+ reg_write(0xC0248114, 0xc0660e00)
+ reg_write(0xC0238284, 0x0000001f)
+
+ time.sleep(0.001)
+
+ reg_write(0xC0238124, 0x0001051e)
+ reg_write(0xC02481a4, 0x0001051e)
+ reg_write(0xC02480a4, 0x0001051e)
+ reg_write(0xC0248124, 0x0001051e)
+ reg_write(0xC02382a0, 0x8100018c)
+ reg_write(0xC02482a0, 0x8100018c)
+ reg_write(0xC02381b8, 0x00040101)
+ reg_write(0xC02381b4, 0x00000000)
+ reg_write(0xC02380b4, 0x00000000)
+ reg_write(0xC0238134, 0x00000000)
+ reg_write(0xC0238c1c, 0x00200000) # ; WJ: LP3
+ reg_write(0xC02481b4, 0x00000000)
+ reg_write(0xC02480b4, 0x00000000)
+ reg_write(0xC0248134, 0x00000000)
+ reg_write(0xC0248c1c, 0x00200000) # ; WJ: LP3
+ reg_write(0xC02300dc, 0x00051008)
+ #;D.S EAXI:0x1024000dc %LE %LONG 0x00050008
+ reg_write(0xC0230000, 0x02101000) # ;[24]=LP2_EN , [25]=LP3_EN, [26]=LP4_EN
+ reg_write(0xC0230640, 0xa688049f)
+ reg_write(0xC0230660, 0x00030053)
+ reg_write(0xC023004c, 0x25712000)
+ reg_write(0xC0230680, 0x00000000)
+ reg_write(0xC0230684, 0x00000000)
+ reg_write(0xC0230688, 0x00000000)
+ reg_write(0xC023068c, 0x00000000)
+ reg_write(0xC0230690, 0x11111011)
+ reg_write(0xC0230694, 0x01101111)
+ reg_write(0xC0230698, 0x11111111)
+ reg_write(0xC023069c, 0x11111111)
+ reg_write(0xC02306a0, 0x11111111) # ;TXDLY DQS
+ reg_write(0xC02306a4, 0x66667777)
+ reg_write(0xC023082c, 0x11111111) # ;TXDLY DQ
+ reg_write(0xC0230830, 0x11111111) # ;TXDLY DQM
+ reg_write(0xC0230834, 0x66667777)
+ reg_write(0xC0230838, 0x66667777)
+ #D.S EAXI:0x1023092c %LE %LONG 0x22222222
+ #D.S EAXI:0x10230930 %LE %LONG 0x22222222
+ #D.S EAXI:0x10230934 %LE %LONG 0x66667777
+ #D.S EAXI:0x10230938 %LE %LONG 0x66667777
+ #D.S EAXI:0x10230a2c %LE %LONG 0x22222222
+ #D.S EAXI:0x10230a30 %LE %LONG 0x22222222
+ #D.S EAXI:0x10230a34 %LE %LONG 0x66667777
+ #D.S EAXI:0x10230a38 %LE %LONG 0x66667777
+ reg_write(0xC023081c, 0x00000000)
+ reg_write(0xC0230820, 0x00000000)
+ #D.S EAXI:0x1023091c %LE %LONG 0x00000000
+ #D.S EAXI:0x10230920 %LE %LONG 0x00000000
+ #D.S EAXI:0x10230a1c %LE %LONG 0x00000000
+ #D.S EAXI:0x10230a20 %LE %LONG 0x66666666
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ reg_write(0xC0230200, 0xf0100000) # ;[31]=DQSIEN MODE
+ reg_write(0xC0230048, 0x08000000)
+ reg_write(0xC0230678, 0xc0000000)
+ reg_write(0xC0230600, 0x09030b06)
+ reg_write(0xC0230604, 0x14090901)
+ reg_write(0xC0230608, 0x0c050201)
+ reg_write(0xC023060c, 0x00490019)
+ reg_write(0xC0230614, 0x01000606)
+ reg_write(0xC023061c, 0x02030408)
+ reg_write(0xC0230620, 0x02000400)
+ reg_write(0xC0230648, 0x9007320f)
+ reg_write(0xC0230644, 0x00000b0d) # ;DATLAT
+ reg_write(0xC0230000, 0x02111000) # ;[24]=LP2_EN , [25]=LP3_EN, [26]=LP4_EN
+ reg_write(0xC0230004, 0x20002000)
+ reg_write(0xC0230008, 0x81080000)
+ reg_write(0xC023000c, 0x0002cf13)
+ reg_write(0xC0230010, 0x00000080)
+ reg_write(0xC0230020, 0x00000009)
+ reg_write(0xC0230024, 0x80030000)
+ reg_write(0xC0230038, 0x80000106)
+ reg_write(0xC0230040, 0x3000000c)
+ reg_write(0xC023004c, 0x25714001)
+ reg_write(0xC0230064, 0x25b1f1cf) # ;REFRDIS=1
+ reg_write(0xC02300b0, 0x04300000)
+ reg_write(0xC0230200, 0xf0310000) # ;[31]=DQSIEN MODE
+ reg_write(0xC0230658, 0x21200001)
+ reg_write(0xC0230800, 0x00000002)
+ #D.S EAXI:0x10230900 %LE %LONG 0x00000002
+ #D.S EAXI:0x10230a00 %LE %LONG 0x00000002
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC0230824, 0x10101010) # ;GATE WINDOW unit:2T
+ reg_write(0xC0230828, 0x17171717)
+ #D.S EAXI:0x10230924 %LE %LONG 0x11111111
+ #D.S EAXI:0x10230928 %LE %LONG 0x42424242
+ #D.S EAXI:0x10230a24 %LE %LONG 0x32323232
+ #D.S EAXI:0x10230a28 %LE %LONG 0x06060606
+ #;D.S EAXI:0x10240a24 %LE %LONG 0x00000000; ;GATE WINDOW unit:2T
+ #;D.S EAXI:0x10240a28 %LE %LONG 0x53535353
+ #;D.S EAXI:0x10240b24 %LE %LONG 0x32323232
+ #;D.S EAXI:0x10240b28 %LE %LONG 0x06060606
+ #;D.S EAXI:0x10240c24 %LE %LONG 0x32323232
+ #;D.S EAXI:0x10240c28 %LE %LONG 0x06060606
+ # 33961 === over_write_setting_begin ===
+ # 33961 === over_write_setting_end ===
+ reg_write(0xC0230034, 0x00731010)
+ reg_write(0xC0230024, 0x80030050)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC023005c, 0x00003f00)
+ reg_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC0230060, 0x00000000)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC023005c, 0x00000aff)
+ reg_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC0230060, 0x00000000)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC023005c, 0x00000183)
+ reg_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC0230060, 0x00000000)
+ reg_write(0xC023005c, 0x00000206) # ;RL/WL
+ reg_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC0230060, 0x00000000)
+ reg_write(0xC0230028, 0x00000034)
+ reg_write(0xC023005c, 0x00000b03)
+ reg_write(0xC0230060, 0x00000001)
+
+ #=============================RANK1 MRW==================
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #D.S EAXI:0x1023005c %LE %LONG 0x01003f00
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000aff
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000183
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000206; ;RL/WL
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000b03
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #================== end RANK1 MRW =====================
+
+
+ reg_write(0xC0230060, 0x00000000)
+ reg_write(0xC0230024, 0x80030040)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ reg_write(0xC023005c, 0x00000400)
+
+
+
+ reg_write(0xC023064c, 0x00000005)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ reg_write(0xC023004c, 0x25774001)
+ reg_write(0xC0230034, 0x00731810)
+ reg_write(0xC0230024, 0x80030000)
+ reg_write(0xC0230004, 0x20082000)
+ reg_write(0xC0230058, 0x00000a56)
+
+ time.sleep(0.001)
+ reg_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ reg_write(0xC023064c, 0x00ff0005)
+ reg_write(0xC0230064, 0x25b1f1cf) # ;REFRDIS=1
+ reg_write(0xC0230610, 0x22653055)
+ reg_write(0xC023004c, 0x45774001)
+ reg_write(0xC0230048, 0x48000000)
+ reg_write(0xC023005c, 0x80000400)
+ reg_write(0xC0230038, 0xc0000107)
+ reg_write(0xC023020c, 0x00010002)
+ reg_write(0xC0230204, 0x00014e00)
+ reg_write(0xC0230094, 0x00100000)
+ reg_write(0xC0230098, 0x00004000)
+ reg_write(0xC023009c, 0x12010480)
+ # 54377 === DE initial sequence done ===
+
+ #selftest
+ #D.S EAXI:0x1023009C %LE %LONG 0x02010080
+ #D.S EAXI:0x10230094 %LE %LONG 0x00100000
+ #D.S EAXI:0x10230098 %LE %LONG 0x00004000
+ #D.S EAXI:0x1023009C %LE %LONG 0x82010080
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ # restore md to ap write secure world register protection
+ reg_write(0xC001DB00, reg_bak_MAS_SEC_0) # MAS_SEC_0[16] = M16_SEC = 0
+ reg_write(0xC001DF00, reg_bak_APC_CON) # APC_CON[2] = DBG_MASK = 1
+
+ print("DRAM_INIT -> elapsed time: {:.3f}".format(time.time()-tim))
+
+
+def DRAM_TEST(thread):
+ """dram test
+ [in] thread, codescape thread object
+ """
+ def _dram_test_by_ice(thread):
+ """simple dram test by ice
+ [in] thread, codescape thread object
+ """
+ adr, siz, omx = 0x0, 0x1000, 0x1000
+ print("_dram_test_by_ice(adr={:#x}, siz={:#x}) ...".format(adr, siz))
+
+ # fix pattern
+ tim = time.time()
+ ptn, inc = 0x55AAAA55, 0
+ print("fix pattern test, {:#010x} ...".format(ptn))
+ idx, rem, err = adr, siz, 0
+ while rem:
+ one = omx if rem > omx else rem
+ thread.memory.Fill(idx, element_size=4, element_count=one>>2, initial_value=ptn, increment=inc)
+ idx += one
+ rem -= one
+ idx, rem = adr, siz
+ while rem:
+ one = omx if rem > omx else rem
+ if not thread.memory.Check(idx, element_size=4, element_count=one>>2, initial_value=ptn, increment=inc):
+ print("-> {:#x}~{:#x} fail ...>\"<".format(idx, idx+one-1))
+ err += 1
+ idx += one
+ rem -= one
+ print("-> elapsed {:.3f} sec, {}".format(time.time()-tim, "fail ...>\"<" if err else "pass"))
+
+ # random pattern
+ print("random pattern test")
+ tim = time.time()
+ ptn = [random.randint(0x0, 0xFFFFFFFF) for _ in range(siz>>2)]
+ idx, rem, err = adr, siz, 0
+ while rem:
+ one = omx if rem > omx else rem
+ thread.memory.Write(idx, ptn[(idx-adr)>>2:(idx-adr+one)>>2])
+ idx += one
+ rem -= one
+ idx, rem, dat = adr, siz, []
+ while rem:
+ one = omx if rem > omx else rem
+ dat.extend(thread.memory.Read(idx, count=one>>2))
+ idx += one
+ rem -= one
+ for idx in range(siz>>2):
+ if ptn[idx] != dat[idx]:
+ print("{:#010x}: {:#010x} -> {:#010x} mismatch".format(idx*4, ptn[idx], dat[idx]))
+ err += 1
+ print("-> elapsed {:.3f} sec, {}".format(time.time()-tim, "fail ...>\"<" if err else "pass"))
+
+ def _dram_test_by_trfg(thread, ctrl=0, loop=2):
+ """use traffic-gen (TRFG) *4 to test DRAM
+ [in] thread, codescape thread object
+ [in] ctrl, all-0: config and start
+ bit-0: start
+ bit-1: pause
+ bit-2: resume
+ [in] loop, test loop, 0:infinite, others:N-times
+ [out] 0:success, 1:fail
+ """
+ TRFG_BASE = 0xC0215000 # TRFG 0~3 offset 0x100
+
+ if ctrl != 0:
+ thread.memory.Write(TRFG_BASE+0x000, ctrl)
+ thread.memory.Write(TRFG_BASE+0x100, ctrl)
+ thread.memory.Write(TRFG_BASE+0x200, ctrl)
+ thread.memory.Write(TRFG_BASE+0x300, ctrl)
+ print("TRFG control done ...")
+ return 0
+
+ print("TRFG config and start ...")
+ for idx in range(4):
+ base = TRFG_BASE + 0x100 * idx
+ start_addr = 0x01000000 * idx
+ pat_ctl = 0x07FF0017 + ((loop & 0xF) << 8)
+ # TRFG_STRAT_CTL, [0]:start, [1]:pause, [2]:resume
+ thread.memory.Write(base+0x00, 0x00000000)
+ # TRFG_INIT_PAT_W3
+ thread.memory.Write(base+0x04, 0x5A5A5A5A)
+ # TRFG_INIT_PAT_W2
+ thread.memory.Write(base+0x08, 0xA5A5A5A5)
+ # TRFG_INIT_PAT_W1
+ thread.memory.Write(base+0x0C, 0x5A5A5A5A)
+ # TRFG_INIT_PAT_W0
+ thread.memory.Write(base+0x10, 0xA5A5A5A5)
+ # TRFG_START_ADDR
+ thread.memory.Write(base+0x14, start_addr)
+ # TRFG_TEST_LEN * 16 byte
+ thread.memory.Write(base+0x18, 0x00040000)
+ # TRFG_PAT_CTL, [11:8]:test_loop, [5:4]:pat_mode
+ thread.memory.Write(base+0x1C, pat_ctl)
+ # TRFG_BUS_CTL, [13:10]:domain, [3:0]:burst_len
+ thread.memory.Write(base+0x20, 0x00000003)
+ # TRFG_STRAT_CTL, [0]:start, [1]:pause, [2]:resume
+ thread.memory.Write(base+0x00, 0x00000001)
+
+ # Wait done
+ print("Wait done")
+ trfg = [None] * 4
+ while None in trfg:
+ print(".")
+ time.sleep(1)
+ for idx in range(4):
+ base = TRFG_BASE + 0x100 * idx
+ if trfg[idx] != None:
+ continue
+ if (thread.memory.Read(base+0x24) & 0x1) == 0x1:
+ continue
+ if (thread.memory.Read(base+0x24) & 0x4) == 0x0:
+ print("-> TRFG {} test fail:".format(idx))
+ print("FAIL_ADDR = {:#010x}".format(thread.memory.Read(base+0x28)))
+ print("EXP_DATA_W3~0 = " + \
+ ", ".join(["{:#010x}".format(thread.memory.Read(base+0x2C+_*4)) for _ in range(4)]))
+ print("FAIL_DATA_W3~0 = " +\
+ ", ".join(["{:#010x}".format(thread.memory.Read(base+0x3C+_*4)) for _ in range(4)]))
+ trfg[idx] = 1
+ else:
+ trfg[idx] = 0
+
+ if trfg == [0,0,0,0]:
+ print("-> TRFG dram test pass ...^_^")
+ return 0
+ else:
+ print("-> TRFG dram test fail ...>'<")
+ return 1
+
+ print("DRAM_TEST() ...")
+ if thread.memory.Read(0xA000001C) < 0x08623511:
+ _dram_test_by_ice(thread)
+ else:
+ _dram_test_by_trfg(thread)
+
+
+def Head8478120_workaround(thread):
+
+ print("Workaround for bitfile(Head8478120) bootslave bug ...")
+ thread.memory.Write(0xA0061118, 0x5500)
+ thread.memory.Write(0xA0061110, 0x9fb40000)
+ thread.memory.Write(0xA0061114, 0x1)
+
+ thread.memory.Write(0xA0061124, 0x5500)
+ thread.memory.Write(0xA006111c, 0x9fb80000)
+ thread.memory.Write(0xA0061120, 0x1)
+
+ thread.memory.Write(0xA0061130, 0x5500)
+ thread.memory.Write(0xA0061128, 0x9fbc0000)
+ thread.memory.Write(0xA006112c, 0x1)
+
+
+if __name__ == "__main__":
+ print "=== Start Initializing ==="
+ umolya_path = ""
+ dsp_path = ""
+ da = codescape.GetFirstProbe()
+ print "Get probe name = %s" %(da.name)
+ probe(da.name)
+ #reset(probe(da.name))
+ #autodetect()
+
+ #config('lazy Freeze',0)
+ #cmdall(halt)
+
+ #print "Enlarge timeout for stability..."
+ #da.SetDASettingValue("Disable MMU Checking", True)
+ #da.SetDASettingValue("apb timeout",500000)
+ #da.SetDASettingValue("Enter Debug Timeout",50000)
+ #da.SetDASettingValue("reset ack timeout",50000)
+ #da.SetDASettingValue("mdh valid retry step",100000)
+ #da.SetDASettingValue("Fast Writes", False)
+
+ thread = da.cores[0].hwthreads[0]
+ core_num = (thread.memory.Read(0x1F000000) & 0xFF)+1
+ print "Get Core Number = %d" %(core_num)
+ #thread = da.cores[0].hwthreads[0]
+ #thread.Stop()
+
+ print "Stop all cores ..."
+ for idx in reversed(range(core_num)):
+ #thread = da.cores[idx].hwthreads[0]
+ #thread.Stop()
+ da.cores[idx].StopAll(False)
+
+ #da.SetDASettingValue("Lock Monitor in Cache", False)
+
+ print "Enable CPU MO port ..."
+ thread.memory.Write(0x1F000020, 0xF)
+ thread.memory.Write(0x1F000090, 0xA0000000)
+ thread.memory.Write(0x1F000098, 0xE0000002)
+ thread.memory.Write(0x1F0000A0, 0xC0000000)
+ thread.memory.Write(0x1F0000A8, 0xC0000002)
+
+ da.SetDASettingValue("Fast Monitor Address", 0x6F800000)
+ da.SetDASettingValue("Fast Writes", False)
+ da.SetDASettingValue("Fast Reads", False)
+
+ time_str = time.time()
+ WDT_Disable(thread)
+ DRAM_INIT(thread)
+ MD_Remap(thread)
+ #Head8478120_workaround(thread)
+ #DRAM_TEST(thread)
+
+ #clear dsp header
+ #print("Clear DSP Header...")
+ #thread.memory.Write(0x0D500000, 0)
+ #thread.memory.Write(0x00080000, 0)
+
+ #print("Clear NVRAM Header...")
+ #Only for BIANCO
+ #thread.memory.Write(0x0D8001FC, 0)
+
+ time_end = time.time()
+ print("Total elapsed time: {:.3f} sec".format(time_end-time_str))
+
+ if codescape.environment == "codescape":
+
+ if codescape.is_script_region:
+ region_thread = codescape.GetRegionThread()
+ # This is a script region, set up events to wait for thread halted
+ import wx
+ class Frame(wx.Frame):
+
+ dsp_bin_addr = dsp_bin_base
+ textctrl = 0
+ restore_callstack_btn = 0
+ def __init__(self, parent, thread):
+ wx.Frame.__init__(self, parent, title="[ModemOnly]LoadBin&Symbol")
+
+ # Initialize UI
+ button_width = 80
+ border_size = 6
+
+ load_all_elf_btn = wx.Button(self, pos=(0, 0), label='Load elf', size=(button_width,-1))
+ load_all_elf_btn.Bind(wx.EVT_BUTTON, self.on_load_all_elf_button)
+
+ button_width = 100
+ border_size = 6
+ load_dsp_btn = wx.Button(self, pos=(0, 35), label='Load DSP Bin', size=(button_width,-1))
+ load_dsp_btn.Bind(wx.EVT_BUTTON, self.on_load_dsp_button)
+
+ statictext = wx.StaticText(self, pos=(110, 40), label="dsp address:")
+
+ button_width = 120
+ border_size = 6
+ Frame.restore_callstack_btn = wx.Button(self, pos=(0, 70), label='Restore CallStack', size=(button_width,-1))
+ Frame.restore_callstack_btn.Bind(wx.EVT_BUTTON, self.on_restore_callstack_button)
+ statictext2 = wx.StaticText(self, pos=(125, 75), label="// use when exception")
+ Frame.restore_callstack_btn.Disable()
+
+ Frame.textctrl = wx.TextCtrl(self,pos=(190, 37), value = self.dsp_bin_addr)
+ Frame.textctrl.Bind(wx.EVT_TEXT, self.OnTextChanged)
+
+
+ # load all elf
+ def on_load_all_elf_button(self, event):
+ #myobject = event.GetEventObject()
+ #myobject.Disable()
+ da.SetDASettingValue("Fast Reads", True)
+ global dsp_bin_base
+ fileDialog = wx.FileDialog(self)
+ fileDialog.ShowModal()
+ umolya_path = fileDialog.GetPath()
+ fileDialog.Destroy()
+ thread = da.cores[0].hwthreads[0]
+ if load_all_elf(da, thread, umolya_path)==1:
+ Frame.restore_callstack_btn.Enable()
+ Frame.dsp_bin_addr = dsp_bin_base
+ Frame.textctrl.SetValue(Frame.dsp_bin_addr)
+ da.SetDASettingValue("Fast Reads", False)
+ #config('lazy Freeze',1)
+ #myobject.Enable()
+
+ # load dsp bin
+ def on_load_dsp_button(self, event):
+ myobject = event.GetEventObject()
+ myobject.Disable()
+ da.SetDASettingValue("Fast Reads", True)
+ print "Select dsp bin...."
+ fileDialog = wx.FileDialog(self)
+ fileDialog.ShowModal()
+ dsp_path = fileDialog.GetPath()
+
+ thread = da.cores[0].hwthreads[0]
+ load_dsp_bin(da, thread, dsp_path,self.dsp_bin_addr)
+ da.SetDASettingValue("Fast Reads", False)
+ myobject.Enable()
+
+ def OnTextChanged(self, event):
+ Frame.dsp_bin_addr = event.String
+ #print "Dsp address set to " + self.dsp_bin_addr
+
+ def on_restore_callstack_button(self, event):
+ myobject = event.GetEventObject()
+ myobject.Disable()
+ da.SetDASettingValue("Fast Reads", True)
+ cmdall(halt)
+ ex_vpe = find_excep_vpe(da)
+ if ex_vpe==-1:
+ print "There is no vpe enter exception!"
+ else:
+ restore_callstack(da, ex_vpe)
+ da.SetDASettingValue("Fast Reads", False)
+ myobject.Enable()
+
+ app = wx.App()
+ frame = Frame(None, region_thread);
+ frame.Show()
+ app.MainLoop()
+ sys.exit()
+ else:
+ if (len(sys.argv) == 2):
+ umolya_path = sys.argv[1]
+ load_all_elf(da, thread, umolya_path)
+ else:
+ # WDT_Disable and DRAM_INIT done
+ sys.exit("[Reminder] Remember to load .elf")
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/APOLLO_EVB.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/APOLLO_EVB.launch
new file mode 100755
index 0000000..aa3527d
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/APOLLO_EVB.launch
@@ -0,0 +1,62 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="["SPV_memset_size_profile[0]","SPV_memset_profile_cnt","SPV_memset_lr_profile[0]"]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.ui.focus_threads" value=""/>
+<stringAttribute key="com.mediatek.ide.dsf.mvpu.dbg_file" value=""/>
+<stringAttribute key="com.mediatek.ide.dsf.mvpu.pattern_file" value=""/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value=""/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.cache.FilePath" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.cache.gdbIndexElf" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.LocalTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.debuggerIpAddress" value="localhost"/>
+<intAttribute key="com.mediatek.ide.util.debuggerPortNumber" value="3333"/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.substitute_path_no_translate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="MT6297_Chip"/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.args" value="-f board/mips/mt6297_mips_chip.cfg -c "adapter_khz 10000""/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.cmds" value=""/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.widget.args" value="{"Clock_10000":"10000"}"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="attach"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
+<booleanAttribute key="org.eclipse.debug.core.capture_output" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_OUTPUT_ON" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/SSButton.act b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/SSButton.act
new file mode 100755
index 0000000..12d8920
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/SSButton.act
@@ -0,0 +1,14 @@
+<Customize>
+ <Action name="LoadDSP">
+ <GDBSource>coretracer_load_dsp.py</GDBSource>
+ </Action>
+ <Action name="SWLA">
+ <GDBSource>coretracer_swla.py</GDBSource>
+ </Action>
+ <Action name="restoreCallStack">
+ <GDBSource>coretracer_restore_callstack.py</GDBSource>
+ </Action>
+ <Action name="DspExceptionInfo">
+ <GDBSource>../../../dsp_debug_info_CoreTracer.py</GDBSource>
+ </Action>
+</Customize>
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/TCF.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/TCF.py
new file mode 100755
index 0000000..bb8c771
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/TCF.py
@@ -0,0 +1,172 @@
+import getopt
+from multiprocessing import Queue
+import socket
+import sys
+from threading import Thread
+import time
+
+SPLITTER = '\x00'
+EOL = '\x03\x01'
+HEADER = '\x03\x03'
+LEN_EOL = len((SPLITTER + EOL))
+
+class Event():
+ def __init__(self, args):
+ b = bytearray(args).split(SPLITTER.encode('utf_8'))
+ self.servicename = b[1]
+ self.eventname = b[2]
+ self.data = b[3]
+ self.elements = b[3:]
+
+ def getServiceName(self):
+ return self.servicename.decode('utf_8')
+
+ def getEventName(self):
+ return self.eventname.decode('utf_8')
+
+ def getData(self):
+ return self.data.decode('utf_8')
+
+ def getElement(self, index):
+ if len(self.elements) == 0:
+ return ''
+ return self.elements[index]
+
+ def toString(self):
+ datastr = ''
+ for b in self.elements:
+ if not b == EOL:
+ datastr = datastr + ' ' + b.decode('utf_8')
+ return 'Event ' + self.getServiceName() + ' ' + self.getEventName() + ' ' + datastr
+
+class Result():
+ def __init__(self, args):
+ b = bytearray(args).split(SPLITTER.encode('utf_8'))
+ self.type = b[0]
+ self.token = b[1]
+ self.data = b[2]
+ self.elements = b[2:]
+
+ def getType(self):
+ return self.type.decode('utf_8')
+
+ def getToken(self):
+ return self.token.decode('utf_8')
+
+ def getData(self):
+ return self.data.decode('utf_8')
+
+ def getElement(self, index):
+ if len(self.elements) == 0:
+ return ''
+ return self.elements[index]
+
+ def toString(self):
+ datastr = ''
+ for b in self.elements:
+ if not b == EOL:
+ datastr = datastr + ' ' + b.decode('utf_8')
+ return self.getType() + ' ' + self.getToken() + ' ' + datastr
+
+class TCFThread(Thread):
+ def __init__(self, host='localhost', port='1534'):
+ Thread.__init__(self)
+ try:
+ opts, args = getopt.getopt(sys.argv[1:],"h:p:",["host=","port="])
+ for opt, arg in opts:
+ if opt in ("-h", "--host"):
+ host = arg
+ elif opt in ("-p", "--port"):
+ port = int(arg)
+ except getopt.GetoptError:
+ pass
+ self.tcf_terminator = (SPLITTER + EOL).encode('utf_8')
+ self.tcf = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+ self.tcf.connect((host, int(port)))
+ self.queue = Queue()
+ self.send(['E','Locator','Hello','["ZeroCopy"]'])
+
+ def run(self):
+ remain = None
+ while 1:
+ try:
+ data = self.tcf.recv(1024)
+ if remain == None:
+ remain = data
+ else:
+ remain = remain + data
+
+ if bytearray(data).endswith(self.tcf_terminator):
+ res, rem = getData(remain)
+ if bytearray(res).startswith('E'.encode('utf_8')):
+ self.queue.put(Event(res))
+ elif bytearray(res).startswith('R'.encode('utf_8')):
+ self.queue.put(Result(res))
+ remain = rem
+ except:
+ break
+ time.sleep(0.1)
+ self.tcf.close()
+
+ def get(self):
+ if not self.queue.empty():
+ return self.queue.get()
+ else:
+ return None
+
+ def send(self, args):
+ for arg in args:
+ self.tcf.send(str(arg + SPLITTER).encode('utf_8'))
+ self.tcf.send(EOL.encode('utf_8'))
+
+ def rawsend(self, rawarg):
+ self.tcf.send(rawarg)
+
+ def close(self):
+ self.tcf.shutdown(1)
+ self.tcf.close()
+
+def getData(arg):
+ data = bytearray(arg)
+ result = None
+ remain = None
+ if data.startswith(HEADER.encode('utf_8')):
+ ind = data.index(HEADER.encode('utf_8'))+2
+ leng, cnt = getDataLength(data, ind, 0)
+ ind = ind + cnt + 1
+ result = data[ind:ind+leng-1]
+ remain = data[ind+leng-1:]
+ else:
+ ind = data.index((SPLITTER + EOL).encode('utf_8'))
+ if not ind == -1:
+ result = data[:ind]
+ remain = data[ind:]
+ else:
+ result = None
+ remain = data
+
+ if not remain == None and bytearray(remain).startswith((SPLITTER + EOL).encode('utf_8')):
+ remain = remain[LEN_EOL:]
+
+# print('result: \'' + str(result) + '\'')
+# print('remain: \'' + str(remain) + '\'')
+# sys.stdout.flush()
+ return result, remain
+
+def getDataLength(_rec, ind, count):
+ rec_bytes = bytearray(_rec);
+ leng = rec_bytes[ind]
+ mulp = 0
+ if count == 0:
+ mulp = 1
+ else:
+ mulp = 128 * count
+
+ if leng & 0x80 == 0:
+ return leng * mulp, count
+ else:
+ num, cnt = getDataLength(rec_bytes, ind + 1, count + 1)
+ return ((leng & 0x7f) * mulp) + num, cnt
+
+def doEcaspe(arg):
+ return str(arg).replace('\\', '\\\\').replace('\"', '\\\"')
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/TCF.pyc b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/TCF.pyc
new file mode 100755
index 0000000..f47f3c8
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/TCF.pyc
Binary files differ
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/coretracer_basic_init.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/coretracer_basic_init.py
new file mode 100755
index 0000000..12d261d
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/coretracer_basic_init.py
@@ -0,0 +1,213 @@
+import sys
+import time
+import os
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+
+#MD Side
+AP_REG_BASE=0xC0000000
+MD_REG_BASE=0xA0000000
+
+#AP side
+#AP_REG_BASE=0x10000000
+#MD_REG_BASE=0x20000000
+
+def switch_to_axi_mode():
+ print("Switch to AXI port ..")
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ mem_value = mem_value[12:23]
+ hex_int = int(mem_value, 16)
+ return hex_int
+
+def WDT_Disable():
+ """diable WDT function
+ [in] thread, codescape thread object
+ """
+ print("WDT disable ..")
+ mdrgu = 0xA00F0000 + 0x0100
+ aprgu = 0xC0007000
+ memory_write(mdrgu, (memory_read(mdrgu) & 0xFFFFFFFC) | 0x55000000)
+ memory_write(aprgu, (memory_read(aprgu) & 0xFFFFFFFE) | 0x22000000)
+
+def MD_SRCLKENA():
+ print("MD_SRCLKENA config ..")
+ """
+ INFRA_MISC2
+ [3:0] : mdsrc_req_0_en = 4'b0001
+ [7:4] : mdsrc_req_1_en = 4'b0010
+ """
+ infra_misc2_addr = 0x10001f0c
+ memory_write(infra_misc2_addr, (memory_read(infra_misc2_addr) & 0xFFFFFF00) | 0x21)
+
+ """
+ SRCLKEN_O1 Force RF On
+ """
+ addr1 = 0xC0006000
+ addr2 = 0xC0006008
+ memory_write(addr1, 0x0B160001) # magic key
+ memory_write(addr2, memory_read(addr2) | (1<<21) ) #set bit[21]
+
+def Config_26M_Quality():
+ print("Config 26M Quality ..")
+ addr = 0xC000C018
+ memory_write(addr, memory_read(addr) | 0x3 ) # set bit[1:0] = 2'b11
+ addr = 0xC000C00C
+ memory_write(addr, memory_read(addr) | 0x3 ) # set bit[1:0] = 2'b11
+ addr = 0xC000C000
+ memory_write(addr, memory_read(addr) | 0x3 ) # set bit[1:0] = 2'b11
+
+def MD_Remap(adr=None):
+ print("MD EMI Remap ..")
+ """MD reamp config
+ [in] thread, codescape thread object
+ [in] adr, user specific remap address (ap infra memory map view, 32M alignment)
+ default: emi start address
+ """
+
+ inf_emi = 0x40000000
+ print("MD_Remap(adr={:#x}) ...".format(inf_emi if adr == None else adr))
+ if adr == None:
+ inf_md = inf_emi
+ else:
+ assert (adr & 0x01FFFFFF) == 0
+ inf_md = adr
+ print("MD_Remap -> md:bank0=>ap:{:#x}, md:bank1=>ap:{:#x}, md:bank4=>ap:{:#x}".format(inf_md, inf_md+0x10000000, inf_emi))
+ # md remap bank 0
+ bnk = inf_md >> 25
+ memory_write(0xC0001300, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ memory_write(0xC0001304, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ memory_write(0xC0001308, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ memory_write(0xC000130c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+ # md remap bank 1
+ bnk = (inf_md+0x10000000) >> 25
+ memory_write(0xC0001310, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ memory_write(0xC0001314, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ memory_write(0xC0001318, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ memory_write(0xC000131c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+ # md remap bank 4
+ bnk = inf_emi >> 25
+ memory_write(0xC0001320, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ memory_write(0xC0001324, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ memory_write(0xC0001328, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ memory_write(0xC000132c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+
+def MO_Port_Enable():
+ print("MO port enable ..")
+ """
+ enable shaolin MO port
+ """
+ memory_write(0x1F000020, 0xF)
+ memory_write(0x1F000090, 0xA0000000)
+ memory_write(0x1F000098, 0xE0000002)
+ memory_write(0x1F0000A0, 0xC0000000)
+ memory_write(0x1F0000A8, 0xC0000002)
+
+def Switch_MDJtag_to_ShaolinDAP():
+ print("Switch MDJtag to ShaolinDAP ..")
+ """
+ switch MD JTAG to shaolinDAP (the jtag is defaultly for codescape. We want to let coretracer can use it.)
+ dbgsys addr = 0x0d101100
+ """
+ memory_write(0xA0601100, 0x3)
+ return
+
+def MD_PLL_Init():
+ print("MD PLL Init ..")
+ REGBASE_PLLMIXED = 0xA0140000
+ REGBASE_CLKSW = 0xA0150000
+
+ # default md_srclken_ack settle time = 150T 32k
+ memory_write(REGBASE_PLLMIXED+0x4, 0x02021c96)
+ # change APBPLL_SETTLE_26M to 0x2f2 => 29us
+ memory_write(REGBASE_PLLMIXED+0x20, 0x17920803)
+
+
+ memory_write(REGBASE_CLKSW+0xB8, 0x0) # Set HRAM to 800Mhz
+ memory_write(REGBASE_CLKSW+0x8c, 0x30)# Set NRPLL4_1_CK to 800Mhz
+ memory_write(REGBASE_CLKSW+0x5c, 0x11)# Set BPIPLL
+ memory_write(REGBASE_CLKSW+0x78, 0x10)# Set NRPLL1
+ memory_write(REGBASE_CLKSW+0x70, 0x21)# Set NRL2 spec to 450Mhz
+ memory_write(REGBASE_CLKSW+0x94, 0x10)# Set MCORE spec to 900MHz
+ memory_write(REGBASE_CLKSW+0x90, 0x10)# Set VCORE spec to 900MHz
+
+
+ memory_write(REGBASE_CLKSW+0xF00, 0x00D7FFFF) # NR0/1/2/4 PLL turn on
+
+ memory_write(REGBASE_PLLMIXED+0x84, memory_read(REGBASE_PLLMIXED+0x84) & 0xfffeffff) # Set FBKSEL = 0
+ memory_write(REGBASE_PLLMIXED+0x8c, memory_read(REGBASE_PLLMIXED+0x8c) & 0xfffeffff) # Set FBKSEL = 0
+
+ memory_write(REGBASE_PLLMIXED+0x58, 0x80117b13) # Fixed Fvco = 1818Mhz
+ memory_write(REGBASE_PLLMIXED+0x50, 0x8023d800) # Fvco = 3728Mhz. 3728/4 = 932Mhz
+ memory_write(REGBASE_PLLMIXED+0x48, 0x80229e00) # Fvco = 3600Mhz. 3600/4 = 900Mhz
+ memory_write(REGBASE_PLLMIXED+0x40, 0x8019f626) # Fvco = 2700Mhz. 2700/3 = 900Mhz
+
+ memory_write(REGBASE_PLLMIXED+0x98, 0x80180000) # Fvco = 2496Mhz. 2496/4 = 624Mhz
+ memory_write(REGBASE_PLLMIXED+0x9c, 0x12)
+
+ memory_write(REGBASE_PLLMIXED+0x68, 0x80133c00) # Fvco = 2000Mhz. 2000/2 = 1000Mhz
+ memory_write(REGBASE_PLLMIXED+0x70, 0x80171400) # Fvco = 2400Mhz. 2400/2 = 1000Mhz
+ memory_write(REGBASE_PLLMIXED+0x78, 0x801aec00) # Fvco = 2800Mhz. 2800/2 = 1400Mhz
+ memory_write(REGBASE_PLLMIXED+0x80, 0x80180000) # Fvco = 2496Mhz. 2496/4 = 624Mhz
+ memory_write(REGBASE_PLLMIXED+0x88, 0x800f6200) # Fvco = 1600Mhz. 1600/1 = 1600Mhz
+ memory_write(REGBASE_PLLMIXED+0x90, 0x801cd800) # Fvco = 3000Mhz. 3000/2 = 1500Mhz
+
+ memory_write(REGBASE_PLLMIXED+0x10, 0x0)
+
+ # polling untill MDMCUPLL complete freq adjustment
+ dummy_x = 0
+ while (memory_read(REGBASE_PLLMIXED+0x800) >> 14) & 0x1 == 0x1 :
+ dummy_x+=1
+
+ # wait MD bus clock ready
+ dummy_y = 0
+ while memory_read(REGBASE_CLKSW+0xcc) & 0x8000 != 0x8000 :
+ dummy_y+=1
+
+ #switch clock source to PLL
+ memory_write(REGBASE_CLKSW+0x24, memory_read(REGBASE_CLKSW+0x24) | 0x3) # switch MDMCU & MDBUS clock to PLL freq
+
+ memory_write(REGBASE_CLKSW+0x24, memory_read(REGBASE_CLKSW+0x24) | 0xfffffffc) # switch all clock to PLL freq
+ memory_write(REGBASE_CLKSW+0x28, memory_read(REGBASE_CLKSW+0x28) | 0x4)
+
+ memory_write(REGBASE_CLKSW+0x20, 0x3) # Turn off all SW clock request
+
+ memory_write(REGBASE_CLKSW+0x2c, memory_read(REGBASE_CLKSW+0x2c) | 0x1100011) # switch SDF clock to PLL freq
+
+ memory_write(REGBASE_PLLMIXED+0x314, 0xffff) # Clear PLL ADJ RDY IRQ fired by initial period adjustment
+ memory_write(REGBASE_PLLMIXED+0x318, 0xffff) # Mask all PLL ADJ RDY IRQ
+
+ memory_write(REGBASE_PLLMIXED+0xf00, 0x62970000) # Write PLL magic number
+ return
+
+if __name__ == "__main__":
+ #MO_Port_Enable()
+ switch_to_axi_mode()
+
+ #Switch_MDJtag_to_ShaolinDAP()
+
+ WDT_Disable()
+
+ #MD_SRCLKENA()
+
+ Config_26M_Quality()
+
+ #MD_Remap()
+
+ #MD_PLL_Init()
+ print "All misc config done!"
+
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/coretracer_init_emi.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/coretracer_init_emi.py
new file mode 100755
index 0000000..f44c884
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/coretracer_init_emi.py
@@ -0,0 +1,707 @@
+import sys
+import time
+import os
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+
+#MD Side
+AP_REG_BASE=0xC0000000
+MD_REG_BASE=0xA0000000
+
+#AP side
+#AP_REG_BASE=0x10000000
+#MD_REG_BASE=0x20000000
+
+def switch_to_axi_mode():
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ mem_value = mem_value[12:23]
+ hex_int = int(mem_value, 16)
+ return hex_int
+
+def DRAM_INIT():
+ print("DRAM_INIT ...")
+ tim = time.time()
+
+ # disable md to ap write secure world register protection
+ reg_bak_APC_CON = memory_read(0xC001DF00)
+ reg_bak_MAS_SEC_0 = memory_read(0xC001DB00)
+ memory_write(0xC001DF00, 0x00000000) # APC_CON[2] = DBG_MASK = 0
+ memory_write(0xC001DB00, 0x00010000) # MAS_SEC_0[16] = M16_SEC = 1
+
+ NR_RNKS=1
+ #EMI
+
+ #DRAMC0_NAO
+ #0x10234***
+ #DRAMC0
+ #0x10230***
+ #DRAMC1
+ #0x10240***
+ #DDRPHY0
+ #0x10238***
+ #DDRPHY1
+ #0x10248***
+
+ #EMI setting
+ memory_write(0xC0219000, 0x00001052) # ;0x00025052
+ memory_write(0xC0219060, 0xff000400)
+ memory_write(0xC0219020, 0x00008000)
+ memory_write(0xC0235000, 0x00001012) # ;0x00005053
+ memory_write(0xC0235010, 0x00000001)
+
+
+ #;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+ memory_write(0xC0238274, 0xffffffff)
+ memory_write(0xC0248278, 0x00000000)
+ memory_write(0xC0248274, 0xffffffff)
+ memory_write(0xC023829c, 0x38030000)
+ #PLL sel
+
+ memory_write(0xC02381a0, 0x00000000)
+ memory_write(0xC02380a0, 0x00000000)
+ memory_write(0xC0238120, 0x00000000)
+ memory_write(0xC02382ac, 0x80000006)
+ memory_write(0xC02481a0, 0x00000000)
+ memory_write(0xC02480a0, 0x00000000)
+ memory_write(0xC0248120, 0x00000000)
+ memory_write(0xC02482ac, 0x80000006)
+ memory_write(0xC02382a0, 0x00000100) # ;PINMUX
+ memory_write(0xC02482a0, 0x00000100)
+ memory_write(0xC0238264, 0x00400000)
+ memory_write(0xC0238268, 0x00000040)
+ memory_write(0xC0248264, 0x00400000)
+ memory_write(0xC0248268, 0x00000040)
+ memory_write(0xC0238e18, 0x00000000)
+ memory_write(0xC0238f18, 0x01010000)
+ memory_write(0xC0239018, 0x02020000)
+ memory_write(0xC0238e68, 0x04040000)
+ memory_write(0xC0238f68, 0x05050000)
+ memory_write(0xC0239068, 0x06060000)
+ memory_write(0xC0238ec4, 0x00000c00)
+ memory_write(0xC0238fc4, 0x00000c00)
+ memory_write(0xC02393c4, 0x00000c00)
+ memory_write(0xC02394c4, 0x00000c00)
+ memory_write(0xC0238e50, 0x00000000)
+ memory_write(0xC0238f50, 0xbbbbbbbb)
+ memory_write(0xC0239050, 0xbbbbbbbb)
+ memory_write(0xC0238e54, 0x00000000)
+ memory_write(0xC0238f54, 0x0000bb00)
+ memory_write(0xC0239054, 0x0000bb00)
+ memory_write(0xC0248ea0, 0x00000000)
+ memory_write(0xC0248fa0, 0x00bbbbbb)
+ memory_write(0xC02490a0, 0x00bbbbbb)
+ memory_write(0xC0248ea4, 0x00000000)
+ memory_write(0xC0248fa4, 0x00000bbb)
+ memory_write(0xC02490a4, 0x00000bbb)
+ memory_write(0xC0248e00, 0x00000000)
+ memory_write(0xC0248f00, 0xbbbbbbbb)
+ memory_write(0xC0249000, 0xbbbbbbbb)
+ memory_write(0xC0248e04, 0x00000000)
+ memory_write(0xC0248f04, 0x0000bb00)
+ memory_write(0xC0249004, 0x0000bb00)
+ memory_write(0xC0248e50, 0x00000000)
+ memory_write(0xC0248f50, 0xbbbbbbbb)
+ memory_write(0xC0249050, 0xbbbbbbbb)
+ memory_write(0xC0248e54, 0x00000000)
+ memory_write(0xC0248f54, 0x0000bb00)
+ memory_write(0xC0249054, 0x0000bb00)
+ memory_write(0xC0238e1c, 0x00000c00)
+ memory_write(0xC0238f1c, 0x00000c00)
+ memory_write(0xC023901c, 0x00000c00)
+ memory_write(0xC0238e6c, 0x000f0f00)
+ memory_write(0xC0238f6c, 0x000f0f00)
+ memory_write(0xC023906c, 0x000f0f00)
+ memory_write(0xC0248ec4, 0x00000f0f)
+ memory_write(0xC0248fc4, 0x00000f0f)
+ memory_write(0xC02490c4, 0x00000f0f)
+ memory_write(0xC0248e1c, 0x000f0f00)
+ memory_write(0xC0248f1c, 0x000f0f00)
+ memory_write(0xC024901c, 0x000f0f00)
+ memory_write(0xC0248e6c, 0x000f0f00)
+ memory_write(0xC0248f6c, 0x000f0f00)
+ memory_write(0xC024906c, 0x000f0f00)
+ memory_write(0xC0238128, 0x00001010)
+ memory_write(0xC023812c, 0x01111010)
+ memory_write(0xC0238130, 0x010c10d0)
+ memory_write(0xC023812c, 0x03111010)
+ memory_write(0xC02381a4, 0x0000008c)
+ #TINFO="SHL ddrphy chA reset release"
+ memory_write(0xC02381b0, 0x00080010) # ;SER MODE
+ memory_write(0xC0238d04, 0x00000101)
+ memory_write(0xC0238d08, 0x00000101)
+ memory_write(0xC0239204, 0x00000101)
+ memory_write(0xC0239208, 0x00000101)
+ memory_write(0xC02380a4, 0x0000008c)
+ memory_write(0xC02380b0, 0x00080010) # ;SER MODE
+ memory_write(0xC0238c04, 0x00000101)
+ memory_write(0xC0238c08, 0x00000101)
+ memory_write(0xC0239104, 0x00000101)
+ memory_write(0xC0239108, 0x00000101)
+ memory_write(0xC02481a8, 0x00001010)
+ memory_write(0xC02481ac, 0x01111010)
+ memory_write(0xC02481b0, 0x010c10d0)
+ memory_write(0xC02481ac, 0x03111010)
+ memory_write(0xC02480a8, 0x00001010)
+ memory_write(0xC02480ac, 0x01111010)
+ memory_write(0xC02480b0, 0x010c10d0)
+ memory_write(0xC02480ac, 0x03111010)
+ memory_write(0xC0248128, 0x00001010)
+ memory_write(0xC024812c, 0x01111010)
+ memory_write(0xC0248130, 0x010c10d0)
+ memory_write(0xC024812c, 0x03111010)
+ #PLL
+
+ memory_write(0xC0238c18, 0x44000000)
+ memory_write(0xC0239118, 0x04000000)
+ memory_write(0xC0238c98, 0x44000000)
+ memory_write(0xC0239198, 0x04000000)
+ memory_write(0xC0238d18, 0x44000000)
+ memory_write(0xC0239218, 0x04000000)
+ memory_write(0xC0248c18, 0x44000000)
+ memory_write(0xC0249118, 0x04000000)
+ memory_write(0xC0248c98, 0x44000000)
+ memory_write(0xC0249198, 0x04000000)
+ memory_write(0xC0248d18, 0x44000000)
+ memory_write(0xC0249218, 0x04000000)
+ memory_write(0xC0238da0, 0x00000000)
+ memory_write(0xC02392a0, 0x00000000)
+ # DLL
+
+ memory_write(0xC0238124, 0x0000051e)
+ memory_write(0xC02481a4, 0x0000051e)
+ #TINFO="SHL ddrphy chB reset release"
+ memory_write(0xC02480a4, 0x0000051e)
+ memory_write(0xC0248124, 0x0000051e)
+ memory_write(0xC0238194, 0x00660600)
+ memory_write(0xC0238094, 0xc0660600)
+ memory_write(0xC0238114, 0xc0660600)
+ memory_write(0xC0248194, 0xc0660600)
+ memory_write(0xC0248094, 0xc0660600)
+ memory_write(0xC0248114, 0xc0660600)
+ memory_write(0xC02381b8, 0x00180101)
+ memory_write(0xC023826c, 0x00000000)
+ memory_write(0xC02481b8, 0x00180101)
+ memory_write(0xC024826c, 0x00000000)
+ memory_write(0xC0238d14, 0x00000000)
+ memory_write(0xC0239214, 0x00000000)
+ memory_write(0xC0239714, 0x00000000)
+ memory_write(0xC0239c14, 0x00000000)
+ memory_write(0xC0248d14, 0x00000000)
+ memory_write(0xC0249214, 0x00000000)
+ memory_write(0xC0249714, 0x00000000)
+ memory_write(0xC0249c14, 0x00000000)
+
+ time.sleep(0.001)
+
+ memory_write(0xC023800c, 0x006d0000)
+ memory_write(0xC0238180, 0x0000000c)
+ memory_write(0xC0238080, 0x00000009)
+ memory_write(0xC0238100, 0x00000009)
+ memory_write(0xC0248180, 0x00000009)
+ memory_write(0xC0248080, 0x00000009)
+ memory_write(0xC0248100, 0x00000009)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238000, 0x80000000)
+ memory_write(0xC0238004, 0x80000000)
+ memory_write(0xC0238004, 0x00000000)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238da4, 0x00019200)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238194, 0x00660e00)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238094, 0xc0660e00)
+ memory_write(0xC0238114, 0xc0660e00)
+ memory_write(0xC0248194, 0xc0660e00)
+ memory_write(0xC0248094, 0xc0660e00)
+ memory_write(0xC0248114, 0xc0660e00)
+ memory_write(0xC0238284, 0x0000001f)
+
+ time.sleep(0.001)
+
+ memory_write(0xC0238124, 0x0001051e)
+ memory_write(0xC02481a4, 0x0001051e)
+ memory_write(0xC02480a4, 0x0001051e)
+ memory_write(0xC0248124, 0x0001051e)
+ memory_write(0xC02382a0, 0x8100018c)
+ memory_write(0xC02482a0, 0x8100018c)
+ memory_write(0xC02381b8, 0x00040101)
+ memory_write(0xC02381b4, 0x00000000)
+ memory_write(0xC02380b4, 0x00000000)
+ memory_write(0xC0238134, 0x00000000)
+ memory_write(0xC0238c1c, 0x00200000) # ; WJ: LP3
+ memory_write(0xC02481b4, 0x00000000)
+ memory_write(0xC02480b4, 0x00000000)
+ memory_write(0xC0248134, 0x00000000)
+ memory_write(0xC0248c1c, 0x00200000) # ; WJ: LP3
+ memory_write(0xC02300dc, 0x00051008)
+ #;D.S EAXI:0x1024000dc %LE %LONG 0x00050008
+ memory_write(0xC0230000, 0x02101000) # ;[24]=LP2_EN , [25]=LP3_EN, [26]=LP4_EN
+ memory_write(0xC0230640, 0xa688049f)
+ memory_write(0xC0230660, 0x00030053)
+ memory_write(0xC023004c, 0x25712000)
+ memory_write(0xC0230680, 0x00000000)
+ memory_write(0xC0230684, 0x00000000)
+ memory_write(0xC0230688, 0x00000000)
+ memory_write(0xC023068c, 0x00000000)
+ memory_write(0xC0230690, 0x11111011)
+ memory_write(0xC0230694, 0x01101111)
+ memory_write(0xC0230698, 0x11111111)
+ memory_write(0xC023069c, 0x11111111)
+ memory_write(0xC02306a0, 0x11111111) # ;TXDLY DQS
+ memory_write(0xC02306a4, 0x66667777)
+ memory_write(0xC023082c, 0x11111111) # ;TXDLY DQ
+ memory_write(0xC0230830, 0x11111111) # ;TXDLY DQM
+ memory_write(0xC0230834, 0x66667777)
+ memory_write(0xC0230838, 0x66667777)
+ #D.S EAXI:0x1023092c %LE %LONG 0x22222222
+ #D.S EAXI:0x10230930 %LE %LONG 0x22222222
+ #D.S EAXI:0x10230934 %LE %LONG 0x66667777
+ #D.S EAXI:0x10230938 %LE %LONG 0x66667777
+ #D.S EAXI:0x10230a2c %LE %LONG 0x22222222
+ #D.S EAXI:0x10230a30 %LE %LONG 0x22222222
+ #D.S EAXI:0x10230a34 %LE %LONG 0x66667777
+ #D.S EAXI:0x10230a38 %LE %LONG 0x66667777
+ memory_write(0xC023081c, 0x00000000)
+ memory_write(0xC0230820, 0x00000000)
+ #D.S EAXI:0x1023091c %LE %LONG 0x00000000
+ #D.S EAXI:0x10230920 %LE %LONG 0x00000000
+ #D.S EAXI:0x10230a1c %LE %LONG 0x00000000
+ #D.S EAXI:0x10230a20 %LE %LONG 0x66666666
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ memory_write(0xC0230200, 0xf0100000) # ;[31]=DQSIEN MODE
+ memory_write(0xC0230048, 0x08000000)
+ memory_write(0xC0230678, 0xc0000000)
+ memory_write(0xC0230600, 0x09030b06)
+ memory_write(0xC0230604, 0x14090901)
+ memory_write(0xC0230608, 0x0c050201)
+ memory_write(0xC023060c, 0x00490019)
+ memory_write(0xC0230614, 0x01000606)
+ memory_write(0xC023061c, 0x02030408)
+ memory_write(0xC0230620, 0x02000400)
+ memory_write(0xC0230648, 0x9007320f)
+ memory_write(0xC0230644, 0x00000b0d) # ;DATLAT
+ memory_write(0xC0230000, 0x02111000) # ;[24]=LP2_EN , [25]=LP3_EN, [26]=LP4_EN
+ memory_write(0xC0230004, 0x20002000)
+ memory_write(0xC0230008, 0x81080000)
+ memory_write(0xC023000c, 0x0002cf13)
+ memory_write(0xC0230010, 0x00000080)
+ memory_write(0xC0230020, 0x00000009)
+ memory_write(0xC0230024, 0x80030000)
+ memory_write(0xC0230038, 0x80000106)
+ memory_write(0xC0230040, 0x3000000c)
+ memory_write(0xC023004c, 0x25714001)
+ memory_write(0xC0230064, 0x25b1f1cf) # ;REFRDIS=1
+ memory_write(0xC02300b0, 0x04300000)
+ memory_write(0xC0230200, 0xf0310000) # ;[31]=DQSIEN MODE
+ memory_write(0xC0230658, 0x21200001)
+ memory_write(0xC0230800, 0x00000002)
+ #D.S EAXI:0x10230900 %LE %LONG 0x00000002
+ #D.S EAXI:0x10230a00 %LE %LONG 0x00000002
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230824, 0x10101010) # ;GATE WINDOW unit:2T
+ memory_write(0xC0230828, 0x17171717)
+ #D.S EAXI:0x10230924 %LE %LONG 0x11111111
+ #D.S EAXI:0x10230928 %LE %LONG 0x42424242
+ #D.S EAXI:0x10230a24 %LE %LONG 0x32323232
+ #D.S EAXI:0x10230a28 %LE %LONG 0x06060606
+ #;D.S EAXI:0x10240a24 %LE %LONG 0x00000000; ;GATE WINDOW unit:2T
+ #;D.S EAXI:0x10240a28 %LE %LONG 0x53535353
+ #;D.S EAXI:0x10240b24 %LE %LONG 0x32323232
+ #;D.S EAXI:0x10240b28 %LE %LONG 0x06060606
+ #;D.S EAXI:0x10240c24 %LE %LONG 0x32323232
+ #;D.S EAXI:0x10240c28 %LE %LONG 0x06060606
+ # 33961 === over_write_setting_begin ===
+ # 33961 === over_write_setting_end ===
+ memory_write(0xC0230034, 0x00731010)
+ memory_write(0xC0230024, 0x80030050)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC023005c, 0x00003f00)
+ memory_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230060, 0x00000000)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC023005c, 0x00000aff)
+ memory_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230060, 0x00000000)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC023005c, 0x00000183)
+ memory_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230060, 0x00000000)
+ memory_write(0xC023005c, 0x00000206) # ;RL/WL
+ memory_write(0xC0230060, 0x00000001)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC0230060, 0x00000000)
+ memory_write(0xC0230028, 0x00000034)
+ memory_write(0xC023005c, 0x00000b03)
+ memory_write(0xC0230060, 0x00000001)
+
+ #=============================RANK1 MRW==================
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #D.S EAXI:0x1023005c %LE %LONG 0x01003f00
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000aff
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000183
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000206; ;RL/WL
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000000
+ #D.S EAXI:0x1023005c %LE %LONG 0x01000b03
+ #D.S EAXI:0x10230060 %LE %LONG 0x00000001
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #================== end RANK1 MRW =====================
+
+
+ memory_write(0xC0230060, 0x00000000)
+ memory_write(0xC0230024, 0x80030040)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ memory_write(0xC023005c, 0x00000400)
+
+
+
+ memory_write(0xC023064c, 0x00000005)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ memory_write(0xC023004c, 0x25774001)
+ memory_write(0xC0230034, 0x00731810)
+ memory_write(0xC0230024, 0x80030000)
+ memory_write(0xC0230004, 0x20082000)
+ memory_write(0xC0230058, 0x00000a56)
+
+ time.sleep(0.001)
+ memory_write(0xC0240060, 0x00000000)
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+
+ memory_write(0xC023064c, 0x00ff0005)
+ memory_write(0xC0230064, 0x25b1f1cf) # ;REFRDIS=1
+ memory_write(0xC0230610, 0x22653055)
+ memory_write(0xC023004c, 0x45774001)
+ memory_write(0xC0230048, 0x48000000)
+ memory_write(0xC023005c, 0x80000400)
+ memory_write(0xC0230038, 0xc0000107)
+ memory_write(0xC023020c, 0x00010002)
+ memory_write(0xC0230204, 0x00014e00)
+ memory_write(0xC0230094, 0x00100000)
+ memory_write(0xC0230098, 0x00004000)
+ memory_write(0xC023009c, 0x12010480)
+ # 54377 === DE initial sequence done ===
+
+ #selftest
+ #D.S EAXI:0x1023009C %LE %LONG 0x02010080
+ #D.S EAXI:0x10230094 %LE %LONG 0x00100000
+ #D.S EAXI:0x10230098 %LE %LONG 0x00004000
+ #D.S EAXI:0x1023009C %LE %LONG 0x82010080
+ #wait 1.ms
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+ #D.S EAXI:0x10240060 %LE %LONG 0x00000000
+
+ # restore md to ap write secure world register protection
+ memory_write(0xC001DB00, reg_bak_MAS_SEC_0) # MAS_SEC_0[16] = M16_SEC = 0
+ memory_write(0xC001DF00, reg_bak_APC_CON) # APC_CON[2] = DBG_MASK = 1
+
+ print("DRAM_INIT -> elapsed time: {:.3f}".format(time.time()-tim))
+
+def MD_Remap(adr=None):
+ """MD reamp config
+ [in] thread, codescape thread object
+ [in] adr, user specific remap address (ap infra memory map view, 32M alignment)
+ default: emi start address
+ """
+
+ inf_emi = 0x80000000 if memory_read(0xA000001C) < 0x08566094 else 0x40000000
+ print("MD_Remap(adr={:#x}) ...".format(inf_emi if adr == None else adr))
+ if adr == None:
+ inf_md = inf_emi
+ else:
+ assert (adr & 0x01FFFFFF) == 0
+ inf_md = adr
+ print("MD_Remap -> md:bank0=>ap:{:#x}, md:bank1=>ap:{:#x}, md:bank4=>ap:{:#x}".format(inf_md, inf_md+0x10000000, inf_emi))
+ # md remap bank 0
+ bnk = inf_md >> 25
+ memory_write(0xC0001300, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ memory_write(0xC0001304, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ memory_write(0xC0001308, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ memory_write(0xC000130c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+ # md remap bank 1
+ bnk = (inf_md+0x10000000) >> 25
+ memory_write(0xC0001310, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ memory_write(0xC0001314, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ memory_write(0xC0001318, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ memory_write(0xC000131c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+ # md remap bank 4
+ bnk = inf_emi >> 25
+ memory_write(0xC0001320, 0x00010001 | ((bnk+1) << 17) | ((bnk+0) << 1))
+ memory_write(0xC0001324, 0x00010001 | ((bnk+3) << 17) | ((bnk+2) << 1))
+ memory_write(0xC0001328, 0x00010001 | ((bnk+5) << 17) | ((bnk+4) << 1))
+ memory_write(0xC000132c, 0x00010001 | ((bnk+7) << 17) | ((bnk+6) << 1))
+
+def WDT_Disable():
+ """diable WDT function
+ [in] thread, codescape thread object
+ """
+ print("WDT disable ...")
+ mdrgu = 0xA00F0000 + 0x0100
+ aprgu = 0xC0007000
+ memory_write(mdrgu, (memory_read(mdrgu) & 0xFFFFFFFC) | 0x55000000)
+ memory_write(aprgu, (memory_read(aprgu) & 0xFFFFFFFE) | 0x22000000)
+
+if __name__ == "__main__":
+ switch_to_axi_mode()
+ WDT_Disable()
+ DRAM_INIT()
+ MD_Remap()
+ tEnd = time.time()
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/coretracer_load_dsp.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/coretracer_load_dsp.py
new file mode 100755
index 0000000..96ff456
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/coretracer_load_dsp.py
@@ -0,0 +1,147 @@
+#from imgtec import codescape
+import sys
+import time
+import os
+sys.path.append(os.path.dirname(os.path.realpath(__file__)))
+import gdb
+import binascii
+import Tkinter, tkFileDialog
+from TCF import Event, Result
+import TCF as client
+
+app = None
+dsp_header = 0x0
+dsp_magic = "4d4d4d01"
+
+TCF_HOST = 'localhost'
+TCF_PORT = 1534
+
+def get_tcf_port():
+ global TCF_PORT
+ gdb_cmd = 'show env tcfport'
+ res = gdb.execute(gdb_cmd, to_string=True)
+ TCF_PORT = int(res.split()[2], 0)
+ print "TCF_PORT = " + str(TCF_PORT)
+
+def switch_to_axi_mode():
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def switch_to_apb_mode():
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write off'
+ gdb.execute(gdb_cmd)
+
+def print_to_log(str):
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','log',str+'\n'])
+ tcf.close()
+
+# load dsp bin file
+def load_dsp_bin(dsp_path):
+ global dsp_header
+
+ time_str = time.time()
+ #print_to_log("=== Start to load dsp bin ===")
+ print_to_log("Dsp bin path: " + dsp_path)
+ if(os.path.exists(dsp_path) == False):
+ print_to_log( "DSP bin doesn't exist: %s" %(dsp_path))
+ print_to_log( "[Error] Load DSP bin failed")
+ return
+ else:
+ with open(dsp_path, "rb") as dsp_bin:
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print_to_log( "No header detected, continue")
+ else:
+ dsp_header = 0x200
+ dsp_bin.seek(dsp_header, os.SEEK_SET)
+ magic_word = dsp_bin.read(4)
+ if binascii.hexlify(magic_word) == dsp_magic:
+ print_to_log( "Header detected, skip first 512B")
+ else:
+ print_to_log( "DSP header detected at neither 0x0 nor 0x200")
+ print_to_log( "Please check the bin is legal!")
+ print_to_log( "[Error] Load DSP bin failed")
+ return
+ gdb_cmd='thread 1'
+ gdb.execute(gdb_cmd)
+ ## a) need parsing: 0x13a0000 <dsp_bin_ro>
+ ##symbol_name='&dsp_bin_ro'
+ ##dsp_addr = gdb.parse_and_eval(symbol_name)
+ ## b) need parsing: $3 = 0x13a0000
+ ##gdb_cmd='p/x &dsp_bin_ro'
+ ##dsp_addr = gdb.execute(gdb_cmd, False, True)
+ symbol_name='dsp_bin_ro'
+ dsp_addr = gdb.parse_and_eval(symbol_name)
+ dsp_addr = str(dsp_addr.address).split(" ")
+ dsp_addr = int(dsp_addr[0], 16) - dsp_header
+ #print_to_log( hex(dsp_addr) )
+ gdb_cmd = " ".join(['restore', dsp_path, 'binary', hex(dsp_addr), hex(dsp_header)])
+ #print_to_log( gdb_cmd)
+ switch_to_axi_mode()
+ print_to_log( "Load DSP bin ......................")
+ gdb.execute(gdb_cmd)
+ switch_to_apb_mode()
+ time_end = time.time()
+ print_to_log("loading dsp is done .... Elapsed time: {:.3f} sec".format(time_end-time_str))
+
+
+class gui_tk(Tkinter.Tk):
+ def __init__(self, parent):
+ Tkinter.Tk.__init__(self, parent)
+ elf_path = ""
+ dsp_path = ""
+ dsp_addr = ""
+ self.file_opt = options = {}
+ options['title'] = 'Choose a file'
+ self.parent = parent
+ self.initialize()
+
+ def initialize(self):
+ self.grid()
+
+ dsp_button = Tkinter.Button(self, text=u"Load DSP bin =>", command=self.dsp_OnButtonClick)
+ dsp_button.grid(column=0, row=4, sticky='W')
+
+ def dsp_OnButtonClick(self):
+ dsp_path = tkFileDialog.askopenfilename(**self.file_opt)
+ if len(dsp_path) > 0:
+ print_to_log( "You chose %s" % dsp_path)
+ load_dsp_bin(dsp_path)
+ self.quit()
+
+ def quit(self):
+ global app
+ print_to_log( "=== Close DSP Loader ===")
+ app.destroy()
+
+def load_dsp_gui():
+ print_to_log( "=== Start DSP Loader UI ===")
+ global app
+ app = gui_tk(None)
+ app.title('DSP Loader')
+ app.mainloop()
+
+def disable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','disable','["LoadDSP"]'])
+ tcf.close()
+
+def enable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','enable','["LoadDSP"]'])
+ tcf.close()
+
+if __name__ == "__main__":
+ get_tcf_port()
+ disable_button()
+ load_dsp_gui()
+ enable_button()
+
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/coretracer_misc.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/coretracer_misc.py
new file mode 100755
index 0000000..11b9be2
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/coretracer_misc.py
@@ -0,0 +1,70 @@
+import sys
+import time
+import os
+import gdb
+import ctypes
+
+dsp_bin_base = "0x0d500000"
+ramdisk_base = "0x0c500000"
+RAMDISK_SIZE = 0x1000
+EXCEPT_RET = 0xdeaddead
+
+def switch_to_axi_mode():
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def switch_to_apb_mode():
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write off'
+ gdb.execute(gdb_cmd)
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def get_symbol_addr(symbol_name):
+ res = -1
+ try:
+ res = gdb.parse_and_eval(symbol_name)
+ except:
+ return EXCEPT_RET
+
+ return str(res.address).split()[0]
+
+def clean_ram_disk_region():
+ global ramdisk_base
+
+ ram_disk_addr = get_symbol_addr('ram_disk')
+
+ if ram_disk_addr != EXCEPT_RET:
+ print("ram_disk = %s . clean 4K .." % ram_disk_addr)
+ switch_to_axi_mode()
+ for i in range(RAMDISK_SIZE/4):
+ memory_write(int(ram_disk_addr,0)+i*4,0)
+ switch_to_apb_mode()
+ ramdisk_base = ram_disk_addr
+ else:
+ print "There is no ram_disk symbol in this elf!"
+
+def clean_dsp_bin_magic():
+ global dsp_bin_base
+
+ magic_addr = get_symbol_addr('dsp_bin_ro')
+
+ if magic_addr != EXCEPT_RET:
+ print("dsp_bin_addr = %s . write the addr with 0 .." % magic_addr)
+ memory_write(magic_addr, 0)
+ dsp_bin_base = magic_addr
+ else:
+ print "There is no dsp_bin_ro symbol in this elf!"
+
+
+if __name__ == "__main__":
+ print "Check dsp bin magic .."
+ clean_dsp_bin_magic()
+ print "Check ramdisk 4k .."
+ clean_ram_disk_region()
+ print "=================== All process done. You can tigger cpu run or load DSP bin ==================="
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/coretracer_restore_callstack.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/coretracer_restore_callstack.py
new file mode 100755
index 0000000..ff9bcef
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/coretracer_restore_callstack.py
@@ -0,0 +1,188 @@
+import sys
+import time
+import os
+sys.path.append(os.path.dirname(os.path.realpath(__file__)))
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+import struct
+from TCF import Event, Result
+import TCF as client
+EXCEPT_RET = 0xdeaddead
+
+TCF_HOST = 'localhost'
+TCF_PORT = 1534
+
+CPU_CORE_NUM =4
+CPU_PER_CORE_VPE_NUM =3
+CPU_PER_CORE_TC_NUM =6
+
+CPUGPR_NAME = ['zero', 'at', 't4', 't5',
+ 'a0', 'a1', 'a2', 'a3',
+ 'a4', 'a5', 'a6', 'a7',
+ 't0', 't1', 't2', 't3',
+ 's0', 's1', 's2', 's3',
+ 's4', 's5', 's6', 's7',
+ 't8', 't9', 'k0', 'k1',
+ 'gp', 'sp', 'raw_fp', 'ra']
+
+OFFENDING_VPE_NONE = 0xffffffff
+
+def get_tcf_port():
+ global TCF_PORT
+ gdb_cmd = 'show env tcfport'
+ res = gdb.execute(gdb_cmd, to_string=True)
+ TCF_PORT = int(res.split()[2], 0)
+ print "TCF_PORT = " + str(TCF_PORT)
+
+def print_to_log(str):
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','log',str+'\n'])
+ tcf.close()
+
+def disable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','disable','["restoreCallStack"]'])
+ tcf.close()
+
+def enable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','enable','["restoreCallStack"]'])
+ tcf.close()
+
+def refresh_callstack_ui():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','refresh','debug'])
+ tcf.close()
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+
+ return int(mem_value.split()[2], 0)
+
+def register_read(reg):
+ gdb_cmd = 'info register '+ str(reg)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ return int(mem_value.split()[1], 0)
+
+def register_write(reg, set_value):
+ gdb_cmd = 'set $' + str(reg) + ' = ' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def get_symbol_addr(symbol_name):
+ res = -1
+ try:
+ res = gdb.parse_and_eval(symbol_name)
+ except:
+ return EXCEPT_RET
+
+ return str(res.address).split()[0]
+
+def get_variable_value(symbol_name):
+ mem_value = gdb.parse_and_eval(symbol_name)
+ return (mem_value)
+
+def find_offender():
+ print_to_log( "checking vpe status ..")
+ offending_core = OFFENDING_VPE_NONE
+ offending_vpe = OFFENDING_VPE_NONE
+ offending_tc = OFFENDING_VPE_NONE
+ try:
+ offending_core = get_variable_value('sst_offending_coreid')
+ offending_vpe = get_variable_value('sst_offending_vpeid')
+ offending_tc = get_variable_value('sst_offending_tcid')
+ except:
+ return [OFFENDING_VPE_NONE, OFFENDING_VPE_NONE, OFFENDING_VPE_NONE]
+
+ return [offending_core, offending_vpe, offending_tc]
+
+def find_thread_id(core_num, vpe_num, tc_num):
+ gdb_cmd = 'thread find Core {}/VPE {}/TC {}'.format(core_num, vpe_num, tc_num)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ print mem_value
+ return int(mem_value.split()[1], 0)
+
+def switch_thread(tid):
+ gdb_cmd = 'thread '+str(tid)
+ gdb.execute(gdb_cmd)
+
+def restore_thread_callstack(core, vpe, tc): # core0~3, vpe0~2, tc0~1
+ # switch thread
+ thread_id = find_thread_id(core, vpe, vpe*2 + tc)
+ switch_thread(thread_id)
+
+ #print_to_log( "CONT. VPE"+str(core*3+vpe) )
+ vpe_ex_tc = get_variable_value('ex_info[{}][0].tcid'.format(core*3+vpe)) # tc0~5
+
+ #print_to_log('CORE{}/vpe{}/tc{}'.format(core, vpe, tc))
+ if vpe_ex_tc%2 == tc :# offender tc will use ex_info to restore
+ #print_to_log("restore from ex_info_reg ..")
+ # restore GPR from variable ex_info_reg
+ base_addr = get_symbol_addr('ex_info[{}][0].SST_Exception_Regs.GPR'.format(core*3+vpe))
+ #print_to_log("ex_info.GPR base addr = {}".format(base_addr))
+ i=0
+ for reg_name in CPUGPR_NAME:
+ val = memory_read(int(base_addr,0) + i*4)
+ register_write(reg_name, val)
+ i+=1
+ else: # else we use interaptive_state
+ #print_to_log("restore from ex_interaptive_state ..")
+ # restore GPR from variable ex_interaptive_state
+ base_addr = get_symbol_addr('ex_interaptive_state.coreregs[{}].tcregs[{}].GPR'.format(core, tc))
+ i=0
+ for reg_name in CPUGPR_NAME:
+ val = memory_read(int(base_addr,0) + i*4)
+ register_write(reg_name, val)
+ i+=1
+
+ # restore EPC -> PC
+# epc_val = get_variable_value('ex_interaptive_state.coreregs[{}].vperegs[{}].EPC'.format(core, vpe))
+ epc_val = get_variable_value('ex_info[{}][0].SST_Exception_Regs.EPC'.format(core*3+vpe))
+ register_write("pc", epc_val)
+
+ # restore status -> status
+ status_val = get_variable_value('ex_info[{}][0].SST_Exception_Regs.status'.format(core*3+vpe))
+ register_write("status", epc_val)
+
+ return
+
+def restore_callstack(offender):
+ core_num = offender[0]
+ vpe_num = offender[1]%3 # VPE0~VPE2
+ tc_num = offender[2]%2 # TC0~TC1
+ print_to_log("============> Offender is CORE{} VPE{} TC{}".format(core_num, vpe_num, tc_num))
+
+ for core in range(CPU_CORE_NUM):
+ for vpe in range(CPU_PER_CORE_VPE_NUM):
+ print_to_log("Restore CORE{} VPE{} ..".format(core, vpe))
+ for tc in range(2):
+ #print_to_log("Restore CORE{} VPE{} TC{} ..".format(core, vpe, vpe*2 + tc))
+ restore_thread_callstack(core, vpe, tc)
+ refresh_callstack_ui()
+ print_to_log("=== restore call stack finish! ===")
+ return
+
+def main_func():
+ print_to_log("=== start to restore call stack! ===")
+ offender = find_offender()
+ if offender[0] == OFFENDING_VPE_NONE:
+ print_to_log( "This is no any exception happened. Restore abort!")
+ return
+ restore_callstack(offender)
+ return
+
+
+if __name__ == "__main__":
+ get_tcf_port()
+ disable_button()
+ main_func()
+ enable_button()
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/coretracer_swla.py b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/coretracer_swla.py
new file mode 100755
index 0000000..138ac69
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/coretracer_swla.py
@@ -0,0 +1,309 @@
+import sys
+import time
+import os
+sys.path.append(os.path.dirname(os.path.realpath(__file__)))
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+import struct
+from TCF import Event, Result
+import TCF as client
+
+CORE_NUM = 4
+CORE_TC_NUM = 6
+LAST_COUNT = 100
+
+EXCEPT_RET = 0xdeaddead
+
+TCF_HOST = 'localhost'
+TCF_PORT = 1534
+
+def get_tcf_port():
+ global TCF_PORT
+ gdb_cmd = 'show env tcfport'
+ res = gdb.execute(gdb_cmd, to_string=True)
+ TCF_PORT = int(res.split()[2], 0)
+ print "TCF_PORT = " + str(TCF_PORT)
+
+def print_to_log(str):
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','log',str+'\n'])
+ tcf.close()
+
+def dump_memory(start_addr, end_addr, filename):
+ gdb_cmd = 'dump binary memory '+str(filename)+' '+hex(start_addr)+' '+hex(end_addr)
+ gdb.execute(gdb_cmd)
+
+def switch_to_axi_mode():
+ gdb_cmd = 'monitor mips bus_read on'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write on'
+ gdb.execute(gdb_cmd)
+
+def switch_to_apb_mode():
+ gdb_cmd = 'monitor mips bus_read off'
+ gdb.execute(gdb_cmd)
+ gdb_cmd = 'monitor mips bus_write off'
+ gdb.execute(gdb_cmd)
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ #print "[DBG] "+ mem_value
+ return int(mem_value.split()[2], 0)
+
+
+def get_symbol_addr(symbol_name):
+ res = -1
+ try:
+ res = gdb.parse_and_eval(symbol_name)
+ except:
+ return EXCEPT_RET
+
+ return str(res.address).split()[0]
+
+def get_variable_value(symbol_name):
+ mem_value = gdb.parse_and_eval(symbol_name)
+ #print "[DBG] " + str(mem_value)
+ return (mem_value)
+
+WRAP_PATTERN = 0x50415257 # WRAP
+def isBufferWrap(f, total_size, entry_size):
+ seek_offset = total_size - entry_size
+ f.seek(seek_offset)
+ raw_dword = f.read(8)
+ word1, word2 = struct.unpack('II', raw_dword)
+ if word1 == WRAP_PATTERN and word2 == WRAP_PATTERN:
+ return False
+ else:
+ print "WRAP!!"
+ return True
+
+def find_first_idx_cus(f, total_size, entry_size, next_avail_idx):
+ avail_buffer_size = total_size - entry_size
+ if next_avail_idx - LAST_COUNT >= 0:
+ return next_avail_idx - LAST_COUNT
+ else:
+ if not isBufferWrap(f, total_size, entry_size):
+ return 0
+ else:
+ return (avail_buffer_size/entry_size) + (next_avail_idx - LAST_COUNT)
+
+def parse_swla_dump(file_path, entry_size, bin_size, next_avail_idx):
+ f = open(file_path, "rb")
+ #first_idx = find_first_idx(f, bin_size, entry_size, next_avail_idx)
+ first_idx = find_first_idx_cus(f, bin_size, entry_size, next_avail_idx)
+ f.seek(first_idx*entry_size)
+
+ cnt, wrap = 0, 0
+ tmp_list = []
+ for i in range(0, CORE_TC_NUM):
+ tmp_list.append([])
+
+ while True:
+ word = f.read(entry_size)
+ tmp_hash = {}
+ context, frc, raw_coretc = struct.unpack('III', word) #################################### need to modify
+ tmp_hash['frc'], tc, core = hex(frc), raw_coretc >> 8, raw_coretc & 0xff
+
+ if context&0xf0==0xe0:
+ tmp_hash['context'] = "CUS"
+ elif context==0xAAAAAAAA:
+ #print "IRQEND!"
+ tmp_hash['context'] = "IRQEND"
+ tmp_list[tc].append(tmp_hash.copy())
+ elif context>>16==0xAAAA:
+ irq_id = int(context & 0xFFFF)
+ tmp_hash['context'] = "IRQ"+str(irq_id)
+ tmp_list[tc].append(tmp_hash.copy())
+ #print tmp_hash['context']
+ else:
+ char1, char2, char3, char4 = (context&0xff), (context>>8&0xff), (context>>16&0xff), (context>>24&0xff)
+ if char4==0:
+ if char3==0:
+ context_name = chr(char1) + chr(char2)
+ else:
+ context_name = chr(char1) + chr(char2) + chr(char3)
+ else:
+ context_name = chr(char1) + chr(char2) + chr(char3) + chr(char4)
+ tmp_hash['context'] = context_name
+ tmp_list[tc].append(tmp_hash.copy())
+
+ #print str(tc)+", "+tmp_hash['context']+", "+hex(frc)
+
+ cnt +=1
+
+ # WRAP condition
+ if f.tell()==bin_size and wrap==0 :
+ f.seek(0)
+ wrap=1
+ print "CORE"+str(file_idx)+" swla buffer WRAP"
+ #print "seek:" + hex(f.tell()) + " cnt*entry_size = "+hex(cnt*entry_size)
+
+ # check END
+ if f.tell()==next_avail_idx*entry_size:
+ #print "END! cnt="+str(cnt)
+ break
+
+ f.close()
+ return tmp_list
+
+def swla_parse(tc_lvl_list):
+ context_list = {}
+
+ irq_queue = []
+ pre_task, pre_frc = 0, 0
+ for context in tc_lvl_list:
+ context_name = context['context']
+ context_start_frc = context['frc']
+ target_context=""
+ if pre_task != 0:
+ # sys_exec case
+ if pre_task=="IRQEND" and len(irq_queue)==0:
+ target_context = "sys_exec"
+ if not target_context in context_list:
+ context_list[target_context] = []
+ context_list[target_context].append([pre_frc, context_start_frc])
+ # irqend case
+ elif pre_task=="IRQEND":
+ last_irq = irq_queue.pop()
+ target_context = last_irq
+ if not target_context in context_list:
+ context_list[target_context] = []
+ context_list[target_context].append([pre_frc, context_start_frc])
+ else:
+ if "IRQ" in context_name and context_name!="IRQEND": # irq
+ irq_queue.append(context_name)
+
+ target_context = pre_task
+ if not target_context in context_list:
+ context_list[target_context] = []
+ context_list[target_context].append([pre_frc, context_start_frc])
+ if target_context=="IRQEND":
+ print "????"
+ pre_task, pre_frc = context_name, context_start_frc
+
+ #print context_list
+ return context_list.copy()
+
+def main_func():
+ print_to_log("=== Start to parse SWLA information ===")
+ """
+ get swla buffer base address
+ """
+ res = get_symbol_addr('SysProfilerBufferAddress')
+ if res==EXCEPT_RET:
+ print_to_log( "[ERR] this elf does not support SWLA!")
+ return
+
+ swla_buffer_base_addr = int(get_symbol_addr('SysProfilerBufferAddress'), 16)
+ swla_buffer_addr_ary = []
+ for i in range(0, CORE_NUM):
+ swla_buffer_addr_ary.append(memory_read(swla_buffer_base_addr+i*4))
+
+ """
+ get swla entry size
+ """
+ swla_entry_size = get_variable_value("SA_LoggingNodeSize[0]") ##########################################
+ #print "SWLA Entry Size: "+str(swla_entry_size)+" B"
+
+ """
+ get swla next available entry index
+ """
+ swla_buffer_next_avail_index = []
+ for i in range(0, CORE_NUM):
+ swla_buffer_next_avail_index.append(get_variable_value("SA_LoggingOffset["+str(i)+"]"))
+
+ """
+ get swla buffer total size
+ """
+ tmp = get_variable_value("SA_LoggingStop[0]")
+ swla_size = int(str(tmp).split()[0], 0) - swla_buffer_addr_ary[0]
+ print_to_log( "SWLA Buffer Size: "+ hex(swla_size)+" B")
+
+ """
+ dump each core's swla raw buffer
+ """
+ swla_dump_file = []
+
+ switch_to_axi_mode() # switch to AXI mode to speed up (axi mode will not go through CPU -> MUST used in non-cache region)
+ for i in range(0, CORE_NUM):
+ print_to_log( "Dump core"+str(i)+" swla raw buffer ..")
+ s_t = time.time()
+ filename = "core"+str(i)+"_raw_swla.bin"
+ dump_memory(swla_buffer_addr_ary[i], swla_buffer_addr_ary[i]+swla_size, filename)
+ swla_dump_file.append(filename)
+ e_t = time.time()
+ print_to_log("Elapsed time: {:.3f} sec".format(e_t-s_t))
+ switch_to_apb_mode() # switch back
+
+ print "All swla raw dump finish!!"
+
+ #exit()
+ """
+ parse swla raw
+ """
+ output = open("final_swla.log", "w")
+ output.write('met-info [000] 0.0: ms_ud_timeline_header: {"resource": [{"entity-attr": ["Interrupt"], "name": "default"}], "name": "MCU Timeline"}'+"\n")
+ output.write('met-info [000] 0.0: ms_ud_timeline_description: MCU Timeline:HAS_CHILD_TRACE=Y;COPY_TO_TOP=Y'+"\n")
+
+ core_num=0
+ log_index=1
+ for file in swla_dump_file:
+ print_to_log( "Parsing "+file+" ...")
+ s_t = time.time()
+ tc_list = parse_swla_dump(file, swla_entry_size, swla_size, swla_buffer_next_avail_index[core_num])
+ #print tc_list
+ e_t = time.time()
+
+ print_to_log("Elapsed time: {:.3f} sec".format(e_t-s_t))
+ print_to_log( "start to write to final_swla ..")
+ tc_num = 0
+ for tc_content in tc_list:
+ #print tc_content
+ context_list = swla_parse(tc_content)
+ #print context_list
+ vpe_num = tc_num/2
+ for context_name, period_list in context_list.items():
+ isIRQ = "NO"
+ if "IRQ" in context_name:
+ isIRQ = "YES"
+ for period in period_list:
+ #print period
+ start_frc, end_frc = int(period[0],0)*1.0/1000000, int(period[1],0)*1.0/1000000
+ #print start_frc
+ out_str1 = "NULL-0 [000] {:.10f}: MCU Timeline: ".format(start_frc)
+ out_str2 = "'CORE{}%%VPE{}%%TC{}%%{}', 'e': [['{}']], 't': ['{:.10f}', '{:.10f}']".format(core_num, vpe_num, tc_num/2, context_name, isIRQ, start_frc, end_frc)
+ output.write(out_str1+"{'r': "+out_str2+"}\n")
+ log_index+=1
+ tc_num+=1
+
+ core_num+=1
+ #break
+ output.close()
+ print_to_log( '=== SWLA parse finish! Please use MET font-end to open final_swla.log for SWLA view ===')
+ print_to_log( '=== The output filename is "final_swla.log" in the same folder of your elf file ===')
+ return
+
+def disable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','disable','["SWLA"]'])
+ tcf.close()
+
+def enable_button():
+ tcf = client.TCFThread(TCF_HOST, int(TCF_PORT))
+ tcf.start()
+ tcf.send(['E','UI','toolbar','enable','["SWLA"]'])
+ tcf.close()
+
+if __name__ == "__main__":
+ get_tcf_port()
+ disable_button()
+ main_func()
+ enable_button()
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/prepare_mode.launch b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/prepare_mode.launch
new file mode 100755
index 0000000..2b67fdb
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/ChipDependent/PETRUS/coretracer/prepare_mode.launch
@@ -0,0 +1,64 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.mediatek.ide.launch.gdbjtag.launchConfigurationType">
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.BREAKPOINT_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.core.EXPRESSION_LIST" value="[]"/>
+<stringAttribute key="com.mediatek.ide.dsf.gdb.ui.focus_threads" value=""/>
+<stringAttribute key="com.mediatek.ide.dsf.mvpu.dbg_file" value=""/>
+<stringAttribute key="com.mediatek.ide.dsf.mvpu.pattern_file" value=""/>
+<stringAttribute key="com.mediatek.ide.util.PROGRAM_NAME" value=""/>
+<stringAttribute key="com.mediatek.ide.util.actionAwarenessConfiguration" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.autoTerminate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.cache.FilePath" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.cache.gdbIndexElf" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.connection" value="com.mediatek.ide.util.LocalTarget"/>
+<stringAttribute key="com.mediatek.ide.util.connectorArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.debuggerIpAddress" value="localhost"/>
+<intAttribute key="com.mediatek.ide.util.debuggerPortNumber" value="3333"/>
+<booleanAttribute key="com.mediatek.ide.util.doReset" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.gdbArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.imageOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.initCommands" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.loadImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.loadSymbols" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgram" value="osawareness.exe"/>
+<stringAttribute key="com.mediatek.ide.util.osAwarenessProgramArguments" value=""/>
+<stringAttribute key="com.mediatek.ide.util.pcRegister" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileAccumulativeMode" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.profileDisableValue" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.profileEnable" value="true"/>
+<stringAttribute key="com.mediatek.ide.util.profileEnableValue" value=""/>
+<stringAttribute key="com.mediatek.ide.util.profileRawData" value="./profile_data"/>
+<stringAttribute key="com.mediatek.ide.util.profileType" value="Profile.Address"/>
+<stringAttribute key="com.mediatek.ide.util.runCommands" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.setPcRegister" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setResume" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.setStopAt" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.stopAt" value=""/>
+<stringAttribute key="com.mediatek.ide.util.substitute_path" value=""/>
+<booleanAttribute key="com.mediatek.ide.util.substitute_path_no_translate" value="false"/>
+<stringAttribute key="com.mediatek.ide.util.symbolsFileName" value=""/>
+<stringAttribute key="com.mediatek.ide.util.symbolsOffset" value=""/>
+<stringAttribute key="com.mediatek.ide.util.target" value="Prepare"/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.args" value="-f board/mips/debug_port_swd.cfg -c "adapter_khz 3000""/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.cmds" value=""/>
+<stringAttribute key="com.mediatek.ide.util.targetopt.widget.args" value="{"Clock_3000":"3000"}"/>
+<booleanAttribute key="com.mediatek.ide.util.useActionAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForImage" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useFileForSymbols" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useOsAwareness" value="false"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="com.mediatek.ide.util.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
+<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
+<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="attach"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value=""/>
+<booleanAttribute key="org.eclipse.debug.core.capture_output" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_OUTPUT_ON" value="true"/>
+<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="false"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+<stringAttribute key="saved_expressions<seperator>Unknown<seperator>APB" value="0xa0638000,0xa0310000"/>
+<stringAttribute key="saved_expressions<seperator>Unknown<seperator>AXI" value="0xa0020000,0xa0630000,0xa0638000,0xa0291e50"/>
+</launchConfiguration>
diff --git a/mcu/tools/DebuggingSuite/Scripts/Gen93_load_elf_only_to_t32.cmm b/mcu/tools/DebuggingSuite/Scripts/Gen93_load_elf_only_to_t32.cmm
new file mode 100644
index 0000000..051fbd9
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/Gen93_load_elf_only_to_t32.cmm
@@ -0,0 +1,53 @@
+system.down
+system.cpu MIPSinterAptiv
+SYSTEM.OPTION.ENDIANESS LITTLE
+SYStem.CONFIG.BaseCoreNumber 2.
+SYStem.CONFIG.CoreNumber 4.
+CORE.NUMber 4.
+
+system.config core 4
+system.config.core 1 1
+system.config.core 2 1
+system.config.core 3 2
+system.config.core 4 2
+
+system.up
+
+&SOURCE_STRING=""
+&ELF_STRING=""
+
+DIALOG
+(
+ HEADER "Download ELF"
+ POS 1. 1. 50. ,
+ TMP: TEXT "ELF-file"
+ POS 1. 2. 50. ,
+ ELF: EDIT "" ""
+ POS 52. 2. 10. ,
+ BUTTON "[:edit]Browse..."
+ (
+ DIALOG.SetFile ELF ~~\*.elf
+ )
+ POS 1. 4. 50. ,
+ TMP2: TEXT "Source path (optional)"
+ POS 1. 5. 50. ,
+ SRC: EDIT "" ""
+ POS 52. 5. 10. ,
+ BUTTON "[:edit]Browse..."
+ (
+ DIALOG.SetDIR SRC ~~\*
+ )
+
+ POS 10. 7. 5. ,
+ DEFBUTTON "OK" "CONTinue"
+)
+STOP
+&SOURCE_STRING=DIALOG.STring(SRC)
+&ELF_STRING=DIALOG.STring(ELF)
+DIALOG.END
+;ENDDO
+
+PRINT "Loading elf-file... "
+B::D.LOAD.elf &ELF_STRING /RELPATH /GNU /DWARF2 /CODESEC /PATH "&SOURCE_STRING"
+
+WINCLEAR
diff --git a/mcu/tools/DebuggingSuite/Scripts/MIPS_MPU_Viewer.cmm b/mcu/tools/DebuggingSuite/Scripts/MIPS_MPU_Viewer.cmm
new file mode 100755
index 0000000..fb1e06b
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/MIPS_MPU_Viewer.cmm
@@ -0,0 +1,338 @@
+;*****************************************************************************
+; Copyright Statement:
+; --------------------
+; This software is protected by Copyright and the information contained
+; herein is confidential. The software may not be copied and the information
+; contained herein may not be used or disclosed except with the written
+; permission of MediaTek Inc. (C) 2016
+;
+;*****************************************************************************
+;
+;*****************************************************************************
+;
+; Filename:
+; ---------
+; MIPS_MPU_Viewer.cmm (v.1.0)
+;
+; Project:
+; --------
+; MT6292
+;
+; Description:
+; ------------
+; This file generates human readable memory map from MPU tables
+;
+; Author:
+; -------
+; Jari Manninen (mtk09391)
+;
+;============================================================================
+; HISTORY
+; Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+;------------------------------------------------------------------------------
+; * $Revision$
+; * $Modtime$
+; * $Log$
+; *
+; * 05 17 2017 hw.jheng
+; * [MOLY00250340] [93] MIPS_MPU_Viewer.cmm update
+; *
+; * 09 02 2017 jari.manninen
+; * Initial Version
+; * Inherited MIP_MMU_View.cmm functionality to a new MPU parser.
+;------------------------------------------------------------------------------
+; Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+;============================================================================
+
+ AREA.Create mpu_area 100. 70.
+ WINPOS , , 100. 50.
+
+ DIALOG.AREA mpu_area
+ (
+ HEADER "DIALOG.AREA MPU Viewer"
+
+ POS 1. 0. 82.
+ LINE "CORE Options"
+
+ POS 0.25 1. 11. 1.
+ BUTTON "CORE 0"
+ (
+ LOCAL &tmp
+ AREA.Select mpu_area
+ AREA.CLEAR mpu_area
+ &CORE_ID=0
+ &tmp=FORMAT.DECIMAL(1,&CORE_ID)
+ DIALOG.SET LINENUM "MPU Table for CORE: &tmp"
+ ; enable clean button
+ DIALOG.Enable BTN_CLEAN
+ GOSUB parse
+ )
+ POS 12.25 1. 11. 1.
+ BUTTON "CORE 1"
+ (
+ LOCAL &tmp
+ AREA.Select mpu_area
+ AREA.CLEAR mpu_area
+ &CORE_ID=1
+ &tmp=FORMAT.DECIMAL(1,&CORE_ID)
+ DIALOG.SET LINENUM "MPU Table for CORE: &tmp"
+ ; enable clean button
+ DIALOG.Enable BTN_CLEAN
+ GOSUB parse
+ )
+
+ POS 24.25 1. 11. 1.
+ BUTTON "Both"
+ (
+ AREA.Select mpu_area
+ AREA.CLEAR mpu_area
+ &CORE_ID=2
+ DIALOG.SET LINENUM "MPU Table for both CORE's"
+ ; enable clean button
+ DIALOG.Enable BTN_CLEAN
+ GOSUB parse
+ )
+
+ POS 63. 1. 11. 1.
+BTN_CLEAN: button "Reset"
+ (
+ AREA.CLEAR mpu_area
+ DIALOG.set LINENUM "Select the CORE from above buttons"
+ ; disable clean button
+ DIALOG.Disable BTN_CLEAN
+ )
+
+ ; close button
+ POS 74. 1. 11. 1.
+ BUTTON "Close" "goto closeDialog"
+
+ ; handle [X] and Escape
+ CLOSE "goto closeDialog"
+
+ POS 2. 2. 20. 1.
+LINENUM: dyntext "Select the CORE from above buttons"
+
+ )
+
+;initialy disable clean button
+ DIALOG.DISABLE BTN_CLEAN
+ STOP
+
+;common jumplabel for closing the dialog and ending script
+closeDialog:
+ DIALOG.END
+ ENDDO
+
+parse:
+ LOCAL &core
+ &core=FORMAT.DECIMAL(1,&CORE_ID)
+ &CORE_ID=0
+
+ IF &core==0
+ (
+ PRINT "MPU Base Segments for CORE 0"
+ PRINT "======================================================================"
+ GOSUB parseBaseSegments 0
+ PRINT " "
+
+ PRINT "MPU Table for CORE 0"
+ PRINT "======================================================================"
+ GOSUB parseCore 0
+ )
+ IF &core==1
+ (
+ PRINT "MPU Base Segments for CORE 1"
+ PRINT "======================================================================"
+ GOSUB parseBaseSegments 1
+ PRINT " "
+
+ PRINT "MPU Table for CORE 1"
+ PRINT "======================================================================"
+ GOSUB parseCore 1
+ )
+ IF &core==2
+ (
+ PRINT "MPU Base Segments for CORE 0"
+ PRINT "======================================================================"
+ GOSUB parseBaseSegments 0
+ PRINT " "
+
+ PRINT "MPU Table for CORE 0"
+ PRINT "======================================================================"
+ GOSUB parseCore 0
+ PRINT " "
+
+ PRINT "MPU Base Segments for CORE 1"
+ PRINT "======================================================================"
+ GOSUB parseBaseSegments 1
+ PRINT " "
+
+ PRINT "MPU Table for CORE 1"
+ PRINT "======================================================================"
+ GOSUB parseCore 1
+ )
+
+ PRINT "======================================================================"
+ RETURN
+
+parseBaseSegments:
+ ENTRY &core_index
+ LOCAL &loop_count
+ LOCAL &index
+ LOCAL &enable
+ LOCAL &start_addr
+ LOCAL &size
+ LOCAL &count
+ LOCAL &RI
+ LOCAL &WI
+ LOCAL &XI
+ LOCAL &CCA
+ &index=0
+ &loop_count=10
+
+ WHILE &index<&loop_count
+ (
+ &ATTRIBUTE_STRING=""
+
+ &start_addr=10000000*&index
+ GOSUB parseStartAddr &start_addr
+
+ &size=1C
+ &count=1
+ GOSUB parseEndAddr &start_addr &size &count
+
+ &RI=v.value(IA_MPU_SETTING_CORE_EX[&core_index].segment_control[&index].RI)
+ &WI=v.value(IA_MPU_SETTING_CORE_EX[&core_index].segment_control[&index].WI)
+ &XI=v.value(IA_MPU_SETTING_CORE_EX[&core_index].segment_control[&index].XI)
+ &CCA=v.value(IA_MPU_SETTING_CORE_EX[&core_index].segment_control[&index].CCA)
+
+ GOSUB parseConfig &RI &WI &XI &CCA
+
+ PRINT FORMAT.Decimal(2.,&index) "&ATTRIBUTE_STRING"
+
+ &index=&index+1
+ )
+ RETURN
+parseCore:
+ ENTRY &core_index
+ LOCAL &loop_count
+ LOCAL &index
+ LOCAL &enable
+ LOCAL &start_addr
+ LOCAL &size
+ LOCAL &count
+ LOCAL &RI
+ LOCAL &WI
+ LOCAL &XI
+ LOCAL &CCA
+ &index=0
+ &loop_count=18
+ &ATTRIBUTE_STRING=""
+
+ WHILE &index<&loop_count
+ (
+ &enable=v.value(IA_MPU_SETTING_CORE_EX[&core_index].region[&index].Region_Enable)
+
+ IF &enable!=0
+ (
+ &ATTRIBUTE_STRING=""
+
+ &start_addr=v.value(IA_MPU_SETTING_CORE_EX[&core_index].region[&index].Region_Base_Address)
+ GOSUB parseStartAddr &start_addr
+
+ &size=v.value(IA_MPU_SETTING_CORE_EX[&core_index].region[&index].SubRegion_Size)
+ &count=v.value(IA_MPU_SETTING_CORE_EX[&core_index].region[&index].SubRegion_Count)+1
+ GOSUB parseEndAddr &start_addr &size &count
+
+ &RI=v.value(IA_MPU_SETTING_CORE_EX[&core_index].region[&index].RI)
+ &WI=v.value(IA_MPU_SETTING_CORE_EX[&core_index].region[&index].WI)
+ &XI=v.value(IA_MPU_SETTING_CORE_EX[&core_index].region[&index].XI)
+ &CCA=v.value(IA_MPU_SETTING_CORE_EX[&core_index].region[&index].CCA)
+
+ GOSUB parseConfig &RI &WI &XI &CCA
+
+ PRINT FORMAT.Decimal(2.,&index) "&ATTRIBUTE_STRING"
+
+ )
+ &index=&index+1
+ )
+ RETURN
+
+parseStartAddr:
+ ENTRY &saddr
+ &ATTRIBUTE_STRING="&ATTRIBUTE_STRING"+" Address:"+"0x"+FORMAT.Hex(8.,&saddr)+"--"
+ RETURN
+
+parseEndAddr:
+ ENTRY &addr ®size ®Count
+ LOCAL &loop_count
+ LOCAL &index
+ LOCAL &mpler
+
+ &loop_count=®size-5
+ &index=0
+ &mpler=1
+
+ WHILE &index<&loop_count
+ (
+ &mpler=&mpler*2
+ &index=&index+1
+ )
+ &mpler=&mpler*20
+ &mpler=&mpler*®Count
+
+ &addr=&addr+&mpler-1
+ &ATTRIBUTE_STRING="&ATTRIBUTE_STRING"+"0x"+FORMAT.Hex(8.,&addr)
+ RETURN
+
+parseConfig:
+ ENTRY &ri &wi &xi &cca
+ IF &cca==2
+ (
+ &ATTRIBUTE_STRING="&ATTRIBUTE_STRING"+" UC "
+ )
+ IF &cca==3
+ (
+ &ATTRIBUTE_STRING="&ATTRIBUTE_STRING"+" WB "
+ )
+ IF &cca==4
+ (
+ &ATTRIBUTE_STRING="&ATTRIBUTE_STRING"+" CWBE"
+ )
+ IF &cca==5
+ (
+ &ATTRIBUTE_STRING="&ATTRIBUTE_STRING"+" CWB "
+ )
+ IF &cca==7
+ (
+ &ATTRIBUTE_STRING="&ATTRIBUTE_STRING"+" UCA "
+ )
+
+ IF &ri==1
+ (
+ &ATTRIBUTE_STRING="&ATTRIBUTE_STRING"+" READ INHIBIT"
+ )
+ ELSE
+ (
+ &ATTRIBUTE_STRING="&ATTRIBUTE_STRING"+" READABLE "
+ )
+
+ IF &wi==1
+ (
+ &ATTRIBUTE_STRING="&ATTRIBUTE_STRING"+" WRITE INHIBIT"
+ )
+ ELSE
+ (
+ &ATTRIBUTE_STRING="&ATTRIBUTE_STRING"+" WRITABLE "
+ )
+
+ IF &xi==1
+ (
+ &ATTRIBUTE_STRING="&ATTRIBUTE_STRING"+" EXE INHIBIT"
+ )
+ ELSE
+ (
+ &ATTRIBUTE_STRING="&ATTRIBUTE_STRING"+" EXECUTABLE "
+ )
+
+ RETURN
diff --git a/mcu/tools/DebuggingSuite/Scripts/dsp_debug_info_Codescape.py b/mcu/tools/DebuggingSuite/Scripts/dsp_debug_info_Codescape.py
new file mode 100644
index 0000000..89715ad
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/dsp_debug_info_Codescape.py
@@ -0,0 +1,321 @@
+################################################################################
+# DSP Debug info script
+# Version 0.5(Beta)
+# - Support parsing uSIP0(inner, brp), uSIP1(speech, fec) and RAKE, scq exception flow is TBD.
+################################################################################
+
+from imgtec import codescape
+from os.path import getsize as get_file_size
+from itertools import chain as list_concat
+from time import sleep as sleep_sec
+import re
+import copy
+
+################################################################################
+# Init
+################################################################################
+print '\n Stopping all threads...'
+da = codescape.GetFirstProbe()
+for idx in reversed(range(2)):
+ da.cores[idx].StopAll(False)
+thread = da.cores[0].hwthreads[0]
+
+################################################################################
+# Entry point
+################################################################################
+
+def get_string(addr):
+ v = thread.memory.ReadString(get_int(addr), 0x40)
+ return v
+
+def get_int(addr):
+ v = int(thread.memory.Read(addr))
+ return v
+
+def get_hex(addr):
+ v = int(thread.memory.Read(addr))
+ return hex(v)
+
+def get_symbol_address(symbol_name):
+ try:
+ sym_addr = thread.GetSymbol(symbol_name).location
+# print "symbol: '" + symbol_name + "' address = " + sym_addr
+ except:
+ print "There is no exception info symbol " + symbol_name
+ return None
+ return sym_addr
+
+def get_symbol_hex_value(symbol_name):
+ try:
+ sym_addr = get_symbol_address(symbol_name)
+ sym_value = get_hex(sym_addr)
+# print "symbol: '" + symbol_name + "' value = " + str(sym_value)
+ return sym_value
+ except:
+ print "There is no exception info symbol " + symbol_name
+ return None
+
+def usip_ex_main():
+ for usip in range(2):
+ for th in range(2):
+ print '---- usip' + str(usip) + ' th' + str(th) + ' ----'
+
+ usip_thread_idx = usip*2 + th
+ sym_name = 'dsp_ex_full_log.usip_ex_type['+str(usip_thread_idx)+']'
+ usip_ex_type_ptr = get_symbol_address(sym_name)
+ usip_ex_type_address = get_int(usip_ex_type_ptr)
+# print ("usip_ex_type address= "+str(hex(usip_ex_type_address)))
+ ex_type = get_int(usip_ex_type_address)
+ print('ex_type: ' + sym_name + ' = ' + str(ex_type))
+ if ex_type == 0:
+ print 'Core not active or exception flow not finished'
+ continue
+
+ if ex_type == 1 or ex_type == 2:
+ assert_param = 'dsp_ex_full_log.usip_ex_log_ptr['+str(usip_thread_idx)+']->ex_params.assert_param.'
+ expr = get_string(get_symbol_address(assert_param+'expr'))
+ file = get_string(get_symbol_address(assert_param+'file'))
+ line = get_symbol_hex_value(assert_param+'line')
+ code1 = get_symbol_hex_value(assert_param+'code[0]')
+ code2 = get_symbol_hex_value(assert_param+'code[1]')
+ code3 = get_symbol_hex_value(assert_param+'code[2]')
+ thread_name = get_string(get_symbol_address('dsp_ex_full_log.usip_ex_log_ptr['+str(usip_thread_idx)+']->ex_thread_name'))
+ print 'Thread name ' + thread_name
+ print 'Assertion at ' + file + ' line ' + line
+ print 'expr ' + expr
+ print 'code1 ' + code1
+ print 'code2 ' + code2
+ print 'code3 ' + code3
+
+ elif ex_type == 3:
+ fatal_error_param = 'dsp_ex_full_log.usip_ex_log_ptr['+str(usip_thread_idx)+']->ex_params.fatal_error_param.'
+ code1 = get_symbol_hex_value(fatal_error_param+'code1')
+ code2 = get_symbol_hex_value(fatal_error_param+'code2')
+ ifabtpc = get_symbol_hex_value(fatal_error_param+'ifabtpc')
+ ifabtcau = get_symbol_hex_value(fatal_error_param+'ifabtcau')
+ daabtcau = get_symbol_hex_value(fatal_error_param+'daabtcau')
+ daabtpc = get_symbol_hex_value(fatal_error_param+'daabtpc')
+ daabtad = get_symbol_hex_value(fatal_error_param+'daabtad')
+ daabtsp = get_symbol_hex_value(fatal_error_param+'daabtsp')
+ thread_name = get_string(get_symbol_address('dsp_ex_full_log.usip_ex_log_ptr['+str(usip_thread_idx)+']->ex_thread_name'))
+ print 'Fatal error'
+ print 'Thread name ' + thread_name
+ print 'code1 ' + code1
+ print 'code2 ' + code2
+ print 'ifabtpc ' + ifabtpc
+ print 'ifabtcau ' + ifabtcau
+ print 'daabtcau ' + daabtcau
+ print 'daabtpc ' + daabtpc
+ print 'daabtad ' + daabtad
+ print 'daabtsp ' + daabtsp
+
+ elif ex_type == 4:
+ print 'CTI triggered by other core'
+
+ else:
+ print 'Unknown status'
+'''
+def get_scq_usif_info_base(scq16):
+ scq16_info = copy.deepcopy(usif_info_offset)
+ iterate_all_item(scq16_info, scq16_usif_info_base[scq16])
+ return scq16_info
+'''
+def scq16_ex_main():
+ for scq16 in range(4):
+ print '---- scq16 ' + str(scq16) + ' ----'
+ sym_name = 'dsp_ex_full_log.scq16_ex_type['+str(scq16)+']'
+ scq16_ex_type_address = get_symbol_hex_value(sym_name)
+# print ("scq16_ex_type address= "+str(scq16_ex_type_address))
+ ex_type = get_int(scq16_ex_type_address)
+ print('ex_type: ' + sym_name + ' = ' + str(ex_type))
+ if ex_type == 0:
+ print 'Core not active or exception flow not finished'
+ continue
+
+# print 'ex_type: ' + str(ex_type)
+ if ex_type == 1 or ex_type == 2:
+ assert_param = '(*dsp_ex_full_log.scq16_ex_log_dptr['+str(scq16)+'])->ex_params.assert_param.'
+ expr = get_string(get_symbol_address(assert_param+'expr'))
+ file = get_string(get_symbol_address(assert_param+'file'))
+ line = get_symbol_hex_value(assert_param+'line')
+ code1 = get_symbol_hex_value(assert_param+'code[0]')
+ code2 = get_symbol_hex_value(assert_param+'code[1]')
+ code3 = get_symbol_hex_value(assert_param+'code[2]')
+ print 'Assertion at ' + file + ' line ' + line
+ print 'expr ' + expr
+ print 'code1 ' + code1
+ print 'code2 ' + code2
+ print 'code3 ' + code3
+
+ elif ex_type == 3:
+ fatal_error_param = '(*dsp_ex_full_log.scq16_ex_log_dptr['+str(scq16)+'])->ex_params.fatal_error_param.'
+ code1 = get_symbol_hex_value(fatal_error_param+'code[0]')
+ code2 = get_symbol_hex_value(fatal_error_param+'code[1]')
+ ifabtpc = get_symbol_hex_value(fatal_error_param+'ifabtpc')
+ ifabtcau = get_symbol_hex_value(fatal_error_param+'ifabtcau')
+ daabtcau = get_symbol_hex_value(fatal_error_param+'daabtcau')
+ daabtpc = get_symbol_hex_value(fatal_error_param+'daabtpc')
+ daabtad = get_symbol_hex_value(fatal_error_param+'daabtad')
+ daabtad1 = get_symbol_hex_value(fatal_error_param+'daabtad1')
+ daabtsp = get_symbol_hex_value(fatal_error_param+'daabtsp')
+ print 'Fatal error'
+ print 'code1 ' + code1
+ print 'code2 ' + code2
+ print 'ifabtpc ' + ifabtpc
+ print 'ifabtcau ' + ifabtcau
+ print 'daabtcau ' + daabtcau
+ print 'daabtpc ' + daabtpc
+ print 'daabtad ' + daabtad
+ print 'daabtad1 ' + daabtad1
+ print 'daabtsp ' + daabtsp
+
+ elif ex_type == 4:
+ print 'CTI triggered by other core'
+
+ else:
+ print 'Unknown status'
+
+def get_name_string(addr, length):
+
+ file_name = ""
+ for offset in xrange(length):
+ digit = get_int(addr + offset*0x4)
+ if not digit:
+ break
+ file_name += format(digit, "x").decode("hex")[::-1]
+ return file_name
+
+def rake_ex_main():
+
+ print 'rake'
+ sym_name = 'dsp_ex_full_log.rake_ex_type'
+ rake_ex_type_address = get_symbol_hex_value(sym_name)
+# print ("rake_ex_type address= "+str(rake_ex_type_address))
+ ex_type = get_int(rake_ex_type_address)
+ print('ex_type: ' + sym_name + ' = ' + str(ex_type))
+ if ex_type == 0:
+ print 'Core not active or exception flow not finished'
+ else:
+ if ex_type == 1 or ex_type == 2:
+ assert_param = 'dsp_ex_full_log.md32_ex_log_ptr->ex_log_info.assert_info.'
+ file = get_name_string(int(get_symbol_address(assert_param+'ex_filename'), 16), 60)
+ line = get_symbol_hex_value(assert_param+'ex_line')
+ code1 = get_symbol_hex_value(assert_param+'ex_code[0]')
+ code2 = get_symbol_hex_value(assert_param+'ex_code[1]')
+ code3 = get_symbol_hex_value(assert_param+'ex_code[2]')
+
+ print 'Assertion at ' + file + ' line ' + line
+ print 'code1 ' + code1
+ print 'code2 ' + code2
+ print 'code3 ' + code3
+
+ elif ex_type == 3:
+ fatal_error_param = 'dsp_ex_full_log.md32_ex_log_ptr->ex_log_info.fatal_error_info.'
+ code1 = get_symbol_hex_value(fatal_error_param+'ex_code[0]')
+ code2 = get_symbol_hex_value(fatal_error_param+'ex_code[1]')
+ ifabtpc = get_symbol_hex_value(fatal_error_param+'ifabtpc')
+ ifabtcau = get_symbol_hex_value(fatal_error_param+'ifabtcau')
+ daabtcau = get_symbol_hex_value(fatal_error_param+'daabtcau')
+ daabtpc = get_symbol_hex_value(fatal_error_param+'daabtpc')
+ daabtad = get_symbol_hex_value(fatal_error_param+'daabtad')
+ daabtsp = get_symbol_hex_value(fatal_error_param+'daabtsp')
+ print 'Fatal error'
+ print 'code1 ' + code1
+ print 'code2 ' + code2
+ print 'ifabtpc ' + ifabtpc
+ print 'ifabtcau ' + ifabtcau
+ print 'daabtcau ' + daabtcau
+ print 'daabtpc ' + daabtpc
+ print 'daabtad ' + daabtad
+ print 'daabtsp ' + daabtsp
+
+ elif ex_type == 4:
+ print 'CTI triggered by other core'
+
+ else:
+ print 'Unknown status'
+
+def sonic_ex_main():
+ # todo to have a variable to escribe range
+ dsp_ex_sonic_amount = get_symbol_hex_value("dsp_ex_sonic_amount")
+ if dsp_ex_sonic_amount==None:
+ dsp_ex_sonic_amount = 12
+ else:
+ dsp_ex_sonic_amount = int(dsp_ex_sonic_amount,16)
+ print ("dsp_ex_sonic_amount value="+str(dsp_ex_sonic_amount))
+ for sonic in range(dsp_ex_sonic_amount):
+ print '---- sonic ' + str(sonic) + ' ----'
+ sym_name = 'dsp_ex_full_log.sonic_ex_type['+str(sonic)+']'
+ sonic_ex_type_address = get_symbol_hex_value(sym_name)
+# print ("sonic_ex_type address= "+str(sonic_ex_type_address))
+ ex_type = get_int(sonic_ex_type_address)
+ print('ex_type: ' + sym_name + ' = ' + str(ex_type))
+ if ex_type == 0:
+ print 'Core not active or exception flow not finished'
+ continue
+
+# print 'ex_type: ' + str(ex_type)
+ if ex_type == 1 or ex_type == 2:
+ assert_param = 'dsp_ex_full_log.sonic_ex_log_ptr['+str(sonic)+']->ex_params.assert_param.'
+ expr = get_string(get_symbol_address(assert_param+'expr'))
+ file = get_string(get_symbol_address(assert_param+'file'))
+ line = get_symbol_hex_value(assert_param+'line')
+ code1 = get_symbol_hex_value(assert_param+'code[0]')
+ code2 = get_symbol_hex_value(assert_param+'code[1]')
+ code3 = get_symbol_hex_value(assert_param+'code[2]')
+ print 'Assertion at ' + file + ' line ' + line
+ print 'expr ' + expr
+ print 'code1 ' + code1
+ print 'code2 ' + code2
+ print 'code3 ' + code3
+
+ elif ex_type == 3:
+ fatal_error_param = 'dsp_ex_full_log.sonic_ex_log_ptr['+str(sonic)+']->ex_params.fatal_error_param.'
+ code1 = get_symbol_hex_value(fatal_error_param+'code[0]')
+ code2 = get_symbol_hex_value(fatal_error_param+'code[1]')
+ fatal_type = get_symbol_hex_value(fatal_error_param+'fatal_type')
+ print 'Fatal error'
+ print 'code1 ' + code1
+ print 'code2 ' + code2
+ print 'fatal_type ' + fatal_type
+
+ elif ex_type == 4:
+ print 'CTI triggered by other core'
+
+ else:
+ print 'Unknown status'
+
+
+def get_cti_status():
+ inner_cti_addr=0xA1630800
+ brp_cti_addr=0xA1630804
+ fec_cti_addr=0xA1630808
+ speech_cti_addr=0xA163080C
+ rake_cti_addr=0xAC358008
+ scq16_0_cti_addr=0xABA10008
+ scq16_1_cti_addr=0xABB10008
+ print 'inner: '+str(get_int(inner_cti_addr))
+ print 'brp: '+str(get_int(brp_cti_addr))
+ print 'fec: '+str(get_int(fec_cti_addr))
+ print 'speech: '+str(get_int(speech_cti_addr))
+ print 'rake: '+str(get_int(rake_cti_addr))
+ print 'scq16_0: '+str(get_int(scq16_0_cti_addr))
+ print 'scq16_1: '+str(get_int(scq16_1_cti_addr))
+
+
+# The real entry point for the script
+'''
+print "<========CTI Status========>"
+print "(1:Exception offender, 0:not offender)"
+get_cti_status()
+print "<======CTI Status End======>"
+'''
+print "<========== SONIC==========>"
+sonic_ex_main()
+print "<========== USIP ==========>"
+usip_ex_main()
+print "<========== SCQ16==========>"
+scq16_ex_main()
+print "<========== RAKE ==========>"
+rake_ex_main()
+print "<========== END ===========>"
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/dsp_debug_info_CoreTracer.py b/mcu/tools/DebuggingSuite/Scripts/dsp_debug_info_CoreTracer.py
new file mode 100644
index 0000000..02ecb84
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/dsp_debug_info_CoreTracer.py
@@ -0,0 +1,319 @@
+################################################################################
+# DSP Debug info script
+# Version 0.5(Beta)
+# - Support parsing uSIP0(inner, brp), uSIP1(speech, fec) and RAKE, scq exception flow is TBD.
+################################################################################
+
+import gdb
+from os.path import getsize as get_file_size
+from itertools import chain as list_concat
+from time import sleep as sleep_sec
+import re
+import copy
+
+################################################################################
+# Gdb related Function
+################################################################################
+def execute_gdb(cmd, get_result=True):
+ result = gdb.execute(cmd, to_string=get_result)
+
+ if get_result:
+ return result[result.index('=')+1:].strip() if '=' in result else result
+
+ return None
+
+################################################################################
+# Entry point
+################################################################################
+
+def get_string(addr):
+ v = execute_gdb('printf "%s", (char*)(*' + str(addr) + ')')
+ return v
+
+def get_int(addr):
+ v = int(execute_gdb('p/x (int*)(*' + str(addr) + ')'), 16)
+ return v
+
+def get_hex(addr):
+ v = get_int(addr)
+# print("get_hex("+ str(addr) +") = " +hex(v))
+ return hex(v)
+
+def get_symbol_address(symbol_name):
+ sym_addr = execute_gdb("p/u &(" +symbol_name+ ")")
+ if "No symbol" in sym_addr:
+ print sym_addr
+ return None
+# print("get_symbol_address symbol_name:"+symbol_name +", its address="+ sym_addr)
+ return sym_addr
+
+def get_symbol_hex_value(symbol_name):
+ try:
+ sym_addr = get_symbol_address(symbol_name)
+# print ("in get_symbol_hex_value sym_addr=" + sym_addr)
+ sym_value = get_hex(sym_addr)
+# print "symbol: '" + symbol_name + "' value = " + str(sym_value)
+ return sym_value
+ except:
+ print "There is no exception info symbol " + symbol_name
+ return None
+
+def usip_ex_main():
+ for usip in range(2):
+ for th in range(2):
+ print '---- usip' + str(usip) + ' th' + str(th) + ' ----'
+
+ usip_thread_idx = usip*2 + th
+ sym_name = 'dsp_ex_full_log.usip_ex_type['+str(usip_thread_idx)+']'
+ usip_ex_type_ptr = get_symbol_address(sym_name)
+ usip_ex_type_address = get_int(usip_ex_type_ptr)
+# print ("usip_ex_type address= "+str(hex(usip_ex_type_address)))
+ ex_type = get_int(usip_ex_type_address)
+ print('ex_type: ' + sym_name + ' = ' + str(ex_type))
+ if ex_type == 0:
+ print 'Core not active or exception flow not finished'
+ continue
+
+ if ex_type == 1 or ex_type == 2:
+ assert_param = 'dsp_ex_full_log.usip_ex_log_ptr['+str(usip_thread_idx)+']->ex_params.assert_param.'
+ expr = get_string(get_symbol_address(assert_param+'expr'))
+ file = get_string(get_symbol_address(assert_param+'file'))
+ line = get_symbol_hex_value(assert_param+'line')
+ code1 = get_symbol_hex_value(assert_param+'code[0]')
+ code2 = get_symbol_hex_value(assert_param+'code[1]')
+ code3 = get_symbol_hex_value(assert_param+'code[2]')
+ thread_name = get_string(get_symbol_address('dsp_ex_full_log.usip_ex_log_ptr['+str(usip_thread_idx)+']->ex_thread_name'))
+ print 'Thread name ' + thread_name
+ print 'Assertion at ' + file + ' line ' + line
+ print 'expr ' + expr
+ print 'code1 ' + code1
+ print 'code2 ' + code2
+ print 'code3 ' + code3
+
+ elif ex_type == 3:
+ fatal_error_param = 'dsp_ex_full_log.usip_ex_log_ptr['+str(usip_thread_idx)+']->ex_params.fatal_error_param.'
+ code1 = get_symbol_hex_value(fatal_error_param+'code1')
+ code2 = get_symbol_hex_value(fatal_error_param+'code2')
+ ifabtpc = get_symbol_hex_value(fatal_error_param+'ifabtpc')
+ ifabtcau = get_symbol_hex_value(fatal_error_param+'ifabtcau')
+ daabtcau = get_symbol_hex_value(fatal_error_param+'daabtcau')
+ daabtpc = get_symbol_hex_value(fatal_error_param+'daabtpc')
+ daabtad = get_symbol_hex_value(fatal_error_param+'daabtad')
+ daabtsp = get_symbol_hex_value(fatal_error_param+'daabtsp')
+ thread_name = get_string(get_symbol_address('dsp_ex_full_log.usip_ex_log_ptr['+str(usip_thread_idx)+']->ex_thread_name'))
+ print 'Fatal error'
+ print 'Thread name ' + thread_name
+ print 'code1 ' + code1
+ print 'code2 ' + code2
+ print 'ifabtpc ' + ifabtpc
+ print 'ifabtcau ' + ifabtcau
+ print 'daabtcau ' + daabtcau
+ print 'daabtpc ' + daabtpc
+ print 'daabtad ' + daabtad
+ print 'daabtsp ' + daabtsp
+
+ elif ex_type == 4:
+ print 'CTI triggered by other core'
+
+ else:
+ print 'Unknown status'
+
+def scq16_ex_main():
+ for scq16 in range(4):
+ print '---- scq16 ' + str(scq16) + ' ----'
+ sym_name = 'dsp_ex_full_log.scq16_ex_type['+str(scq16)+']'
+ scq16_ex_type_address = get_symbol_hex_value(sym_name)
+# print ("scq16_ex_type address= "+str(scq16_ex_type_address))
+ ex_type = get_int(scq16_ex_type_address)
+ print('ex_type: ' + sym_name + ' = ' + str(ex_type))
+ if ex_type == 0:
+ print 'Core not active or exception flow not finished'
+ continue
+
+# print 'ex_type: ' + str(ex_type)
+ if ex_type == 1 or ex_type == 2:
+ assert_param = '(*dsp_ex_full_log.scq16_ex_log_dptr['+str(scq16)+'])->ex_params.assert_param.'
+ expr = get_string(get_symbol_address(assert_param+'expr'))
+ file = get_string(get_symbol_address(assert_param+'file'))
+ line = get_symbol_hex_value(assert_param+'line')
+ code1 = get_symbol_hex_value(assert_param+'code[0]')
+ code2 = get_symbol_hex_value(assert_param+'code[1]')
+ code3 = get_symbol_hex_value(assert_param+'code[2]')
+ print 'Assertion at ' + file + ' line ' + line
+ print 'expr ' + expr
+ print 'code1 ' + code1
+ print 'code2 ' + code2
+ print 'code3 ' + code3
+
+ elif ex_type == 3:
+ fatal_error_param = '(*dsp_ex_full_log.scq16_ex_log_dptr['+str(scq16)+'])->ex_params.fatal_error_param.'
+ code1 = get_symbol_hex_value(fatal_error_param+'code[0]')
+ code2 = get_symbol_hex_value(fatal_error_param+'code[1]')
+ ifabtpc = get_symbol_hex_value(fatal_error_param+'ifabtpc')
+ ifabtcau = get_symbol_hex_value(fatal_error_param+'ifabtcau')
+ daabtcau = get_symbol_hex_value(fatal_error_param+'daabtcau')
+ daabtpc = get_symbol_hex_value(fatal_error_param+'daabtpc')
+ daabtad = get_symbol_hex_value(fatal_error_param+'daabtad')
+ daabtad1 = get_symbol_hex_value(fatal_error_param+'daabtad1')
+ daabtsp = get_symbol_hex_value(fatal_error_param+'daabtsp')
+ print 'Fatal error'
+ print 'code1 ' + code1
+ print 'code2 ' + code2
+ print 'ifabtpc ' + ifabtpc
+ print 'ifabtcau ' + ifabtcau
+ print 'daabtcau ' + daabtcau
+ print 'daabtpc ' + daabtpc
+ print 'daabtad ' + daabtad
+ print 'daabtad1 ' + daabtad1
+ print 'daabtsp ' + daabtsp
+
+ elif ex_type == 4:
+ print 'CTI triggered by other core'
+
+ else:
+ print 'Unknown status'
+
+def get_name_string(addr, length):
+
+ file_name = ""
+ for offset in xrange(length):
+ digit = get_int(addr + offset*0x4)
+ if not digit:
+ break
+ file_name += format(digit, "x").decode("hex")[::-1]
+ return file_name
+
+def rake_ex_main():
+
+ print 'rake'
+ sym_name = 'dsp_ex_full_log.rake_ex_type'
+ rake_ex_type_address = get_symbol_hex_value(sym_name)
+# print ("rake_ex_type address= "+str(rake_ex_type_address))
+ ex_type = get_int(rake_ex_type_address)
+ print('ex_type: ' + sym_name + ' = ' + str(ex_type))
+ if ex_type == 0:
+ print 'Core not active or exception flow not finished'
+ else:
+ if ex_type == 1 or ex_type == 2:
+ assert_param = 'dsp_ex_full_log.md32_ex_log_ptr->ex_log_info.assert_info.'
+ file = get_name_string(int(get_symbol_address(assert_param+'ex_filename'), 16), 60)
+ line = get_symbol_hex_value(assert_param+'ex_line')
+ code1 = get_symbol_hex_value(assert_param+'ex_code[0]')
+ code2 = get_symbol_hex_value(assert_param+'ex_code[1]')
+ code3 = get_symbol_hex_value(assert_param+'ex_code[2]')
+
+ print 'Assertion at ' + file + ' line ' + line
+ print 'code1 ' + code1
+ print 'code2 ' + code2
+ print 'code3 ' + code3
+
+ elif ex_type == 3:
+ fatal_error_param = 'dsp_ex_full_log.md32_ex_log_ptr->ex_log_info.fatal_error_info.'
+ code1 = get_symbol_hex_value(fatal_error_param+'ex_code[0]')
+ code2 = get_symbol_hex_value(fatal_error_param+'ex_code[1]')
+ ifabtpc = get_symbol_hex_value(fatal_error_param+'ifabtpc')
+ ifabtcau = get_symbol_hex_value(fatal_error_param+'ifabtcau')
+ daabtcau = get_symbol_hex_value(fatal_error_param+'daabtcau')
+ daabtpc = get_symbol_hex_value(fatal_error_param+'daabtpc')
+ daabtad = get_symbol_hex_value(fatal_error_param+'daabtad')
+ daabtsp = get_symbol_hex_value(fatal_error_param+'daabtsp')
+ print 'Fatal error'
+ print 'code1 ' + code1
+ print 'code2 ' + code2
+ print 'ifabtpc ' + ifabtpc
+ print 'ifabtcau ' + ifabtcau
+ print 'daabtcau ' + daabtcau
+ print 'daabtpc ' + daabtpc
+ print 'daabtad ' + daabtad
+ print 'daabtsp ' + daabtsp
+
+ elif ex_type == 4:
+ print 'CTI triggered by other core'
+
+ else:
+ print 'Unknown status'
+
+def sonic_ex_main():
+ # todo to have a variable to escribe range
+ dsp_ex_sonic_amount = get_symbol_hex_value("dsp_ex_sonic_amount")
+ if dsp_ex_sonic_amount==None:
+ dsp_ex_sonic_amount = 12
+ else:
+ dsp_ex_sonic_amount = int(dsp_ex_sonic_amount,16)
+ print ("dsp_ex_sonic_amount value="+str(dsp_ex_sonic_amount))
+ for sonic in range(dsp_ex_sonic_amount):
+ print '---- sonic ' + str(sonic) + ' ----'
+ sym_name = 'dsp_ex_full_log.sonic_ex_type['+str(sonic)+']'
+ sonic_ex_type_address = get_symbol_hex_value(sym_name)
+# print ("sonic_ex_type address= "+str(sonic_ex_type_address))
+ ex_type = get_int(sonic_ex_type_address)
+ print('ex_type: ' + sym_name + ' = ' + str(ex_type))
+ if ex_type == 0:
+ print 'Core not active or exception flow not finished'
+ continue
+
+# print 'ex_type: ' + str(ex_type)
+ if ex_type == 1 or ex_type == 2:
+ assert_param = 'dsp_ex_full_log.sonic_ex_log_ptr['+str(sonic)+']->ex_params.assert_param.'
+ expr = get_string(get_symbol_address(assert_param+'expr'))
+ file = get_string(get_symbol_address(assert_param+'file'))
+ line = get_symbol_hex_value(assert_param+'line')
+ code1 = get_symbol_hex_value(assert_param+'code[0]')
+ code2 = get_symbol_hex_value(assert_param+'code[1]')
+ code3 = get_symbol_hex_value(assert_param+'code[2]')
+ print 'Assertion at ' + file + ' line ' + line
+ print 'expr ' + expr
+ print 'code1 ' + code1
+ print 'code2 ' + code2
+ print 'code3 ' + code3
+
+ elif ex_type == 3:
+ fatal_error_param = 'dsp_ex_full_log.sonic_ex_log_ptr['+str(sonic)+']->ex_params.fatal_error_param.'
+ code1 = get_symbol_hex_value(fatal_error_param+'code[0]')
+ code2 = get_symbol_hex_value(fatal_error_param+'code[1]')
+ fatal_type = get_symbol_hex_value(fatal_error_param+'fatal_type')
+ print 'Fatal error'
+ print 'code1 ' + code1
+ print 'code2 ' + code2
+ print 'fatal_type ' + fatal_type
+
+ elif ex_type == 4:
+ print 'CTI triggered by other core'
+
+ else:
+ print 'Unknown status'
+
+
+def get_cti_status():
+ inner_cti_addr=0xA1630800
+ brp_cti_addr=0xA1630804
+ fec_cti_addr=0xA1630808
+ speech_cti_addr=0xA163080C
+ rake_cti_addr=0xAC358008
+ scq16_0_cti_addr=0xABA10008
+ scq16_1_cti_addr=0xABB10008
+ print 'inner: '+str(get_int(inner_cti_addr))
+ print 'brp: '+str(get_int(brp_cti_addr))
+ print 'fec: '+str(get_int(fec_cti_addr))
+ print 'speech: '+str(get_int(speech_cti_addr))
+ print 'rake: '+str(get_int(rake_cti_addr))
+ print 'scq16_0: '+str(get_int(scq16_0_cti_addr))
+ print 'scq16_1: '+str(get_int(scq16_1_cti_addr))
+
+
+# The real entry point for the script
+'''
+print "<========CTI Status========>"
+print "(1:Exception offender, 0:not offender)"
+get_cti_status()
+print "<======CTI Status End======>"
+'''
+print "<========== SONIC==========>"
+sonic_ex_main()
+print "<========== USIP ==========>"
+usip_ex_main()
+print "<========== SCQ16==========>"
+scq16_ex_main()
+print "<========== RAKE ==========>"
+rake_ex_main()
+print "<========== END ===========>"
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/Scripts/dump_sys_mem.py b/mcu/tools/DebuggingSuite/Scripts/dump_sys_mem.py
new file mode 100755
index 0000000..dc325e0
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/Scripts/dump_sys_mem.py
@@ -0,0 +1,89 @@
+#from imgtec import codescape
+import sys
+import time
+import os
+import gdb
+import Tkinter, tkFileDialog
+import ctypes
+import re
+
+#MD Side
+AP_REG_BASE=0xC0000000
+MD_REG_BASE=0xA0000000
+
+#AP side
+#AP_REG_BASE=0x10000000
+#MD_REG_BASE=0x20000000
+
+def memory_write( mem_addr, set_value ):
+ gdb_cmd = 'set *' + str(mem_addr) + '=' + str(set_value)
+ gdb.execute(gdb_cmd)
+
+def memory_read(mem_addr):
+ gdb_cmd = 'x/x ' + str(mem_addr)
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ mem_value = mem_value[12:23]
+ hex_int = int(mem_value, 16)
+ return hex_int
+
+def bus_dump_mem( file_name, start_addr, end_addr):
+ gdb_cmds = [
+ 'monitor mips bus_read on',
+ 'dump memory ' + str(file_name) + ' ' + str(start_addr) + ' ' + str(end_addr),
+ 'monitor mips bus_read off'
+ ]
+ for cmd in gdb_cmds:
+ retval = gdb.execute(cmd, to_string=True)
+
+def core_dump_mem( file_name, start_addr, end_addr):
+ gdb_cmds = [
+ 'monitor mips bus_read off',
+ 'dump binary memory ' + str(file_name) + ' ' + str(start_addr) + ' ' + str(end_addr),
+ ]
+ for cmd in gdb_cmds:
+ retval = gdb.execute(cmd, to_string=True)
+
+def symbol_read(symbol):
+ gdb_cmd = 'p ' + symbol
+ mem_value = gdb.execute(gdb_cmd, to_string=True)
+ return mem_value
+
+def dump_sys_mem():
+ result = symbol_read('SysMemoryInfo')
+ # $2 = {16384, 4103412, 79691776, 0, ... }
+ m = re.search(r'{(.+?)}', result)
+ sys_mem_arr = m.group(1).split(',')
+ print 'total regions: ', len(sys_mem_arr)/2
+ print sys_mem_arr
+ for i in range(2, len(sys_mem_arr), 2):
+ addr = int(sys_mem_arr[i],10)
+ size = int(sys_mem_arr[i+1],10)
+ print i,"start to dump", format(addr, '#010x'), format(size, '#x')
+ if size != 0 and size != 0xFFFFFFFF:
+ #seg_size = 102400
+ #for j in range(addr, addr+size-seg_size, seg_size):
+ # print " start to dump segment", format(j, '#010x'), format(seg_size, '#x')
+ # core_dump_mem('sys_mem_'+format(j, '#010x')+'.bin', j, j+seg_size)
+ core_dump_mem('sys_mem_'+format(addr, '#010x')+'.bin', addr, addr+size)
+
+
+if __name__ == "__main__":
+
+
+ print "=== Start Dump Mem ==="
+ tStart = time.time()
+ dump_sys_mem()
+ tEnd = time.time()
+ print "=== End Dump Mem ==="
+ print "elapsed time %f sec" % (tEnd - tStart)
+
+ # tStart = time.time()
+ # bus_dump_mem('a.bin', 0x0, 0x2000)
+ # tEnd = time.time()
+ # print "bus_dump_mem cost %f sec" % (tEnd - tStart)
+
+ # tStart = time.time()
+ # core_dump_mem('b.bin', 0x0, 0x2000)
+ # tEnd = time.time()
+ # print "core_dump_mem cost %f sec" % (tEnd - tStart)
+ #
\ No newline at end of file
diff --git a/mcu/tools/DebuggingSuite/convertAddr2FuncAndFile.pl b/mcu/tools/DebuggingSuite/convertAddr2FuncAndFile.pl
new file mode 100644
index 0000000..9a81d58
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/convertAddr2FuncAndFile.pl
@@ -0,0 +1,363 @@
+#!/usr/bin/perl
+#
+# Copyright Statement:
+# --------------------
+# This software is protected by Copyright and the information contained
+# herein is confidential. The software may not be copied and the information
+# contained herein may not be used or disclosed except with the written
+# permission of MediaTek Inc. (C) 2006
+#
+# BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+# THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+# RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+# AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+# NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+# SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+# SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+# THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+# NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+# SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+#
+# BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+# LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+# AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+# OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+# MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+#
+# THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+# WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+# LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+# RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+# THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+#
+#*****************************************************************************
+#*
+#* Filename:
+#* ---------
+#* exLogParser.pl
+#*
+#* Project:
+#* --------
+#*
+#*
+#* Description:
+#* ------------
+#* This script parses raw data of the exception log
+#*
+#* Author:
+#* -------
+#* xxx (mtkxxxxx)
+#*
+#*============================================================================
+#* HISTORY
+#* Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+#*------------------------------------------------------------------------------
+#* $Revision$
+#* $Modtime$
+#* $Log$
+#*
+#* 04 28 2014 woody.kuo
+#* [MOLY00054950] [System Service][MOLY Kernel Internal Request] To prevent nested exception during KAL_ERROR_BUFFMNGR_ISVALID_FAILED
+#* change file to binmode due to 0xa 0xd
+#*
+#*------------------------------------------------------------------------------
+#* Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+#*============================================================================
+#****************************************************************************/
+
+#****************************************************************************
+# Included Modules
+#****************************************************************************
+
+
+#****************************************************************************
+# Constants
+#****************************************************************************
+my $MY_VERNO = " v0.02";
+ # v0.01 , initial draft
+
+
+#****************************************************************************
+# File Names
+#****************************************************************************
+my $DBGINFO = $ARGV[0];
+my $ADDRESS = $ARGV[1];
+my $AddressInDecimal;
+
+my $DebugPrint = 0; # 1 for debug; 0 for non-debug
+
+printf STDERR "version: $MY_VERNO\n" if($DebugPrint == 1);
+#****************************************************************************
+# 0 >>> Print out input parameters for checking
+#****************************************************************************
+if ($DebugPrint == 1) {
+ printf "DBGINFO: $DBGINFO\n";
+ printf "ADDRESS: $ADDRESS\n";
+ printf "\n";
+}
+
+#****************************************************************************
+# 1 >>> Check Input ADDRESS
+#****************************************************************************
+printf "Starting stage1... (Check input ADDRESS)\n" if($DebugPrint == 1);
+if ($ADDRESS =~ m/0x[a-fA-F0-9]+/) {
+ $AddressInDecimal = hex($ADDRESS);
+ printf "input ADDRESS = 0x%x\n", $AddressInDecimal if($DebugPrint == 1);
+}
+else {
+ &error_handler("Illegal ADDRESS: $ADDRESS! please input address beginning with format \"0x?\"", __FILE__, __LINE__);
+}
+print "\n" if($DebugPrint == 1);
+
+my $func = convert2FuncName($AddressInDecimal);
+my $file = convert2FileName($AddressInDecimal);
+
+if ($func eq "\0"){
+ printf "error: input address $ADDRESS is not a function address!!!";
+} else {
+ printf "file: $file, func: $func \n";
+}
+
+#****************************************************************************
+# oo >>> Finished
+#****************************************************************************
+exit 0;
+
+#-------------------------------------------------------------------------------------------------------------
+#| DbgInfo output file format |
+#|-----------------------------------------------------------------------------------------------------------|
+#| Item | Content | Size |
+#|------------------------------------------------------|-----------------------------------------|----------|
+#| DEBUGINFO_DB_FILE_PREFIX | CATI | 4 |
+#|------------------------------------------------------|-----------------------------------------|----------|
+#| DEBUGINFO_DB_VER_MAIN | 1 | 4 |
+#|------------------------------------------------------|-----------------------------------------|----------|
+#| DEBUGINFO_DB_VER_SUB | 0 | 4 |
+#|------------------------------------------------------|-----------------------------------------|----------|
+#| Project Name | (string)argv[3] | length+1 |
+#|------------------------------------------------------|-----------------------------------------|----------|
+#| HW Version | (string)argv[4] | length+1 |
+#|------------------------------------------------------|-----------------------------------------|----------|
+#| SW Version | (string)argv[5] | length+1 |
+#|------------------------------------------------------|-----------------------------------------|----------|
+#| Build Time | (string)argv[6] | length+1 |
+#|------------------------------------------------------|-----------------------------------------|----------|
+#| Sym Table Offset | nSymTableOffset | 4 |
+#|------------------------------------------------------|-----------------------------------------|----------|
+#| File Table Offset | nFileTableOffset | 4 |
+#|------------------------------------------------------|-----------------------------------------|----------|
+#| Symbol Table | Function name | m_mFunctions.m_Name | length+1 |
+#| |---------------------------------------|-----------------------------------------|----------|
+#| | Start Address | m_mFunctions.m_Addr | 4 |
+#| |---------------------------------------|-----------------------------------------|----------|
+#| | End Address | m_mFunctions.m_Addr+m_mFunctions.m_Size | 4 |
+#| |--------------------------------------------------------------------------------------------|
+#| | Repeat above 3 items�K |
+#| |--------------------------------------------------------------------------------------------|
+#| | NULL Function Name | "" | 1 |
+#|--------------|---------------------------------------|-----------------------------------------|----------|
+#| File Table | m_mRangesByFile | File Path | key | length+1 |
+#| |-----------------------|---------------|-----------------------------------------|----------|
+#| | m_mRangesByFile | Count | value.size | 4 |
+#| |-----------------------|---------------|-----------------------------------------|----------|
+#| | m_mRangesByFile.value | Start Address | m_mRangesByFile.value.key | 4 |
+#| | |---------------|-----------------------------------------|----------|
+#| | | End Address | m_mRangesByFile.value.value | 4 |
+#| | |--------------------------------------------------------------------|
+#| | | Repeat above 2 items�K |
+#| |--------------------------------------------------------------------------------------------|
+#| | Repeat above 3 items�K |
+#| |--------------------------------------------------------------------------------------------|
+#| | NULL Function Name | "" | 1 |
+#-------------------------------------------------------------------------------------------------------------
+
+#****************************************************************************
+# subroutine: convert2FuncName
+# input: addr
+#****************************************************************************
+sub convert2FuncName
+{
+ my ($addr) = @_;
+ my ($data, @byte, $n, $i);
+ my ($str, $start_addr, $end_addr);
+
+ # open DbgInfo
+ &error_handler("$DBGINFO: NOT exist!", __FILE__, __LINE__) if (!-e $DBGINFO);
+ open (FILE_HANDLE, "<$DBGINFO") or &error_handler("$DBGINFO: file error!", __FILE__, __LINE__);
+ binmode FILE_HANDLE;
+
+ # skip three words & four strings
+ foreach (1..3) {
+ read FILE_HANDLE, $data, 4;
+ }
+ foreach (1..4) {
+ while (($n = read FILE_HANDLE, $data, 1) != 0) {
+ last if (ord($data) == 0);
+ }
+ }
+
+ # skip two words (nSymTableOffset & nFileTableOffset)
+ foreach (1..2) {
+ read FILE_HANDLE, $data, 4;
+ }
+
+ # find the corresponding function name
+ while (1) {
+ # read a string
+ $str = "";
+ while (($n = read FILE_HANDLE, $data, 1) != 0) {
+ $str .= $data;
+ last if (ord($data) == 0);
+ }
+
+ # check if NULL string
+ last if ($str eq "\0");
+ printf "function name = \"%40s\"", $str if($DebugPrint == 1);
+
+ # read start address
+ for ($i = 0; $i < 4; $i++) {
+ read FILE_HANDLE, $byte[$i], 1;
+ }
+ $start_addr = get_int32(ord($byte[0]), ord($byte[1]), ord($byte[2]), ord($byte[3]));
+ printf ", start_addr = 0x%08x", $start_addr if($DebugPrint == 1);
+
+ # read end address
+ for ($i = 0; $i < 4; $i++) {
+ read FILE_HANDLE, $byte[$i], 1;
+ }
+ $end_addr = get_int32(ord($byte[0]), ord($byte[1]), ord($byte[2]), ord($byte[3]));
+ printf ", end_addr = 0x%08x\n", $end_addr if($DebugPrint == 1);
+
+ #check if the one we want
+ last if ($start_addr <= ($addr + 1) && ($addr + 1) < $end_addr);
+ }
+
+ # close DbgInfo
+ close(FILE_HANDLE);
+
+ if ($DebugPrint == 1) {
+ print sprintf("start_addr: 0x%08X, end_addr: 0x%08X\n", $start_addr, $end_addr);
+ print sprintf("addr: 0x%08X\n", $addr);
+ print "func_name returned: $str\n";
+ }
+
+ return $str;
+}
+
+#****************************************************************************
+# subroutine: convert2FileName
+# input: addr
+#****************************************************************************
+sub convert2FileName
+{
+ my ($addr) = @_;
+ my ($data, @byte, $offset, $n, $i, $j);
+ my ($nFileTableOffset, $str, $count, $start_addr, $end_addr);
+
+ # open DbgInfo
+ &error_handler("$DBGINFO: NOT exist!", __FILE__, __LINE__) if (!-e $DBGINFO);
+ open (FILE_HANDLE, "<$DBGINFO") or &error_handler("$DBGINFO: file error!", __FILE__, __LINE__);
+
+ # skip three words & four strings
+ foreach (1..3) {
+ read FILE_HANDLE, $data, 4;
+ }
+ $offset = 12;
+ foreach (1..4) {
+ while (($n = read FILE_HANDLE, $data, 1) != 0) {
+ $offset++;
+ last if (ord($data) == 0);
+ }
+ }
+
+ # read nFileTableOffset
+ read FILE_HANDLE, $data, 4;
+ for ($i = 0; $i < 4; $i++) {
+ read FILE_HANDLE, $byte[$i], 1;
+ }
+ $nFileTableOffset = get_int32(ord($byte[0]), ord($byte[1]), ord($byte[2]), ord($byte[3]));
+ $offset += 8;
+
+ # go to the offset
+ while($offset < $nFileTableOffset) {
+ read FILE_HANDLE, $data, 1;
+ $offset++;
+ }
+
+ # find the corresponding file name
+ while (1) {
+ # read a string
+ $str = "";
+ while (($n = read FILE_HANDLE, $data, 1) != 0) {
+ $str .= $data;
+ last if (ord($data) == 0);
+ }
+
+ # check if NULL string
+ last if ($str eq "\0");
+
+ #read count
+ for ($i = 0; $i < 4; $i++) {
+ read FILE_HANDLE, $byte[$i], 1;
+ }
+ $count = get_int32(ord($byte[0]), ord($byte[1]), ord($byte[2]), ord($byte[3]));
+
+ for ($i = 0; $i < $count; $i++) {
+ # read start address
+ for ($j = 0; $j < 4; $j++) {
+ read FILE_HANDLE, $byte[$j], 1;
+ }
+ $start_addr = get_int32(ord($byte[0]), ord($byte[1]), ord($byte[2]), ord($byte[3]));
+
+ # read end address
+ for ($j = 0; $j < 4; $j++) {
+ read FILE_HANDLE, $byte[$j], 1;
+ }
+ $end_addr = get_int32(ord($byte[0]), ord($byte[1]), ord($byte[2]), ord($byte[3]));
+
+ # check if the one we want
+ last if ($start_addr <= ($addr + 1) && ($addr + 1) < $end_addr);
+ }
+ last if ($i < $count);
+ }
+
+ # close DbgInfo
+ close(FILE_HANDLE);
+
+ if ($DebugPrint == 1) {
+ print sprintf("start_addr: 0x%08X, end_addr: 0x%08X\n", $start_addr, $end_addr);
+ print sprintf("addr: 0x%08X\n", $addr);
+ print "file_name returned: $str\n";
+ }
+
+ return $str;
+}
+
+#****************************************************************************
+# subroutine: get_int32
+# input: $byte0
+# $byte1
+# $byte2
+# $byte3
+#****************************************************************************
+sub get_int32
+{
+ my ($byte0, $byte1, $byte2, $byte3) = @_;
+ return ($byte3 << 24) | ($byte2 << 16) | ($byte1 << 8) | $byte0;
+}
+
+#****************************************************************************
+# subroutine: error_handler
+# input: $error_msg: error message
+# $file: filename
+# $line_no: line number
+#****************************************************************************
+sub error_handler
+{
+ my ($error_msg, $file, $line_no) = @_;
+
+ my $final_error_msg = "PARSER ERROR: $error_msg at $file line $line_no\n";
+ die $final_error_msg;
+}
diff --git a/mcu/tools/DebuggingSuite/initLogParser.pl b/mcu/tools/DebuggingSuite/initLogParser.pl
new file mode 100644
index 0000000..9f5f111
--- /dev/null
+++ b/mcu/tools/DebuggingSuite/initLogParser.pl
@@ -0,0 +1,313 @@
+#!/usr/bin/perl
+#
+# Copyright Statement:
+# --------------------
+# This software is protected by Copyright and the information contained
+# herein is confidential. The software may not be copied and the information
+# contained herein may not be used or disclosed except with the written
+# permission of MediaTek Inc. (C) 2006
+#
+# BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+# THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+# RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+# AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+# NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+# SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+# SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+# THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+# NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+# SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+#
+# BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+# LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+# AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+# OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+# MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+#
+# THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+# WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+# LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+# RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+# THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+#
+#*****************************************************************************
+#*
+#* Filename:
+#* ---------
+#* initLogParser.pl
+#*
+#* Project:
+#* --------
+#*
+#*
+#* Description:
+#* ------------
+#* This script parses raw data of the boot-up log
+#*
+#* Author:
+#* -------
+#* Dot Li (mtk02439)
+#*
+#*============================================================================
+#* HISTORY
+#* Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+#*------------------------------------------------------------------------------
+#* $Revision$
+#* $Modtime$
+#* $Log$
+#*
+#* 04 17 2013 dot.li
+#* [MOLY00019590] [SystemService][Init] Smartphone modem boot-up trace phase 2
+#* .
+#*
+#* 03 12 2013 dot.li
+#* [MOLY00011540] [SystemService][Init] Smartphone modem boot-up trace
+#* .
+#*
+#*------------------------------------------------------------------------------
+#* Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+#*============================================================================
+#****************************************************************************/
+
+BEGIN { push @INC, "pcore/" , '..' } # add additional library path
+
+#****************************************************************************
+# Input arguments
+#****************************************************************************
+my $LOG_STAGE = $ARGV[0];
+
+my $DebugPrint = 1; # 1 for debug; 0 for non-debug
+
+#****************************************************************************
+# >>> Handle boot-up stage
+#****************************************************************************
+#****************************************************************************
+# 1 >>> Abort at stage 1
+#****************************************************************************
+if ($LOG_STAGE eq "HS1") {
+ print "MD init stage 1\n";
+
+ #****************************************************************************
+ # 1-1 >>> Parsing stage 1 label
+ #****************************************************************************
+ my $stage1_label_file = "../../../pcore/driver/sys_drv/init/inc/bootarm.h";
+
+ &error_handler("$stage1_label_file: NOT exist!", __FILE__, __LINE__) if (!-e $stage1_label_file);
+ open (FILE_HANDLE, "<$stage1_label_file") or &error_handler("$stage1_label_file: file error!", __FILE__, __LINE__);
+
+ my ($line, $add_label, @boot_stage_label, @boot_stage_code, $i);
+
+ $add_label = 0; # not start enum
+ $i = 0;
+
+ # parsing enum info
+ while ($line = <FILE_HANDLE>) {
+ if ($line =~ m/#define LABEL/) {
+ $boot_stage_label[$i] = $1 if ($line =~ m/(LABEL_(\w|\d)+)/ );
+ $boot_stage_code[$i] = $1 if ($line =~ m/((0x|0X)[0-9A-Fa-f]+)/ );
+ $i++;
+ }
+ }
+
+ #****************************************************************************
+ # 1-2 >>> Matching and output result
+ #****************************************************************************
+
+ print "Magic:";
+ $hex=$ARGV[1];
+ while($hex =~ /(.{2})/sg) {
+ print chr(hex($1));
+ }
+ print " (0x$ARGV[1])\n";
+
+ if ($ARGV[1] =~ /30305f49/) {
+ $matching = 0;
+
+ for($i = 0; $i < $#boot_stage_label; $i++) {
+ if(hex($boot_stage_code[$i]) == hex($ARGV[2])) {
+ print "last label record: $boot_stage_label[$i]\n";
+ $matching = 1;
+ last;
+ }
+ }
+ print "No matching stage found!!\n" if ($matching == 0);
+ }
+} # boot stage HS1
+#****************************************************************************
+# 2 >>> Abort at stage 2
+# input format: ./initLogParser.pl HS2 [project flavor] [log file]
+#****************************************************************************
+if ($LOG_STAGE eq "HS2") {
+
+ #****************************************************************************
+ # 2-0 >>> Parse CPU speed
+ #****************************************************************************
+
+ use FileInfoParser;
+ my %MAKEFILE_OPTIONS;
+ my $themf = "../../make/" . $ARGV[1];
+ if(1!=&FileInfo::Parse_MAKEFILE($themf, \%MAKEFILE_OPTIONS))
+ {
+ &sysUtil::sysgen_die("[1.1]Parse MakeFile failed");
+ }
+
+ my $CPU_MHZ = $MAKEFILE_OPTIONS{'MCU_CLOCK'};
+
+ $CPU_MHZ =~ s/\D//g;
+
+ my $LOG_FILE = $ARGV[2];
+
+ # to align error message file name format
+ $LOG_FILE =~ s/^.\\|^\\//;
+
+ #****************************************************************************
+ # 2-1 >>> Print out input parameters for checking
+ #****************************************************************************
+ if ($DebugPrint == 1) {
+ print "LOG_STAGE: $LOG_STAGE\n";
+ print "LOG_FILE: $LOG_FILE\n";
+ print "\n";
+ }
+
+ my (@boot_log_raw, $boot_log, $start_idx, $i);
+
+ #****************************************************************************
+ # 2-2 >>> Read In Exception Log
+ #****************************************************************************
+ print "Starting stage1... (Read in boot-up log)\n" if($DebugPrint == 1);
+
+ &error_handler("$LOG_FILE: NOT exist!", __FILE__, __LINE__) if (!-e $LOG_FILE);
+ open (FILE_HANDLE, "<$LOG_FILE") or &error_handler("$LOG_FILE: file error!", __FILE__, __LINE__);
+ #binmode FILE_HANDLE;
+
+ # parsing log file
+ use constant TASK_MAGIC => 0x4B534154;
+
+ my ($line, @data32);
+
+ $i = 0;
+ while ($line = <FILE_HANDLE>) {
+ if ($line =~ /(\w+) (\w+) (\w+) (\w+)/) {
+ $data32[0] = $1;
+ $data32[1] = $2;
+ $data32[2] = $3;
+ $data32[3] = $4;
+ foreach $_ (@data32) {
+ $boot_log_raw[$i++] = hex($_);
+ }
+ }
+ }
+
+ close (FILE_HANDLE);
+
+ #****************************************************************************
+ # 2-3 >>> Parse Header for log address
+ #****************************************************************************
+ print "Starting stage2... (Parse header for log address)\n" if($DebugPrint == 1);
+
+ $start_idx = $boot_log_raw[0]/16;
+ #print "$boot_log_raw[0] , $start_idx\n";
+
+ #****************************************************************************
+ # 2-4 >>> Parse Boot-Up Log
+ #****************************************************************************
+ print "Starting stage3... (Parse boot-up log)\n" if($DebugPrint == 1);
+
+ $boot_log .= "CPU Speed = ".$CPU_MHZ." MHz\n";
+
+ print "MD init stage 2\n";
+ my @boot_stage = &hs2_label_parse();
+
+ $boot_log .= sprintf("%4s%10s (%10s)\t\tLog\n","Idx","msec","CPU cycle");
+
+ my ($parse_task, $log_size, $ts_msec, $temp_str);
+ $i = $start_idx;
+ while($i < @boot_log_raw) {
+ if($boot_log_raw[$i] != 0) {
+ if($boot_log_raw[$i] == TASK_MAGIC) {
+ $parse_task = $boot_log_raw[$i+1];
+ } else {
+ $log_size++;
+ $ts_msec = sprintf("%.2f", $boot_log_raw[$i+1] / $CPU_MHZ / 1000); # milli-second
+ if ($parse_task == 1) {
+ $boot_log .= sprintf("[%2d]%10.2f ms (%10d)\t\t[Task] Start of task index $boot_log_raw[$i] init \n", $log_size, $ts_msec, $boot_log_raw[$i+1]);
+ } else {
+ $boot_log .= sprintf("[%2d]%10.2f ms (%10d)\t\Start of $boot_stage[$boot_log_raw[$i]]\n", $log_size, $ts_msec, $boot_log_raw[$i+1]);
+ }
+ }
+ }
+ $i += 2;
+ }
+
+ # print to console
+ print $boot_log;
+ print "Number of log = $log_size\n" if($DebugPrint == 1);
+
+ #****************************************************************************
+ # 2-5 >>> Output to a TXT
+ #****************************************************************************
+ print "Output to $LOG_FILE.txt\n";
+ open (FILE_HANDLE, ">$LOG_FILE.txt") or &error_handler("$LOG_FILE: file error!", __FILE__, __LINE__);
+ print FILE_HANDLE $boot_log;
+ close (FILE_HANDLE);
+
+} # boot stage HS2
+
+#****************************************************************************
+# oo >>> Finished
+#****************************************************************************
+exit 0;
+
+
+#****************************************************************************
+# subroutine: error_handler
+# input: $error_msg: error message
+# $file: filename
+# $line_no: line number
+#****************************************************************************
+sub error_handler
+{
+ my ($error_msg, $file, $line_no) = @_;
+
+ my $final_error_msg = "BOOT LOG PARSER ERROR: $error_msg at $file line $line_no\n";
+ die $final_error_msg;
+}
+
+
+#****************************************************************************
+# subroutine: hs2_label_parse
+#****************************************************************************
+sub hs2_label_parse
+{
+ my $stage2_label_file = "../../../pcore/driver/sys_drv/init/inc/init_trc_id.h";
+
+ &error_handler("$stage2_label_file: NOT exist!", __FILE__, __LINE__) if (!-e $stage2_label_file);
+ open (FILE_HANDLE, "<$stage2_label_file") or &error_handler("$stage2_label_file: file error!", __FILE__, __LINE__);
+
+ my ($line, $add_label, @label_arr, $i);
+
+ $add_label = 0; # not start enum
+ $i = 0;
+
+ # parsing enum info
+ while ($line = <FILE_HANDLE>) {
+ if ($line =~ m/typedef enum {/) {
+ $add_label = 1;
+ }
+
+ if ($line =~ m/} BOOT;/) {
+ $add_label = 2;
+ }
+
+ if($add_label == 1) {
+ if ($line =~ m/(BOOT_(\w|\d)+)/) {
+ $label_arr[$i++]=$1;
+ }
+ }
+ }
+
+
+ return @label_arr;
+}