| /***************************************************************************** |
| * Copyright Statement: |
| * -------------------- |
| * This software is protected by Copyright and the information contained |
| * herein is confidential. The software may not be copied and the information |
| * contained herein may not be used or disclosed except with the written |
| * permission of MediaTek Inc. (C) 2016 |
| * |
| * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
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| * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
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| * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| * |
| * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
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| * |
| * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
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| * |
| *****************************************************************************/ |
| |
| #ifndef _CL1FHRTBACONSTANT_H_ |
| #define _CL1FHRTBACONSTANT_H_ |
| |
| #ifdef MTK_DEV_93M_PREIT |
| |
| |
| /***************************************************************************** |
| |
| FILE NAME: cl1fhrtbaconstant.h |
| |
| DESCRIPTION: |
| |
| This file contains the constant definition of RTBA module in 93m |
| |
| *****************************************************************************/ |
| |
| /*---------------------------------------------------------------------------- |
| * Definitions |
| *----------------------------------------------------------------------------*/ |
| #define FEC_DDL_RX_MARGIN (850) |
| #define FEC_DDL_TRX_MARGIN (950) |
| #define FEC_DDL_RX_MARGIN_CONN_STANDBY_MEAS (5000) |
| |
| /** Define for the RTBA Channel related block info. */ |
| #define RTBA_BASIC_BLOCK_LENGTH (20000) /** The RTBA basic block length in us unit. */ |
| #define RTBA_XL1_ICS_SYNC_SMALL_BLOCK_LENGTH (80000/3) /** The XL1 sync channel small block reserve length, in us unit. */ |
| #define RTBA_XL1_CONN_PS_RX_BLOCK_LENGTH (RTBA_BASIC_BLOCK_LENGTH * 6) /** The XL1 connect ps block length. */ |
| #define RTBA_XL1_SLT_PCH_LOST_DET_BLOCK_LENGTH RTBA_BASIC_BLOCK_LENGTH /** The XL1 PCH Lost block length. */ |
| #define RTBA_XL1_NSLT_PCH_OVHD_BLOCK_LENGTH RTBA_BASIC_BLOCK_LENGTH /** The XL1 non-slotted PCH overhead block length. */ |
| #define RTBA_XL1_NSLT_PCH_LONG_BLOCK_LENGTH (RTBA_XL1_NSLT_PCH_OVHD_BLOCK_LENGTH * 16) |
| |
| #ifdef MTK_CBP_SYNC_OPTIMIZE |
| #define XL1_MINI_ACQ_FAST_AGC_ICS_LENGTH (3500) |
| #endif |
| |
| #define XL1_MINI_ACQ_FAST_AGC_LENGTH (5750) /** The XL1 mini acquisition length,which needs to be added to RTB block |
| when previously preempt, in us unit. */ |
| #define RTBA_EVL1_ICS_SYNC_SMALL_BLOCK_LENGTH RTBA_BASIC_BLOCK_LENGTH /** The EvL1 Sync pch channel basic block length in us unit. */ |
| #define RTBA_EVL1_NSLT_CC_OVHD_BLOCK_LENGTH RTBA_BASIC_BLOCK_LENGTH /** The EvL1 non-slotted pch channel basic block length in us unit. */ |
| #define RTBA_EVL1_CONN_RX_BLOCK_LENGTH RTBA_BASIC_BLOCK_LENGTH /** The EvL1 Connect Rx channel basic block length in us unit. */ |
| |
| #define RTBA_XL1_BRP_TAIL_MARGIN_20MS (3*1250) /** 1xRTT's BRP Tail Margin for 20ms frame size (3PCG).*/ |
| #define RTBA_XL1_BRP_TAIL_MARGIN_26MS (3*1667) /** 1xRTT's BRP Tail Margin for 26ms frame size (3PCG).*/ |
| #define RTBA_XL1_BRP_TAIL_MARGIN_20MS_TRAFFIC (6*1250) /** 1xRTT's BRP Tail Margin for 20ms FCH frame size (3PCG).*/ |
| |
| #define RTBA_SCHE_FAKE_MARGIN_20MS (1250) /** The fake margin for RTBA schedule for RC control.*/ |
| #define RTBA_SCHE_FAKE_MARGIN_26MS (1667) /** The fake margin for RTBA schedule for RC control.*/ |
| |
| #define RTBA_SCHE_CHECK_DSP_IDLE_MARGIN_20MS (1250) /** The check dsp idle margin for RC control.*/ |
| #define RTBA_SCHE_CHECK_DSP_IDLE_MARGIN_26MS (1667) /** The check dsp idle margin for RC control.*/ |
| #define RTBA_SCHE_CHECK_DSP_IDLE_MARGIN_20MS_LONG (6250) /** The check dsp idle margin for RC control due to un-alignment timing between IA and MD32, 5*1250.*/ |
| |
| #define RTBA_SCHE_CHECK_DSP_IDLE_MARGIN_26MS_LONG (10000) /** The check dsp idle margin for RC control due to un-alignment timing between IA and MD32, 6*1667us.*/ |
| #define RTBA_SCHE_CHECK_DSP_IDLE_MARGIN_26MS_MED (6666) /** The check dsp idle margin for RC control due to un-alignment timing between IA and MD32, 4*1667us.*/ |
| |
| |
| #define RTBA_SCHE_HSC_PREEMPT_ADVANCE_OFFSET (RTBA_SCHE_CHECK_DSP_IDLE_MARGIN_26MS_MED) /** Indicate the HSC preempt gap for HSC fully/div preemption.*/ |
| #define RTBA_INVALID_GAP_START_TIME (0xFFFFFFFF) |
| |
| |
| /***************************************************************************** |
| * End of File |
| *****************************************************************************/ |
| #endif |
| #endif |
| |