| /***************************************************************************** |
| * Copyright Statement: |
| * -------------------- |
| * This software is protected by Copyright and the information contained |
| * herein is confidential. The software may not be copied and the information |
| * contained herein may not be used or disclosed except with the written |
| * permission of MediaTek Inc. (C) 2016 |
| * |
| * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS (""MEDIATEK SOFTWARE"") |
| * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| * AN ""AS-IS"" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| * |
| * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| * |
| * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSKTRUED IN ACCORDANCE |
| * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| * |
| *****************************************************************************/ |
| #ifndef _HSCDEFS_H_ |
| #define _HSCDEFS_H_ |
| /***************************************************************************** |
| * |
| * FILE NAME : hscdefs.h |
| * |
| * DESCRIPTION : This file contains general constants and definitions used by |
| * the L1D unit |
| * |
| * HISTORY : |
| * See Log at end of file |
| * |
| *****************************************************************************/ |
| |
| /*---------------------------------------------------------------------------- |
| Include Files |
| ----------------------------------------------------------------------------*/ |
| #include "do_mpaapi.h" |
| #include "hscapi.h" |
| #include "hscapiex.h" |
| #include "systyp.h" |
| |
| /*---------------------------------------------------------------------------- |
| Hardware Macros |
| ----------------------------------------------------------------------------*/ |
| /*---------------------------------------------------------------------------- |
| MPA definitions |
| ----------------------------------------------------------------------------*/ |
| typedef struct |
| { |
| MpaAntennaInfoT MpaRfAntenna[MPA_RF_NUM_PATHS]; /*HWD_RF_MPA_MAX_PATH_NUM */ |
| kal_uint8 AllStatus; |
| kal_uint8 Status[MPA_RF_NUM_APPS]; |
| kal_uint8 RfPriv[MPA_RF_NUM_APPS]; |
| } HscMpaT; |
| |
| typedef enum |
| { |
| HSC_OP_MODE_LEGACY_HYBRID_BN = 0, |
| HSC_OP_MODE_SHDR_WITH_DIV_BN, |
| HSC_OP_MODE_SHDR_2_MAINS_BN, |
| HSC_OP_MODE_SVDO_2_RX_BN, |
| HSC_OP_MODE_SVDO_3_RX_BN |
| }HscMpaOpModeT; |
| |
| #define HSC_OP_MODE_LEGACY_HYBRID (1<<HSC_OP_MODE_LEGACY_HYBRID_BN) |
| #define HSC_OP_MODE_SHDR_WITH_DIV (1<<HSC_OP_MODE_SHDR_WITH_DIV_BN) |
| #define HSC_OP_MODE_SHDR_2_MAINS (1<<HSC_OP_MODE_SHDR_2_MAINS_BN) |
| #define HSC_OP_MODE_SVDO_2_RX (1<<HSC_OP_MODE_SVDO_2_RX_BN) |
| #define HSC_OP_MODE_SVDO_3_RX (1<<HSC_OP_MODE_SVDO_3_RX_BN) |
| #define HSC_OP_MODE_SHDR (HSC_OP_MODE_SHDR_WITH_DIV | HSC_OP_MODE_SHDR_2_MAINS) |
| #define HSC_OP_MODE_SVDO (HSC_OP_MODE_SVDO_2_RX | HSC_OP_MODE_SVDO_3_RX) |
| #define HSC_OP_MODE_SHDR_OR_SVDO (HSC_OP_MODE_SHDR | HSC_OP_MODE_SVDO) |
| |
| extern kal_uint8 hscMpaOpMode; |
| extern kal_uint8 hscMpaOpModeHwdConfig; |
| |
| /*---------------------------------------------------------------------------- |
| Clk Calibration definitions |
| ----------------------------------------------------------------------------*/ |
| #define SP_CNT_32K_UPPER_8_MASK 0x00FF /* Upper mask 8bits:[23-16] of 32kHz counter [23:0] */ |
| #define SP_CNT_9MHZ_UPPER_4_MASK 0x000F /* Upper mask 4bits:[19-16] of 9MHz counter [19:0] */ |
| #define SP_CNT_9MHZ_UPPER_2_MASK 0x0003 /* bits [17-16] of 9MHz counter [19:0] */ |
| #define HSC_CLK_CAL_DO_PILOT_HIGH_CONFID 16462 /* -6dB in Q16 */ |
| #define HSC_CLK_CAL_DO_PILOT_MED_CONFID 8231 /* -9dB in Q16 */ |
| #define HSC_CLK_CAL_DO_PILOT_MIN_CONFID 4135 /* -12dB in Q16 */ |
| #define HSC_CLK_CAL_SETTLE_TIME_16X 16 /* settle time in units of slot cycle length */ |
| #define HSC_CLK_CAL_SETTLE_TIME_8X 8 /* settle time in units of slot cycle length */ |
| #define HSC_CLK_CAL_SETTLE_TIME_4X 4 /* settle time in units of slot cycle length */ |
| #define HSC_CLK_CAL_SETTLE_TIME_2X 2 /* settle time in units of slot cycle length */ |
| #define HSC_CLK_CAL_SETTLE_TIME_1X 1 /* settle time in units of slot cycle length */ |
| #define HSC_CLK_CAL_FAST_SETTLE_PERIOD 120 /* fast settle period in units of seconds */ |
| #define HSC_MINI_ACQ_ERR_TC8_THRESH (45*8) /* Threshold set at 45 chips */ |
| |
| |
| |
| /*------------------------------------------------------------------------------ |
| Spage Backoff Time Definitions (CBP7.0 Slotted Operation Section 2.4, Jing Su) |
| -------------------------------------------------------------------------------*/ |
| #define HSC_SP_SLOTTED_WAKE_SCHE_SLOT_CNT 1 |
| #define HSC_SP_RX_AGC_SETTLE_SHORT_SLOT_CNT 2 |
| #define HSC_SP_RX_AGC_SETTLE_LONG_SLOT_CNT 4 |
| #define HSC_SP_MINI_ACQ_DATA_CAP_SLOT_CNT 3 |
| #define HSC_SP_MINI_ACQ_POST_PROC_SLOT_CNT 2 |
| #define HSC_SP_FING_ALLOC_SLOT_CNT 7 |
| |
| /*---------------------------------------------------------------------------- |
| DO TxFreeze Backoff Time Definitions |
| ----------------------------------------------------------------------------*/ |
| #define HSC_STOPDO_GUARD_FRMS 10 /* 10 guard frames whether in 1X or DO */ |
| |
| /*---------------------------------------------------------------------------- |
| HscSsm Definitions |
| ----------------------------------------------------------------------------*/ |
| #define HSC_32K_STEP_FRAC_SHIFT (18) |
| |
| #define HSC_9M_CNTS_PER_2048_80MS 0x60000000UL /* 9MHz count in max duration of Slotted cycle (9.8304MHz * 2048 * 80 ms) */ |
| #define HSC_26MS_FRM_CNTS_PER_2048_80MS 0x1800 /* 26ms Frame cnt in max duration of Slotted cycle (2048 * 3) */ |
| #define HSC_26MS_FRM_CNTS_MOD_MAX_SLOTPERIOD HSC_26MS_FRM_CNTS_PER_2048_80MS |
| #define HSC_26MS_FRM_CNTS_MOD_MAX_32BITS 0xFFFFF000UL /* 0xFFFFF000 = 0x100000000/0x1800 */ |
| |
| #define HSC_SSM_RESYNC_CAL_BACKOFF_SP_CLK_CNT (FRC_FREQ * 80 / 1000) /* Clk Cal Collision buffer 80ms */ |
| #define HSC_SSM_RESYNC_COLLISION_US (FRC_FREQ * 150 / 1000) /* Resync Collision buffer 150ms */ |
| #define HSC_SSM_DUAL_RESYNC_COLLISION_US (FRC_FREQ * 40 / 1000) /* Resync Collision buffer 40ms */ |
| #define HSC_SSM_RESYNC_SHDR_HYBRID_TIMER (150000) /* 150ms ahead, Resync decision to wake up in SHDR or hybrid */ |
| #define HSC_SSM_RESYNC_1X_SCAN_BACKOFF_US (2*FRC_FREQ) /* Resync Collision buffer 2s */ |
| #define HSC_SSM_RESYNC_DO_SCAN_BACKOFF_US (0*FRC_FREQ) /* Resync Collision buffer 0s */ |
| #define HSC_SSM_REF_TIME_SV_PERIOD (40) /* DO ref time supervision period: 40s */ |
| #define HSC_DO_SLT_BLOCK_LENGTH (106667) /* 64 slots */ |
| #define HSC_DO_WAKE_BLOCK_LENGTH (53333) /* 32 slots */ |
| |
| #define HSC_SSM_STATUS_DO_BN 0 |
| #define HSC_SSM_STATUS_RESYNC_CMPLT_BN 1 /* completed hw Resync */ |
| #define HSC_SSM_STATUS_RESYNC_DENIED_BN 2 /* Slotted wakeup was denied */ |
| #define HSC_SSM_STATUS_SUSPENDED_BN 3 /* preempted and suspended */ |
| #define HSC_SSM_STATUS_WAKE_PENDING_BN 4 /* Wake Cmd was received */ |
| #define HSC_SSM_STATUS_WAKE_SCHEDULED_BN 5 /* Resync has been scheduled for the wake command */ |
| #define HSC_SSM_STATUS_MPA_NORM_REQ_PENDING_BN 6 /* waiting for RF Norm Req results */ |
| #define HSC_SSM_STATUS_MPA_NORM_REQ_IMMED_BN 7 /* Immediate RF request (1^MpaReqMsg.QueueRequest) */ |
| #define HSC_SSM_STATUS_TX_AVAILABLE_BN 10 /* Tx available Ind */ |
| #define HSC_SSM_STATUS_MPA_MEAS_REQ_BN 11 /* Antenna request is for Meas */ |
| #define HSC_SSM_STATUS_WAKE_PROCESSED_BN 12 /* Wake cmd is processed */ |
| #define HSC_SSM_STATUS_SLOTTED_BN 13 /* Slotted mode */ |
| |
| #define HSC_SSM_STATUS_DO (1<<HSC_SSM_STATUS_DO_BN) /*0x0001*/ |
| #define HSC_SSM_STATUS_RESYNC_CMPLT (1<<HSC_SSM_STATUS_RESYNC_CMPLT_BN) /*0x0002*/ |
| #define HSC_SSM_STATUS_RESYNC_DENIED (1<<HSC_SSM_STATUS_RESYNC_DENIED_BN) /*0x0004*/ |
| #define HSC_SSM_STATUS_SUSPENDED (1<<HSC_SSM_STATUS_SUSPENDED_BN) /*0x0008*/ |
| #define HSC_SSM_STATUS_WAKE_PENDING (1<<HSC_SSM_STATUS_WAKE_PENDING_BN) /*0x0010*/ |
| #define HSC_SSM_STATUS_WAKE_SCHEDULED (1<<HSC_SSM_STATUS_WAKE_SCHEDULED_BN) /*0x0020*/ |
| #define HSC_SSM_STATUS_MPA_NORM_REQ_PENDING (1<<HSC_SSM_STATUS_MPA_NORM_REQ_PENDING_BN) /*0x0040*/ |
| #define HSC_SSM_STATUS_MPA_NORM_REQ_IMMED (1<<HSC_SSM_STATUS_MPA_NORM_REQ_IMMED_BN) /*0x0080*/ |
| #define HSC_SSM_STATUS_TX_AVAIL_IND_PEND (1<<HSC_SSM_STATUS_TX_AVAILABLE_BN) /*0x0400*/ |
| #define HSC_SSM_STATUS_MPA_MEAS_REQ (1<<HSC_SSM_STATUS_MPA_MEAS_REQ_BN) /*0x0800*/ |
| #define HSC_SSM_STATUS_WAKE_PROCESSED (1<<HSC_SSM_STATUS_WAKE_PROCESSED_BN) /*0x1000*/ |
| #define HSC_SSM_STATUS_SLOTTED (1<<HSC_SSM_STATUS_SLOTTED_BN) |
| |
| #define HSC_SSM_STATUS_RESYNC_RESET ( HSC_SSM_STATUS_RESYNC_CMPLT | \ |
| HSC_SSM_STATUS_RESYNC_DENIED | \ |
| HSC_SSM_STATUS_SUSPENDED ) |
| |
| typedef enum |
| { |
| HSC_SSM_ACTIVE_1xRTT, |
| HSC_SSM_ACTIVE_EVDO, |
| HSC_SSM_RESYNC, |
| HSC_SSM_WAIT_1, |
| HSC_SSM_WAIT_2, |
| HSC_SSM_SUSPENDED, |
| HSC_SSM_NUM_WAKE |
| } WakeTypeT; |
| |
| typedef enum |
| { |
| HSC_FM_NONE, |
| HSC_FM_ONGOING, |
| HSC_FM_DONE |
| } HscFmStatusT; |
| |
| typedef struct |
| { |
| HscFmStatusT FmStatus; |
| HscFmResultT FmResult; |
| kal_int32 MiniAcqCorrectionTc8; |
| kal_int32 OnlineAdj; |
| kal_int32 CalValue; |
| kal_uint16 MiniAcqPwrEst; |
| kal_int32 MiniAcqCalValue; |
| kal_uint8 CalScale[HSC_NUM_APPS]; /* CalScale = ResyncDenyCnt+1 */ |
| kal_uint8 ResyncDenyCnt[HSC_NUM_APPS]; |
| kal_uint32 SleepTimes; |
| } HscClkCalT; /* This is the clk cal structure for DO, see SPageCal in l1d for 1X */ |
| |
| |
| typedef struct |
| { |
| kal_uint32 RxPllSettle; /* Slotted Paging RF Rx Pll settle in symbols.*/ |
| kal_uint32 RxAgcSettle; /* This is updated in frame handler */ |
| kal_uint32 RxAgcSettleShort; /* Short Slotted Paging RxAgc settle in symbols.*/ |
| kal_uint32 RxAgcSettleLong; /* Long Slotted Paging RxAgc settle in symbols.*/ |
| kal_uint32 MiniAcq; /* Buffer Capture, search, and finger allocation delay in ms */ |
| kal_uint32 MiscAdj; /* Time between Resync Lisr to Resync Hisr */ |
| } HscSpBackoffT; |
| |
| typedef struct |
| { |
| FrameRecT WakeFrame; |
| kal_uint32 FRC_Resync; |
| } HscDoStopTxT; |
| |
| typedef struct |
| { /* WARNING! THis structure is reset to 0 before every Resync Time calc */ |
| kal_bool Valid; |
| FrameRecT PchWakeSystemTimeFrame; |
| kal_uint32 Total9MHzDuration; |
| kal_int32 TotalCalValue; |
| kal_int32 Backoff9MHz; |
| SysSFrameTimeT Sframe_PrevResync; |
| SysSFrameTimeT Sframe_Resync; |
| kal_uint32 FRC_Resync; |
| kal_uint32 FRC_Rtb; /* in FRC, for resync polling in frame tick */ |
| } HscResyncT; |
| |
| |
| typedef struct |
| { |
| HscSysAirInterfaceT Owner; |
| kal_uint16 Status; |
| kal_uint8 RfReq; |
| HscResyncT Resync; |
| kal_bool (*InTraffic)(void); |
| kal_uint8 ActiveQnum; |
| kal_bool WakeSchedulePend; |
| kal_uint8 WakeScheLen; /* In frame */ |
| kal_bool ModemWakePend; |
| kal_bool HscShdrWakeup; |
| kal_bool TimeCopyProhibit; |
| } HscAppT; |
| |
| typedef struct |
| { |
| HscAppT *Ptr; |
| void (*DeQueueP) (kal_uint8); |
| } HscQueueT; |
| |
| typedef struct |
| { |
| kal_bool Special1xPreemption; |
| kal_uint8 Priority; |
| HscSysAirInterfaceT ResyncOwner; |
| HscQueueT WakeQueue[HSC_SSM_NUM_WAKE]; |
| HscAppT App[HSC_NUM_APPS]; |
| HscSpBackoffT Backoff; |
| kal_uint32 ScanBackoff[HSC_NUM_APPS]; |
| HscDoStopTxT DoStopTx; |
| kal_uint32 ResyncCollisionBuffer; /* In FRC unit */ |
| kal_bool ShdrModeCheckingFlag; |
| kal_uint32 ShdrModeCheckingTime; |
| } HscSsmStatusT; |
| |
| /* Deep Sleep Request in HSC */ |
| typedef struct |
| { |
| kal_uint32 VetoFlag[HSC_NUM_APPS]; |
| } HscSsmDeepSleepT; |
| |
| |
| /* Deep Sleep Request in HSC */ |
| typedef struct |
| { |
| FrameRecT PchWakeSystemTimeFrame; /* in frame */ |
| kal_uint32 Backoff9MHz; /* in echip */ |
| kal_uint32 AgcSettle; /* in echip */ |
| SysSFrameTimeT SframeResync; /* in supframe+echip */ |
| kal_uint32 FrcResync; /* in FRC */ |
| kal_uint32 FrcRtb; /* in FRC, for resync polling in frame tick */ |
| } HscSsmDoSleepCmdT; |
| |
| typedef struct |
| { |
| FrameRecT PchWakeSystemTimeFrame; /* in frame */ |
| kal_uint32 Backoff9MHz; /* in echip */ |
| SysSFrameTimeT SframeResync; /* in supframe+echip */ |
| kal_uint32 FrcResync; /* in FRC */ |
| kal_uint32 FrcRtb; /* in FRC, for resync polling in frame tick */ |
| } HscSsm1xSleepCmdT; |
| |
| |
| /*---------------------------------------------------------------------------- |
| SPage definitions |
| ----------------------------------------------------------------------------*/ |
| #define SP_STATUS_SP_ENABLED_BN 0 |
| #define SP_STATUS_CAL_DONE_BN 1 |
| #define SP_STATUS_SRCH_DONE_BN 2 |
| #define SP_STATUS_SLEEP_CMD_RECVD_BN 3 |
| #define SP_STATUS_SLEEP_CMD_PEND_BN 4 |
| #define SP_STATUS_STOP_ACK_RECVD_BN 5 |
| #define SP_STATUS_RESYNC_CMPLT_BN 6 /* send RESYNC_IND, WAKE_IND, or THAW_IND if not set */ |
| #define SP_STATUS_MINI_ACQ_CMPLT_BN 7 /* rf is current, a RxActivate request was sent */ |
| #define SP_STATUS_MINI_ACQ_REQ_BN 8 /* Mini Acq is required upon resuming from preemption */ |
| #define SP_STATUS_SP_DISABLE_PEND_BN 9 /* Pending Slotted Disable */ |
| #define SP_STATUS_SUSPENDED_BN 10 |
| #define SP_STATUS_SLEEP_CMD_DISCARD_BN 11 |
| #define SP_STATUS_RESYNC_DENIED_BN 12 |
| |
| #define SP_STATUS_SP_ENABLED (1<<SP_STATUS_SP_ENABLED_BN) /*0x0001*/ |
| #define SP_STATUS_CAL_DONE (1<<SP_STATUS_CAL_DONE_BN) /*0x0002*/ |
| #define SP_STATUS_SRCH_DONE (1<<SP_STATUS_SRCH_DONE_BN) /*0x0004*/ |
| #define SP_STATUS_SLEEP_CMD_RECVD (1<<SP_STATUS_SLEEP_CMD_RECVD_BN) /*0x0008*/ |
| #define SP_STATUS_SLEEP_CMD_PEND (1<<SP_STATUS_SLEEP_CMD_PEND_BN) /*0x0010*/ |
| #define SP_STATUS_STOP_ACK_RECVD (1<<SP_STATUS_STOP_ACK_RECVD_BN) /*0x0020*/ |
| #define SP_STATUS_RESYNC_CMPLT (1<<SP_STATUS_RESYNC_CMPLT_BN) /*0x0040*/ |
| #define SP_STATUS_MINI_ACQ_CMPLT (1<<SP_STATUS_MINI_ACQ_CMPLT_BN) /*0x0080*/ |
| #define SP_STATUS_MINI_ACQ_REQ (1<<SP_STATUS_MINI_ACQ_REQ_BN) /*0x0100*/ |
| #define SP_STATUS_SP_DISABLE_PEND (1<<SP_STATUS_SP_DISABLE_PEND_BN) /*0x0200*/ |
| #define SP_STATUS_SUSPENDED (1<<SP_STATUS_SUSPENDED_BN) /*0x0400*/ |
| #define SP_STATUS_SLEEP_CMD_DISCARD (1<<SP_STATUS_SLEEP_CMD_DISCARD_BN) /*0x0800*/ |
| #define SP_STATUS_RESYNC_DENIED (1<<SP_STATUS_RESYNC_DENIED_BN) /*0x1000*/ |
| |
| #define SP_ENABLING_TRIGGERS (SP_STATUS_SP_ENABLED | SP_STATUS_CAL_DONE) /*0x0003*/ |
| |
| #define SP_EVENT_TRIGGERS (SP_STATUS_SRCH_DONE | \ |
| SP_STATUS_SLEEP_CMD_RECVD | \ |
| SP_STATUS_SLEEP_CMD_PEND | \ |
| SP_STATUS_STOP_ACK_RECVD | \ |
| SP_STATUS_RESYNC_CMPLT ) |
| #define SP_SLEEP_RESET (SP_STATUS_SRCH_DONE | \ |
| SP_STATUS_SLEEP_CMD_RECVD | \ |
| SP_STATUS_SLEEP_CMD_PEND | \ |
| SP_STATUS_STOP_ACK_RECVD | \ |
| SP_STATUS_MINI_ACQ_CMPLT | \ |
| SP_STATUS_MINI_ACQ_REQ | \ |
| SP_STATUS_RESYNC_CMPLT ) |
| #define SP_SUSPEND_RESET (SP_STATUS_SRCH_DONE | \ |
| SP_STATUS_SLEEP_CMD_RECVD | \ |
| SP_STATUS_SLEEP_CMD_PEND | \ |
| SP_STATUS_STOP_ACK_RECVD | \ |
| SP_STATUS_MINI_ACQ_CMPLT ) |
| #define SP_ACTIVATE_RESET (SP_STATUS_SRCH_DONE | \ |
| SP_STATUS_SLEEP_CMD_RECVD | \ |
| SP_STATUS_STOP_ACK_RECVD | \ |
| SP_STATUS_MINI_ACQ_REQ ) |
| |
| |
| typedef struct |
| { |
| kal_uint8 Enabled; |
| kal_uint8 State; |
| kal_uint32 History; |
| kal_uint8 SlotCycleIdx[2]; |
| kal_uint8 CalSettleTime; |
| kal_uint8 ImmediateMode; |
| } HscSpStatusT; |
| |
| typedef struct |
| { |
| kal_uint16 History; |
| kal_uint8 ImmediateMode; |
| } L1dSPageStatusT; |
| |
| typedef enum |
| { |
| SP_STATE_NONSLOTTED = 0, /* slotted page mode is disabled */ |
| SP_STATE_PCH_MONITOR, |
| SP_STATE_WAIT_FOR_STOP_ACK, |
| SP_STATE_SPAGE_SLEEP, |
| SP_STATE_MAX |
| } SpStateT; |
| |
| typedef struct |
| { |
| kal_uint8 RepeatOk; |
| void (*FuncP)(void); |
| kal_uint16 Triggers; |
| kal_uint8 Next; |
| } SpDoStateTblEntryT; |
| |
| typedef struct |
| { |
| SpDoStateTblEntryT State[SP_STATE_MAX]; |
| } HscSpDoStateTblT; |
| |
| |
| typedef struct |
| { |
| HscSysAirInterfaceT ResyncOwner; |
| HscResyncT Resync[HSC_NUM_APPS]; |
| } HscSpResyncRecordT; |
| |
| |
| /*---------------------------------------------------------------------------- |
| HSC OOSA definitions |
| ----------------------------------------------------------------------------*/ |
| typedef enum |
| { |
| OOSA_STATE_INIT = 0, /* slotted page mode is disabled */ |
| OOSA_STATE_IN_SLEEP, |
| OOSA_STATE_ENTERING_SLEEP, |
| OOSA_STATE_WAKE_BEFORE_SLEEP /* OOSA wake cmd assert before OOSA sleep flow finished */ |
| } OosaStateT; |
| |
| #define HSC_OOSA_TYPE_NORMAL (1<<0) |
| #define HSC_OOSA_TYPE_RAVAS_SUSPEND (1<<1) |
| #define HSC_OOSA_TYPE_INFINITE_SLEEP (1<<2) |
| #define HSC_OOSA_TYPE_FLIGHT_MODE (1<<3) |
| #define MAX_OOSA_SLEEP_DURATION_1XRTT (1800) /*unit:0.1s, 180 s for 1xRTT */ |
| #define MAX_OOSA_SLEEP_DURATION_EVDO (6000) /*unit:0.1s, 600 s for 1xRTT */ |
| |
| /* Convert the OOSA sleep duration(unit 0.1 second) to FRC( Unit 1 us), |
| the MAX SLEEP DURATION: 600s for EVDO, 180 s for 1xRTT */ |
| #define M_0P1SEC_TO_FRC(a) ((kal_uint64)a*100000L) |
| |
| typedef struct |
| { |
| kal_uint8 OosaSleepType; |
| OosaStateT OosaState; |
| kal_uint32 StartTime; /* In FRC */ |
| kal_uint32 WakeTime; /* In FRC */ |
| kal_uint32 SleepDuration; /* In 0.1s */ |
| kal_bool WakeupFlag; |
| kal_uint8 OosaWakeupType; |
| } HscOosaT; |
| |
| |
| typedef struct |
| { |
| HscSysAirInterfaceT Owner; |
| } HscOosaSleepEvtT; |
| |
| |
| |
| |
| #if defined (MTK_DEV_C2K_IRAT) && defined (MTK_DEV_C2K_SRLTE_L1) |
| /*---------------------------------------------------------------------------- |
| HSC GAP servive definitions |
| ----------------------------------------------------------------------------*/ |
| typedef struct |
| { |
| kal_bool SltWakePend; /* DO slotted wake pending for GAP stopping */ |
| kal_bool OosaWakePend; /* OOSA wake pending for GAP stopping */ |
| kal_bool ContOosaPend; /* CONT OOSA sleep pending */ |
| kal_uint32 GapEndFrame; /* Frame number of GAP end when DO slotted sleep */ |
| kal_uint32 ContSleepDuration; /* in 100ms */ |
| kal_bool GapGate; /* KAL_TRUE: means can't offer gap to MD1 */ |
| } HscGapT; |
| #endif |
| |
| |
| /*---------------------------------------------------------------------------- |
| HSC General definitions |
| ----------------------------------------------------------------------------*/ |
| typedef enum |
| { |
| HSC_OOSA_TIMER_1X_ID, |
| HSC_OOSA_TIMER_DO_ID, |
| HSC_CLK_CAL_FAST_SETTLE_TIMER_ID, |
| HSC_SHDR_MODE_TIMER_ID, |
| HSC_NUM_TIMERS |
| } HscTimerIds; |
| |
| typedef enum |
| { |
| HSC_T_MPA_ANT_AVAILABLE, |
| HSC_T_MPA_ANT_ASSIGNED |
| }HscAntStatusT; |
| |
| |
| #if defined (MTK_DEV_C2K_IRAT) && defined (MTK_DEV_C2K_SRLTE_L1) |
| /* GAP servive */ |
| extern HscGapT HscGap; |
| #endif |
| |
| |
| |
| /***************************************************************************** |
| * $Log: hscdefs.h $ |
| *****************************************************************************/ |
| |
| /***************************************************************************** |
| * End of File |
| *****************************************************************************/ |
| #endif |
| /**Log information: \main\Trophy\Trophy_ylxiao_href22033\1 2013-03-18 14:14:24 GMT ylxiao |
| ** HREF#22033, merge 4.6.0**/ |
| /**Log information: \main\Trophy\1 2013-03-19 05:18:41 GMT hzhang |
| ** HREF#22033 to merge 0.4.6 code from SD.**/ |
| /**Log information: \main\Trophy\Trophy_jluo_href22084\1 2013-04-03 04:11:28 GMT jluo |
| ** HREF#22084:HANDROID#1723**/ |
| /**Log information: \main\Trophy\2 2013-04-03 06:24:59 GMT czhang |
| ** HREF#22084**/ |
| |