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192.168.1.100 / T800_MD_V1.6 / c33b3079c38f91561c2f84f1ebed20ad8c60532a / . / mcu / driver / peripheral / inc / i2c.h
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yu.dongc33b3072024-08-21 23:14:49 -0700[diff] [blame^]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * sccb_v2.h
41 *
42 *
43 * Description:
44 * ------------
45 * SCCB/I2C V2 Driver
46 *
47 * Author:
48 * -------
49 * -------
50 *
51 *============================================================================
52 * HISTORY
53 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
54 *------------------------------------------------------------------------------
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193 *
194 *------------------------------------------------------------------------------
195 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
196 *============================================================================
197 *****************************************************************************/
198#ifndef __I2C_H__
199#define __I2C_H__
200
201#include "drv_features_i2c.h"
202#include "dcl_i2c_owner.h"
203
204#if (defined(DRV_I2C_25_SERIES))
205
206#include "drv_comm.h"
207
208#include "kal_general_types.h"
209#include "reg_base.h"
210
211#ifdef I2C_V2_DVT
212 #if !defined(DRV_I2C_DMA_ENABLED)
213 #define DRV_I2C_DMA_ENABLED
214 #endif // #if !defined(DRV_I2C_DMA_ENABLED)
215#endif // #ifdef I2C_V2_DVT
216
217
218#ifndef __DRV_DEBUG_I2C_REG_READ_WRITE__
219#define DRV_I2C_ClearBits16(addr, data) DRV_ClearBits(addr,data)
220#define DRV_I2C_SetBits16(addr, data) DRV_SetBits(addr,data)
221#define DRV_I2C_WriteReg16(addr, data) DRV_WriteReg(addr, data)
222#define DRV_I2C_ReadReg16(addr) DRV_Reg(addr)
223#define DRV_I2C_SetData16(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
224#else // #ifndef __DRV_DEBUG_PMU_REG_READ_WRITE__
225#define DRV_I2C_ClearBits16(addr,data) DRV_DBG_ClearBits(addr,data)
226#define DRV_I2C_SetBits16(addr) DRV_DBG_SetBits(addr)
227#define DRV_I2C_WriteReg16(addr, data) DRV_DBG_WriteReg(addr, data)
228#define DRV_I2C_ReadReg16(addr) DRV_DBG_Reg(addr)
229#define DRV_I2C_SetData16(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
230#endif // #ifndef __DRV_DEBUG_PMU_REG_READ_WRITE__
231
232#define SCCB_MAXIMUM_TRANSACTION_LENGTH 8 // SCCB backward compatible
233
234
235#if defined(DRV_I2C_CLOCK_RATE_15_360_MHZ)
236#define I2C_CLOCK_RATE 15360 //15.36MHz
237#elif defined(DRV_I2C_CLOCK_RATE_3_000_MHZ)
238#define I2C_CLOCK_RATE 3000 //3.0MHz
239#else // #if defined(DRV_I2C_CLOCK_RATE_15_360_MHZ)
240#define I2C_CLOCK_RATE 13000 //13MHz
241#endif // #if defined(DRV_I2C_CLOCK_RATE_15_360_MHZ)
242
243
244#if (defined(DRV_I2C_DMA_ENABLED))
245#include "dma_hw.h"
246 #include "dma_sw.h"
247 #if (defined(__DMA_API_V2__))
248 #define DRV_I2C_USE_DMA_V2_API // 76 and later chips are all applied V2 DMA API
249 #else
250 #define DRV_I2C_USE_DMA_V1_API // 35, 38, 39, 53, 68, 36 chips are all applied V1 DMA API
251 #endif
252#endif // #if (defined(DRV_I2C_DMA_ENABLED))
253
254// Some common structures are defined in sccb.h
255
256typedef enum
257{
258 I2C_TRANSACTION_COMPLETE,
259 I2C_TRANSACTION_FAIL,
260 I2C_TRANSACTION_IS_BUSY,
261 I2C_TRANSACTION_ACKERR,
262 I2C_TRANSACTION_HS_NACKERR,
263 I2C_TRANSACTION_SUCCESS,
264 I2C_TRANSACTION_TIMEOUT
265}I2C_TRANSACTION_RESULT;
266
267
268typedef enum
269{
270 I2C_IDLE_STATE = 0,
271 I2C_READY_STATE,
272 I2C_BUSY_STATE
273}I2C_STATE;
274
275/* Transaction mode for new SCCB APIs */
276typedef enum
277{
278 I2C_TRANSACTION_FAST_MODE,
279 I2C_TRANSACTION_HIGH_SPEED_MODE
280}I2C_TRANSACTION_MODE;
281
282/* Transaction type for batch transaction */
283typedef enum
284{
285 I2C_TRANSACTION_WRITE,
286 I2C_TRANSACTION_READ,
287 I2C_TRANSACTION_CONT_WRITE,
288 I2C_TRANSACTION_CONT_READ,
289 I2C_TRANSACTION_WRITE_AND_READ
290}I2C_TRANSACTION_TYPE;
291
292typedef struct
293{
294 kal_uint8 *data;
295 kal_uint32 data_len;
296}i2c_single_write_struct, i2c_single_read_struct;
297/* For I2C_CMD_CONT_WRITE, I2C_CMD_CONT_READ command. */
298typedef struct
299{
300 kal_uint8 *data;
301 kal_uint32 data_len;
302 kal_uint32 transfer_num;
303}i2c_cont_write_struct, i2c_cont_read_struct;
304/* For I2C_CMD_WRITE_AND_READ command. */
305typedef struct
306{
307 kal_uint8 *indata;
308 kal_uint32 indata_len;
309 kal_uint8 *outdata;
310 kal_uint32 outdata_len;
311}i2c_write_and_read_struct;
312/* */
313typedef union
314{
315 i2c_single_write_struct single_write;
316 i2c_single_read_struct single_read;
317 i2c_cont_write_struct cont_write;
318 i2c_cont_write_struct cont_read;
319 i2c_write_and_read_struct write_and_read;
320}i2c_transaction_data_struct;
321/* For I2C_CMD_SINGLE_BATCH command. */
322typedef struct
323{
324 I2C_TRANSACTION_TYPE transaction_type;
325 i2c_transaction_data_struct transaction_data;
326}i2c_batch_data_struct;
327
328typedef enum
329{
330#if defined(DRV_I2C_CLOCK_RATE_15_360_MHZ)
331 // Module source clock is 15.36Mhz
332 I2C_100KB, //99.74KB
333 I2C_200KB, //196.9KB
334 I2C_300KB, //295.4KB
335 I2C_400KB, //384.0KB
336 /* HS Mode */
337 I2C_960KB, //960.0KB
338 I2C_1280KB, //1280.0KB
339 I2C_1536KB, //1536.0KB
340 I2C_1920KB, //1920.0KB
341 I2C_2560KB, //2560.0KB
342 I2C_3840KB //3840.0KB
343#elif defined(DRV_I2C_CLOCK_RATE_3_000_MHZ)
344 // Module source clock is 3.0Mhz
345 I2C_100KB, //100.0KB
346 I2C_200KB, //196.9KB
347 I2C_400KB, //384.0KB
348 /* HS Mode */
349 I2C_750KB, //750.0KB
350 I2C_1500KB //1500.0KB
351#else // #if defined(DRV_I2C_CLOCK_RATE_15_360_MHZ)
352 // Module source clock is 13Mhz
353 I2C_100KB, //101.5KB
354 I2C_200KB, //203.1KB
355 I2C_300KB, //295.5KB
356 I2C_400KB, //382.4KB
357 /* HS Mode */
358 I2C_460KB, //464.3KB
359 I2C_540KB, //541.7KB
360 I2C_650KB, //650.0KB
361 I2C_720KB, //722.0KB
362
363 I2C_810KB, //812.5KB
364 I2C_930KB, //928.6KB
365 I2C_1100KB, //1083.3KB
366 I2C_1300KB, //1300.0KB
367 I2C_1625KB, //1625.0KB
368 I2C_2150KB, //2166.6KB
369 I2C_3250KB //3250.6KB
370#endif // #if defined(DRV_I2C_CLOCK_RATE_15_360_MHZ)
371}I2C_SPEED_ENUM;
372
373typedef struct
374{
375 //kal_uint8 sccb_mode; // Transaction mode for existing SCCB APIs
376
377 kal_bool get_handle_wait; //When get handle wait until the I2C is avaliable
378
379 kal_uint8 slave_address; //the address of the slave device
380
381 kal_uint8 delay_len; //number of half pulse between transfers in a trasaction
382
383 I2C_TRANSACTION_MODE transaction_mode; //I2C_TRANSACTION_FAST_MODE or I2C_TRANSACTION_HIGH_SPEED_MODE
384
385 kal_uint16 Fast_Mode_Speed; //The speed of I2C fast mode(Kb)
386
387 kal_uint16 HS_Mode_Speed; //The speed of I2C high speed mode(Kb)
388
389 #if (defined(DRV_I2C_DMA_ENABLED))
390 kal_bool is_DMA_enabled; //Transaction via DMA instead of 8-byte FIFO
391 #endif // #if (defined(DRV_I2C_DMA_ENABLED))
392
393}i2c_config_struct;
394
395typedef struct
396{
397 i2c_config_struct i2c_config;
398
399 kal_uint8 fs_sample_cnt_div; //these two parameters are used to specify I2C clock rate
400 kal_uint8 fs_step_cnt_div; //half pulse width=step_cnt_div*sample_cnt_div*(1/13Mhz)
401
402 kal_uint8 hs_sample_cnt_div; //these two parameters are used to specify I2C clock rate
403 kal_uint8 hs_step_cnt_div; //half pulse width=step_cnt_div*sample_cnt_div*(1/13Mhz)
404
405 I2C_TRANSACTION_RESULT transaction_result; /* The result of the end of transaction
406 (I2C_TRANSACTION_COMPLETE|I2C_TRANSACTION_FAIL) */
407
408}i2c_handle_struct;
409
410typedef struct
411{
412 volatile I2C_STATE state;
413 DCL_I2C_OWNER owner;
414
415 kal_uint8 number_of_read;
416 kal_uint8* read_buffer;
417
418 #if (defined(DRV_I2C_DMA_ENABLED))
419 kal_bool is_DMA_enabled;
420 #endif // #if (defined(DRV_I2C_DMA_ENABLED))
421
422}i2c_status_struct;
423
424
425
426#ifndef DRV_I2C_OFF
427/* Register Definitions */
428#define REG_I2C_DATA_PORT (I2C_base + 0x00)
429#define REG_I2C_SLAVE_ADDR (I2C_base + 0x04)
430#define REG_I2C_INT_MASK (I2C_base + 0x08)
431#define REG_I2C_INT_STA (I2C_base + 0x0c)
432#define REG_I2C_CONTROL (I2C_base + 0x10)
433#define REG_I2C_TRANSFER_LEN (I2C_base + 0x14)
434#define REG_I2C_TRANSAC_LEN (I2C_base + 0x18)
435#define REG_I2C_DELAY_LEN (I2C_base + 0x1c)
436#define REG_I2C_TIMING (I2C_base + 0x20)
437#define REG_I2C_START (I2C_base + 0x24)
438#define REG_I2C_FIFO_STAT (I2C_base + 0x30)
439#define REG_I2C_FIFO_THRESH (I2C_base + 0x34)
440#define REG_I2C_FIFO_ADDR_CLR (I2C_base + 0x38)
441#define REG_I2C_IO_CONFIG (I2C_base + 0x40)
442#define REG_I2C_MULTI_MASTER (I2C_base + 0x44)
443#define REG_I2C_HS_MODE (I2C_base + 0x48)
444#define REG_I2C_SOFTRESET (I2C_base + 0x50)
445#define REG_I2C_TRANSFER_LEN_AUX (I2C_base + 0x6C) ///new from MT6256E2
446#define REG_I2C_HW_Version (I2C_base + 0x78)
447#define REG_I2C_DBG_STA (I2C_base + 0x64) //only for debug
448#define REG_I2C_TIMEOUT_TIMING (I2C_base + 0x74) //timeout timing reg
449#endif // DRV_I2C_OFF
450
451/* Register masks */
452#define I2C_1_BIT_MASK 0x01
453#define I2C_3_BIT_MASK 0x07
454#define I2C_4_BIT_MASK 0x0f
455#define I2C_6_BIT_MASK 0x3f
456#define I2C_8_BIT_MASK 0xff
457#define I2C_16_BIT_MASK 0xffff
458
459#define I2C_RX_FIFO_THRESH_MASK 0x0007
460#define I2C_RX_FIFO_THRESH_SHIFT 0
461#define I2C_TX_FIFO_THRESH_MASK 0x0700
462#define I2C_TX_FIFO_THRESH_SHIFT 8
463
464#define I2C_AUX_LEN_MASK 0x1f00
465#define I2C_AUX_LEN_SHIFT 8
466
467#define I2C_SAMPLE_CNT_DIV_MASK 0x0700
468#define I2C_SAMPLE_CNT_DIV_SHIFT 8
469#define I2C_DATA_READ_TIME_MASK 0x7000
470#define I2C_DATA_READ_TIME_SHIFT 12
471
472#define I2C_MASTER_READ 0x01
473#define I2C_MASTER_WRITE 0x00
474
475//#define I2C_CTL_MODE_BIT 0x01
476#define I2C_CTL_RS_STOP_BIT 0x02
477#define I2C_CTL_DMA_EN_BIT 0x04
478#define I2C_CTL_CLK_EXT_EN_BIT 0x08
479#define I2C_CTL_DIR_CHANGE_BIT 0x10
480#define I2C_CTL_ACK_ERR_DET_BIT 0x20
481#define I2C_CTL_TRANSFER_LEN_CHG_BIT 0x40
482
483#define I2C_DATA_READ_ADJ_BIT 0x8000
484
485#define I2C_SCL_MODE_BIT 0x01
486#define I2C_SDA_MODE_BIT 0x02
487#define I2C_BUS_DETECT_EN_BIT 0x04
488
489#define I2C_ARBITRATION_BIT 0x01
490#define I2C_CLOCK_SYNC_BIT 0x02
491#define I2C_BUS_BUSY_DET_BIT 0x04
492
493#define I2C_HS_EN_BIT 0x01
494#define I2C_HS_NACK_ERR_DET_EN_BIT 0x02
495#define I2C_HS_MASTER_CODE_MASK 0x0070
496#define I2C_HS_MASTER_CODE_SHIFT 4
497#define I2C_HS_STEP_CNT_DIV_MASK 0x0700
498#define I2C_HS_STEP_CNT_DIV_SHIFT 8
499#define I2C_HS_SAMPLE_CNT_DIV_MASK 0x7000
500#define I2C_HS_SAMPLE_CNT_DIV_SHIFT 12
501
502/* I2C Status */
503#define I2C_FIFO_FULL_STATUS 0x01
504#define I2C_FIFO_EMPTY_STATUS 0x02
505
506/* Register Settings */
507#define SET_I2C_SLAVE_ADDRESS(n,rw) do{DRV_I2C_SetData16(REG_I2C_SLAVE_ADDR, I2C_8_BIT_MASK, (((n>>1)<<1) + rw));} while(0);
508
509#define DISABLE_I2C_INT do{DRV_I2C_WriteReg16(REG_I2C_INT_MASK, 0);} while(0);
510#define ENABLE_I2C_INT do{DRV_I2C_WriteReg16(REG_I2C_INT_MASK,I2C_1_BIT_MASK);} while(0);
511
512#define CLEAR_I2C_STA do{DRV_I2C_WriteReg16(REG_I2C_INT_STA, I2C_4_BIT_MASK);} while(0);
513
514//#define SET_I2C_FAST_SPEED_MODE REG_I2C_CONTROL &= ~I2C_CTL_MODE_BIT;
515//#define SET_I2C_HIGH_SPEED_MODE REG_I2C_CONTROL |= I2C_CTL_MODE_BIT;
516
517#define SET_I2C_ST_BETWEEN_TRANSFER do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_RS_STOP_BIT);} while(0);
518#define SET_I2C_RS_BETWEEN_TRANSFER do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_RS_STOP_BIT);} while(0);
519#define ENABLE_I2C_DMA_TRANSFER do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_DMA_EN_BIT);} while(0);
520#define ENABLE_I2C_CLOCK_EXTENSION do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_CLK_EXT_EN_BIT);} while(0);
521#define ENABLE_I2C_DIR_CHANGE do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_DIR_CHANGE_BIT);} while(0);
522#define ENABLE_I2C_ACK_ERR_DET do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_ACK_ERR_DET_BIT);} while(0);
523#define ENABLE_I2C_TRANSFER_LEN_CHG do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_TRANSFER_LEN_CHG_BIT);} while(0);
524#define ENABLE_I2C_BUS_BUSY_RESET do{DRV_I2C_SetBits16(REG_I2C_CONTROL, 0x80);} while(0);
525#define ENABLE_I2C_TIMEOUT do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_TIMEOUT);} while(0);
526
527#define DISABLE_I2C_DMA_TRANSFER do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_DMA_EN_BIT);} while(0);
528#define DISABLE_I2C_CLOCK_EXTENSION do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_CLK_EXT_EN_BIT);} while(0);
529#define DISABLE_I2C_DIR_CHANGE do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_DIR_CHANGE_BIT);} while(0);
530#define DISABLE_I2C_ACK_ERR_DET do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_ACK_ERR_DET_BIT);} while(0);
531#define DISABLE_I2C_TRANSFER_LEN_CHG do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_TRANSFER_LEN_CHG_BIT);} while(0);
532#define DISABLE_I2C_BUS_BUSY_RESET do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, 0x80);} while(0);
533#define DISABLE_I2C_TIMEOUT do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_TIMEOUT);} while(0);
534
535#ifdef DRV_I2C_MAX_65535_TRANSFER_LENGTH
536#define SET_I2C_TRANSFER_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_TRANSFER_LEN, I2C_16_BIT_MASK, (n));} while(0);
537#define SET_I2C_AUX_TRANSFER_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_TRANSFER_LEN_AUX, I2C_16_BIT_MASK, (n));} while(0);
538#else
539#define SET_I2C_TRANSFER_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_TRANSFER_LEN, I2C_8_BIT_MASK, (n));} while(0);
540#define SET_I2C_AUX_TRANSFER_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_TRANSFER_LEN, I2C_AUX_LEN_MASK, ((n)<<I2C_AUX_LEN_SHIFT));} while(0);
541#endif
542
543#define SET_I2C_TRANSACTION_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_TRANSAC_LEN, I2C_8_BIT_MASK, (n));} while(0);
544#define SET_I2C_DELAY_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_DELAY_LEN, I2C_8_BIT_MASK, (n));} while(0);
545
546#define SET_I2C_STEP_CNT_DIV(n) do{DRV_I2C_SetData16(REG_I2C_TIMING, I2C_6_BIT_MASK, (n));} while(0);
547#define SET_I2C_SAMPLE_CNT_DIV(n) do{DRV_I2C_SetData16(REG_I2C_TIMING, I2C_SAMPLE_CNT_DIV_MASK, ((n)<<I2C_SAMPLE_CNT_DIV_SHIFT));} while(0);
548#define SET_I2C_DATA_READ_TIME(n) do{DRV_I2C_SetData16(REG_I2C_TIMING, I2C_DATA_READ_TIME_MASK, ((n)<<I2C_DATA_READ_TIME_SHIFT));} while(0);
549#define ENABLE_I2C_DATA_READ_ADJ do{DRV_I2C_SetBits16(REG_I2C_TIMING, I2C_DATA_READ_ADJ_BIT);} while(0);
550#define DISABLE_I2C_DATA_READ_ADJ do{DRV_I2C_ClearBits16(REG_I2C_TIMING, I2C_DATA_READ_ADJ_BIT);} while(0);
551
552#define START_I2C_TRANSACTION do{DRV_I2C_WriteReg16(REG_I2C_START, 0x01);} while(0);
553
554// #define I2C_FIFO_FULL ((REG_I2C_FIFO_STAT>>1)&0x01)
555// #define I2C_FIFO_EMPTY (REG_I2C_FIFO_STAT & 0x01)
556
557#define SET_I2C_RX_FIFO_THRESH(n) do{DRV_I2C_SetData16(REG_I2C_FIFO_THRESH, I2C_RX_FIFO_THRESH_MASK, ((n)<< I2C_RX_FIFO_THRESH_SHIFT));} while(0);
558#define SET_I2C_TX_FIFO_THRESH(n) do{DRV_I2C_SetData16(REG_I2C_FIFO_THRESH, I2C_TX_FIFO_THRESH_MASK, ((n)<< I2C_TX_FIFO_THRESH_SHIFT));} while(0);
559
560#define CLEAR_I2C_FIFO do{DRV_I2C_WriteReg16(REG_I2C_FIFO_ADDR_CLR, 0x01);} while(0);
561
562#define SET_I2C_SCL_NORMAL_MODE do{DRV_I2C_ClearBits16(REG_I2C_IO_CONFIG, I2C_SCL_MODE_BIT);} while(0);
563#define SET_I2C_SCL_WIRED_AND_MODE do{DRV_I2C_SetBits16(REG_I2C_IO_CONFIG, I2C_SCL_MODE_BIT);} while(0);
564#define SET_I2C_SDA_NORMAL_MODE do{DRV_I2C_ClearBits16(REG_I2C_IO_CONFIG, I2C_SDA_MODE_BIT);} while(0);
565#define SET_I2C_SDA_WIRED_AND_MODE do{DRV_I2C_SetBits16(REG_I2C_IO_CONFIG, I2C_SDA_MODE_BIT);} while(0);
566#define ENABLE_I2C_BUS_DETECT do{DRV_I2C_SetBits16(REG_I2C_IO_CONFIG, I2C_BUS_DETECT_EN_BIT);} while(0);
567#define DISABLE_I2C_BUS_DETECT do{DRV_I2C_ClearBits16(REG_I2C_IO_CONFIG, I2C_BUS_DETECT_EN_BIT);} while(0);
568
569#define ENABLE_I2C_CLOCK_SYNC do{DRV_I2C_SetBits16(REG_I2C_MULTI_MASTER, I2C_ARBITRATION_BIT);} while(0);
570#define ENABLE_DATA_ARBITION do{DRV_I2C_SetBits16(REG_I2C_MULTI_MASTER, I2C_CLOCK_SYNC_BIT);} while(0);
571#define ENABLE_I2C_BUS_BUSY_DET do{DRV_I2C_SetBits16(REG_I2C_MULTI_MASTER, I2C_BUS_BUSY_DET_BIT);} while(0);
572#define DISABLE_I2C_CLOCK_SYNC do{DRV_I2C_ClearBits16(REG_I2C_MULTI_MASTER, I2C_ARBITRATION_BIT);} while(0);
573#define DISABLE_DATA_ARBITION do{DRV_I2C_ClearBits16(REG_I2C_MULTI_MASTER, I2C_CLOCK_SYNC_BIT);} while(0);
574#define DISABLE_I2C_BUS_BUSY_DET do{DRV_I2C_ClearBits16(REG_I2C_MULTI_MASTER, I2C_BUS_BUSY_DET_BIT);} while(0);
575
576#define SET_I2C_HIGH_SPEED_MODE_800KB do{DRV_I2C_WriteReg16(REG_I2C_HS_MODE, 0x0703);} while(0);
577#define SET_I2C_HIGH_SPEED_MODE_1000KB do{DRV_I2C_WriteReg16(REG_I2C_HS_MODE, 0x0503);} while(0);
578
579#define SET_I2C_FAST_MODE do{DRV_I2C_ClearBits16(REG_I2C_HS_MODE, I2C_HS_EN_BIT);} while(0);
580#define SET_I2C_HS_MODE do{DRV_I2C_SetBits16(REG_I2C_HS_MODE, I2C_HS_EN_BIT);} while(0);
581#define ENABLE_I2C_NAKERR_DET do{DRV_I2C_SetBits16(REG_I2C_HS_MODE, I2C_HS_NACK_ERR_DET_EN_BIT);} while(0);
582#define DISABLE_I2C_NAKERR_DET do{DRV_I2C_ClearBits16(REG_I2C_HS_MODE, I2C_HS_NACK_ERR_DET_EN_BIT);} while(0);
583#define SET_I2C_HS_MASTER_CODE(n) do{DRV_I2C_SetData16(REG_I2C_HS_MODE, I2C_HS_MASTER_CODE_MASK, ((n)<<I2C_HS_MASTER_CODE_SHIFT));} while(0);
584
585#define SET_I2C_HS_STEP_CNT_DIV(n) do{DRV_I2C_SetData16(REG_I2C_HS_MODE, I2C_HS_STEP_CNT_DIV_MASK, ((n)<<I2C_HS_STEP_CNT_DIV_SHIFT));} while(0);
586#define SET_I2C_HS_SAMPLE_CNT_DIV(n) do{DRV_I2C_SetData16(REG_I2C_HS_MODE, I2C_HS_SAMPLE_CNT_DIV_MASK, ((n)<<I2C_HS_SAMPLE_CNT_DIV_SHIFT));} while(0);
587
588#define RESET_I2C do{DRV_I2C_WriteReg16(REG_I2C_SOFTRESET, 0x01);} while(0);
589
590//---------------- DMA ----------------
591#if defined(DRV_I2C_DIRECT_CONFIG_DMA_REGISTER)
592
593//#define DMA_base 0x80030000 -->defined in /inc/reg_base.h
594
595/* Regidter Definitions */
596#define REG_DMA_CHANNEL_CONTROL(c) *((volatile unsigned int *) (DMA_base + 0x14+ (c<<8)))
597#define REG_DMA_CHANNEL_START(c) *((volatile unsigned int *) (DMA_base + 0x18+ (c<<8)))
598#define REG_DMA_PROG_ADDR(c) *((volatile unsigned int *) (DMA_base + 0x2c+ (c<<8)))
599#define REG_DMA_TRANSFER_COUNT(c) *((volatile unsigned int *) (DMA_base + 0x10+ (c<<8)))
600
601/* Master Definitions*/
602#define DMA_MASTER_I2C_TX DMA_CON_MASTER_I2CTX
603#define DMA_MASTER_I2C_RX DMA_CON_MASTER_I2CRX
604#define DMA_MASTER_IRDA_TX 0x02
605#define DMA_MASTER_IRDA_RX 0x03
606
607#define DMA_I2C_TX_CHANNEL 4
608#define DMA_I2C_RX_CHANNEL 5
609
610/* Register masks */
611#define DMA_CON_DIR_MASK 0x40000
612#define DMA_CON_MAS_MASK 0x01f00000
613
614#define I2C_SET_TX_DMA_CONTROL(c,m) REG_DMA_CHANNEL_CONTROL(c) = 0x00000014;\
615 REG_DMA_CHANNEL_CONTROL(c) |= (((m)<<20) & DMA_CON_MAS_MASK);
616
617#define I2C_SET_RX_DMA_CONTROL(c,m) REG_DMA_CHANNEL_CONTROL(c) = 0x00040018;\
618 REG_DMA_CHANNEL_CONTROL(c) |= (((m)<<20) & DMA_CON_MAS_MASK);
619
620#define I2C_SET_DMA_PROGRAMMABLE_ADDR(c,addr) REG_DMA_PROG_ADDR(c) = (addr);
621#define I2C_SET_DMA_TRANSFER_COUNT(c,size) REG_DMA_TRANSFER_COUNT(c)= size ;
622#define I2C_START_DMA_TRANSFER(c) REG_DMA_CHANNEL_START(c) = 0x8000;
623#define I2C_STOP_DMA_TRANSFER(c) REG_DMA_CHANNEL_START(c) = 0;
624
625#endif // #if defined(DRV_I2C_DIRECT_CONFIG_DMA_REGISTER)
626
627/****** SW definitions******/
628#define I2C_READ_BIT 0x01
629#define I2C_WRITE_BIT 0x00
630
631#define I2C_TRANSAC_COMPLETE 0x01
632#define I2C_TRANSAC_ACK_ERR 0x02
633#define I2C_HS_NACK_ERR 0x04
634#define I2C_TIMEOUT 0x10
635
636//extern kal_bool dcl_i2c_init_done_flag;
637//extern i2c_handle_struct i2c_handle[DCL_I2C_NUM_OF_OWNER];
638
639void dcl_i2c_init(void);
640extern void dcl_i2c_hw_cfg (DCL_I2C_OWNER owner, I2C_TRANSACTION_TYPE type, kal_uint8* write_buffer, kal_uint32 write_len, kal_uint8* read_buffer, kal_uint32 read_len, kal_uint32 transfer_num);
641void dcl_i2c_set_transaction_speed(DCL_I2C_OWNER owner,I2C_TRANSACTION_MODE mode,kal_uint16* Fast_Mode_Speed,kal_uint16* HS_Mode_Speed);
642extern kal_uint32 dcl_i2c_wait_transaction_complete_and_lock(DCL_I2C_OWNER owner);
643void dcl_i2c_wait_transaction_complete(kal_uint32 savedMask);
644#if defined(DRV_I2C_BATCH_TRANSACTION_SUPPORT)
645I2C_TRANSACTION_RESULT dcl_i2c_get_batch_transaction_result(DCL_I2C_OWNER owner,kal_uint32* batch_num);
646I2C_TRANSACTION_RESULT dcl_i2c_batch_transaction(DCL_I2C_OWNER owner, i2c_batch_data_struct *batch_data, kal_uint32 batch_num);
647#endif // #if (defined(DRV_I2C_DMA_ENABLED))
648
649#endif // #if (defined(DRV_I2C_25_SERIES))
650
651void CameraSccbPadEnable(kal_bool On);
652#endif // #ifndef __I2C_H__
653