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192.168.1.100 / T800_MD_V1.6 / c33b3079c38f91561c2f84f1ebed20ad8c60532a / . / mcu / driver / peripheral / inc / pwm_sw.h
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yu.dongc33b3072024-08-21 23:14:49 -0700[diff] [blame^]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * pwm_sw.h
41 *
42 * Project:
43 * --------
44 * Maui_Software
45 *
46 * Description:
47 * ------------
48 * This file is intended for PWM driver.
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
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194 *------------------------------------------------------------------------------
195 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
196 *============================================================================
197 ****************************************************************************/
198#ifndef PWM_SW_H
199#define PWM_SW_H
200
201#include "drv_features_pwm.h"
202#include "rwg_sw.h"
203#include "kal_general_types.h"
204#include "dcl.h"
205#include "drv_comm.h"
206
207#if !defined(DRV_PWM_RWG)
208
209//this should move to pwm_sw.h
210#if defined(DRV_PWM_PWM2)
211#if defined(DRV_PWM_PWM3)
212#if defined(DRV_PWM_PWM4)
213#define PWM_COUNT 4
214#else //defined(DRV_PWM_PWM4)
215#define PWM_COUNT 3
216#endif//defined(DRV_PWM_PWM4)
217#else //defined(DRV_PWM_PWM3)
218#define PWM_COUNT 2
219#endif //defined(DRV_PWM_PWM3)
220#else //defined(DRV_PWM_PWM2)
221#define PWM_COUNT 1
222#endif//defined(DRV_PWM_PWM2)
223
224typedef enum
225{
226 pwmclk_1MHZ=0,
227 pwmclk_2MHZ,
228 pwmclk_4MHZ,
229 pwmclk_8MHZ
230}PWMClock_DIV;
231
232typedef enum
233{
234 pwmclk_13M=0,
235 pwmclk_32k
236}PWMClock_SEL;
237
238typedef enum
239{
240 PWM1=0,
241 PWM2,
242 PWM3,
243 PWM4
244}PWM_TYPE;
245
246typedef void (*DCL_PWM_INIT)(void);
247typedef void (*DCL_PWM_CLK_INIT)(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 clk_sel, kal_uint32 clk_div);
248typedef void (*DCL_PWM_START)(DCL_UINT8 owner, DCL_UINT32 pwm_num);
249typedef void (*DCL_PWM_STOP)(DCL_UINT8 owner, DCL_UINT32 pwm_num);
250typedef void (*DCL_PWM_CONFIG_OLD)(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 freq, kal_uint8 duty);
251typedef DCL_UINT8 (*DCL_PWM_GETCURRENT_LEVEL)(DCL_UINT8 pwm_num);
252typedef DCL_UINT32(*DCL_PWM_GETCURRENT_FREQ)(DCL_UINT8 pwm_num);
253typedef DCL_UINT8 (*DCL_PWM_GETCURRENT_DUTY)(DCL_UINT8 pwm_num);
254
255typedef struct
256{
257 DCL_PWM_INIT pwmInit;
258 DCL_PWM_CLK_INIT pwmClkInit;
259 DCL_PWM_START pwmStart;
260 DCL_PWM_STOP pwmStop;
261 DCL_PWM_GETCURRENT_LEVEL pwmGetCurrent_level;
262 DCL_PWM_GETCURRENT_FREQ pwmGetCurrent_Freq;
263 DCL_PWM_GETCURRENT_DUTY pwmGetCurrent_Duty;
264 DCL_PWM_CONFIG_OLD pwmConfigOld;
265}PWMDriver_t;
266
267extern void DCL_PWM_Init(void);
268extern void DCL_PWM_SetClock(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 clk_sel, kal_uint32 clk_div);
269extern void DCL_PWM_Start(kal_uint8 owner, kal_uint32 pwm_num);
270extern void DCL_PWM_Stop(kal_uint8 owner, kal_uint32 pwm_num);
271extern void DCL_PWM_ConfigOld(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 freq, kal_uint8 duty);
272extern kal_uint8 DCL_PWM_GetCurrent_Level(kal_uint8 pwm_num);
273extern kal_uint8 DCL_PWM_GetCurrentDuty(kal_uint8 pwm_num);
274extern kal_uint32 DCL_PWM_GetCurrentFreq(kal_uint8 pwm_num);
275
276
277extern void PWM_Init(PWMClock_SEL clk_sel,PWMClock_DIV Clock_div);
278extern void PWM1_Configure(kal_uint32 freq, kal_uint8 duty);
279extern void PWM1_Start(void);
280extern void PWM1_Stop(void);
281extern kal_uint8 PWM1_GetCurrentLevel(void);
282extern kal_uint8 PMW1_GetCurrentDuty(void);
283extern kal_uint32 PMW1_GetCurrentFreq(void);
284#if defined(DRV_PWM_PWM2)
285 extern void PWM2_Init(PWMClock_SEL clk_sel,PWMClock_DIV Clock_div);
286 extern void PWM2_Configure(kal_uint32 freq, kal_uint8 duty);
287 extern void PWM2_Start(void);
288 extern void PWM2_Stop(void);
289 extern kal_uint8 PWM2_GetCurrentLevel(void);
290 extern kal_uint8 PMW2_GetCurrentDuty(void);
291 extern kal_uint32 PMW2_GetCurrentFreq(void);
292#if defined(DRV_PWM_PWM3)
293 extern void PWM3_Init(PWMClock_SEL clk_sel,PWMClock_DIV Clock_div);
294 extern void PWM3_Configure(kal_uint32 freq, kal_uint8 duty);
295 extern void PWM3_Start(void);
296 extern void PWM3_Stop(void);
297 extern kal_uint8 PWM3_GetCurrentLevel(void);
298 extern kal_uint8 PMW3_GetCurrentDuty(void);
299 extern kal_uint32 PMW3_GetCurrentFreq(void);
300#if defined(__DRV_PMU53_SPEC_V2__)
301extern void PWM3_Output_High(void);
302#endif //#if defined(__DRV_PMU53_SPEC_V2__)
303#if defined(DRV_PWM_PWM4)
304 extern void PWM4_Init(PWMClock_SEL clk_sel,PWMClock_DIV Clock_div);
305 extern void PWM4_Configure(kal_uint32 freq, kal_uint8 duty);
306 extern void PWM4_Start(void);
307 extern void PWM4_Stop(void);
308 extern kal_uint8 PWM4_GetCurrentLevel(void);
309 extern kal_uint8 PMW4_GetCurrentDuty(void);
310 extern kal_uint32 PMW4_GetCurrentFreq(void);
311#endif /* DRV_PWM_PWM4 */
312
313#endif /* DRV_PWM_PWM3 */
314#endif /* DRV_PWM_PWM2 */
315
316#endif /* !defined(DRV_PWM_RWG) */
317
318
319#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_PWM_REG_DBG__)
320#define DRV_PWM_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
321#define DRV_PWM_Reg(addr) DRV_DBG_Reg(addr)
322#define DRV_PWM_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
323#define DRV_PWM_Reg32(addr) DRV_DBG_Reg32(addr)
324#define DRV_PWM_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
325#define DRV_PWM_Reg8(addr) DRV_DBG_Reg8(addr)
326#define DRV_PWM_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
327#define DRV_PWM_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
328#define DRV_PWM_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
329#define DRV_PWM_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
330#define DRV_PWM_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
331#define DRV_PWM_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
332#define DRV_PWM_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
333#define DRV_PWM_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
334#define DRV_PWM_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
335#else
336#define DRV_PWM_WriteReg(addr,data) DRV_WriteReg(addr,data)
337#define DRV_PWM_Reg(addr) DRV_Reg(addr)
338#define DRV_PWM_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
339#define DRV_PWM_Reg32(addr) DRV_Reg32(addr)
340#define DRV_PWM_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
341#define DRV_PWM_Reg8(addr) DRV_Reg8(addr)
342#define DRV_PWM_ClearBits(addr,data) DRV_ClearBits(addr,data)
343#define DRV_PWM_SetBits(addr,data) DRV_SetBits(addr,data)
344#define DRV_PWM_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
345#define DRV_PWM_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
346#define DRV_PWM_SetBits32(addr,data) DRV_SetBits32(addr,data)
347#define DRV_PWM_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
348#define DRV_PWM_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
349#define DRV_PWM_SetBits8(addr,data) DRV_SetBits8(addr,data)
350#define DRV_PWM_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
351#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_PWM_REG_DBG__)
352#endif
353