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192.168.1.100 / T800_MD_V1.6 / c33b3079c38f91561c2f84f1ebed20ad8c60532a / . / mcu / driver / peripheral / inc / ts_hw.h
blob: c3ea3f0bc7f6842e19a6751eece9c2940cddc231 [file] [log] [blame]
yu.dongc33b3072024-08-21 23:14:49 -0700[diff] [blame^]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * tp_hw.h
41 *
42 * Project:
43 * --------
44 * Maui_Software
45 *
46 * Description:
47 * ------------
48 * This file is intends for GPT driver.
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
58 *------------------------------------------------------------------------------
59 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
60 *============================================================================
61 ****************************************************************************/
62#ifndef TP_HW_H
63#define TP_HW_H
64#include "drv_features.h"
65#include "drv_comm.h"
66#if defined(DRV_ADC_TOUCH_SCREEN)
67#if !defined(DRV_TS_OFF)
68
69#if defined(DRV_ADC_OFF)
70#error "ADC module should exist!! "
71#endif
72#include "reg_base.h"
73 #ifdef DRV_ADC_TOUCH_SCREEN_OFFSET_0X50
74 #define AUX_TS_DEBT (AUXADC_base+0x0050)
75 #define AUX_TS_CMD (AUXADC_base+0x0054)
76 #define AUX_TS_CON (AUXADC_base+0x0058)
77 #define AUX_TS_DATA0 (AUXADC_base+0x005c)
78 #else // #ifdef DRV_ADC_TOUCH_SCREEN_OFFSET_0X50
79 #define AUX_TS_DEBT (AUXADC_base+0x0030)
80 #define AUX_TS_CMD (AUXADC_base+0x0034)
81 #define AUX_TS_CON (AUXADC_base+0x0038)
82 #define AUX_TS_DATA0 (AUXADC_base+0x003c)
83 #endif // #ifdef DRV_ADC_TOUCH_SCREEN_OFFSET_0X50
84
85#endif /*#if !defined(DRV_TS_OFF)*/
86
87#define TS_DEBT_MASK 0x3fff
88
89#define TS_CMD_PD_MASK 0x0003
90 #define TS_CMD_PD_YDRV_SH 0x0000
91 #define TS_CMD_PD_IRQ_SH 0x0001
92 #define TS_CMD_PD_IRQ 0x0003
93#define TS_CMD_SE_DF_MASK 0x0004
94 #define TS_CMD_DIFFERENTIAL 0x0000
95 #define TS_CMD_SINGLE_END 0x0004
96#define TS_CMD_MODE_MASK 0x0008
97 #define TS_CMD_MODE_10BIT 0x0000
98 #define TS_CMD_MODE_8BIT 0x0008
99#define TS_CMD_ADDR_MASK 0x0070
100 #define TS_CMD_ADDR_Y 0x0010
101 #define TS_CMD_ADDR_Z1 0x0030
102 #define TS_CMD_ADDR_Z2 0x0040
103 #define TS_CMD_ADDR_X 0x0050
104
105#define TS_CON_SPL_MASK 0x0001
106
107#if defined(DRV_TP_PENUP_FIXED)
108 #define TS_CON_SPL_TRIGGER 0x8001
109 #else
110 #define TS_CON_SPL_TRIGGER 0x0001
111#endif
112
113#define TS_CON_STATUS_MASK 0x0002
114
115#define TS_DAT0_DAT_MASK 0x03ff
116
117#if defined(DRV_TP_SPL_NUM_ABB_1708)
118#define AUX_SPL_NUM (PLL_base+0x1708)
119#define AUX_SPL_NUM_SHIFT 8
120#define AUX_SPL_NUM_MASK 0xFF00
121
122#elif defined(DRV_TP_SPL_NUM_ABB_8708)
123#define AUX_SPL_NUM (ABBSYS_base+0x8708)
124#define AUX_SPL_NUM_SHIFT 8
125#define AUX_SPL_NUM_MASK 0xFF00
126
127#else
128#define AUX_SPL_NUM 0
129#define AUX_SPL_NUM_SHIFT 0
130#define AUX_SPL_NUM_MASK 0
131#endif//#if defined(DRV_TP_SPL_NUM_ABB_1708)
132
133#if !defined(DRV_TS_OFF)
134
135#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_TP_REG_DBG__)
136#define DRV_TP_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
137#define DRV_TP_Reg(addr) DRV_DBG_Reg(addr)
138#define DRV_TP_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
139#define DRV_TP_Reg32(addr) DRV_DBG_Reg32(addr)
140#define DRV_TP_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
141#define DRV_TP_Reg8(addr) DRV_DBG_Reg8(addr)
142#define DRV_TP_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
143#define DRV_TP_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
144#define DRV_TP_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
145#define DRV_TP_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
146#define DRV_TP_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
147#define DRV_TP_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
148#define DRV_TP_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
149#define DRV_TP_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
150#define DRV_TP_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
151#else
152#define DRV_TP_WriteReg(addr,data) DRV_WriteReg(addr,data)
153#define DRV_TP_Reg(addr) DRV_Reg(addr)
154#define DRV_TP_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
155#define DRV_TP_Reg32(addr) DRV_Reg32(addr)
156#define DRV_TP_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
157#define DRV_TP_Reg8(addr) DRV_Reg8(addr)
158#define DRV_TP_ClearBits(addr,data) DRV_ClearBits(addr,data)
159#define DRV_TP_SetBits(addr,data) DRV_SetBits(addr,data)
160#define DRV_TP_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
161#define DRV_TP_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
162#define DRV_TP_SetBits32(addr,data) DRV_SetBits32(addr,data)
163#define DRV_TP_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
164#define DRV_TP_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
165#define DRV_TP_SetBits8(addr,data) DRV_SetBits8(addr,data)
166#define DRV_TP_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
167#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_TP_REG_DBG__)
168
169#else //!defined(DRV_TS_OFF)
170
171#define DRV_TP_WriteReg(addr,data)
172#define DRV_TP_Reg(addr) drv_dummy_return()
173#define DRV_TP_WriteReg32(addr,data)
174#define DRV_TP_Reg32(addr) drv_dummy_return()
175#define DRV_TP_WriteReg8(addr,data)
176#define DRV_TP_Reg8(addr) drv_dummy_return()
177#define DRV_TP_ClearBits(addr,data)
178#define DRV_TP_SetBits(addr,data)
179#define DRV_TP_SetData(addr, bitmask, value)
180#define DRV_TP_ClearBits32(addr,data)
181#define DRV_TP_SetBits32(addr,data)
182#define DRV_TP_SetData32(addr, bitmask, value)
183#define DRV_TP_ClearBits8(addr,data)
184#define DRV_TP_SetBits8(addr,data)
185#define DRV_TP_SetData8(addr, bitmask, value)
186
187#endif //!defined(DRV_TS_OFF)
188
189#endif /*defined(DRV_ADC_TOUCH_SCREEN)*/
190
191#endif /*TP_HW_H*/
192