| yu.dong | c33b307 | 2024-08-21 23:14:49 -0700 | [diff] [blame^] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2005 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | /***************************************************************************** |
| 37 | * |
| 38 | * Filename: |
| 39 | * --------- |
| 40 | * wdt_hw.h |
| 41 | * |
| 42 | * Project: |
| 43 | * -------- |
| 44 | * Maui_Software |
| 45 | * |
| 46 | * Description: |
| 47 | * ------------ |
| 48 | * This file is intends for WDT driver. |
| 49 | * |
| 50 | * Author: |
| 51 | * ------- |
| 52 | * ------- |
| 53 | * |
| 54 | *============================================================================ |
| 55 | * HISTORY |
| 56 | * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 57 | *------------------------------------------------------------------------------ |
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| 175 | *------------------------------------------------------------------------------ |
| 176 | * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 177 | *============================================================================ |
| 178 | ****************************************************************************/ |
| 179 | #ifndef _WDT_HW_H |
| 180 | #define _WDT_HW_H |
| 181 | #include "drv_features_wdt.h" |
| 182 | #include "reg_base.h" |
| 183 | #if !defined(DRV_WDT_OFF) |
| 184 | |
| 185 | #define WDT_base RGU_base /* Watchdog Timer */ |
| 186 | |
| 187 | /***************** |
| 188 | * WDT Registers * |
| 189 | *****************/ |
| 190 | #if defined(DRV_WDT_LIMIT_REG) || defined(FPGA) |
| 191 | #define WDT_MODE (WDT_base+0x0000) |
| 192 | #define WDT_LENGTH (WDT_base+0x0004) |
| 193 | #define WDT_RESTART (WDT_base+0x0008) |
| 194 | #define WDT_STATUS (WDT_base+0x000C) |
| 195 | #define RGU_PERIPH_RESET (WDT_base+0x0010) |
| 196 | #define RGU_DSP_RESET (WDT_base+0x0014) |
| 197 | #define WDT_RSTINTERVAL (WDT_base+0x0018) |
| 198 | |
| 199 | #define WDT_MODE_KEYMASK 0xff00 |
| 200 | #define WDT_MODE_EXTEN 0x0004 |
| 201 | #define WDT_MODE_EXTPOL 0x0002 |
| 202 | #define WDT_MODE_ENABLE 0x0001 |
| 203 | #define WDT_LENGTH_TOUT 0xff00 |
| 204 | #define WDT_LENGTH_KEYMASK 0x00ff |
| 205 | #define WDT_RESTART_KEY 0x1971 |
| 206 | #define WDT_STATUS_BITMASK 0x8000 |
| 207 | #define WDT_LENGTH_KEY 0x0008 |
| 208 | #define WDT_MODE_KEY 0x2200 |
| 209 | #define WDT_RSTINTERVAL_MASK 0x0fff |
| 210 | |
| 211 | #define RGU_PERIPH_RESET_APB_PERIPH 0x8000 |
| 212 | #define RGU_PERIPH_RESET_DMA 0x4000 |
| 213 | |
| 214 | #define RGU_DSP_RESET_BIT 0x8000 |
| 215 | #endif /*DRV_WDT_LIMIT_REG,FPGA*/ |
| 216 | |
| 217 | #if defined(DRV_WDT_BASIC_REG) |
| 218 | #define WDT_MODE (WDT_base+0x0000) |
| 219 | #define WDT_LENGTH (WDT_base+0x0004) |
| 220 | #define WDT_RESTART (WDT_base+0x0008) |
| 221 | #define WDT_STATUS (WDT_base+0x000C) |
| 222 | #define RGU_PERIPH_RESET (WDT_base+0x0010) |
| 223 | #define RGU_DSP_RESET (WDT_base+0x0014) |
| 224 | #define WDT_RSTINTERVAL (WDT_base+0x0018) |
| 225 | #define WDT_SWRST (WDT_base+0x001c) |
| 226 | |
| 227 | /*WDT_MODE*/ |
| 228 | #define WDT_MODE_KEYMASK 0xff00 |
| 229 | #define WDT_MODE_AUTORST 0x0010 |
| 230 | #define WDT_MODE_IRQEN 0x0008 |
| 231 | #define WDT_MODE_EXTEN 0x0004 |
| 232 | #define WDT_MODE_EXTPOL 0x0002 |
| 233 | #define WDT_MODE_ENABLE 0x0001 |
| 234 | #define WDT_MODE_KEY 0x2200 |
| 235 | |
| 236 | /*WDT_LENGTH*/ |
| 237 | #define WDT_LENGTH_TOUT 0xffe0 |
| 238 | #define WDT_LENGTH_KEYMASK 0x001f |
| 239 | #define WDT_LENGTH_KEY 0x0008 |
| 240 | |
| 241 | /*WDT_RESTART*/ |
| 242 | #define WDT_RESTART_KEY 0x1971 |
| 243 | |
| 244 | /*WDT_STATUS*/ |
| 245 | #define WDT_STATUS_BITMASK 0xc000 |
| 246 | #define WDT_STATUS_SWWDT 0x4000 |
| 247 | |
| 248 | /*WDT_RSTINTERVAL*/ |
| 249 | #define WDT_RSTINTERVAL_MASK 0x0fff |
| 250 | #define WDT_RSTINTERVAL_VAL 0x0ffa //KC |
| 251 | |
| 252 | /*RGU_PERIPH_RESET*/ |
| 253 | #define RGU_PERIPH_RESET_APB_PERIPH 0x8000 |
| 254 | #define RGU_PERIPH_RESET_DMA 0x4000 |
| 255 | #define RGU_PERIPH_RESET_USB 0x2000 |
| 256 | #define RGU_PERIPH_RESET_DISP 0x0800 |
| 257 | |
| 258 | /*RGU_DSP_RESET*/ |
| 259 | #define RGU_DSP_RESET_BIT 0x8000 |
| 260 | |
| 261 | /*WDT_SWRST*/ |
| 262 | #define WDT_SWRST_KEY 0x1209 |
| 263 | #endif /*DRV_WDT_BASIC_REG*/ |
| 264 | |
| 265 | #if defined(DRV_WDT_RETN_REG) |
| 266 | //for USBDLv2,when WDT reset,let BROM or bootloader know the two things: |
| 267 | // 1: whether do USBDL or not is depends on The register:RETN_FLAG |
| 268 | // 2: RETN_DAT0: How long the USBDL timeout |
| 269 | #define WDT_RETN_FLAG (WDT_base+0x800) |
| 270 | #define WDT_RETN_FLAG_SET (WDT_base+0x804) |
| 271 | #define WDT_RETN_FLAG_CLR (WDT_base+0x808) |
| 272 | #define WDT_RETN_DAT0 (WDT_base+0x814) |
| 273 | |
| 274 | #define WDT_RETN_FLAG_KEY 0x4e000000 |
| 275 | #endif |
| 276 | |
| 277 | |
| 278 | #if defined(DRV_WDT_6573_REG) |
| 279 | |
| 280 | |
| 281 | #define WDT_base RGU_SD_base |
| 282 | |
| 283 | #define WDT_MODE (WDT_base+0x0000) |
| 284 | #define WDT_LENGTH (WDT_base+0x0004) |
| 285 | #define WDT_RESTART (WDT_base+0x0008) |
| 286 | #define WDT_STATUS (WDT_base+0x000C) |
| 287 | #define WDT_RSTINTERVAL (WDT_base+0x0010) |
| 288 | #define WDT_SWRST (WDT_base+0x0014) |
| 289 | |
| 290 | /*WDT_MODE*/ |
| 291 | #define WDT_MODE_KEYMASK 0xff00 |
| 292 | #define WDT_MODE_IRQEN 0x0008 |
| 293 | #define WDT_MODE_EXTEN 0x0000 |
| 294 | #define WDT_MODE_EXTPOL 0x0000 |
| 295 | #define WDT_MODE_ENABLE 0x0001 |
| 296 | #define WDT_MODE_KEY 0x2200 |
| 297 | |
| 298 | /*WDT_LENGTH*/ |
| 299 | #define WDT_LENGTH_TOUT 0xffe0 |
| 300 | #define WDT_LENGTH_KEYMASK 0x001f |
| 301 | #define WDT_LENGTH_KEY 0x0008 |
| 302 | |
| 303 | /*WDT_RESTART*/ |
| 304 | #define WDT_RESTART_KEY 0x1971 |
| 305 | |
| 306 | /*WDT_STATUS*/ |
| 307 | #define WDT_STATUS_BITMASK 0xc000 |
| 308 | #define WDT_STATUS_SWWDT 0x4000 |
| 309 | |
| 310 | /*WDT_RSTINTERVAL*/ |
| 311 | #define WDT_RSTINTERVAL_MASK 0x0fff |
| 312 | #define WDT_RSTINTERVAL_VAL 0x0ffa //KC |
| 313 | |
| 314 | /*WDT_SWRST*/ |
| 315 | #define WDT_SWRST_KEY 0x1209 |
| 316 | #endif /*DRV_WDT_6573_REG*/ |
| 317 | |
| 318 | #if defined(DRV_WDT_6575_REG) |
| 319 | #define WDT_MODE (WDT_base+0x0000) |
| 320 | #define WDT_LENGTH (WDT_base+0x0004) |
| 321 | #define WDT_RESTART (WDT_base+0x0008) |
| 322 | #define WDT_STATUS (WDT_base+0x000C) |
| 323 | #define WDT_SWRST (WDT_base+0x0010) |
| 324 | #define MCU_RESET (WDT_base+0x0040) |
| 325 | #define RGU_DSP_RESET (WDT_base+0x0044) |
| 326 | |
| 327 | /*WDT_MODE*/ |
| 328 | #define WDT_MODE_KEYMASK 0xff00 |
| 329 | #define WDT_MODE_IRQEN 0x0002 |
| 330 | // #define WDT_MODE_EXTEN 0x0000 |
| 331 | // #define WDT_MODE_EXTPOL 0x0000 |
| 332 | #define WDT_MODE_ENABLE 0x0001 |
| 333 | #define WDT_MODE_KEY 0x2200 |
| 334 | |
| 335 | /*WDT_LENGTH*/ |
| 336 | #define WDT_LENGTH_TOUT 0xffe0 |
| 337 | #define WDT_LENGTH_KEYMASK 0x001f |
| 338 | #define WDT_LENGTH_KEY 0x0008 |
| 339 | |
| 340 | /*WDT_RESTART*/ |
| 341 | #define WDT_RESTART_KEY 0x1971 |
| 342 | |
| 343 | /*WDT_STATUS*/ |
| 344 | #define WDT_STATUS_BITMASK 0xc000 |
| 345 | #define WDT_STATUS_SWWDT 0x4000 |
| 346 | |
| 347 | /*WDT_RSTINTERVAL*/ |
| 348 | #define WDT_RSTINTERVAL_MASK 0x0fff |
| 349 | |
| 350 | /*WDT_SWRST*/ |
| 351 | #define WDT_SWRST_KEY 0x1209 |
| 352 | |
| 353 | /*MCU_SWRST*/ |
| 354 | #define MCU_RESET_KEY 0x37 |
| 355 | |
| 356 | /*DSP_SWRST*/ |
| 357 | #define MCU_RESET_KEY 0x48 |
| 358 | |
| 359 | /*WDT_LENGTH_VALUE_INIT*/ |
| 360 | #define WDT_LENGTH_VALUE_INIT 0x1fe0 |
| 361 | #endif /*DRV_WDT_6575_REG*/ |
| 362 | |
| 363 | #endif /*#if !defined(DRV_WDT_OFF)*/ |
| 364 | #endif /*_WDT_HW_H*/ |
| 365 | |