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192.168.1.100 / T800_MD_V1.6 / c33b3079c38f91561c2f84f1ebed20ad8c60532a / . / mcu / interface / driver / hwdrv / sdio_sw.h
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yu.dongc33b3072024-08-21 23:14:49 -0700[diff] [blame^]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2001
8*
9*****************************************************************************/
10
11/*****************************************************************************
12 *
13 * Filename:
14 * ---------
15 * sdio_sw.h
16 *
17 * Project:
18 * --------
19 * Maui_Software
20 *
21 * Description:
22 * ------------
23 * Header file of SDIO driver
24 *
25 * Author:
26 * -------
27 * -------
28 *
29 *============================================================================
30 * HISTORY
31 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
32 *------------------------------------------------------------------------------
33
34 *------------------------------------------------------------------------------
35 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
36 *============================================================================
37 ****************************************************************************/
38#ifndef SDIO_SW_H
39#define SDIO_SW_H
40
41/*SW*/
42
43#define SDIO_CCCR_VERISON_MASK 0xf
44#define SDIO_SD_VERISON_MASK 0xf
45#define SDIO_VERISON_MASK 0xf0
46#define SDIO_VERISON_SHIFT 4
47
48/*CIS tuple code*/
49#define CISTPL_NULL 0x0
50#define CISTPL_CHECKSUM 0x10
51#define CISTPL_VERS_1 0x15
52#define CISTPL_ALTSTR 0x16
53#define CISTPL_MANFID 0x20
54#define CISTPL_FUNCID 0x21
55#define CISTPL_FUNCE 0x22
56#define CISTPL_SDIO_STD 0x91
57#define CISTPL_SDIO_EXT 0x92
58#define CISTPL_END 0xff
59
60/*Function definition*/
61#define SDIO_CCCR_SIZE 32
62#define SDIO_FBR_SIZE 256
63#define SDIO_TUPLE_SIZE 256
64
65typedef enum{
66 SDIO_FUCN_0=0,
67 SDIO_FUCN_1,
68 SDIO_MAX_FUCN_ID,
69 SDIO_FUCN_MEM=0x1000
70}SDIO_function_id_enum;
71typedef enum{
72 SDIO_BS_FREE=0,
73 SDIO_BS_BUS
74}SDIO_bus_status_enum;
75typedef enum{
76 SDIO_INTERFACE_NULL=0,
77 SDIO_INTERFACE_UART,
78 SDIO_INTERFACE_A_BT,
79 SDIO_INTERFACE_B_BT,
80 SDIO_INTERFACE_GPS,
81 SDIO_INTERFACE_CAMERA,
82 SDIO_INTERFACE_PHS,
83 SDIO_INTERFACE_WLAN
84}SDIO_interface_code_enum;
85
86typedef enum{
87 SDIO_FIX, //multi byte r/w at fixed address
88 SDIO_INC //multi byte r/w at incrementing address
89}cmd53_op_enum;
90typedef enum{
91 SDIO_READ,
92 SDIO_WRITE
93}rw_dir_enum;
94typedef enum{
95 DIS,
96 CMD,
97 TRN,
98 RFU
99}sdio_state_enum;
100typedef struct{
101 rw_dir_enum rw; // directon (input)
102 kal_uint8 func; // function (input)
103 kal_bool raw; // read after write
104 kal_bool stop; // stop data transfer
105 kal_uint8 data; // write data or read back data (Input , output)
106 kal_uint32 adrs; // address (input)
107}cmd52_config_struct;
108
109#define SDIO_SUPPORT_FUNCTION (SDIO_MAX_FUCN_ID-1)
110typedef struct{
111 rw_dir_enum rw; // directon
112 kal_uint8 func; // function
113 kal_bool block; // block mode or not
114 cmd53_op_enum op; // operation mode
115 kal_uint16 count; // byte or block count
116 kal_uint32 adrs; // address
117 kal_uint32 buffer; // address of buffer for data transfer
118}cmd53_config_struct;
119
120typedef struct{
121 kal_uint8 num_func;
122 kal_bool mem_present;
123 kal_bool io_ready;
124 kal_bool ocr_valid;
125 kal_bool stop; // stop trans issued
126 sdio_state_enum state;
127 kal_uint8 resp;
128 kal_uint8 bit_width;
129 kal_uint8 capability;
130 kal_uint32 ocr;
131 kal_uint8 power_control;
132 kal_uint32 block_size[SDIO_MAX_FUCN_ID];
133 void (*callback[SDIO_MAX_FUCN_ID])(void);
134}sdio_dcb_struct;
135
136/*SDIO command set*/
137SDC_CMD_STATUS SDIO_Cmd5(kal_uint32 ocr);
138SDC_CMD_STATUS SDIO_Cmd52_isr(cmd52_config_struct *p);
139SDC_CMD_STATUS SDIO_Cmd52(cmd52_config_struct *p);
140SDC_CMD_STATUS SDIO_Cmd53_isr(cmd53_config_struct *p);
141SDC_CMD_STATUS SDIO_Cmd53(cmd53_config_struct *p);
142SDC_CMD_STATUS SD_Send_Cmd_poll(kal_uint32 cmd, kal_uint32 arg);
143SDC_CMD_STATUS SD_WaitCmdRdyOrTo_poll(void);
144SDC_CMD_STATUS SD_StopTrans_poll(void);
145/*Driver only*/
146SDC_CMD_STATUS SDIO_read_FBR(SDIO_function_id_enum function);
147SDC_CMD_STATUS SDIO_read_CCCR(void);
148SDC_CMD_STATUS SDIO_read_CIS(SDIO_function_id_enum function);
149SDC_CMD_STATUS SDIO_read_capacity(void);
150SDC_CMD_STATUS SDIO_abort_IO(SDIO_function_id_enum function);
151SDC_CMD_STATUS SDIO_SW_reset(void);
152SDC_CMD_STATUS SDIO_check_IO_Int(SDIO_function_id_enum function, kal_bool *pending);
153SDC_CMD_STATUS SDIO_check_IO_ready(SDIO_function_id_enum function, kal_bool *ready);
154SDC_CMD_STATUS SDIO_configure_bus(SD_BITWIDTH bus);
155SDC_CMD_STATUS SDIO_enable_E4MI(kal_bool enable);
156SDC_CMD_STATUS SDIO_read_power_control(void);
157SDC_CMD_STATUS SDIO_enable_MPS(kal_bool enable);
158kal_bool SDIO_support_MPS(void);
159kal_bool SDIO_support_SDC(void);
160kal_bool SDIO_support_SMB(void);
161kal_bool SDIO_support_SRW(void);
162kal_bool SDIO_support_SBS(void);
163kal_bool SDIO_support_S4MI(void);
164kal_bool SDIO_support_LSC(void);
165kal_bool SDIO_support_4BLS(void);
166void SDIO_HISR_Entry(void);
167kal_bool SDIO_Register_Read_poll(SDIO_function_id_enum function,
168 kal_uint32 addr,
169 kal_uint32 *data,
170 cmd53_op_enum op);
171SDC_CMD_STATUS SDIO_stop(void);
172SDC_CMD_STATUS SDIO_WaitDatRdyOrTo(void);
173/*SDIO function */
174SDC_CMD_STATUS SDIO_read_CCCR_ver(kal_uint8 *version);
175SDC_CMD_STATUS SDIO_read_SDIO_ver(kal_uint8 *version);
176SDC_CMD_STATUS SDIO_read_SD_ver(kal_uint8 *version);
177SDC_CMD_STATUS SDIO_configure_BLK_size(SDIO_function_id_enum function, kal_uint32 size);
178SDC_CMD_STATUS SDIO_get_BLK_size(SDIO_function_id_enum function, kal_uint32 *size);
179kal_uint32 SDIO_query_BLK_size(SDIO_function_id_enum function);
180SDIO_function_id_enum SDIO_query_IO_id(SDIO_interface_code_enum ap);
181SDC_CMD_STATUS SDIO_enable_IO_Int(SDIO_function_id_enum function, kal_bool enable);
182SDC_CMD_STATUS SDIO_enable_IO(SDIO_function_id_enum function, kal_bool enable);
183void SDIO_int_registration(SDIO_function_id_enum function, void (func)(void));
184/*Function for WiFi */
185/*Write Register*/
186kal_bool SDIO_Register_Write(SDIO_function_id_enum function,
187 kal_uint32 addr,
188 kal_uint32 data,
189 cmd53_op_enum op);
190kal_bool SDIO_Register_Write_isr(SDIO_function_id_enum function,
191 kal_uint32 addr,
192 kal_uint32 data,
193 cmd53_op_enum op);
194/*Write Data */
195kal_bool SDIO_Data_Write(SDIO_function_id_enum function,
196 kal_uint32 addr,
197 kal_uint8 *data,
198 cmd53_op_enum op,
199 kal_uint32 count,
200 kal_bool block);
201/*Read Register*/
202kal_bool SDIO_Register_Read(SDIO_function_id_enum function,
203 kal_uint32 addr,
204 kal_uint32 *data,
205 cmd53_op_enum op);
206kal_bool SDIO_Data_Read(SDIO_function_id_enum function,
207 kal_uint32 addr,
208 kal_uint8 *data,
209 cmd53_op_enum op,
210 kal_uint32 count,
211 kal_bool block);
212
213//guilin
214DCL_SDC_CMD_STATUS SDIO_cmd52_read(DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT8 *rdata, DCL_UINT8 *r5resp);
215DCL_SDC_CMD_STATUS SDIO_cmd52_write(DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT8 wdata, DCL_UINT8 *r5resp);
216DCL_SDC_CMD_STATUS SDIO_cmd52_write_read(DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT8 wdata, DCL_UINT8 *rdata, DCL_UINT8 *r5resp);
217DCL_SDC_CMD_STATUS SDIO_cmd53_read(DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT32 data, DCL_SDIO_cmd53_op_enum op, DCL_UINT32 count, DCL_BOOL block, DCL_UINT8 *r5resp);
218DCL_SDC_CMD_STATUS SDIO_cmd53_write(DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT32 data, DCL_SDIO_cmd53_op_enum op, DCL_UINT32 count, DCL_BOOL block, DCL_UINT8 *r5resp);
219DCL_SDC_CMD_STATUS SDIO_mcudma_read(DCL_UINT32 *rdata);
220DCL_SDC_CMD_STATUS SDIO_mcudma_write(DCL_UINT32 wdata);
221DCL_SDC_CMD_STATUS SDIO_clkpadred_read(DCL_UINT32 *rdata);
222DCL_SDC_CMD_STATUS SDIO_clkpadred_write(DCL_UINT32 wdata);
223DCL_SDC_CMD_STATUS SDIO_forcemcu_read(DCL_UINT32 *rdata);
224DCL_SDC_CMD_STATUS SDIO_forcemcu_write(DCL_UINT32 wdata);
225DCL_SDC_CMD_STATUS SDIO_getclk(DCL_UINT32 *rdata);
226DCL_SDC_CMD_STATUS SDIO_setclk(DCL_UINT32 wdata);
227
228void SDIO_dispatch_IO(SDIO_function_id_enum function);
229void SDIO_resume_IO(SDIO_function_id_enum function);
230
231
232
233
234#ifdef __SDIO_SRW_SRW__
235SDC_CMD_STATUS SDIO_suspend_IO(SDIO_bus_status_enum *bus_status);
236SDC_CMD_STATUS SDIO_select_IO(SDIO_function_id_enum function, kal_bool *resume_data);
237SDC_CMD_STATUS SDIO_check_IO_exec(SDIO_function_id_enum function, kal_bool *execution);
238SDC_CMD_STATUS SDIO_check_IO_ready_flag(SDIO_function_id_enum function, kal_bool *ready);
239#endif
240
241/*extern varibale*/
242extern sdio_dcb_struct gSDIO;
243#endif // end of SD_DEF_H