blob: e3fb488a98d0af442e8f0e3747ff383128454418 [file] [log] [blame]
yu.dongc33b3072024-08-21 23:14:49 -07001/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * dcl_msdc.h
41 *
42 * Project:
43 * --------
44 * Maui_Software
45 *
46 * Description:
47 * ------------
48 * This file defines common part of msdc related modules.
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
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148 *------------------------------------------------------------------------------
149 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
150 *============================================================================
151 ****************************************************************************/
152
153#ifdef DCL_DEFINITION_STRUCT
154#ifndef __DCL_MSDC_H_FRONT__
155#define __DCL_MSDC_H_FRONT__
156
157//RHR ADD
158#include "kal_general_types.h"
159//RHR REMOVE
160/*
161//MSBB remove #include "kal_non_specific_general_types.h"
162*/
163//RHR
164
165#define DCL_MSDC_HW_MSDC1 1
166#define DCL_MSDC_HW_MSDC2 2
167
168/*********************************************************************************************************
169*followings we defines the structure used by DCL user, this is prevent DCL user from include invividual moudles' header file.
170**********************************************************************************************************/
171typedef DCL_UINT32 DCL_SDC_CMD_STATUS;//this is to replace SDC_CMD_STATUS
172
173
174/*this is to replace cmd53_op_enum*/
175typedef enum{
176 DCL_SDIO_FIX, //multi byte r/w at fixed address
177 DCL_SDIO_INC //multi byte r/w at incrementing address
178}DCL_SDIO_cmd53_op_enum;
179
180/*this is to replace SDIO_function_id_enum*/
181typedef enum{
182 DCL_SDIO_FUCN_0=0,
183 DCL_SDIO_FUCN_1,
184 DCL_SDIO_MAX_FUCN_ID,
185 DCL_SDIO_FUCN_MEM=0x1000
186}DCL_SDIO_function_id_enum;
187
188/*this is to replace SD_BITWIDTH*/
189typedef enum{
190 DCL_BIT_1W = 0x0000,
191 DCL_BIT_4W = 0x0002
192}DCL_SD_BITWIDTH;
193
194typedef void ( *MSDC_CALLBACK) (void);
195#define DCL_SECTOR_SIZE 512
196
197/*******************************************************************************
198 * driver function tables exposed to DCL, in SD layer, SDIO layer, and MSDC layer
199 *******************************************************************************/
200/*here are type definition for functions*/
201typedef DCL_SDC_CMD_STATUS (*DCL_SINGLE_BLK_RD) (DCL_UINT32 data_adrs, DCL_UINT32 *rxbuffer);
202typedef DCL_SDC_CMD_STATUS (*DCL_MUL_BLK_RD) (DCL_UINT32 data_adrs, DCL_UINT32 *rxbuffer, DCL_UINT32 num);
203typedef DCL_SDC_CMD_STATUS (*DCL_SINGLE_BLK_WR) (DCL_UINT32 address, DCL_UINT32 *txbuffer);
204typedef DCL_SDC_CMD_STATUS (*DCL_MUL_BLK_WR) (DCL_UINT32 address, DCL_UINT32 *txbuffer, DCL_UINT32 num);
205typedef DCL_SDC_CMD_STATUS (*DCL_SD_INITITALIZE) (void);
206typedef DCL_SDC_CMD_STATUS (*DCL_SET_PRE_ERASE_CNT) (DCL_UINT32 num);
207typedef DCL_SDC_CMD_STATUS (*DCL_SD_SET_CALLBACK)(MSDC_CALLBACK callback1, MSDC_CALLBACK callback2, MSDC_CALLBACK callback3,MSDC_CALLBACK callback4,MSDC_CALLBACK callback5,MSDC_CALLBACK callback6);
208typedef DCL_SDC_CMD_STATUS (*DCL_SET_READ_TEST_FLAG)(kal_uint32 readTestFlag);
209typedef DCL_SDC_CMD_STATUS(*DCL_SD_READ_TEST)(void);
210typedef DCL_SDC_CMD_STATUS(*DCL_SD_SET_UPLL_CLOCK_TEST)(void);
211typedef DCL_SDC_CMD_STATUS(*DCL_SD_ERASE_BLK)(DCL_UINT32 startSector, DCL_UINT32 sectorNum);
212typedef DCL_SDC_CMD_STATUS (*DCL_GPD_MUL_BLK_RD) (DCL_UINT32 data_addrs,DCL_UINT32 num, void *data_buf);
213typedef DCL_SDC_CMD_STATUS (*DCL_GPD_MUL_BLK_WR) (DCL_UINT32 data_addrs,DCL_UINT32 num, void *data_buf);
214
215
216typedef struct
217{
218 DCL_SINGLE_BLK_RD singleBlkRd;
219 DCL_MUL_BLK_RD mulBlkRd;
220 DCL_SINGLE_BLK_WR singleBlkWr;
221 DCL_MUL_BLK_WR mulBlkWr;
222 DCL_SD_INITITALIZE sdInititalize;
223 DCL_SET_PRE_ERASE_CNT setPreEraseCnt;
224 DCL_SD_SET_CALLBACK sdSetCallBack;
225 DCL_SET_READ_TEST_FLAG sdSetReadTestFlag;
226 DCL_SD_READ_TEST sdSetReadTest;
227 DCL_SD_SET_UPLL_CLOCK_TEST sdSetUpllClock;
228 DCL_SD_ERASE_BLK eraseBlk;
229 DCL_GPD_MUL_BLK_RD GpdMulBlkRd;
230 DCL_GPD_MUL_BLK_WR GpdMulBlkWr;
231}SDDriver_t;
232
233
234typedef DCL_BOOL (*DCL_SDIO_REG_WR) (DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT32 data, DCL_SDIO_cmd53_op_enum op);
235typedef DCL_BOOL (*DCL_SDIO_REG_WR_ISR) (DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT32 data, DCL_SDIO_cmd53_op_enum op);
236typedef DCL_BOOL (*DCL_SDIO_DATA_WR) (DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT8 *data, DCL_SDIO_cmd53_op_enum op, DCL_UINT32 count, DCL_BOOL block);
237typedef DCL_BOOL (*DCL_SDIO_REG_RD) (DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT32 *data, DCL_SDIO_cmd53_op_enum op);
238typedef DCL_BOOL (*DCL_SDIO_DATA_RD) (DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT8 *data, DCL_SDIO_cmd53_op_enum op, DCL_UINT32 count, DCL_BOOL block);
239typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_CHECK_INTR) (DCL_SDIO_function_id_enum function, DCL_BOOL *pending);
240typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_ENABLE_INTR) (DCL_SDIO_function_id_enum function, DCL_BOOL enable);
241typedef DCL_UINT32 (*DCL_SDIO_INIT) (void);
242typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_ABORT) (DCL_SDIO_function_id_enum function);
243typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_SW_RST) (void);
244typedef DCL_UINT32 (*DCL_SDIO_QRY_BLOCK_SIZE) (DCL_SDIO_function_id_enum function);
245typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_SET_BLOCK_SIZE) (DCL_SDIO_function_id_enum function, DCL_UINT32 size);
246typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_GET_BLOCK_SIZE) (DCL_SDIO_function_id_enum function, DCL_UINT32 *size);
247typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_ENABLE_IO) (DCL_SDIO_function_id_enum function, DCL_BOOL enable);
248typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_SET_BUS_WIDTH) (DCL_SD_BITWIDTH bus);
249typedef void (*DCL_SDIO_GET_CCCR) (DCL_UINT8 *buf, DCL_UINT32 bufLen);
250typedef void (*DCL_SDIO_GET_FBR) (DCL_UINT8 *buf, DCL_UINT32 bufLen);
251
252typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_CMD52_READ)(DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT8 *rdata, DCL_UINT8 *r5resp);
253typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_CMD52_WRITE)(DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT8 wdata, DCL_UINT8 *r5resp);
254typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_CMD52_WRITE_READ)(DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT8 wdata, DCL_UINT8 *rdata, DCL_UINT8 *r5resp);
255typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_CMD53_READ)(DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT32 data, DCL_SDIO_cmd53_op_enum op, DCL_UINT32 count, DCL_BOOL block, DCL_UINT8 *r5resp);
256typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_CMD53_WRITE)(DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT32 data, DCL_SDIO_cmd53_op_enum op, DCL_UINT32 count, DCL_BOOL block, DCL_UINT8 *r5resp);
257typedef void (*DCL_SDIO_int_registration)(DCL_SDIO_function_id_enum function, void (func)(void));
258typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_MCUDMA_READ)(DCL_UINT32 *rdata);
259typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_MCUDMA_WRITE)(DCL_UINT32 wdata);
260typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_CLKPADRED_READ)(DCL_UINT32 *rdata);
261typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_CLKPADRED_WRITE)(DCL_UINT32 wdata);
262typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_FORCEMCU_READ)(DCL_UINT32 *rdata);
263typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_FORCEMCU_WRITE)(DCL_UINT32 wdata);
264typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_GETCLK)(DCL_UINT32 *rdata);
265typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_SETCLK)(DCL_UINT32 wdata);
266
267//guilin
268
269typedef struct
270{
271 DCL_SDIO_REG_WR regWr;
272 DCL_SDIO_REG_WR_ISR regWrInIsr;
273 DCL_SDIO_DATA_WR dataWr;
274 DCL_SDIO_REG_RD regRd;
275 DCL_SDIO_DATA_RD dataRd;
276 DCL_SDIO_CHECK_INTR checkIntr;
277 DCL_SDIO_ENABLE_INTR enableIntr;
278 DCL_SDIO_INIT sdioInititalize;
279 DCL_SDIO_ABORT abort;
280 DCL_SDIO_SW_RST swRst;
281 DCL_SDIO_QRY_BLOCK_SIZE qryBlkSize;
282 DCL_SDIO_SET_BLOCK_SIZE setBlkSize;
283 DCL_SDIO_GET_BLOCK_SIZE getBlkSize;
284 DCL_SDIO_ENABLE_IO enableIO;
285 DCL_SDIO_SET_BUS_WIDTH setBusWidth;
286 DCL_SDIO_GET_CCCR getCCCR;
287 DCL_SDIO_GET_FBR getFBR;
288
289 DCL_SDIO_CMD52_READ cmd52_read;
290 DCL_SDIO_CMD52_WRITE cmd52_write;
291 DCL_SDIO_CMD52_WRITE_READ cmd52_write_read;
292 DCL_SDIO_CMD53_READ cmd53_read;
293 DCL_SDIO_CMD53_WRITE cmd53_write;
294 DCL_SDIO_int_registration hisr_callback;
295 DCL_SDIO_MCUDMA_READ mcudma_read;
296 DCL_SDIO_MCUDMA_WRITE mcudma_write;
297 DCL_SDIO_CLKPADRED_READ clkpadred_read;
298 DCL_SDIO_CLKPADRED_WRITE clkpadred_write;
299 DCL_SDIO_FORCEMCU_READ forcemcu_read;
300 DCL_SDIO_FORCEMCU_WRITE forcemcu_write;
301 DCL_SDIO_GETCLK getclk;
302 DCL_SDIO_SETCLK setclk;
303
304}SDIODriver_t;
305//guilin
306typedef void (* DCL_MSDC_PDN)(DCL_BOOLEAN pwDown);
307
308typedef struct
309{
310 //void (*modulePDN) (DCL_BOOLEAN pwDown);
311 DCL_MSDC_PDN modulePDN;
312}MSDCDriver_t;
313
314
315/*******************************************************************************
316 * DCL_FLAGS_T for SD
317 *******************************************************************************/
318#define DCL_SD_FLAGS_DEVICE_CARD1 0x1
319#define DCL_SD_FLAGS_DEVICE_CARD2 0x2
320#define DCL_SD_FLAGS_DEVICE_SIMPLUS 0x4
321#define DCL_SDIO_FLAGS_SDIO1 0x100
322#define DCL_SDIO_FLAGS_SDIO2 0x200
323#define DCL_SDIO_FLAGS_ALL 0x300
324#define DCL_SD_FLAGS_USAGE_GET_INFORMATION 0x10000
325#define DCL_SD_FLAGS_USAGE_CMD 0x20000
326
327#define DCL_SD_FLAGS_DEVICE_ALL (DCL_SD_FLAGS_DEVICE_CARD1|DCL_SD_FLAGS_DEVICE_CARD2|DCL_SD_FLAGS_DEVICE_SIMPLUS)
328#define DCL_SD_FLAGS_USAGE_ALL (DCL_SD_FLAGS_USAGE_GET_INFORMATION|DCL_SD_FLAGS_USAGE_CMD)
329/*******************************************************************************
330 * DCL_CTRL_CMD for SD
331 *******************************************************************************/
332#define SD_CMDS \
333 SD_CTRL_CMD_BASE, \
334 SD_CTRL_CMD_READ = SD_CTRL_CMD_BASE, \
335 SD_CTRL_CMD_WRITE, \
336 SD_CTRL_CMD_READ_ODD_SIZE, \
337 SD_CTRL_CMD_WRITE_ODD_SIZE, \
338 SD_CTRL_CMD_INIT, \
339 SD_CTRL_CMD_IS_INITED, \
340 SD_CTRL_CMD_ANALOG_SWITCH, \
341 SD_CTRL_CMD_FAST_FORMAT_START, \
342 SD_CTRL_CMD_FAST_FORMAT_STOP, \
343 SD_CTRL_CMD_IS_FAST_FORMAT_RUNNING, \
344 SD_CTRL_CMD_GET_CAPACITY, \
345 SD_CTRL_CMD_IS_EXISTENCE, \
346 SD_CTRL_CMD_POLL_EXISTENCE, \
347 SD_CTRL_CMD_SET_CLEAR_EXISTENCE, \
348 SD_CTRL_CMD_WRITE_PROTECTION, \
349 SD_CTRL_CMD_QUERY_EVER_PLUGOUT, \
350 SD_CTRL_CMD_RESET_EVER_PLUGOUT, \
351 SD_CTRL_CMD_FORCE_SINGLE_LINE, \
352 SD_CTRL_CMD_GO_IDLE, \
353 SD_CTRL_CMD_CACHEABLE_BUFFER, \
354 SD_CTRL_CMD_ADD_CALLBACK, \
355 SD_CTRL_CMD_SET_FLAG, \
356 SD_CTRL_CMD_READ_TEST, \
357 SD_CTRL_CMD_SET_CLOCK_TEST, \
358 SD_CTRL_CMD_FLUSH, \
359 SD_CTRL_CMD_GET_AND_CLEAR_MEDIA_CHANGED, \
360 SD_CTRL_CMD_GPD_READ,\
361 SD_CTRL_CMD_GPD_WRITE,\
362 SD_CTRL_CMD_GET_BD_STRUCT_NUM,\
363 SD_CTRL_CMD_DUMMY_END,
364
365
366/*******************************************************************************
367 * DCL_CTRL_DATA_T: Define the Control data structure for each module's command
368 *******************************************************************************/
369/* FOR SD_CTRL_CMD_READ control command. */
370typedef struct
371{
372 DCL_UINT32 u4Sector; //this specify the starting sector to read
373 DCL_UINT32 u4Sectors; //this specify the number of sectors to read
374 void *bufferAddr; //we will move read data from card to this address
375} SD_CTRL_READ_T;
376
377/* FOR SD_CTRL_CMD_WRITE control command. */
378typedef struct
379{
380 DCL_UINT32 u4Sector; //this specify the starting sector to write
381 DCL_UINT32 u4Sectors; //this specify the number of sectors to write
382 void *bufferAddr; //we will move move data from this address to card
383} SD_CTRL_WRITE_T;
384
385/* FOR SD_CTRL_CMD_GPD_READ control command. */
386typedef struct
387{
388 DCL_UINT32 u4Sector; //this specify the starting sector to read
389 DCL_UINT32 u4Sectors; //this specify the number of sectors to read
390 void *bufferHead; //we will move read data from card to this address
391 void *bufferTail;
392} SD_CTRL_GPD_READ_T;
393
394/* FOR SD_CTRL_CMD_GPD_WRITE control command. */
395typedef struct
396{
397 DCL_UINT32 u4Sector; //this specify the starting sector to write
398 DCL_UINT32 u4Sectors; //this specify the number of sectors to write
399 void *bufferHead; //we will move move data from this address to card
400 void *bufferTail;
401} SD_CTRL_GPD_WRITE_T;
402typedef struct
403{
404 DCL_UINT32 max_bd_num;//specify the max bd struct num for link list dma transfer
405} SD_CTRL_MAX_BD_STRUCT_NUM_T;
406
407/* FOR SD_CTRL_CMD_READ_ODD_SIZE control command. */
408typedef struct
409{
410 DCL_UINT32 u4Sector; //this specify the starting sector to read
411 DCL_UINT32 u4Size; //this specify the number of bytes to read
412 void *bufferAddr; //we will move read data from card to this address
413} SD_CTRL_READ_ODD_T;
414
415/* FOR SD_CTRL_CMD_WRITE_ODD_SIZE control command. */
416typedef struct
417{
418 DCL_UINT32 u4Sector; //this specify the starting sector to write
419 DCL_UINT32 u4Size; //this specify the number of bytes to write
420 void *bufferAddr; //we will move move data from this address to card
421} SD_CTRL_WRITE_ODD_T;
422
423/* FOR SD_CTRL_CMD_ANALOG_SWITCH control command. */
424typedef struct
425{
426 DCL_UINT32 u4TargetInterface;
427} SD_CTRL_ANALOG_SWITCH_T;
428
429/* FOR SD_CTRL_CMD_GET_CAPACITY control command. */
430typedef struct
431{
432 DCL_BOOL gHighCapacityCard;
433 DCL_UINT64 pu8Capacity;
434} SD_CTRL_GET_CAPACITY_T;
435
436/* FOR SD_CTRL_CMD_READY control command. */
437typedef struct
438{
439 DCL_BOOL fgInited;
440} SD_CTRL_INITED_T;
441
442/* FOR SD_CTRL_CMD_IS_EXISTENCE and SD_CTRL_CMD_POLL_EXISTENCE control command. */
443typedef struct
444{
445 DCL_BOOL fgPresent;
446} SD_CTRL_EXISTENCE_T;
447
448/* FOR SD_CTRL_CMD_WRITE_PROTECTION control command. */
449typedef struct
450{
451 DCL_BOOL fgReadOnly;
452} SD_CTRL_WRITE_PROTECTION_T;
453
454/* FOR SD_CTRL_CMD_QUERY_EVER_PLUGOUT control command. */
455typedef struct
456{
457 DCL_BOOL fgEverPLugOut;
458} SD_CTRL_QUERY_EVER_PLUGOUT_T;
459
460/* FOR SD_CTRL_CMD_FORCE_SINGLE_LINE control command. */
461typedef struct
462{
463 DCL_BOOL fgIsItTrue;
464} SD_CTRL_FORCE_SINGLE_LINE_T;
465
466/* FOR SD_CTRL_CMD_CACHEABLE_BUFFER control command. */
467typedef struct
468{
469 DCL_BOOL fgIsCACHEABLE;
470} SD_CTRL_CACHEABLE_BUFFER_T;
471
472typedef struct
473{
474 MSDC_CALLBACK callback1;
475 MSDC_CALLBACK callback2;
476 MSDC_CALLBACK callback3;
477 MSDC_CALLBACK callback4;
478 MSDC_CALLBACK callback5;
479 MSDC_CALLBACK callback6;
480}SD_CTRL_CALLBACK_T;
481
482typedef struct
483{
484 DCL_UINT32 readTestFlag;
485}SD_CTRL_SET_READ_TEST_FLAG_T;
486
487typedef struct
488{
489 DCL_UINT32 startSector;
490 DCL_UINT32 sectorNum;
491}SD_CTRL_FLUSH_T;
492
493typedef struct
494{
495 DCL_BOOL enable;
496}SD_CTRL_FAST_FORMAT_T;
497
498typedef struct
499{
500 DCL_BOOL changed;
501}SD_CTRL_MEDIA_CHANGED_T;
502
503#define SD_CTRLS \
504 SD_CTRL_READ_T rSDRead; \
505 SD_CTRL_WRITE_T rSDWrite; \
506 SD_CTRL_READ_ODD_T rSDReadOdd;\
507 SD_CTRL_WRITE_ODD_T rSDWriteOdd; \
508 SD_CTRL_ANALOG_SWITCH_T rSDSwitch; \
509 SD_CTRL_GET_CAPACITY_T rSDGetCapacity; \
510 SD_CTRL_INITED_T rSDInited; \
511 SD_CTRL_EXISTENCE_T rSDExistence; \
512 SD_CTRL_EXISTENCE_T rSDPollExistence; \
513 SD_CTRL_WRITE_PROTECTION_T rSDWriteProrect; \
514 SD_CTRL_QUERY_EVER_PLUGOUT_T rSDQueryEverPugOut; \
515 SD_CTRL_FORCE_SINGLE_LINE_T rSDForceSingleLine; \
516 SD_CTRL_CACHEABLE_BUFFER_T rSDCacheableBuf; \
517 SD_CTRL_CALLBACK_T rSDCallBackFunc; \
518 SD_CTRL_SET_READ_TEST_FLAG_T rSDSetReadTestFlag; \
519 SD_CTRL_FLUSH_T rSDFlush; \
520 SD_CTRL_FAST_FORMAT_T rSDFastFormat; \
521 SD_CTRL_MEDIA_CHANGED_T rSDMediaChanged; \
522 SD_CTRL_GPD_READ_T rSDReadGPD;\
523 SD_CTRL_GPD_WRITE_T rSDWriteGPD;\
524 SD_CTRL_MAX_BD_STRUCT_NUM_T rSDMaxBD;
525
526
527/***********************************************************************************
528* following is the part of SDIO
529************************************************************************************/
530
531/*******************************************************************************
532 * DCL_FLAGS_T for SDIO
533 *******************************************************************************/
534#define DCL_SDIO_FLAGS_DEVICE_CARD1 0x1
535#define DCL_SDIO_FLAGS_DEVICE_CARD2 0x2
536#define DCL_SDIO_FLAGS_USAGE_GET_INFORMATION 0x10
537#define DCL_SDIO_FLAGS_USAGE_CMD 0x20
538
539#define DCL_SDIO_FLAGS_DEVICE_ALL (DCL_SDIO_FLAGS_DEVICE_CARD1|DCL_SDIO_FLAGS_DEVICE_CARD2)
540#define DCL_SDIO_FLAGS_USAGE_ALL (DCL_SDIO_FLAGS_USAGE_GET_INFORMATION|DCL_SDIO_FLAGS_USAGE_CMD)
541
542
543/*******************************************************************************
544 * DCL_CTRL_CMD for SDIO
545 *******************************************************************************/
546#define SDIO_CMDS \
547 SDIO_CTRL_CMD_REG_WR, \
548 SDIO_CTRL_CMD_REG_WR_ISR, \
549 SDIO_CTRL_CMD_DATA_WR, \
550 SDIO_CTRL_CMD_REG_RD, \
551 SDIO_CTRL_CMD_DATA_RD, \
552 SDIO_CTRL_CMD_CHECK_INTR, \
553 SDIO_CTRL_CMD_ENABLE_INTR, \
554 SDIO_CTRL_CMD_INIT, \
555 SDIO_CTRL_CMD_ABORT, \
556 SDIO_CTRL_CMD_SW_RST, \
557 SDIO_CTRL_CMD_QUERY_BLK_SIZE, \
558 SDIO_CTRL_CMD_SET_BLK_SIZE, \
559 SDIO_CTRL_CMD_GET_BLK_SIZE, \
560 SDIO_CTRL_CMD_ENABLE_IO, \
561 SDIO_CTRL_CMD_SET_BUS_WIDTH, \
562 SDIO_CTRL_CMD_GET_CCCR, \
563 SDIO_CTRL_CMD_GET_FBR, \
564 SDIO_CTRL_CMD_CMD52_READ, \
565 SDIO_CTRL_CMD_CMD52_WRITE, \
566 SDIO_CTRL_CMD_CMD52_WRITE_READ, \
567 SDIO_CTRL_CMD_CMD53_READ, \
568 SDIO_CTRL_CMD_CMD53_WRITE, \
569 SDIO_CTRL_CMD_MCUDMA_READ, \
570 SDIO_CTRL_CMD_MCUDMA_WRITE, \
571 SDIO_CTRL_CMD_CLKPADRED_READ, \
572 SDIO_CTRL_CMD_CLKPADRED_WRITE, \
573 SDIO_CTRL_CMD_FORCEMCU_READ, \
574 SDIO_CTRL_CMD_FORCEMCU_WRITE, \
575 SDIO_CTRL_CMD_GETCLK, \
576 SDIO_CTRL_CMD_SETCLK,
577//guilin
578/*******************************************************************************
579 * DCL_CTRL_DATA_T: Define the Control data structure for each module's command
580 *******************************************************************************/
581
582/* For SDIO_CTRL_CMD_REG_WR, SDIO_CTRL_CMD_REG_WR_ISR, SDIO_CTRL_CMD_REG_RD control command.*/
583typedef struct
584{
585 DCL_SDIO_function_id_enum function;
586 DCL_UINT32 addr; // card's address to access
587 DCL_UINT32 data; // the data want to read from/write from card
588 DCL_SDIO_cmd53_op_enum op; // operation mode
589} SDIO_CTRL_REG_RW_T;
590
591/* For SDIO_CTRL_CMD_DATA_WR, SDIO_CTRL_CMD_DATA_RD, control command.*/
592typedef struct{
593 DCL_SDIO_function_id_enum function; // function
594 DCL_BOOL block; // block mode or not
595 DCL_SDIO_cmd53_op_enum op; // operation mode
596 DCL_UINT16 count; // byte or block count
597 DCL_UINT32 addr; // address
598 DCL_UINT32 buffer; // address of buffer for data transfer
599}SDIO_CTRL_DAT_RW_T;
600
601/* For SDIO_CTRL_CMD_SET_BLK_SIZE, SDIO_CTRL_CMD_GET_BLK_SIZE , control command.*/
602typedef struct{
603 DCL_SDIO_function_id_enum function;
604 DCL_UINT32 size;
605}SDIO_CTRL_SET_BLK_SIZE_T;
606
607/* For SDIO_CTRL_CMD_CHECK_INTR, control command.*/
608typedef struct{
609 DCL_SDIO_function_id_enum function;
610 DCL_BOOL *pending;
611}SDIO_CTRL_CHECK_INTR_T;
612
613/* For SDIO_CTRL_CMD_ENABLE_INTR, control command.*/
614typedef struct{
615 DCL_SDIO_function_id_enum function;
616 DCL_BOOL enable;
617}SDIO_CTRL_ENABLE_T;
618
619/* For SDIO_CTRL_CMD_GET_CCCR and SDIO_CTRL_CMD_GET_FBR, control command.*/
620typedef struct{
621 DCL_UINT8 *buffer;
622 DCL_UINT32 bufferLength;
623}SDIO_CTRL_GET_INFO_T;
624
625typedef struct{
626// rw_dir_enum rw; // directon (input)0=read,1=write
627 kal_uint8 rw; // directon (input)0=read,1=write
628 kal_uint8 func; // function (input)
629 kal_uint8 rdata; // write data or read back data (Input , output)
630 kal_uint8 wdata; // write data or read back data (Input , output)
631 kal_bool raw; // read after write
632 kal_bool stop; // stop data transfer
633 kal_uint32 addr; // address (input)
634 kal_uint8 r5_resp; // R5
635}SDIO_CTRL_CMD52_T;
636
637typedef struct{
638// rw_dir_enum rw; // directon (input)0=read,1=write
639 kal_uint8 rw; // directon (input)0=read,1=write
640 kal_uint8 func; // function (input)
641 kal_uint8 r5_resp; // R5
642// cmd53_op_enum op; // operation mode,0=FIX,1=INC
643 kal_uint8 op; // operation mode,0=FIX,1=INC
644 kal_bool block; // block mode or not
645 kal_uint16 count; // byte or block count
646 kal_uint32 addr; // address
647 kal_uint32 buffer; // address of buffer for data transfer
648}SDIO_CTRL_CMD53_T;
649
650typedef struct{
651 kal_uint32 data;
652}SDIO_CTRL_CMD_REG_T;
653
654#define SDIO_CTRLS \
655 SDIO_CTRL_REG_RW_T rSDIORegRw; \
656 SDIO_CTRL_DAT_RW_T rSDIODatRw; \
657 DCL_SDIO_function_id_enum rSDIOFunction; \
658 SDIO_CTRL_SET_BLK_SIZE_T rSDIOSetBlkSize; \
659 SDIO_CTRL_CHECK_INTR_T rSDIOCheckIntr; \
660 SDIO_CTRL_ENABLE_T rSDIOEnable; \
661 DCL_SD_BITWIDTH rSDIOBusWidth; \
662 SDIO_CTRL_GET_INFO_T rSDIOGetInfo; \
663 SDIO_CTRL_CMD52_T rSDIOCMD52; \
664 SDIO_CTRL_CMD53_T rSDIOCMD53; \
665 SDIO_CTRL_CMD_REG_T rSDIOCMDREG;
666//guilin
667#endif /*__DCL_MSDC_H_FRONT__*/
668#endif /*DCL_DEFINITION_STRUCT*/
669
670#ifdef DCL_DEFINITION_PROTOTYPE
671//#ifndef __DCL_MSDC_H_FRONT__
672//#define __DCL_MSDC_H_FRONT__
673
674/*******************************************************************************
675 * Declare function prototype.
676 *******************************************************************************/
677/* DCL for SD/MMC*/
678/* DCL for SDIO */
679extern DCL_STATUS DclSD_Initialize(void);
680extern DCL_HANDLE DclSD_Open(DCL_DEV dev, DCL_FLAGS flags);
681extern DCL_STATUS DclSD_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
682extern DCL_STATUS DclSD_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
683extern DCL_STATUS DclSD_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
684extern DCL_STATUS DclSD_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
685extern DCL_STATUS DclSD_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
686extern DCL_STATUS DclSD_Close(DCL_HANDLE handle);
687//#endif /*__DCL_MSDC_H_FRONT__*/
688#endif /*DCL_DEFINITION_PROTOTYPE*/
689
690