| yu.dong | c33b307 | 2024-08-21 23:14:49 -0700 | [diff] [blame^] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2016 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | #ifndef _CL1FHRTBACONSTANT_H_ |
| 37 | #define _CL1FHRTBACONSTANT_H_ |
| 38 | |
| 39 | #ifdef MTK_DEV_93M_PREIT |
| 40 | |
| 41 | |
| 42 | /***************************************************************************** |
| 43 | |
| 44 | FILE NAME: cl1fhrtbaconstant.h |
| 45 | |
| 46 | DESCRIPTION: |
| 47 | |
| 48 | This file contains the constant definition of RTBA module in 93m |
| 49 | |
| 50 | *****************************************************************************/ |
| 51 | |
| 52 | /*---------------------------------------------------------------------------- |
| 53 | * Definitions |
| 54 | *----------------------------------------------------------------------------*/ |
| 55 | #define FEC_DDL_RX_MARGIN (850) |
| 56 | #define FEC_DDL_TRX_MARGIN (950) |
| 57 | #define FEC_DDL_RX_MARGIN_CONN_STANDBY_MEAS (5000) |
| 58 | |
| 59 | /** Define for the RTBA Channel related block info. */ |
| 60 | #define RTBA_BASIC_BLOCK_LENGTH (20000) /** The RTBA basic block length in us unit. */ |
| 61 | #define RTBA_XL1_ICS_SYNC_SMALL_BLOCK_LENGTH (80000/3) /** The XL1 sync channel small block reserve length, in us unit. */ |
| 62 | #define RTBA_XL1_CONN_PS_RX_BLOCK_LENGTH (RTBA_BASIC_BLOCK_LENGTH * 6) /** The XL1 connect ps block length. */ |
| 63 | #define RTBA_XL1_SLT_PCH_LOST_DET_BLOCK_LENGTH RTBA_BASIC_BLOCK_LENGTH /** The XL1 PCH Lost block length. */ |
| 64 | #define RTBA_XL1_NSLT_PCH_OVHD_BLOCK_LENGTH RTBA_BASIC_BLOCK_LENGTH /** The XL1 non-slotted PCH overhead block length. */ |
| 65 | #define RTBA_XL1_NSLT_PCH_LONG_BLOCK_LENGTH (RTBA_XL1_NSLT_PCH_OVHD_BLOCK_LENGTH * 16) |
| 66 | |
| 67 | #ifdef MTK_CBP_SYNC_OPTIMIZE |
| 68 | #define XL1_MINI_ACQ_FAST_AGC_ICS_LENGTH (3500) |
| 69 | #endif |
| 70 | |
| 71 | #define XL1_MINI_ACQ_FAST_AGC_LENGTH (5750) /** The XL1 mini acquisition length,which needs to be added to RTB block |
| 72 | when previously preempt, in us unit. */ |
| 73 | #define RTBA_EVL1_ICS_SYNC_SMALL_BLOCK_LENGTH RTBA_BASIC_BLOCK_LENGTH /** The EvL1 Sync pch channel basic block length in us unit. */ |
| 74 | #define RTBA_EVL1_NSLT_CC_OVHD_BLOCK_LENGTH RTBA_BASIC_BLOCK_LENGTH /** The EvL1 non-slotted pch channel basic block length in us unit. */ |
| 75 | #define RTBA_EVL1_CONN_RX_BLOCK_LENGTH RTBA_BASIC_BLOCK_LENGTH /** The EvL1 Connect Rx channel basic block length in us unit. */ |
| 76 | |
| 77 | #define RTBA_XL1_BRP_TAIL_MARGIN_20MS (3*1250) /** 1xRTT's BRP Tail Margin for 20ms frame size (3PCG).*/ |
| 78 | #define RTBA_XL1_BRP_TAIL_MARGIN_26MS (3*1667) /** 1xRTT's BRP Tail Margin for 26ms frame size (3PCG).*/ |
| 79 | #define RTBA_XL1_BRP_TAIL_MARGIN_20MS_TRAFFIC (6*1250) /** 1xRTT's BRP Tail Margin for 20ms FCH frame size (3PCG).*/ |
| 80 | |
| 81 | #define RTBA_SCHE_FAKE_MARGIN_20MS (1250) /** The fake margin for RTBA schedule for RC control.*/ |
| 82 | #define RTBA_SCHE_FAKE_MARGIN_26MS (1667) /** The fake margin for RTBA schedule for RC control.*/ |
| 83 | |
| 84 | #define RTBA_SCHE_CHECK_DSP_IDLE_MARGIN_20MS (1250) /** The check dsp idle margin for RC control.*/ |
| 85 | #define RTBA_SCHE_CHECK_DSP_IDLE_MARGIN_26MS (1667) /** The check dsp idle margin for RC control.*/ |
| 86 | #define RTBA_SCHE_CHECK_DSP_IDLE_MARGIN_20MS_LONG (6250) /** The check dsp idle margin for RC control due to un-alignment timing between IA and MD32, 5*1250.*/ |
| 87 | |
| 88 | #define RTBA_SCHE_CHECK_DSP_IDLE_MARGIN_26MS_LONG (10000) /** The check dsp idle margin for RC control due to un-alignment timing between IA and MD32, 6*1667us.*/ |
| 89 | #define RTBA_SCHE_CHECK_DSP_IDLE_MARGIN_26MS_MED (6666) /** The check dsp idle margin for RC control due to un-alignment timing between IA and MD32, 4*1667us.*/ |
| 90 | |
| 91 | |
| 92 | #define RTBA_SCHE_HSC_PREEMPT_ADVANCE_OFFSET (RTBA_SCHE_CHECK_DSP_IDLE_MARGIN_26MS_MED) /** Indicate the HSC preempt gap for HSC fully/div preemption.*/ |
| 93 | #define RTBA_INVALID_GAP_START_TIME (0xFFFFFFFF) |
| 94 | |
| 95 | |
| 96 | /***************************************************************************** |
| 97 | * End of File |
| 98 | *****************************************************************************/ |
| 99 | #endif |
| 100 | #endif |
| 101 | |