yu.dong | c33b307 | 2024-08-21 23:14:49 -0700 | [diff] [blame^] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2016 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | #ifndef _CL1_SH_RFC_H_ |
| 36 | #define _CL1_SH_RFC_H_ |
| 37 | |
| 38 | /*********************************************************************************** |
| 39 | * |
| 40 | * FILE NAME : cl1shrfc.h |
| 41 | * |
| 42 | * DESCRIPTION : RF control interface defination |
| 43 | * |
| 44 | * HISTORY : |
| 45 | * See Log at end of file |
| 46 | * |
| 47 | ************************************************************************************/ |
| 48 | |
| 49 | |
| 50 | #include "kal_public_api.h" |
| 51 | #include "sysapi.h" |
| 52 | #include "cl1rcapi.h" |
| 53 | #if (!defined(__MD93__)) && (!defined(__MD95__)) |
| 54 | #include "../rfd/cl1_rf_tas_public.h" |
| 55 | #include "cl1d_rf_common_defs.h" |
| 56 | #endif |
| 57 | |
| 58 | /*---------------------------------------------------------------------------- |
| 59 | Global Defines |
| 60 | ----------------------------------------------------------------------------*/ |
| 61 | /* Pll settling time In Echip, TBD, would be replaced by RFD interface*/ |
| 62 | #define RFC_PLL_TIM_ECHIP (246*8) |
| 63 | |
| 64 | #if defined( __MD93__)||defined( __MD95__) |
| 65 | #define RFC_DO_RXPATH_DELAY (128) |
| 66 | #else |
| 67 | #if defined(MT6297) |
| 68 | #define RFC_DO_RXPATH_DELAY (213) |
| 69 | #elif defined(MT6885) || defined(MT6873) |
| 70 | #define RFC_DO_RXPATH_DELAY (193) |
| 71 | #else |
| 72 | #define RFC_DO_RXPATH_DELAY (193) |
| 73 | #endif |
| 74 | #endif |
| 75 | |
| 76 | /**For MD93 and MD95, the RFC_RTT_TRXPATH_DELAY need to set different value!*/ |
| 77 | #ifdef __MD93__ |
| 78 | #define RFC_DO_TRXPATH_DELAY (278) //Same as DO_TXRXDELAY |
| 79 | #elif defined __MD95__ |
| 80 | #define RFC_DO_TRXPATH_DELAY (273) //Same as DO_TXRXDELAY |
| 81 | #else |
| 82 | /**Used to Other Setting ,for example MD97*/ |
| 83 | #if defined(MT6297) |
| 84 | #define RFC_DO_TRXPATH_DELAY (419) //Same as DO_TXRXDELAY /**415 -->419, Tx Transmite Error change from 0.5us to 0.05us for Apollo*/ |
| 85 | #elif defined(MT6885)|| defined(MT6873) |
| 86 | #define RFC_DO_TRXPATH_DELAY (402) //Same as DO_TXRXDELAY /**419 -->399, Tx Transmite Error change from 1.9us to 0.05us for Petrus*/ |
| 87 | #else |
| 88 | #define RFC_DO_TRXPATH_DELAY (402) //Same as DO_TXRXDELAY |
| 89 | #endif |
| 90 | |
| 91 | #endif |
| 92 | |
| 93 | /**For MD93 and MD95, the RFC_RTT_TRXPATH_DELAY need to set different value!*/ |
| 94 | #ifdef __MD93__ |
| 95 | #define RFC_RTT_TRXPATH_DELAY (278) //Same as RTT_TXRXDELAY_INIT |
| 96 | #define RFC_RTT_RXPATH_DELAY (128) |
| 97 | #elif defined __MD95__ |
| 98 | #define RFC_RTT_TRXPATH_DELAY (273) //Same as RTT_TXRXDELAY_INIT |
| 99 | #define RFC_RTT_RXPATH_DELAY (128) |
| 100 | #else |
| 101 | /**Used to Other Setting ,for example MD97*/ |
| 102 | #if defined(MT6297) |
| 103 | #define RFC_RTT_TRXPATH_DELAY (419) //Same as RTT_TXRXDELAY_INIT /**415 -->419, Tx Transmite Error change from 0.5us to 0.05us for Apollo*/ |
| 104 | #define RFC_RTT_RXPATH_DELAY (213) |
| 105 | #elif defined(MT6885) || defined(MT6873) |
| 106 | #define RFC_RTT_TRXPATH_DELAY (402) //Same as RTT_TXRXDELAY_INIT /**419 -->399, Tx Transmite Error change from 1.9us to 0.05us for Petrus*/ |
| 107 | #define RFC_RTT_RXPATH_DELAY (193) |
| 108 | #else |
| 109 | #define RFC_RTT_TRXPATH_DELAY (402) //Same as RTT_TXRXDELAY_INIT |
| 110 | #define RFC_RTT_RXPATH_DELAY (193) |
| 111 | #endif |
| 112 | #endif |
| 113 | |
| 114 | #define RFC_RTT_TXPATH_DELAY (RFC_RTT_TRXPATH_DELAY - RFC_RTT_RXPATH_DELAY) |
| 115 | |
| 116 | #define RFC_RTT_GATE_ON_OFF_DELAY (400/*TBD*/) |
| 117 | |
| 118 | |
| 119 | /* 80ms Period length in Echip*/ |
| 120 | #define RFC_80MS_PERIOD 0xC0000 |
| 121 | |
| 122 | /* PCG Period Length In Echip*/ |
| 123 | #define RFC_RTT_PCG_PERIOD (1536*8) |
| 124 | |
| 125 | /* Slot Period Length In Echip*/ |
| 126 | #define RFC_EVDO_SLOT_PERIOD (2048*8) |
| 127 | |
| 128 | |
| 129 | typedef enum |
| 130 | { |
| 131 | RFC_PATH_RxM = 0, |
| 132 | RFC_PATH_RxD, |
| 133 | RFC_PATH_RxS, |
| 134 | RFC_PATH_Tx, |
| 135 | RFC_MAX_PATH |
| 136 | }RfcPathTypT; |
| 137 | |
| 138 | typedef enum |
| 139 | { |
| 140 | RFC_FREEZE_NONE = 0, |
| 141 | RFC_TX_FREEZE, |
| 142 | RFC_TX_UNFREEZE, |
| 143 | }RfcFreezeTypT; |
| 144 | |
| 145 | |
| 146 | typedef enum |
| 147 | { |
| 148 | RFC_TASK_REQUEST = 0, |
| 149 | RFC_FRAME_REQUEST, |
| 150 | RFC_SLOT_PCG_REQUEST |
| 151 | }RfcRequestTypT; |
| 152 | |
| 153 | |
| 154 | typedef enum |
| 155 | { |
| 156 | RFC_PATH_OFF, |
| 157 | RFC_PATH_OFF_ONGOING, |
| 158 | RFC_PATH_ON, |
| 159 | RFC_PATH_ON_ONGOING |
| 160 | }RfcPathStatusT; |
| 161 | |
| 162 | |
| 163 | typedef enum |
| 164 | { |
| 165 | RFC_PATH_RC_OFF, |
| 166 | RFC_PATH_RC_ONGOING, |
| 167 | RFC_PATH_RC_ON |
| 168 | }RfcPathRcStatusT; |
| 169 | |
| 170 | |
| 171 | typedef enum |
| 172 | { |
| 173 | RFC_IDLE, |
| 174 | RFC_1X_MAIN_ONLY, |
| 175 | RFC_1X_DIV_ONLY, |
| 176 | RFC_1X_DIV_RX, |
| 177 | RFC_DO_MAIN_ONLY, |
| 178 | RFC_DO_DIV_ONLY, |
| 179 | RFC_DO_DIV_RX, |
| 180 | RFC_SHDR, |
| 181 | RFC_1X_DFS, |
| 182 | RFC_DO_DFS |
| 183 | }RfcScenarioT; |
| 184 | |
| 185 | |
| 186 | typedef enum |
| 187 | { |
| 188 | ACTION_OFF = 0, |
| 189 | ACTION_ON = 1, |
| 190 | ACTION_NUM = 2 |
| 191 | }RfcActionOnOffT; |
| 192 | |
| 193 | typedef struct |
| 194 | { |
| 195 | SysAirInterfaceT Interface; |
| 196 | SysCdmaBandT Band; |
| 197 | kal_uint16 Chan; |
| 198 | RfcPathTypT Path; |
| 199 | RfcActionOnOffT ActionTyp; |
| 200 | RfcRequestTypT RequestTyp; |
| 201 | void* CommonParmPtr; |
| 202 | }RfcActionT; |
| 203 | |
| 204 | |
| 205 | typedef struct |
| 206 | { |
| 207 | /* 80ms timing, in echip*/ |
| 208 | kal_int32 Timing; |
| 209 | |
| 210 | /* Super Frame number*/ |
| 211 | kal_uint64 SuperFrame; |
| 212 | |
| 213 | /* Immaction, if TRUE, "Timing&SuperFrame" would be obmitted*/ |
| 214 | kal_bool ImmAction; |
| 215 | }RfcActionTimeT; |
| 216 | |
| 217 | |
| 218 | typedef struct |
| 219 | { |
| 220 | /* Req Timing Info, Filled Rx Modules(RTBA) in FH |
| 221 | * if "RcCtrl" is TRUE, filled with RC timing. |
| 222 | * Otherwise, filled with RF timing. |
| 223 | */ |
| 224 | RtbaRcTimingTypeT ReqTiming; |
| 225 | |
| 226 | /* Rake Ddl Indication , for Rx Only*/ |
| 227 | kal_bool RakeDdlInd; |
| 228 | |
| 229 | /* Rc Control Indication*/ |
| 230 | kal_bool RcCtrl; |
| 231 | |
| 232 | /* Used for Rc RxOff with "RcCtrl"== TRUE Only*/ |
| 233 | Cl1RcReqEndIndT EndIndication; |
| 234 | |
| 235 | /* Access Tx Indication*/ |
| 236 | kal_bool AcTxInd; |
| 237 | |
| 238 | /* Action body*/ |
| 239 | RfcActionT Action; |
| 240 | |
| 241 | /* Action Timing, Filled by Tx Modules in Task(Without RTBA) |
| 242 | * "ImmAction" is valid for both Tx and Rx immedaite action. |
| 243 | */ |
| 244 | RfcActionTimeT ActionTiming; |
| 245 | }RfcActionReqT; |
| 246 | |
| 247 | |
| 248 | /*---------------------------------------------------------------------------- |
| 249 | Global Data |
| 250 | ----------------------------------------------------------------------------*/ |
| 251 | |
| 252 | /*---------------------------------------------------------------------------- |
| 253 | Global Variables |
| 254 | ----------------------------------------------------------------------------*/ |
| 255 | #if (!defined(__MD93__)) && (!defined(__MD95__)) |
| 256 | extern C2K_CUSTOM_TAS_STATE_E AntCurrentState[RF_Band_NUM_MAX]; |
| 257 | extern C2K_CUSTOM_TAS_STATE_E GetAntCurrentState(SysCdmaBandT band); |
| 258 | #endif |
| 259 | |
| 260 | /*---------------------------------------------------------------------------- |
| 261 | Global Function Prototypes |
| 262 | ----------------------------------------------------------------------------*/ |
| 263 | void Cl1ShRfcInit(void); |
| 264 | void Cl1ShRfcActionReq(RfcActionReqT *ActionReqPtr); |
| 265 | void Cl1ShRfcMain(SysAirInterfaceT Interface); |
| 266 | void Cl1ShRfcStatChange(kal_uint32 Param); |
| 267 | void Cl1ShRfcRcStatToOff(kal_uint32 Param); |
| 268 | void Cl1ShRfcRcStatToOn(kal_uint32 Param); |
| 269 | RfcPathStatusT Cl1ShRfcRfStatGet(SysAirInterfaceT Interface, RfcPathTypT Path); |
| 270 | RfcScenarioT Cl1ShRfcScenarioGet(void); |
| 271 | void Cl1ShRfcTxFreezeReq(SysAirInterfaceT Interface); |
| 272 | void Cl1ShRfcTxUnFreezeReq(SysAirInterfaceT Interface); |
| 273 | kal_bool Cl1ShRfcTxFreezeReqCheck(SysAirInterfaceT Interface); |
| 274 | RfcPathRcStatusT Cl1ShRfcRcStatGet(SysAirInterfaceT Interface, RfcPathTypT Path); |
| 275 | void Cl1RfcGetNextRxBoundary(SysAirInterfaceT Interface, kal_int32 *EchipTime, kal_uint64 *SuperFrame); |
| 276 | void Cl1ShRfcRcReq(SysAirInterfaceT Interface, RfcPathTypT Path, RfcActionOnOffT ActionTyp, RtbaRcTimingTypeT *RcReqTimingPtr, Cl1RcReqEndIndT EndIndication, kal_bool RakeDdlInd, kal_bool AcTxInd); |
| 277 | void Cl1ShRfcrRxPathInfoGet(SysAirInterfaceT Interface, kal_uint16 *BandPtr, kal_uint16 *ChanPtr); |
| 278 | void Cl1ShRfcTxOnTimingLogging(void); |
| 279 | |
| 280 | #ifdef SYS_OPTION_TX_TAS_ENABLE |
| 281 | kal_bool Cl1ShRfcOnlyRfImmediateOn(SysAirInterfaceT CurrInterface, kal_uint16 CurrBand, |
| 282 | kal_uint16 CurrChan); |
| 283 | kal_bool Cl1ShRfcOnlyRfImmediateOff(SysAirInterfaceT CurrInterface, kal_uint16 CurrBand, |
| 284 | kal_uint16 CurrChan); |
| 285 | #endif |
| 286 | #ifdef MTK_DEV_TEMP_C2K_OTFC |
| 287 | extern kal_uint8 Cl1ShTxDpdOtfcHistoryRecPush(SysAirInterfaceT Interface, kal_uint32 Channel, SysCdmaBandT BandClass); |
| 288 | extern kal_uint8 Cl1ShTxDpdOtfcGetHistoryRecIdx(SysAirInterfaceT Interface, kal_uint32 Channel, SysCdmaBandT BandClass); |
| 289 | #endif |
| 290 | /***************************************************************************** |
| 291 | * End of File |
| 292 | *****************************************************************************/ |
| 293 | #endif |
| 294 | |