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192.168.1.100 / T800_MD_V1.6 / c33b3079c38f91561c2f84f1ebed20ad8c60532a / . / mcu / interface / l1 / cl1 / common / cl1tstmetaif.h
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yu.dongc33b3072024-08-21 23:14:49 -0700[diff] [blame^]1/*******************************************************************************
2* Modification Notice:
3* --------------------------
4* This software is modified by MediaTek Inc. and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2016
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*******************************************************************************/
35
36/*******************************************************************************
37*
38* Filename:
39* ---------
40* cl1tstmetaif.h
41*
42* Project:
43* --------
44* MTXXXX Project
45*
46* Description:
47* ------------
48* This file contains the log IQ functions.
49*
50* Author:
51* -------
52*
53*
54*==============================================================================
55* HISTORY
56* Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57*------------------------------------------------------------------------------
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238*==============================================================================
239******************************************************************************/
240
241#ifndef _CL1TST_META_IF_H_
242#define _CL1TST_META_IF_H_
243
244/*----------------------------------------------------------------------------
245 Include Files
246----------------------------------------------------------------------------*/
247#include "kal_general_types.h"
248#include "kal_public_defs.h"
249#include "ft_msg_common.h"
250#include "cl1d_rf_public.h"
251#include "systyp.h"
252#include "cl1_rf_public.h"
253
254#define CL1TST_TEMP_SECTION_NUM 8
255#define CL1TST_FREQ_SECTION_NUM 16
256#define CL1TST_RX_PATH_NUM 3
257#define CL1TST_POWER_MODE_NUM 2
258#define CL1TST_LNA_MODE_NUM 8
259#define CL1TST_PA_SECTION_NUM 8
260#define CL1TST_PA_MODE_NUM 3
261
262#define CL1TST_FHC_TX_ELEMENT_NUM 1000
263#define CL1TST_FHC_RX_ELEMENT_NUM 1000
264
265#define CL1TST_RX_PATH_MAIN (1 << 0)
266#define CL1TST_RX_PATH_DIV (1 << 1)
267#define CL1TST_RX_PATH_SHDR (1 << 2)
268
269#define CL1TST_CAL_RSSI_WIN_ECHIP 0x1000 /* unit E chip (512 chips) */
270#define CL1TST_SUP_FRAME_LEN_ECHIP ST_9M_CNTS_PER_80MS /* unit E chip (80 ms) */
271#define CL1TST_SLOT_LEN_ECHIP ST_9M_CNTS_PER_1PT67MS /* unit E chip (1.66666 ms) */
272#define CL1TST_PCG_LEN_ECHIP ST_9M_CNTS_PER_1PT25MS /* unit E chip (1.25 ms) */
273#define CL1TST_HALF_SLOT_LEN_ECHIP 0x2000 /* unit E chip (1.66666 ms)/2 */
274#define CL1TST_HALF_SLOT_LEN_US 0x341 /* unit us (0.83333 ms) */
275#if (!defined(__MD93__)) && (!defined(__MD95__))
276#define CL1TST_FIVE_PCG_LEN_US 0x186A /* unit us (6.25 ms) */
277#endif
278#define CL1TST_QUART_SLOT_LEN_ECHIP 0x1000 /* unit E chip (1.66666 ms)/4 */
279#define CL1TST_TRC_RSSI_WIN_NUM 12 /* 5ms */
280#define CL1TST_RX_ON_HRT_ECHIP 0x7AE /* unit E chip (200 us), TBD */
281#define CL1TST_RX_DELAY_ECHIP 20 /* unit E chip (20chip), TBD */
282
283#define CL1TST_MOD_HALF_SLOT_ECHIP(A) (A & 0x000001FFF)
284#define CL1TST_MOD_SLOT_ECHIP(A) (A & 0x000003FFF)
285#define CL1TST_MOD_CAL_RSSI_WIN_ECHIP(A) (A & 0x000000FFF)
286
287#define CL1TST_MOD_SUP_FRAME_ECHIP(A) while (A >= ST_9M_CNTS_PER_80MS) \
288 { \
289 A -=ST_9M_CNTS_PER_80MS; \
290 }
291
292
293#define CL1TST_NST_MAX_LIST_NUM 50
294#define CL1TST_NST_MAX_TX_PWR_COUNT 20
295#define CL1TST_NST_MAX_RX_PWR_COUNT 20
296#define CL1TST_RF_BAND_NUM_MAX 5
297#if defined( __MD93__)||defined( __MD95__)
298#define CL1TST_93M_95M_RXAGC_CFG_DELAY 14 /*in 93M and 95M, cfg complete after 10.84ms, and after 1slot,dsp send rssi to IA(after 12.5ms), delay 14ms to make sure rssi is readed after cfg really set*/
299#else
300#define CL1TST_97M_RXAGC_CFG_DELAY 7 /*in 97M,invoking cfg Api in n slot(or pcg). cfg take affect in slot(pcg)n+1,RFD get rssi in n+2 slot(pcg), L1 get it in n+3 slot(pcg), delay 7ms to rssi is readed after cfg really set*/
301#endif
302
303
304/** Tx power differ between bb sine tone and modulate signal if bb sine freq sel is 6 and AMP is 1/2 */
305#define CL1TST_TX_DIFFER_BB_TONE_MODULDATE_SIG (84)
306
307/** define RFD test mode enumeration */
308typedef enum
309{
310 CL1TST_RFD_RX_TST_MODE = 0,
311 CL1TST_RFD_TX_TST_MODE = 1,
312 CL1TST_RFD_META_MODE = 2,
313 CL1TST_RFD_INVALID = 0xFF
314} Cl1TstRfdTstModeT;
315
316typedef enum
317{
318 CL1TST_RX_AGC_FSM_ICS = 0,
319 CL1TST_RX_AGC_FSM_CAL = 1,
320 CL1TST_RX_AGC_FSM_INVALID = 0x7FFF
321}Cl1TstRxAgcFsmT;
322
323/* this enum is TBD (temp use) */
324typedef enum
325{
326 MIPI0,
327 MIPI1,
328 MIPI2,
329 MIPI3,
330 MIPI_END,
331 BSI1 = MIPI_END,
332 BSI_NAME_MAX,
333 BSI_NAME_INVALID = BSI_NAME_MAX
334} BsiNameT;
335
336/** define the RF mode enumeration */
337typedef enum
338{
339 CL1TST_RF_MODE_1XRTT,
340 CL1TST_RF_MODE_EVDO
341} Cl1TstRfModeT;
342
343/** define the RX agc control mode */
344typedef enum
345{
346 CL1TST_RX_AGC_AUTO = 0,
347 CL1TST_RX_AGC_MANUAL = 1
348} Cl1TstRxAgcModeT;
349
350/** define the command action enumeration */
351typedef enum
352{
353 CL1TST_ACTION_OFF,
354 CL1TST_ACTION_ON
355} Cl1TstActionT;
356
357/** define the NVRAM operation enumeration */
358typedef enum
359{
360 CL1TST_NV_NOT_UPDATE,
361 CL1TST_NV_UPDATE,
362 CL1TST_NV_INVALID = 0xFF
363} Cl1TstNvOptT;
364
365/** define the step indication enumeration */
366typedef enum
367{
368 CL1TST_FHC_STEP_IND_NORMAL, /* next step is normal step */
369 CL1TST_FHC_STEP_IND_RETUNE, /* next step is retune step */
370 CL1TST_FHC_STEP_IND_END, /* current step is last step */
371 CL1TST_FHC_STEP_IND_SWITCH, /* next step is switch step */
372 CL1TST_FHC_STEP_IND_NUM
373} Cl1TstFhcStepIndT;
374
375/** define the transmission signal type enumeration */
376typedef enum
377{
378 CL1TST_TX_SIG_TYPE_RF_TONE,
379 CL1TST_TX_SIG_TYPE_BB_TONE,
380 CL1TST_TX_SIG_TYPE_1X,
381 CL1TST_TX_SIG_TYPE_DO_PILOT,
382 CL1TST_TX_SIG_TYPE_DO_ST2
383} Cl1TstTxSigTypeT;
384
385/** define the command execute status enumeration */
386typedef enum
387{
388 CL1TST_REQ_SUCCESS,
389 CL1TST_REQ_FAILURE,
390 CL1TST_REQ_NOT_SUPPORT,
391 CL1TST_REQ_INVALID = 0x7FFFFFFF
392} Cl1TstReqStatusE;
393
394/** define the command Nst Cmd Status enumeration */
395typedef enum
396{
397 CL1TST_NST_CMD_SUCCESS,
398 CL1TST_NST_CMD_FAILURE_CMD,
399 CL1TST_NST_CMD_FAILURE_ICS,
400
401 CL1TST_NST_CMD_FAILURE_SYNC,
402
403 CL1TST_NST_CMD_FAILURE_TCH,
404
405 CL1TST_NST_CMD_FAILURE_HHO,
406 CL1TST_NST_CMD_FAILURE_NOT_SUPPORT,
407 CL1TST_NST_CMD_INVALID = 0x7FFFFFFF
408} Cl1TstNstCmdStatusE;
409
410
411/* CL1TST command type */
412typedef enum
413{
414 CL1TST_CMD_GET_RF_PLAT_INFO =0,
415 CL1TST_CMD_RFD_TEST_MODE_REQ =1,
416 CL1TST_CMD_RFD_INIT_REQ =2,
417 CL1TST_CMD_SET_MIPI_CW =3,
418 CL1TST_CMD_GET_MIPI_CW =4,
419 CL1TST_CMD_SET_SPI_DATA =5,
420 CL1TST_CMD_GET_SPI_DATA =6,
421 CL1TST_CMD_TRANSMIT_CTRL =7,
422 CL1TST_CMD_RECEIVE_CTRL =8,
423 CL1TST_CMD_AFC_CONFIG =9,
424 CL1TST_CMD_TX_AGC_CONFIG =10,
425 CL1TST_CMD_TX_POWER_QUERY =11,
426 CL1TST_CMD_RX_AGC_CONFIG =12,
427 CL1TST_CMD_RX_RSSI_QUERY =13,
428 CL1TST_CMD_AFC_CAL_DATA_SET =14,
429 CL1TST_CMD_AFC_CAL_DATA_GET =15,
430 CL1TST_CMD_RX_CAL_DATA_SET =16,
431 CL1TST_CMD_RX_CAL_DATA_GET =17,
432 CL1TST_CMD_TX_CAL_DATA_SET =18,
433 CL1TST_CMD_TX_CAL_DATA_GET =19,
434 CL1TST_CMD_FHC_START =20,
435 CL1TST_CMD_DPD_PA_DATA_SET =21,
436 CL1TST_CMD_DPD_PA_DATA_GET =22,
437 CL1TST_CMD_DPD_AM_PM_DATA_SET =23,
438 CL1TST_CMD_DPD_AM_PM_DATA_GET =24,
439 CL1TST_CMD_DPD_FAC_START =25,
440#ifndef __MD93__
441 CL1TST_CMD_RX_LNA_PWR_RANGE_GET =26,
442#endif
443#if (!defined(__MD93__)) && (!defined(__MD95__))
444 CL1TST_CMD_RX_GAIN_GET =27,
445 CL1TST_CMD_TX_GAIN_GET =28,
446 CL1TST_CMD_SET_BPI_DATA =29,
447 CL1TST_CMD_GET_BPI_DATA =30,
448 CL1TST_CMD_RX_AGC_FIX_MANUAL_CONFIG =31,
449 CL1TST_CMD_RXDFE_IQ_DUMP_CFG =32,
450 CL1TST_CMD_TXDFE_IQ_DUMP_CFG =33,
451 CL1TST_CMD_TXKDFE_IQ_DUMP_CFG =34,
452 CL1TST_CMD_RXTXDFE_IQ_DUMP_QUERY =35,
453#endif
454
455 CL1TST_CMD_FACTORY_MODE_REQ =40,
456 CL1TST_CMD_NORMAL_MODE_REQ =41,
457 CL1TST_CMD_SET_MEID =42,
458 CL1TST_CMD_GET_MEID =43,
459 CL1TST_CMD_UBIN_INIT =44,
460 CL1TST_CMD_UBIN_DEINIT =45,
461
462 CL1TST_CMD_NST_POWER_UP =0x100,
463 CL1TST_CMD_NST_TCH_FER_CFG =0x101,
464 CL1TST_CMD_NST_TX_PWR_MEAS_CFG =0x102,
465 CL1TST_CMD_NST_RX_PWR_MEAS_CFG =0x103,
466 CL1TST_CMD_NST_LIST_MODE_SET_CFG =0x104,
467 CL1TST_CMD_NST_ENTER_TEST_MODE =0x105,
468 CL1TST_CMD_NST_EXIT_TEST_MODE =0x106,
469
470 CL1TST_CMD_RX_ANT_TESTMODE_SET_REQ =0x120,
471
472 CL1TST_CMD_TARGET_ASSERT =0x3E8,
473
474 CL1TST_CMD_INVALID =0x7FFFFFFF
475} Cl1TstCmdTypeE;
476
477#if 0
478#ifdef MTK_PLT_ON_PC_IT
479/* under construction !*/
480/* under construction !*/
481#endif
482#endif
483
484/** define RF platform information getting command structure */
485typedef struct
486{
487 kal_uint32 Reserved;
488} Cl1TstGetRfPlatInfoCmdT;
489
490/** define RF platform information for calibration */
491typedef struct
492{
493 kal_uint16 RfId;
494 kal_uint16 XoType;
495 kal_uint32 BandSupportBmp; // Band support bitmap
496 kal_uint32 RxDivSupportBmp;// RXD band support bitmap
497
498 kal_uint32 MipiSupportBmp; // MIPI band support bitmap
499 kal_uint32 DpdSupportBmp; // DPD band support bitmap
500 kal_uint32 RxSynthNum; // 1: main+div, 2: main+div+SHDR
501 kal_uint32 C2kNsftCapability; // Bit0 indicate the List Nsft Support: 0 means modmem is not support List Nsft; 1: modmem is support List Nsft(5Frame Tx Meas);
502#ifndef __MD93__
503 kal_uint32 OtherCapability; //bit0 used indicate if using cw for rx cal: 0 is disable, 1 is enable, other bits reserved.
504#endif
505}Cl1TstPlatInfoFacT;
506
507/** define RF platform information getting confirm structure */
508typedef struct
509{
510 /* Request execute status */
511 Cl1TstReqStatusE Status;
512
513 /* Platform info for factory calibration */
514 Cl1TstPlatInfoFacT PlatInfoFac;
515}Cl1TstGetRfPlatInfoRspT;
516
517/** define RFD test mode request structure */
518typedef struct
519{
520 /** [in] - 0: 1xRTT, 1: EVDO */
521 kal_uint8 RfMode;
522
523 /** [in] - 1: test mode enable
524 0: test mode disablein */
525 kal_uint8 TstModeEn;
526
527 /** [in] - bit0: RX test mode
528 bit1: TX test mode
529 bit2: META mode
530 Note: just one bit can be set/clear every time
531 */
532 kal_uint8 TstModeBmp;
533
534 /** [in] - 1: L1 normal mode enable */
535 kal_uint8 L1NorModeEn;
536} Cl1TstRfdTestModeReqCmdT;
537
538/** define RFD test mode confirm structure */
539typedef struct
540{
541 /* Request execute status */
542 Cl1TstReqStatusE Status;
543} Cl1TstRfdTestModeReqRspT;
544
545/** define RF driver init command structure */
546typedef struct
547{
548 kal_uint32 Reserved;
549} Cl1TstRfdInitReqCmdT;
550
551/** define RF driver init response structure */
552typedef struct
553{
554 /* Request execute status */
555 Cl1TstReqStatusE Status;
556} Cl1TstRfdInitReqRspT;
557
558/** define MIPI codeword setting command structure */
559typedef struct
560{
561 kal_uint16 MipiPort;
562 kal_uint16 Reserved;
563 kal_uint32 MipiUsid;
564 kal_uint32 MipiAddr;
565 kal_uint32 MipiData;
566} Cl1TstSetMipiCodeWordCmdT;
567
568/** define MIPI codeword setting confirm structure */
569typedef struct
570{
571 /* Request execute status */
572 Cl1TstReqStatusE Status;
573} Cl1TstSetMipiCodeWordRspT;
574
575/** define MIPI codeword getting command structure */
576typedef struct
577{
578 kal_uint16 MipiPort;
579 kal_uint16 Reserved;
580 kal_uint32 MipiUsid;
581 kal_uint32 MipiAddr;
582} Cl1TstGetMipiCodeWordCmdT;
583
584/** define MIPI codeword getting confirm structure */
585typedef struct
586{
587 /* Request execute status */
588 Cl1TstReqStatusE Status;
589
590 /* MIPI data */
591 kal_uint32 MipiData;
592} Cl1TstGetMipiCodeWordRspT;
593
594/** define SPI data setting command structure */
595typedef struct
596{
597 kal_uint16 SpiId;
598 kal_uint16 Reserved;
599 kal_uint32 SpiAddr;
600 kal_uint32 SpiData;
601} Cl1TstSetSpiDataCmdT;
602
603/** define SPI data setting confirm structure */
604typedef struct
605{
606 /* Request execute status */
607 Cl1TstReqStatusE Status;
608} Cl1TstSetSpiDataRspT;
609
610/** define SPI data getting command structure */
611typedef struct
612{
613 kal_uint16 SpiId;
614 kal_uint16 Reserved;
615 kal_uint32 SpiAddr;
616} Cl1TstGetSpiDataCmdT;
617
618/** define SPI data getting confirm structure */
619typedef struct
620{
621 /* Request execute status */
622 Cl1TstReqStatusE Status;
623
624 /* SPI data */
625 kal_uint32 SpiData;
626} Cl1TstGetSpiDataRspT;
627
628/** define 1xRTT signal parameters */
629typedef struct
630{
631 /* Only for RTT */
632 /**0->RC1,1->RC2, etc*/
633 kal_uint8 RevRc;
634 /* Only for RTT */
635 //0: ACCESS, 1: FCH 2: FCH+SCH
636 kal_uint8 ChnType;
637 /* Only for RTT */
638 /**0->Full,1->Half Rate, etc*/
639 kal_uint8 FchRate;
640 /* Only for RTT */
641 kal_uint8 SchRate;
642
643 /* Only for RTT */
644 kal_uint16 GatePat; //GateOn/Off pattern
645
646 /* Only for RTT */
647 kal_uint16 FpcPat; //FPC pattern
648
649 /* Only for RTT */
650 kal_uint16 TxPreamble;
651
652 /* Only for RTT */
653 kal_uint16 LcmLow;
654
655 /* Only for RTT */
656 kal_uint16 SchWc; //Walsh code for SCH channel
657
658 /* Only for RTT */
659 kal_uint16 RaDly; //RA chip delay for access transmission
660
661 /* Only for RTT */
662 kal_uint16 TurboEn; //Indicate Turbo or CC encode for SCH channel
663 kal_uint16 Reserved;
664
665} Cl1Tst1xSigParaT;
666
667/** define RF transmitter control command structure */
668typedef struct
669{
670 /* 0: 1xRTT, 1: EVDO */
671 kal_uint8 RfMode;
672
673 /* 0: OFF, 1: ON */
674 kal_uint8 Action;
675
676 /* 0: TXDFE RF tone for 1xRTT and EVDO
677 1: TXDFE BB signal tone for 1xRTT and EVDO
678 2: reverse 1xRTT signal for 1xRTT
679 3: reverse EVDO pilot only for EVDO
680 4: reverse EVDO subtype2 for EVDO */
681 kal_uint8 SigType;
682
683 /* CDMA Band Class to turn on*/
684 kal_uint8 BandClass;
685
686 /* Channel Number to turn on*/
687 kal_uint16 ChannelNum;
688
689 /* Reserved */
690 kal_uint16 Reserved1;
691
692 /* Frequency offset for RF tone transmission */
693 kal_uint32 FreqOffset;
694
695 /* BB tone configuration parameters */
696 kal_uint32 BbToneCfg;
697
698 Cl1Tst1xSigParaT RttSigPara;
699
700} Cl1TstTransmitCtrlCmdT;
701
702/** define RF transmitter control confirm structure */
703typedef struct
704{
705 /* Request execute status */
706 Cl1TstReqStatusE Status;
707} Cl1TstTransmitCtrlRspT;
708
709/** define RF receive control command structure */
710typedef struct
711{
712 /* 0: 1xRTT, 1: EVDO */
713 kal_uint8 RfMode;
714
715 /* 0: OFF, 1: ON */
716 kal_uint8 Action;
717
718 /* bit0 for Main, bit1 for Div, bit2 for SHDR */
719 kal_uint8 PathBitmap;
720
721 /* Band Class to turn on*/
722 kal_uint8 BandClass;
723
724 /* Channel number to turn on*/
725 kal_uint16 ChannelNum;
726
727 /* Rx AGC FSM, 0 : Auto(RSSI scan) 1: calibration */
728 kal_uint16 RxAgcFsm;
729
730} Cl1TstReceiveCtrlCmdT;
731
732/** define RF receive control confirm structure */
733typedef struct
734{
735 /* Request execute status */
736 Cl1TstReqStatusE Status;
737} Cl1TstReceiveCtrlRspT;
738
739/** define AFC configure command structure */
740typedef struct
741{
742 /* Manual for auto mode*/
743 kal_uint8 CtrlMode;
744
745 /* Cap Id valid indication*/
746 kal_uint8 CapIdValid;
747
748 /* Cap Id*/
749 kal_uint16 CapId;
750
751 /* Reserved */
752 kal_uint8 Reserved;
753
754 /* AFC DAC valid indication*/
755 kal_uint8 DacValid;
756
757 /*AFC DAC value*/
758 kal_uint16 DacValue;
759} Cl1TstAfcConfigCmdT;
760
761/** define AFC configure confirm structure */
762typedef struct
763{
764 /* Request execute status */
765 Cl1TstReqStatusE Status;
766} Cl1TstAfcConfigRspT;
767
768/** define Tx AGC configuration command structure for RF test and traditional calibration */
769typedef struct
770{
771 /* 0: 1xRTT, 1: EVDO */
772 kal_uint8 RfMode;
773
774 /* 0: APT mode, 1: DPD mode */
775 kal_uint8 PaType;
776
777 /* 0: fix power 1: manual mode */
778 kal_uint8 CtrlMode;
779
780 /* ILPC enable or disable */
781 kal_uint8 IlpcEnable;
782
783 /* PA table index */
784 kal_uint8 PaTblIdx;
785
786 /* PA mode, 0: high, 1: middle, 2: low */
787 kal_uint8 PaMode;
788
789 /* Tx Power in dBm for fix power, Q5*/
790 kal_int16 TxPwr;
791
792 /* Tx Power in dBm for calibration, Q5*/
793 kal_int16 TxPwrCal;
794
795 /* PA gain, Q5 dBm */
796 kal_int16 PaGain;
797
798 /* Coupler loss, Q5 dB */
799 kal_int16 CpLoss;
800
801 /* AM */
802 kal_int16 Am;
803
804 /* PM */
805 kal_int16 Pm;
806
807 /* 0/1*/
808 kal_uint8 Vm1;
809
810 /*0/1*/
811 kal_uint8 Vm2;
812
813 /* voltage, in unit of mV*/
814 kal_uint16 Vcc;
815
816} Cl1TstTxAgcConfigCmdT;
817
818/** define Tx AGC configuration confirm structure for RF test and traditional calibration */
819typedef struct
820{
821 /* Request execute status */
822 Cl1TstReqStatusE Status;
823} Cl1TstTxAgcConfigRspT;
824
825/** define DDPC result getting command structure */
826typedef struct
827{
828 kal_uint8 Reserved;
829} Cl1TstTxPowerQueryCmdT;
830
831/** define DDPC result getting confirm structure */
832typedef struct
833{
834 /* Request execute status */
835 Cl1TstReqStatusE Status;
836
837 /* Tx power, unit is Q5 dBm */
838 kal_int16 Power;
839 kal_int16 Reserved;
840} Cl1TstTxPowerQueryRspT;
841
842/** define Rx AGC configuration command structure for RF test and traditional calibration */
843typedef struct
844{
845 /* 0: 1xRTT, 1: EVDO */
846 kal_uint8 RfMode;
847
848 /* Bit0: main antenna, Bit1: diversity antenna, Bit2: SHDR */
849 kal_uint8 PathBitMap;
850
851 /* 0: Auto, 1: Manual for calibration and test, 2: RSSI scan */
852 kal_uint8 CtrlMode;
853
854 /* 0: high power mode, 1: low power mode */
855 kal_uint8 PwrMode;
856
857 /* 0: stage 0, 1: stage 1....5: stage 5 */
858 kal_uint8 LnaMode;
859
860#ifdef __MD93__
861 kal_uint8 Reserved1;
862#else
863 /* 0: disable, 1: enable */
864 kal_uint8 DigGainFix;
865#endif
866
867 /* Reserved */
868 kal_uint16 Reserved2;
869
870} Cl1TstRxAgcConfigCmdT;
871
872/** define Rx AGC configuration confirm structure for RF test and traditional calibration */
873typedef struct
874{
875 /* Request execute status */
876 Cl1TstReqStatusE Status;
877} Cl1TstRxAgcConfigRspT;
878
879
880/** define RSSI query command structure */
881typedef struct
882{
883 /* 0: 1xRTT, 1: EVDO */
884 kal_uint8 RfMode;
885
886 /* Bit0: main antenna, Bit1: diversity antenna, Bit2: SHDR */
887 kal_uint8 PathBitMap;
888
889 /* Reserved */
890 kal_uint16 Reserved;
891} Cl1TstRxRssiQueryCmdT;
892
893/** define RSSI query confirm structure */
894typedef struct
895{
896 /* Request execute status */
897 Cl1TstReqStatusE Status;
898
899 /* Main antenna Rx power, unit is Q5 dBm */
900 kal_int16 RxMainPower;
901
902 /* Diversity antenna Rx power, unit is Q5 dBm */
903 kal_int16 RxDivPower;
904
905} Cl1TstRxRssiQueryRspT;
906
907/** define AFC calibration data setting command structure */
908typedef struct
909{
910 /* update NVRAM flag, 0: do not update, 1: update */
911 kal_uint8 UpdateNvram;
912
913 /* Reserved */
914 kal_uint8 Reserved1;
915
916 /* Reserved */
917 kal_uint16 Reserved2;
918
919 /* AFC calibration data */
920 CL1D_RF_AFC_DATA_T AfcCalData;
921
922} Cl1TstAfcCalDataSetCmdT;
923
924/** define AFC calibration data setting confirm structure */
925typedef struct
926{
927 /* Request execute status */
928 Cl1TstReqStatusE Status;
929} Cl1TstAfcCalDataSetRspT;
930
931/** define AFC calibration data getting command structure */
932typedef struct
933{
934 kal_uint32 Reserved;
935} Cl1TstAfcCalDataGetCmdT;
936
937/** define AFC calibration data getting confirm structure */
938typedef struct
939{
940 /* Request execute status */
941 Cl1TstReqStatusE Status;
942
943 /* AFC calibration data */
944 /* LID:NVRAM_EF_CL1_AFC_DATA__LID */
945 CL1D_RF_AFC_DATA_T AfcCalData;
946
947} Cl1TstAfcCalDataGetRspT;
948
949/** define Rx calibration data structure */
950typedef struct
951{
952 /* High power mode path loss */
953 /* LID NVRAM_EF_CL1_MAIN_RX_PATH_LOSS_HPM_BAND_X_LID */
954 CL1D_RF_RX_PATH_LOSS_COMP_T RxPLossHPM;
955
956 /* Low power mode path loss */
957 /* LID:NVRAM_EF_CL1_MAIN_RX_PATH_LOSS_LPM_BAND_X_LID */
958 CL1D_RF_RX_PATH_LOSS_COMP_T RxPLossLPM;
959} Cl1TstRxCalDataT;
960
961/** define Rx calibration data setting command structure */
962typedef struct
963{
964 /* update NVRAM flag, 0: do not update, 1: update */
965 kal_uint8 UpdateNvram;
966
967 /* CDMA Band Class to turn on */
968 kal_uint8 BandClass;
969
970 /* path bitmap, bit0--main, bit1--diversity, bit2--SHDR */
971 kal_uint8 PathBmp;
972
973 /* Reserved */
974 kal_uint8 Reserved;
975
976 /* Rx calibration data */
977 Cl1TstRxCalDataT RxCalData;
978
979} Cl1TstRxCalDataSetCmdT;
980
981/** define Rx calibration data setting confirm structure */
982typedef struct
983{
984 /* Request execute status */
985 Cl1TstReqStatusE Status;
986} Cl1TstRxCalDataSetRspT;
987
988/** define Rx calibration data getting command structure */
989typedef struct
990{
991 /* CDMA Band Class to turn on*/
992 kal_uint8 BandClass;
993
994 /* path bitmap, bit0--main, bit1--diversity, bit2--SHDR */
995 kal_uint8 PathBmp;
996
997 /* Reserved */
998 kal_uint16 Reserved;
999
1000} Cl1TstRxCalDataGetCmdT;
1001
1002/** define Rx calibration data getting confirm structure */
1003typedef struct
1004{
1005 /* Request execute status */
1006 Cl1TstReqStatusE Status;
1007
1008 /* Rx calibration data */
1009 Cl1TstRxCalDataT RxCalData;
1010
1011} Cl1TstRxCalDataGetRspT;
1012
1013/** define Tx calibration data structure */
1014typedef struct
1015{
1016 /* PA context */
1017 /* LID:NVRAM_EF_CL1_TX_APT_PA_CONTEXT_XX_BAND_X_LID */
1018 CL1D_RF_TX_APT_PA_CONTEXT_T TxAptPaCtx;
1019
1020 /* PA gain temperature and frequency compensation, Q5 dB */
1021 /* LID:NVRAM_EF_CL1_TX_APT_PA_GAIN_COMP_XX_BAND_X_LID */
1022 CL1D_RF_TX_APT_PA_GAIN_COMP_T TxAptPaGainComp;
1023
1024 /* Coupler loss temperature and frequency compensation, Q5 dB */
1025 /* LID:NVRAM_EF_CL1_DET_COUPLE_LOSS_COMP_XX_BAND_X_LID */
1026 CL1D_RF_DET_COUPLE_LOSS_COMP_T CplLossComp;
1027
1028 /* Coupler loss, Q5 dB */
1029 /* LID:NVRAM_EF_CL1_DET_COUPLE_LOSS_XX_BAND_X_LID */
1030 CL1D_RF_DET_COUPLE_LOSS_T CplLoss;
1031
1032 /* Reserved */
1033 kal_uint16 Reserved;
1034} Cl1TstTxCalDataT;
1035
1036/** define Tx calibration data setting command structure */
1037typedef struct
1038{
1039 /* update NVRAM flag, 0: do not update, 1: update */
1040 kal_uint8 UpdateNvram;
1041
1042 /* 0: 1xRTT, 1: EVDO */
1043 kal_uint8 RfMode;
1044
1045 /* CDMA Band Class to turn on*/
1046 kal_uint8 BandClass;
1047
1048 /* Reserved */
1049 kal_uint8 Reserved;
1050
1051 /* Tx calibration data */
1052 Cl1TstTxCalDataT TxCalData;
1053
1054} Cl1TstTxCalDataSetCmdT;
1055
1056/** define Tx calibration data setting confirm structure */
1057typedef struct
1058{
1059 /* Request execute status */
1060 Cl1TstReqStatusE Status;
1061} Cl1TstTxCalDataSetRspT;
1062
1063/** define Tx calibration data getting command structure */
1064typedef struct
1065{
1066 /* 0: 1xRTT, 1: EVDO */
1067 kal_uint8 RfMode;
1068
1069 /* CDMA Band Class to turn on*/
1070 kal_uint8 BandClass;
1071
1072 /* Reserved */
1073 kal_uint16 Reserved;
1074
1075} Cl1TstTxCalDataGetCmdT;
1076
1077/** define Tx calibration data getting confirm structure */
1078typedef struct
1079{
1080 /* Request execute status */
1081 Cl1TstReqStatusE Status;
1082
1083 /* Tx calibration data */
1084 Cl1TstTxCalDataT TxCalData;
1085
1086} Cl1TstTxCalDataGetRspT;
1087
1088#ifndef __MD93__
1089/** define Lna calibration power point getting command structure */
1090typedef struct
1091{
1092 /* Band Num to cal */
1093 kal_uint8 BandNum;
1094
1095 /* CDMA Band Class to turn on*/
1096 kal_uint8 BandClass[RF_Band_NUM_MAX];
1097
1098 /* Reserved */
1099 kal_uint16 Reserved;
1100
1101} Cl1TstLnaCalPwrPointGetCmdT;
1102
1103/** define Lna calibration power point and range confirm structure */
1104typedef struct
1105{
1106 /* Request execute status */
1107 Cl1TstReqStatusE Status;
1108
1109 /* Lna calibration power point and range */
1110 CL1D_RF_RX_LNA_CALIBRATION_POWER_AND_RANGE_T LnaCalPwrPoint[RF_Band_NUM_MAX];
1111
1112} Cl1TstLnaCalPwrPointGetRspT;
1113#endif
1114
1115#if (!defined(__MD93__)) && (!defined(__MD95__))
1116/** define Rx Agc Gain getting command structure */
1117typedef struct
1118{
1119 CL1D_RF_RAT_TYPE_E RatType;
1120 CL1D_RF_PATH_E Path;
1121}Cl1TstRxGainGetCmdT;
1122
1123/** define Rx Agc Gain getting command structure */
1124typedef struct
1125{
1126 /* Request execute status */
1127 Cl1TstReqStatusE Status;
1128
1129 CL1D_RF_AGC_ALGO_RESULT_QUERY_T RxGainPara;
1130}Cl1TstRxGainGetRspT;
1131
1132/** define Tx Agc Gain getting command structure */
1133typedef struct
1134{
1135 CL1D_RF_RAT_TYPE_E RatType;
1136}Cl1TstTxGainGetCmdT;
1137
1138/** define Tx Agc Gain getting command structure */
1139typedef struct
1140{
1141 /* Request execute status */
1142 Cl1TstReqStatusE Status;
1143
1144 CL1D_RF_TPC_ALGO_RESULT_QUERY_T TxGainPara;
1145}Cl1TstTxGainGetRspT;
1146
1147/** define SPI data setting command structure */
1148typedef struct
1149{
1150 CL1D_RF_RAT_TYPE_E RatType; // is need add Reserved?
1151 kal_uint32 BpiData;
1152} Cl1TstSetBpiDataCmdT;
1153
1154/** define SPI data setting confirm structure */
1155typedef struct
1156{
1157 /* Request execute status */
1158 Cl1TstReqStatusE Status;
1159} Cl1TstSetBpiDataRspT;
1160
1161/** define SPI data getting command structure */
1162typedef struct
1163{
1164 CL1D_RF_RAT_TYPE_E RatType;
1165} Cl1TstGetBpiDataCmdT;
1166
1167/** define SPI data getting confirm structure */
1168typedef struct
1169{
1170 /* Request execute status */
1171 Cl1TstReqStatusE Status;
1172
1173 /* SPI data */
1174 kal_uint32 BpiData;
1175} Cl1TstGetBpiDataRspT;
1176
1177/** define Rx AGC configuration command structure for RF test and traditional calibration */
1178typedef struct
1179{
1180 /* 0: 1xRTT, 1: EVDO */
1181 kal_uint8 RfMode;
1182
1183 /* Bit0: main antenna, Bit1: diversity antenna, Bit2: SHDR */
1184 kal_uint8 PathBitMap;
1185
1186 /* 0: fixed gain, 1:manual */
1187 kal_uint8 TestMode;
1188
1189 /* C2K RX AGC FSM type, 0:FAST, 1:STEADY, 2:ICS, 3:CAL, 4:FIX_GAIN*/
1190 kal_uint8 AgcFsm;
1191
1192 /* 0: high power mode, 1: low power mode */
1193 kal_uint8 PwrMode;
1194
1195 /* 0: stage 0, 1: stage 1....5: stage 5 */
1196 kal_uint8 LnaMode;
1197
1198 /** PGA index of CL1D_RF_PGA_INDEX_E */
1199 kal_uint8 PgaIndex;
1200
1201 /* indicate which parameters to be fixed, bit0: rf gain, bit1: rf DC, bit2: digital gain, bit3: digital DC */
1202 kal_uint8 AgcDcFixBmp;
1203
1204 /* digital gain in DB2 format, S5.5*/
1205 kal_uint32 DigGain;
1206} Cl1TstRxAgcFixManualConfigCmdT;
1207
1208/** define Rx AGC configuration confirm structure for RF test and traditional calibration */
1209typedef struct
1210{
1211 /* Request execute status */
1212 Cl1TstReqStatusE Status;
1213} Cl1TstRxAgcFixManualConfigRspT;
1214
1215/** define SPI data getting command structure */
1216typedef struct
1217{
1218 /* Rat,0:1x,1:DO */
1219 kal_uint32 RatType;
1220 /* PathBitMap*/
1221 kal_uint32 PathBmp;
1222 /* Dump node*/
1223 kal_uint32 DumpNode;
1224 /* IQ number*/
1225 kal_uint32 IqNum;
1226} Cl1TstRxDfeIqDumpCfgCmdT;
1227
1228/** define SPI data getting confirm structure */
1229typedef struct
1230{
1231 /* Request execute status */
1232 Cl1TstReqStatusE Status;
1233 /*Total block size */
1234 kal_uint32 BufferSize;
1235 /*bock number */
1236 kal_uint32 BlockNum;
1237} Cl1TstRxDfeIqDumpCfgRspT;
1238
1239/** define SPI data getting command structure */
1240typedef struct
1241{
1242 /* Rat,0:1x,1:DO */
1243 kal_uint32 RatType;
1244 /** [in] - BB or RF or MRX**/
1245 kal_uint32 DumpSel;
1246 /** [in] - For TXDFE_BB:0:bb input; 1:firad input; 2:src input; 3:cic1x input; 4:cic2x input; 5:nco input; 6:nco ouput
1247 For TXDFE_RF:0:gain_bb; 1:dpd comp; 2:gain bkf; 3:ga comp; 4:ad comp; 5:main phase r delay; 6:main dc; 7:main fi; 8:main fd**/
1248 kal_uint32 NodeSel;
1249 /* IQ number*/
1250 kal_uint32 IqNum;
1251} Cl1TstTxDfeIqDumpCfgCmdT;
1252
1253/** define SPI data getting confirm structure */
1254typedef struct
1255{
1256 /* Request execute status */
1257 Cl1TstReqStatusE Status;
1258 /*Total block size */
1259 kal_uint32 BufferSize;
1260 /*bock number */
1261 kal_uint32 BlockNum;
1262} Cl1TstTxDfeIqDumpCfgRspT;
1263
1264/** define SPI data getting command structure */
1265typedef struct
1266{
1267 /* Rat,0:1x,1:DO */
1268 kal_uint32 RatType;
1269 /** [in] - 0:TXK_REF; 1:TXDFE_BB; 2:TXDFE_RF; 3:TXDFE_ET; 4:TXK_DET**/
1270 kal_uint32 DumpSel;
1271 /** [in] - For TXK DET: 0:det afifo out; 1:det cic out; 2:det out;
1272 For TXK REF: 0:ref scale out; 1:ref i delay out; 2:ref f delay out; 3:ref dcm out**/
1273 kal_uint32 NodeSel;
1274 /* IQ number*/
1275 kal_uint32 IqNum;
1276} Cl1TstTxkDfeIqDumpCfgCmdT;
1277
1278/** define SPI data getting confirm structure */
1279typedef struct
1280{
1281 /* Request execute status */
1282 Cl1TstReqStatusE Status;
1283 /*Total block size */
1284 kal_uint32 BufferSize;
1285 /*bock number */
1286 kal_uint32 BlockNum;
1287} Cl1TstTxkDfeIqDumpCfgRspT;
1288
1289typedef struct
1290{
1291 kal_uint32 BlockIndex;
1292} Cl1TstRxTxDfeIqDumpQryCmdT;
1293
1294/** define SPI data getting confirm structure */
1295typedef struct
1296{
1297 /* Request execute status */
1298 Cl1TstReqStatusE Status;
1299 /* last block flag */
1300 kal_uint16 LastBlockInd;
1301 /* partial block size */
1302 kal_uint16 PtBlockSize;
1303 /* block offset */
1304 kal_uint32 BlockOffset;
1305 /* Data buffer*/
1306 kal_uint32 Data[CL1TST_RX_TX_IQ_DUMP_NUM];
1307} Cl1TstRxTxDfeIqDumpQryRspT;
1308#endif
1309
1310/** define FHC start common data structure */
1311typedef struct
1312{
1313 /* Tx RX delay for FHC, unit us (> 10us) */
1314 kal_uint16 TxRxDelay;
1315
1316 /* Tx step length, unit us (>= 1000us and <= 20000 us) */
1317 kal_uint16 TxStepLength;
1318
1319 /* Tx retune length, unit us (>= 500us) */
1320 kal_uint16 TxRetuLength;
1321
1322 /* RF mode switch length, unit us, the integer multiple of step length */
1323 kal_uint16 RfMSwhLength;
1324
1325 /* Rx step length, unit us (>= 1000us and <= 20000 us) */
1326 kal_uint16 RxStepLength;
1327
1328 /* Rx retune length, unit us (>= 500us) */
1329 kal_uint16 RxRetuLength;
1330
1331} Cl1TstFhcCommonT;
1332
1333/** define Tx calibration element structure */
1334typedef struct
1335{
1336 /* 0: 1xRTT, 1: EVDO */
1337 kal_uint8 RfMode;
1338
1339 /* Step indication, 0: next step is normal step,
1340 1: next step is retune step,
1341 2: the current step is the last step,
1342 3: next step is RF mode switch step
1343 */
1344 kal_uint8 StepInd;
1345
1346 /* CDMA band class */
1347 kal_uint8 BandClass;
1348
1349 /* Reserved */
1350 kal_uint8 Reserved;
1351
1352 /* CDMA channel */
1353 kal_uint16 ChanNum;
1354
1355 /* RF calibration power points, dBm, Q5 */
1356 kal_int16 TxPwr;
1357
1358} Cl1TstFhcTxElementT;
1359
1360/** define Rx calibration element structure */
1361typedef struct
1362{
1363 /* Step indication, 0: next step is normal step,
1364 1: next step is retune step,
1365 2: the current step is the last step
1366 */
1367 kal_uint8 StepInd;
1368
1369 /* CDMA band class */
1370 kal_uint8 BandClass;
1371
1372 /* CDMA channel */
1373 kal_uint16 ChanNum;
1374
1375 /* Bit0: main antenna, Bit1: diversity antenna, Bit2: SHDR */
1376 kal_uint8 PathBitmap;
1377
1378 /* Power mode, 0: high power mode, 1: low power mode */
1379 kal_uint8 PwrMode;
1380
1381 /* LNA mode, 0~7 */
1382 kal_uint8 LnaMode;
1383
1384 /* Reserved */
1385 kal_uint8 Reserved;
1386
1387} Cl1TstFhcRxElementT;
1388
1389/** define FHC calibration start command structure */
1390typedef struct
1391{
1392 /* FHC calibration common data */
1393 Cl1TstFhcCommonT CommonData;
1394
1395 /* Reserved */
1396 kal_uint16 Reserved1;
1397
1398 /* Tx calibration elements number (1~1000) */
1399 kal_uint16 TxElementNum;
1400
1401 /* Tx calibration elements */
1402 Cl1TstFhcTxElementT TxElement[CL1TST_FHC_TX_ELEMENT_NUM];
1403
1404 /* Reserved */
1405 kal_uint16 Reserved2;
1406
1407 /* Rx calibration elements number (1~1000) */
1408 kal_uint16 RxElementNum;
1409
1410 /* Rx calibration elements */
1411 Cl1TstFhcRxElementT RxElement[CL1TST_FHC_RX_ELEMENT_NUM];
1412
1413} Cl1TstFhcStartCmdT;
1414
1415/** define FHC report result structure */
1416typedef struct
1417{
1418 /* power detect result number */
1419 kal_uint16 PdetNum;
1420
1421 /* RSSI number */
1422 kal_uint16 RssiNum;
1423
1424 /* power detect result, unit is Q5 dBm */
1425 kal_int16 Pdet[CL1TST_FHC_TX_ELEMENT_NUM];
1426
1427 /* Main antenna RSSI, unit is Q5 dBm */
1428 kal_int16 RssiMain[CL1TST_FHC_RX_ELEMENT_NUM];
1429
1430 /* Diversity antenna RSSI, unit is Q5 dBm */
1431 kal_int16 RssiDiv[CL1TST_FHC_RX_ELEMENT_NUM];
1432} Cl1TstFhcRptDataT;
1433
1434/** define FHC calibration start confirm structure */
1435typedef struct
1436{
1437 /* Request execute status */
1438 Cl1TstReqStatusE Status;
1439
1440 /* FHC report result */
1441 Cl1TstFhcRptDataT RptData;
1442} Cl1TstFhcStartRspT;
1443
1444/** define 1xrtt NST Relation command and confirm structure */
1445
1446typedef struct
1447{
1448 /* CDMA Band Class to turn on*/
1449 kal_uint16 BandClass;
1450 /* CDMA Freq Channel to turn on*/
1451 kal_uint16 Channel;
1452 /* CDMA Walsh Code Channel*/
1453 kal_uint8 CodeChan;
1454 /* CDMA Radio configuration,1 is RC1, 2 is RC2 Etc*/
1455 kal_uint8 RadioConfig;
1456} Cl1TstNstPowerUpCmdT;
1457
1458typedef struct
1459{
1460 /* Request execute status */
1461 Cl1TstReqStatusE Status;
1462
1463 /* Nst Cmd Result status */
1464 Cl1TstNstCmdStatusE NstStatus;
1465} Cl1TstNstPowerUpRspT;
1466
1467typedef struct
1468{
1469 /* CDMA Band Class to turn on*/
1470 kal_uint16 BandClass;
1471 /* CDMA Freq Channel to turn on*/
1472 kal_uint16 Channel;
1473 /* Number of Fer cacualte Frames*/
1474 kal_uint16 NumFrames;
1475 /* Flag of Enable AFC Config*/
1476 kal_bool EnableAFC;
1477} Cl1TstNstTchFerCfgCmdT;
1478
1479typedef struct
1480{
1481 /* Request execute status */
1482 Cl1TstReqStatusE Status;
1483
1484 /* Nst Cmd Result status */
1485 Cl1TstNstCmdStatusE NstStatus;
1486 kal_uint16 BadFrames;
1487 kal_uint16 TotalFrames;
1488} Cl1TstNstTchFerCfgRspT;
1489
1490typedef struct
1491{
1492 /* CDMA Band Class to turn on*/
1493 kal_uint16 BandClass;
1494 /* CDMA Freq Channel to turn on*/
1495 kal_uint16 Channel;
1496 /* Tx Power Level ,unint is Q6*/
1497 kal_uint16 TxPwrQ6;
1498} Cl1TstNstTxPwrMeasCfgCmdT;
1499
1500typedef struct
1501{
1502 /* Request execute status */
1503 Cl1TstReqStatusE Status;
1504
1505 /* Nst Cmd Result status */
1506 Cl1TstNstCmdStatusE NstStatus;
1507} Cl1TstNstTxPwrMeasCfgRspT;
1508
1509typedef struct
1510{
1511 /* CDMA Band Class to turn on*/
1512 kal_uint16 BandClass;
1513 /* CDMA Freq Channel to turn on*/
1514 kal_uint16 Channel;
1515} Cl1TstNstRxPwrMeasCfgCmdT;
1516
1517typedef struct
1518{
1519 /* Request execute status */
1520 Cl1TstReqStatusE Status;
1521
1522 /* Nst Cmd Result status */
1523 Cl1TstNstCmdStatusE NstStatus;
1524 /* Current PN Offset */
1525 kal_uint16 PnOffset;
1526 /* Current Aset Pilot Strength */
1527 kal_int16 Strength;
1528 /* Current Main Ant Rx Power,unit is Q5 */
1529 kal_int16 MainRxPwrQ5;
1530 /* Current Div Ant Rx Power,unit is Q5 */
1531 kal_int16 DivRxPwrQ5;
1532} Cl1TstNstRxPwrMeasCfgRspT;
1533
1534typedef struct
1535{
1536 /* Total Count of NST List */
1537 kal_uint8 Count;
1538 /* Num of frame offset */
1539 kal_uint8 Offset[CL1TST_NST_MAX_LIST_NUM];
1540 /* CDMA Band Class to turn on*/
1541 kal_uint16 BandClass[CL1TST_NST_MAX_LIST_NUM];
1542 /* CDMA Freq Channel to turn on*/
1543 kal_uint16 Channel[CL1TST_NST_MAX_LIST_NUM];
1544 /* CDMA Walsh Code Channel*/
1545 kal_uint8 CodeChan[CL1TST_NST_MAX_LIST_NUM];
1546 /* CDMA Radio configuration,1 is RC1, 2 is RC2 Etc*/
1547 kal_uint8 RadioConfig[CL1TST_NST_MAX_LIST_NUM];
1548
1549 /* Number of Fer cacualte Frames*/
1550 kal_uint16 NumFrames[CL1TST_NST_MAX_LIST_NUM];
1551 /* Count of Meas Tx Pwr Level for Per Freq Chan*/
1552 kal_uint8 TxPwrCount[CL1TST_NST_MAX_LIST_NUM];
1553 /* Meas Tx Pwr Level for Per Freq Chan*/
1554 kal_uint16 TxPwrLevelQ6[CL1TST_NST_MAX_LIST_NUM][CL1TST_NST_MAX_TX_PWR_COUNT];
1555 /* Count of Meas Rx Pwr Level for Per Freq Chan*/
1556 kal_uint8 RxPwrCount[CL1TST_NST_MAX_LIST_NUM];
1557} Cl1TstNstListSetCfgCmdT;
1558
1559typedef struct
1560{
1561 /* Request execute status */
1562 Cl1TstReqStatusE Status;
1563
1564 /* Nst Cmd Result status */
1565 Cl1TstNstCmdStatusE NstStatus;
1566 /* Total Count of NST List */
1567 kal_uint8 Count;
1568 /* Index of list */
1569 kal_uint8 Index[CL1TST_NST_MAX_LIST_NUM];
1570 /* CDMA Band Class to turn on*/
1571 kal_uint16 BandClass[CL1TST_NST_MAX_LIST_NUM];
1572 /* CDMA Freq Channel to turn on*/
1573 kal_uint16 Channel[CL1TST_NST_MAX_LIST_NUM];
1574 /* Number of Bad Frames for Per Freq Chan */
1575 kal_uint8 BadFrames[CL1TST_NST_MAX_LIST_NUM];
1576 /* Number of Total Meas Frames for Per Freq Chan */
1577 kal_uint8 TotalFrames[CL1TST_NST_MAX_LIST_NUM];
1578 /* Current Main Ant Rx Power,unit is Q5 */
1579 kal_int16 MainRxPwrQ5[CL1TST_NST_MAX_LIST_NUM][CL1TST_NST_MAX_RX_PWR_COUNT];
1580 /* Current Div Ant Rx Power,unit is Q5 */
1581 kal_int16 DivRxPwrQ5[CL1TST_NST_MAX_LIST_NUM][CL1TST_NST_MAX_RX_PWR_COUNT];
1582} Cl1TstNstListSetCfgRspT;
1583
1584typedef struct
1585{
1586 kal_uint32 Reserved;
1587} Cl1TstNstEnterTestModeCmdT;
1588
1589typedef struct
1590{
1591 /* Request execute status */
1592 Cl1TstReqStatusE Status;
1593
1594 /* Nst Cmd Result status */
1595 Cl1TstNstCmdStatusE NstStatus;
1596} Cl1TstNstEnterTestModeRspT;
1597
1598typedef struct
1599{
1600 kal_uint32 Reserved;
1601} Cl1TstNstExitTestModeCmdT;
1602
1603typedef struct
1604{
1605 /* Request execute status */
1606 Cl1TstReqStatusE Status;
1607
1608 /* Nst Cmd Result status */
1609 Cl1TstNstCmdStatusE NstStatus;
1610} Cl1TstNstExitTestModeRspT;
1611
1612/** define enter factory mode request structure */
1613typedef struct
1614{
1615 kal_uint32 Reserved;
1616} Cl1TstFactoryModeReqCmdT;
1617
1618/** define enter factory mode confirm structure */
1619typedef struct
1620{
1621 /* Request execute status */
1622 Cl1TstReqStatusE Status;
1623} Cl1TstFactoryModeReqRspT;
1624
1625/** define enter normal mode request structure */
1626typedef struct
1627{
1628 kal_uint32 Reserved;
1629} Cl1TstNormalModeReqCmdT;
1630
1631/** define enter normal mode confirm structure */
1632typedef struct
1633{
1634 /* Request execute status */
1635 Cl1TstReqStatusE Status;
1636} Cl1TstNormalModeReqRspT;
1637
1638typedef struct
1639{
1640 kal_uint32 Meid_L;
1641 kal_uint32 Meid_H;
1642} Cl1TstSetMeidCmdT;
1643
1644/** define MEID setting confirm structure */
1645typedef struct
1646{
1647 /* Request execute status */
1648 Cl1TstReqStatusE Status;
1649} Cl1TstSetMeidRspT;
1650
1651/** define MEID getting command structure */
1652typedef struct
1653{
1654 kal_uint32 Reserved;
1655} Cl1TstGetMeidCmdT;
1656
1657/** define MEID getting confirm structure */
1658typedef struct
1659{
1660 /* Request execute status */
1661 Cl1TstReqStatusE Status;
1662
1663 /* MEID data */
1664 kal_uint32 Meid_L;
1665 kal_uint32 Meid_H;
1666
1667 /* ESN data */
1668 kal_uint32 Esn;
1669} Cl1TstGetMeidRspT;
1670
1671/** define UBIN init request structure */
1672typedef struct
1673{
1674 kal_uint32 Reserved;
1675} Cl1TstUbinInitCmdT;
1676
1677/** define UBIN init confirm structure */
1678typedef struct
1679{
1680 /* Request execute status */
1681 Cl1TstReqStatusE Status;
1682} Cl1TstUbinInitRspT;
1683
1684/** define UBIN De init request structure */
1685typedef struct
1686{
1687 kal_uint32 Reserved;
1688} Cl1TstUbinDeInitCmdT;
1689
1690/** define UBIN Deinit confirm structure */
1691typedef struct
1692{
1693 /* Request execute status */
1694 Cl1TstReqStatusE Status;
1695} Cl1TstUbinDeInitRspT;
1696
1697
1698
1699typedef struct
1700{
1701 /* Ant Test Mode Set:0 means disable test Mode,1 means Main Rx Only,and
1702 * 2 means Div Rx Only Mode,3 means Dual Mode(Main+Div).*/
1703 kal_uint32 AntTestMode;
1704} Cl1TstRxAntTestModeSetCmdT;
1705
1706typedef struct
1707{
1708 /* Request execute status */
1709 Cl1TstReqStatusE Status;
1710} Cl1TstRxAntTestModeSetRspT;
1711
1712
1713#if 0
1714#ifdef MTK_PLT_ON_PC_IT
1715/* under construction !*/
1716/* under construction !*/
1717#endif
1718#endif
1719
1720/* C2K meta interface command union */
1721typedef union
1722{
1723 Cl1TstGetRfPlatInfoCmdT GetRfPlatInfoCmd; // for CL1TST_CMD_GET_RF_PLATFORM_INFO
1724 Cl1TstRfdTestModeReqCmdT RfdTestModeReqCmd; // for CL1TST_CMD_RFD_ENTER_TEST_MODE
1725 Cl1TstRfdInitReqCmdT RfdInitReqCmd; // for CL1TST_CMD_RFD_INIT_REQ
1726 Cl1TstSetMipiCodeWordCmdT SetMipiCodeWordCmd; // for CL1TST_CMD_SET_MIPI_CW
1727 Cl1TstGetMipiCodeWordCmdT GetMipiCodeWordCmd; // for CL1TST_CMD_GET_MIPI_CW
1728 Cl1TstSetSpiDataCmdT SetSpiDataCmd; // for CL1TST_CMD_SET_SPI_DATA
1729 Cl1TstGetSpiDataCmdT GetSpiDataCmd; // for CL1TST_CMD_GET_SPI_DATA
1730 Cl1TstTransmitCtrlCmdT TransmitCtrlCmd; // for CL1TST_CMD_TRANSMIT_CTRL
1731 Cl1TstReceiveCtrlCmdT ReceiveCtrlCmd; // for CL1TST_CMD_RECEIVE_CTRL
1732 Cl1TstAfcConfigCmdT AfcConfigCmd; // for CL1TST_CMD_AFC_CONFIG
1733 Cl1TstTxAgcConfigCmdT TxAgcConfigCmd; // for CL1TST_CMD_TX_AGC_CONFIG
1734 Cl1TstTxPowerQueryCmdT TxPowerQueryCmd; // for CL1TST_CMD_TX_POWER_QUERY
1735 Cl1TstRxAgcConfigCmdT RxAgcConfigCmd; // for CL1TST_CMD_RX_AGC_CONFIG
1736 Cl1TstRxRssiQueryCmdT RxRssiQueryCmd; // for CL1TST_CMD_RX_RSSI_QUERY
1737 Cl1TstAfcCalDataSetCmdT AfcCalDataSetCmd; // for CL1TST_CMD_AFC_CAL_DATA_SET
1738 Cl1TstAfcCalDataGetCmdT AfcCalDataGetCmd; // for CL1TST_CMD_AFC_CAL_DATA_GET
1739 Cl1TstRxCalDataSetCmdT RxCalDataSetCmd; // for CL1TST_CMD_RX_CAL_DATA_SET
1740 Cl1TstRxCalDataGetCmdT RxCalDataGetCmd; // for CL1TST_CMD_RX_CAL_DATA_GET
1741 Cl1TstTxCalDataSetCmdT TxCalDataSetCmd; // for CL1TST_CMD_TX_CAL_DATA_SET
1742 Cl1TstTxCalDataGetCmdT TxCalDataGetCmd; // for CL1TST_CMD_TX_CAL_DATA_GET
1743#ifndef __MD93__
1744 Cl1TstLnaCalPwrPointGetCmdT LnaCalPwrPointGetCmd; // for CL1TST_CMD_RX_LNA_PWR_RANGE_GET
1745#endif
1746#if (!defined(__MD93__)) && (!defined(__MD95__))
1747 Cl1TstRxGainGetCmdT RxGainGetCmd; // for CL1TST_CMD_RX_GAIN_GET
1748 Cl1TstTxGainGetCmdT TxGainGetCmd; // for CL1TST_CMD_TX_GAIN_GET
1749 Cl1TstSetBpiDataCmdT SetBpiDataCmd; // for CL1TST_CMD_SET_BPI_DATA
1750 Cl1TstGetBpiDataCmdT GetBpiDataCmd; // for CL1TST_CMD_GET_BPI_DATA
1751 Cl1TstRxAgcFixManualConfigCmdT RxAgcFixManualConfigCmd; // for CL1TST_CMD_RX_AGC_FIX_MANUAL_CONFIG
1752 Cl1TstRxDfeIqDumpCfgCmdT RxDfeIqDumpCfgCmd; // for CL1TST_CMD_RXDFE_IQ_DUMP_CFG
1753 Cl1TstTxDfeIqDumpCfgCmdT TxDfeIqDumpCfgCmd; // for CL1TST_CMD_TXDFE_IQ_DUMP_CFG
1754 Cl1TstTxkDfeIqDumpCfgCmdT TxkDfeIqDumpCfgCmd; // for CL1TST_CMD_TXDFE_IQ_DUMP_CFG
1755 Cl1TstRxTxDfeIqDumpQryCmdT RxTxDfeIqDumpQryCmd; // for CL1TST_CMD_RXDFE_IQ_DUMP_QUERY / CL1TST_CMD_TXDFE_IQ_DUMP_QUERY / CL1TST_CMD_TXDFE_IQ_DUMP_QUERY
1756#endif
1757
1758 Cl1TstFhcStartCmdT FhcStartCmd; // for CL1TST_CMD_FHC_START
1759 Cl1TstFactoryModeReqCmdT FactoryModeReqCmd; // for CL1TST_CMD_FACTORY_MODE_REQ
1760 Cl1TstNormalModeReqCmdT NormalModeReqCmd; // for CL1TST_CMD_NORMAL_MODE_REQ
1761 Cl1TstSetMeidCmdT SetMeidCmd; // for CL1TST_CMD_SET_MEID
1762 Cl1TstGetMeidCmdT GetMeidCmd; // for CL1TST_CMD_GET_MEID
1763 Cl1TstUbinInitCmdT UbinInitCmd; // for CL1TST_CMD_UBIN_INIT
1764 Cl1TstUbinDeInitCmdT UbinDeInitCmd; // for CL1TST_CMD_UBIN_DEINIT
1765
1766 Cl1TstNstPowerUpCmdT NstPowerUpCmd;
1767 Cl1TstNstTchFerCfgCmdT NstTchFerCfgCmd;
1768 Cl1TstNstTxPwrMeasCfgCmdT NstTxPwrMeasCfgCmd;
1769
1770 Cl1TstNstRxPwrMeasCfgCmdT NstRxPwrMeasCfgCmd;
1771 Cl1TstNstListSetCfgCmdT NstListSetCfgCmd;
1772 Cl1TstNstEnterTestModeCmdT NstEnterTestModeCmd;
1773 Cl1TstNstExitTestModeCmdT NstExitTestModeCmd;
1774
1775 Cl1TstRxAntTestModeSetCmdT RxAntTestModeSetCmd;
1776}Cl1TstCmdParam;
1777
1778/* C2K meta interface confirm union */
1779typedef union
1780{
1781 Cl1TstGetRfPlatInfoRspT GetRfPlatInfoRsp; // for CL1TST_CMD_GET_RF_PLATFORM_INFO
1782 Cl1TstRfdTestModeReqRspT RfdTestModeReqRsp; // for CL1TST_CMD_RFD_EXIT_TEST_MODE
1783 Cl1TstRfdInitReqRspT RfdInitReqRsp; // for CL1TST_CMD_RFD_INIT_REQ
1784 Cl1TstSetMipiCodeWordRspT SetMipiCodeWordRsp; // for CL1TST_CMD_SET_MIPI_CW
1785 Cl1TstGetMipiCodeWordRspT GetMipiCodeWordRsp; // for CL1TST_CMD_GET_MIPI_CW
1786 Cl1TstSetSpiDataRspT SetSpiDataRsp; // for CL1TST_CMD_SET_SPI_DATA
1787 Cl1TstGetSpiDataRspT GetSpiDataRsp; // for CL1TST_CMD_GET_SPI_DATA
1788 Cl1TstTransmitCtrlRspT TransmitCtrlRsp; // for CL1TST_CMD_TRANSMIT_CTRL
1789 Cl1TstReceiveCtrlRspT ReceiveCtrlRsp; // for CL1TST_CMD_RECEIVE_CTRL
1790 Cl1TstAfcConfigRspT AfcConfigRsp; // for CL1TST_CMD_AFC_CONFIG
1791 Cl1TstTxAgcConfigRspT TxAgcConfigRsp; // for CL1TST_CMD_TX_AGC_CONFIG
1792 Cl1TstTxPowerQueryRspT TxPowerQueryRsp; // for CL1TST_CMD_TX_POWER_QUERY
1793 Cl1TstRxAgcConfigRspT RxAgcConfigRsp; // for CL1TST_CMD_RX_AGC_CONFIG
1794 Cl1TstRxRssiQueryRspT RxRssiQueryRsp; // for CL1TST_CMD_RX_RSSI_QUERY
1795 Cl1TstAfcCalDataSetRspT AfcCalDataSetRsp; // for CL1TST_CMD_AFC_CAL_DATA_SET
1796 Cl1TstAfcCalDataGetRspT AfcCalDataGetRsp; // for CL1TST_CMD_AFC_CAL_DATA_GET
1797 Cl1TstRxCalDataSetRspT RxCalDataSetRsp; // for CL1TST_CMD_RX_CAL_DATA_SET
1798 Cl1TstRxCalDataGetRspT RxCalDataGetRsp; // for CL1TST_CMD_RX_CAL_DATA_GET
1799 Cl1TstTxCalDataSetRspT TxCalDataSetRsp; // for CL1TST_CMD_TX_CAL_DATA_SET
1800 Cl1TstTxCalDataGetRspT TxCalDataGetRsp; // for CL1TST_CMD_TX_CAL_DATA_GET
1801#ifndef __MD93__
1802 Cl1TstLnaCalPwrPointGetRspT LnaCalPwrPointGetRsp; // for CL1TST_CMD_RX_LNA_PWR_RANGE_GET
1803#endif
1804#if (!defined(__MD93__)) && (!defined(__MD95__))
1805 Cl1TstRxGainGetRspT RxGainGetRsp; // for CL1TST_CMD_RX_GAIN_GET
1806 Cl1TstTxGainGetRspT TxGainGetRsp; // for CL1TST_CMD_TX_GAIN_GET
1807 Cl1TstSetBpiDataRspT SetBpiDataRsp; // for CL1TST_CMD_SET_BPI_DATA
1808 Cl1TstGetBpiDataRspT GetBpiDataRsp; // for CL1TST_CMD_GET_BPI_DATA
1809 Cl1TstRxAgcFixManualConfigRspT RxAgcFixManualConfigRsp; // for CL1TST_CMD_RX_AGC_FIX_MANUAL_CONFIG
1810 Cl1TstRxDfeIqDumpCfgRspT RxDfeIqDumpCfgRsp; // for CL1TST_CMD_RXDFE_IQ_DUMP_CFG
1811 Cl1TstTxDfeIqDumpCfgRspT TxDfeIqDumpCfgRsp; // for CL1TST_CMD_TXDFE_IQ_DUMP_CFG
1812 Cl1TstTxkDfeIqDumpCfgRspT TxkDfeIqDumpCfgRsp; // for CL1TST_CMD_TXkDFE_IQ_DUMP_CFG
1813 Cl1TstRxTxDfeIqDumpQryRspT RxTxDfeIqDumpQryRsp; // for CL1TST_CMD_RXDFE_IQ_DUMP_QUERY / CL1TST_CMD_TXDFE_IQ_DUMP_QUERY / CL1TST_CMD_TXkDFE_IQ_DUMP_QUERY
1814#endif
1815
1816 Cl1TstFhcStartRspT FhcStartRsp; // for CL1TST_CMD_FHC_START
1817 Cl1TstFactoryModeReqRspT FactoryModeReqRsp; // for CL1TST_CMD_FACTORY_MODE_REQ
1818 Cl1TstNormalModeReqRspT NormalModeReqRsp; // for CL1TST_CMD_NORMAL_MODE_REQ
1819 Cl1TstSetMeidRspT SetMeidRsp; // for CL1TST_CMD_SET_MEID
1820 Cl1TstGetMeidRspT GetMeidRsp; // for CL1TST_CMD_GET_MEID
1821 Cl1TstUbinInitRspT UbinInitRsp; // for CL1TST_CMD_UBIN_INIT
1822 Cl1TstUbinDeInitRspT UbinDeInitRsp; // for CL1TST_CMD_UBIN_DEINIT
1823
1824 Cl1TstNstPowerUpRspT NstPowerUpRsp;
1825 Cl1TstNstTchFerCfgRspT NstTchFerCfgRsp;
1826 Cl1TstNstTxPwrMeasCfgRspT NstTxPwrMeasCfgRsp;
1827
1828 Cl1TstNstRxPwrMeasCfgRspT NstRxPwrMeasCfgRsp;
1829 Cl1TstNstListSetCfgRspT NstListSetCfgRsp;
1830 Cl1TstNstEnterTestModeRspT NstEnterTestModeRsp;
1831 Cl1TstNstExitTestModeRspT NstExitTestModeRsp;
1832
1833 Cl1TstRxAntTestModeSetRspT RxAntTestModeSetRsp;
1834}Cl1TstRspParam;
1835
1836/* FT peer buffer request structure */
1837typedef struct
1838{
1839 Cl1TstCmdTypeE Type;
1840 Cl1TstCmdParam Para;
1841}FT_CRF_PEER_CMD;
1842
1843/* FT peer buffer confirm structure */
1844typedef struct
1845{
1846 Cl1TstCmdTypeE Type;
1847 Cl1TstRspParam Para;
1848}FT_CRF_PEER_RSP;
1849
1850/* struct definition for FT request & confirm */
1851typedef FT_H FT_CRF_LOCAL_PARA;
1852
1853/*----------------------------------------------------------------------------
1854 Global Typedefs
1855----------------------------------------------------------------------------*/
1856extern void CL1TST_ALLOC_MSG_CC(ilm_struct* ilm_ptr, kal_uint32 local_param_size, kal_uint32 peer_pdu_size);
1857extern void CL1TST_SEND_MSG_TO_FT(ilm_struct *ilm_ptr);
1858extern void CL1TST_BackupFtHeader(kal_uint16 taken);
1859extern void CL1TST_SetFtHeader(FT_CRF_LOCAL_PARA *rsp_loc);
1860
1861extern void Cl1TstRfdTestModeReqPro(Cl1TstRfdTestModeReqCmdT *Ptr);
1862
1863extern void Cl1TstTxPathOnTimingCalc(kal_uint8 RfMode,
1864 kal_uint16 RaDly,
1865 kal_uint32 *TxStartOfst,
1866 kal_uint32 *RxStartOfst);
1867
1868extern void Cl1TstTxPathOffTimingCalc(kal_uint8 RfMode,
1869 kal_uint32 *TxStartOfst,
1870 kal_uint32 *RxStartOfst);
1871
1872extern void Cl1TstTxPathOn1xSigPro(kal_uint8 Action, Cl1Tst1xSigParaT *Ptr, kal_bool FlagL1d);
1873
1874extern kal_uint8 Cl1TstDoActionQuery(kal_uint8 Action);
1875
1876extern void Cl1TstTransmitCtrlPathPro(Cl1TstTransmitCtrlCmdT *Ptr);
1877extern void Cl1TstTransmitCtrlSigPro(Cl1TstTransmitCtrlCmdT *Ptr, kal_bool L1dFlag);
1878extern void Cl1TstReceiveCtrlPathPro(Cl1TstReceiveCtrlCmdT *Ptr);
1879extern void Cl1TstAfcConfigPro(Cl1TstAfcConfigCmdT *Ptr);
1880extern void Cl1TstAfcConfigPro(Cl1TstAfcConfigCmdT *Ptr);
1881extern void Cl1TstTxAgcConfigPro(Cl1TstTxAgcConfigCmdT *Ptr);
1882extern void Cl1TstRxAgcConfigPro(Cl1TstRxAgcConfigCmdT *Ptr);
1883extern void CltstAfcCalDataSet(Cl1TstAfcCalDataSetCmdT *Ptr);
1884extern void CltstAfcCalDataGet(CL1D_RF_AFC_DATA_T *Ptr);
1885extern void CltstRxCalDataSet(Cl1TstRxCalDataSetCmdT *Ptr);
1886extern void CltstRxCalDataGet(Cl1TstRxCalDataGetCmdT *GetPtr, Cl1TstRxCalDataT *DatPtr);
1887extern void CltstTxCalDataSet(Cl1TstTxCalDataSetCmdT *Ptr);
1888extern void CltstTxCalDataGet(Cl1TstTxCalDataGetCmdT *GetPtr, Cl1TstTxCalDataT *DatPtr);
1889extern void Cl1tstTxDfeBbToneCfg(kal_uint32 CfgData);
1890extern void Cl1TstRxRssiQuery(Cl1TstRxRssiQueryCmdT *Ptr,
1891 CL1D_RF_AGC_RSSI_QUERY_T *AdsPtr);
1892extern void Cl1TstRxRssiQueryPduFill(Cl1TstRxRssiQueryCmdT *Ptr,
1893 CL1D_RF_AGC_RSSI_QUERY_T *AdsPtr,
1894 Cl1TstRxRssiQueryRspT *RspPdu);
1895extern void Cl1TstMetaIfGetRfPlatInfo(Cl1TstGetRfPlatInfoCmdT *Ptr);
1896extern void Cl1TstMetaIfRfdTestModeReq(Cl1TstRfdTestModeReqCmdT *Ptr);
1897extern void Cl1TstMetaIfRfdInitReq(Cl1TstRfdInitReqCmdT *Ptr);
1898extern void Cl1TstMetaIfSetMipiCodeWord(Cl1TstSetMipiCodeWordCmdT *Ptr);
1899extern void Cl1TstMetaIfGetMipiCodeWord(Cl1TstGetMipiCodeWordCmdT *Ptr);
1900extern void Cl1TstMetaIfSetSpiData(Cl1TstSetSpiDataCmdT *Ptr);
1901extern void Cl1TstMetaIfGetSpiData(Cl1TstGetSpiDataCmdT *Ptr);
1902extern void Cl1TstMetaIfTransmitCtrl(Cl1TstTransmitCtrlCmdT *Ptr);
1903extern void Cl1TstMetaIfReceiveCtrl(Cl1TstReceiveCtrlCmdT *Ptr);
1904extern void Cl1TstMetaIfAfcConfig(Cl1TstAfcConfigCmdT *Ptr);
1905extern void Cl1TstMetaIfTxAgcConfig(Cl1TstTxAgcConfigCmdT *Ptr);
1906extern void Cl1TstMetaIfTxPowerQuery(Cl1TstTxPowerQueryCmdT *Ptr);
1907extern void Cl1TstMetaIfRxAgcConfig(Cl1TstRxAgcConfigCmdT *Ptr);
1908extern void Cl1TstMetaIfRxRssiQuery(Cl1TstRxRssiQueryCmdT *Ptr);
1909extern void Cl1TstMetaIfAfcCalDataSet(Cl1TstAfcCalDataSetCmdT *Ptr);
1910extern void Cl1TstMetaIfAfcCalDataGet(Cl1TstAfcCalDataGetCmdT *Ptr);
1911extern void Cl1TstMetaIfRxCalDataSet(Cl1TstRxCalDataSetCmdT *Ptr);
1912extern void Cl1TstMetaIfRxCalDataGet(Cl1TstRxCalDataGetCmdT *Ptr);
1913extern void Cl1TstMetaIfTxCalDataSet(Cl1TstTxCalDataSetCmdT *Ptr);
1914extern void Cl1TstMetaIfTxCalDataGet(Cl1TstTxCalDataGetCmdT *Ptr);
1915#ifndef __MD93__
1916extern void Cl1TstMetaIfLnaCalPwrPointGet(Cl1TstLnaCalPwrPointGetCmdT *Ptr);
1917#endif
1918#if (!defined(__MD93__)) && (!defined(__MD95__))
1919extern void Cl1TstMetaIfRxGainGet(Cl1TstRxGainGetCmdT *Ptr);
1920extern void Cl1TstMetaIfTxGainGet(Cl1TstTxGainGetCmdT *Ptr);
1921extern void Cl1TstMetaIfSetBpiData(Cl1TstSetBpiDataCmdT *Ptr);
1922extern void Cl1TstMetaIfGetBpiData(Cl1TstGetBpiDataCmdT *Ptr);
1923extern void Cl1TstRxAgcFixManualConfigPro(Cl1TstRxAgcFixManualConfigCmdT *Ptr);
1924extern void Cl1TstMetaIfRxAgcFixManualConfig(Cl1TstRxAgcFixManualConfigCmdT *Ptr);
1925extern void Cl1TstMetaIfRxDfeIqDumpCfg(Cl1TstRxDfeIqDumpCfgCmdT *Ptr);
1926extern void Cl1TstMetaIfTxDfeIqDumpCfg(Cl1TstTxDfeIqDumpCfgCmdT *Ptr);
1927extern void Cl1TstMetaIfTxkDfeIqDumpCfg(Cl1TstTxkDfeIqDumpCfgCmdT *Ptr);
1928extern void Cl1TstMetaIfRxTxDfeIqDumpQry(Cl1TstRxTxDfeIqDumpQryCmdT *Ptr);
1929#endif
1930extern void Cl1TstMetaIfFhcStart(Cl1TstFhcStartCmdT *Ptr);
1931extern void Cl1tstMetaIfFactoryModeReq(Cl1TstFactoryModeReqCmdT * Ptr);
1932extern void Cl1tstMetaIfNormalModeReq(Cl1TstNormalModeReqCmdT * Ptr);
1933extern void Cl1TstMetaIfSetMeid(Cl1TstSetMeidCmdT *Ptr);
1934extern void Cl1TstMetaIfGetMeid(Cl1TstGetMeidCmdT *Ptr);
1935extern void Cl1TstMetaIfUbinInit(Cl1TstUbinInitCmdT *Ptr);
1936extern void Cl1TstMetaIfUbinDeInit(Cl1TstUbinDeInitCmdT *Ptr);
1937extern void Cl1TstMetaIfTargetAssert();
1938extern kal_uint32 CltstNvOperBmpGet(kal_uint8 UpdateNvram);
1939extern kal_bool Cl1tstDoTrigTxSlpRsmDlyQuery();
1940extern void Cl1tstDoTrigTxSlpRsmDlyClear();
1941
1942#endif /* _CL1TST_META_IF_H_ */
1943