mcu/interface/l1/cl1/common/cphevdoflsrp.h

/*****************************************************************************
*  Copyright Statement:
*  --------------------
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*  herein is confidential. The software may not be copied and the information
*  contained herein may not be used or disclosed except with the written
*  permission of MediaTek Inc. (C) 2016
*
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*****************************************************************************/
#ifndef _CPHEVDOFLSRP_H_
#define _CPHEVDOFLSRP_H_

#include "cl1common.h"
#include "kal_general_types.h"
#define EVDO_MAX_NUM_PILOTS               (6)
#define EVDO_MAX_NUM_DATA_FINGERS         (3)
#define EVDO_MAX_NUM_MAC_FINGERS          (12)
#define EVDO_MAX_TOTAL_FINGERS            (EVDO_MAX_NUM_DATA_FINGERS + EVDO_MAX_NUM_MAC_FINGERS)
#define EVDO_MAX_NUM_PCG                  (6)
#define EVDO_INVALID_SECTORID             (0xFF)
#define EVDO_INVALID_PCGID                (0xFF)
#define EVDO_INVALID_PNOFFSET             (0xFFFF)
#define EVDO_MAX_MACINDEX                 (127)
#define EVDO_MAX_SPEED                    (200)
#define T3_INIT_ADDR                      (0)
#define DRC_REG_SIZE_M                    15  /* DRC Offset is from 0 -14 */ 
#define RXC_INTERLACE_LENGTH              (4) 
#define EVDO_REV_A                        (0x02) 


#define BR_DMA_BASIC_ADDRESS        (0xAB860000)
#define BIGRAM_BASE_ADDRESS         (0xA9000000)
#define EVDO_INIT_SPEED              (160)

//#define C2K_RAKE_CMIF_REG_BASE 1

/*Rake Generate*/
typedef enum
{
    TRAFFIC_MODE_WCDMA,
    TRAFFIC_MODE_1XRTT,
    TRAFFIC_MODE_EVDO,
    TRAFFIC_MODE_1XRTT_QLIC
} CphEvl1TrafficMode;


/*Rake Bootup*/
typedef enum
{
    BOOT_UP_MODE_WCDMA = 0,
    BOOT_UP_MODE_C2K
} CphRakeBootUpMode;

/*Rake State*/
typedef enum
{
    EVL1_SYNC = 1,
    EVL1_IDLE = 2, 
    EVL1_CONNECTED = 4
} CphEvl1StateT;

/*Rake Mode*/
typedef enum
{
    RAKE_MODE_DISABLE = 0,
    RAKE_MODE_1X,
    RAKE_MODE_DO, 
    RAKE_MODE_SHDR
} CphRakeMode;

/*PMB CH type*/
typedef enum
{
    PILOT_TRAFFIC_CH = 0,
    PILOT_MAC_CH = PILOT_TRAFFIC_CH,
    MAC_CH = 1,
    RA_CH = MAC_CH,
    PMB0_CH = 7,
    PMB1_CH = PMB0_CH,
    PMB2_CH  = PMB0_CH,
    PMB_FTC_CH = PMB0_CH,
} CphEvl1ChType;


/*Spreading factor*/
typedef enum
{
    EVL1_SF4 = 0,
    EVL1_SF8,
    EVL1_SF16,
    EVL1_SF32,
    EVL1_SF64,
    EVL1_SF128,
    EVL1_SF256
} CphEvl1SFType;

/*Spreading factor*/
typedef enum
{
    FINGER_NO_CHANGE = 0,
    FINGER_ASSIGN,
    FINGER_RELEASE
} CphEvl1FngAllocAction;

/*Spreading factor*/
typedef enum
{
    FINGER_RELEASED = 0,
    FINGER_ACTIVATED = 1,
    FINGER_OBSERVED = 2,
}Evl1FngStatusT;


/* AFC_Mode */
typedef enum
{
   AFC_FAST,
   AFC_NORMAL   
} CphAfcModeT;


typedef enum
{
    CONFIG_MU = 0x01,
    CONFIG_DOF = 0x02,
    CONFIG_PMB_MODE = 0x04,
    CONFIG_MACINDEX = 0x08,
    CONFIG_PD_RESET = 0x10,
    CONFIG_PD_ENABLE = 0x20
} CphEvl1FlSrpPdCfgType;

typedef enum
{
    PD_MODE_INIT_ACQ,
    PD_MODE_TRAFFIC,
    PD_MODE_IDLE    
} CphEvl1FlSrpPdMode;


typedef enum
{
    DRC_TABLE_INIT = 0x01,
    DRC_SLMS_INIT = 0x02,
    DRC_SW_PARA_INIT = 0x04,
    DRC_REINIT = 0x08
} CphEvl1FlSrpDrcInitType;


typedef enum
{
    EVENT_DRC_INIT = 0x01,
    EVENT_DRC_CFG = 0x02,
    EVENT_DRC_TABLE_UPDATE =0x04
} CphEvl1FlSrpDrcEventType;


typedef enum
{
    CFG_DRC_LEN = 0x01,
    CFG_DRC_GATING = 0x02,
    CFG_FIX_TX_RATE = 0x04,
    CFG_FIX_TX_RATE_DISABLE =0x08,
    CFG_GLOBAL_BYPASS = 0x10,
    CFG_ADJ_C2I_LEVEL_LENGTH = 0x20,
    CFG_GlOBAL_ADJ = 0x40,
    CFG_PREDICTION = 0x80,
    CFG_DRC_RANGE = 0x100
} CphEvl1FlSrpDrcCfgType;


typedef struct  
{
    /** [In]*/
    CphEvl1StateT Evl1State;
    /** [In]*/    
    kal_uint32 RxPath;
    /** [In]*/    
    kal_uint32 Evl1Subtype;
    /** [In]*/    
    kal_uint32 T3Dist;
    /** [In]*/    
    kal_uint32 DLCarrierFreq;
    /** [In]*/    
    kal_uint32 T3Time;  
    /** [In]*/    
    kal_uint32 T2Time;
    /** [In]*/    
    kal_uint32 CpichOnTime;  
    /** [In] */
    kal_bool   Evl1Enabled;
}CphEvl1RakeStartT;


typedef struct
{
    kal_uint16  PilotPN;
    kal_uint16  PwrEst;    
    kal_uint8   PcgId;
    kal_uint8   ServCell;
    kal_uint8   MacId;
    kal_uint8   MacWalshId;
    kal_uint8   RABLength;
    kal_uint8   RABOffset;
    kal_uint8   RAChannelGain;
    kal_uint8   Res;
}RakeSectorInfoT;

typedef struct
{
    /** [In]*/
    kal_bool PmbFtcCfgChange;
    /** [In]*/    
    kal_uint8   MacCfgChange;
    /** [In]*/    
    kal_uint8   ServingSecId; 
    /** [In]*/    
    kal_uint16  ServingPN;
    /** [In]*/
    kal_uint16  UserMacIdx;
    /** [In]*/
    kal_uint16  CcShortPktIdx;    
    /** [In]*/    
    kal_uint8   NumSec;
    /** [In]*/   
    kal_uint8   SecRenumId[EVDO_MAX_NUM_PILOTS];
    /** [In]*/    
    RakeSectorInfoT SectorInfo[EVDO_MAX_NUM_PILOTS]; 
}CphEvl1RakeChT;

typedef struct 
{
    /** [In]*/
    kal_uint8 FngIdx;
    /** [In]*/    
    kal_uint8 SecId;
    /** [In]*/    
    CphEvl1FngAllocAction Action;
    /** [In]*/    
    Evl1FngStatusT FngStatus;
    /** [In]*/    
    kal_uint16 FngAddr;
    /** [In]*/    
    kal_uint16 FngSymIdx;
    /** [In]*/    
    kal_uint32 FngInitPower;
 } CphEvl1RakeFngCfgT;

typedef struct
{
    /** [Out]*/
    kal_uint32    RefTimeEchip;
    /** [Out]*/    
    kal_uint32     RefGsrAddr;
}CphEvl1FlSrpGsrT;

typedef struct
{    
    kal_uint8   FngIdx;
    kal_uint16   FngSnr; 
} CphEvl1RakeFngSNRResultT; 

typedef struct
{
    /** [In]*/
    kal_bool RssiStableFlag;
    /** [In]*/
    kal_uint8 PrevSpeedResult;
    /** [Out]*/
    kal_uint8  FinalSpeed;
} CphEvl1SpestCfgT; 

typedef struct
{
    kal_uint8   FngIdx;
    kal_int8    FngAccDriftValue;
}AccDriftT;

typedef struct
{
    /** [In]*/
    kal_int16  A2OPilot;
    /** [In]*/    
    kal_int16  O2APilot;
    /** [In]*/
    kal_int16   A2OMac;
    /** [In]*/
    kal_int16   O2AMac;
    /** [In]*/
    kal_uint8   NumFngUpd;
    /** [In]*/
    AccDriftT    AccDrift[EVDO_MAX_TOTAL_FINGERS];
}CphEvl1TrackerCfgT;


typedef struct
{
    /** [In]*/
    kal_uint8  FngIdx;
    /** [Out]*/
    kal_uint8  FngStatus; 
    /** [Out]*/
    kal_int8  FngAccuDrift;
    /** [Out]*/
    kal_uint32 FngMicPower;
} CphEvl1TrackerResultT;


typedef struct
{
    kal_bool RcpDbgEn;  /* 1->RCP subchannel in Debug mode, 0->normal mode */
    kal_bool RcpDbgVal;
    kal_bool ArqDbgEn;  /* 1->H/LARQ subchannel in Debug mode, 0->normal mode */
    kal_bool ArqDbgVal;
}Evl1McdDebugParamT;


typedef struct
{
    /** [In]*/
    kal_uint8  DrcLockPeriod;
    /** [In]*/    
    kal_uint8  DrcLockLen;
    /** [In]*/
    kal_uint8  ArqMode;
    /** [In]*/
    kal_uint8  ArqType;
    /** [In]*/
    kal_uint8  FrabTc;
    /** [In]*/
    kal_uint8  QrabTc;
    /** [In]*/
    Evl1McdDebugParamT  McdDbgData; /* 1->RCP subchannel in Debug mode, 0->normal mode */   
}CphEvl1BsrpMcdInfoT;

typedef struct
{
    /** [In]*/
    kal_uint8 NextArqtype;   
} CphEvl1McdArqTypeCfgT;


typedef struct
{
    /** [In]*/
    kal_bool ParqValid;
    /** [In]*/
    kal_uint8 RtcMacSubType;
    /** [In]*/
    kal_uint8 NumSec;
    /** [In]*/
    kal_uint8 NumPcg;
    /** [In]*/
    kal_uint8 SecRenumId[EVDO_MAX_NUM_PILOTS];
    /** [In]*/
    kal_uint8 PcgRenumId[EVDO_MAX_NUM_PCG];
} CphEvl1McdGetMacBitsInputT;

typedef struct
{
  /** [Out]*/
  kal_int16  RAB;               /* <13,1,t> for SoftRAB(MAC subtype 0/1), <16,15,t> for RAB(MAC subtype 2/3) */
  /** [Out]*/
  kal_uint8  SlotRAB;           /* [0], hard limited RAB */
  /** [Out]*/
  kal_uint8  SlotQRAB;          /* [0], subframe rate sampling */
  /** [Out]*/
  kal_int32  SlotFRAB;          /* <13,1,t>, subframe rate sampling */
} CphMacBitsSectorT;

typedef struct
{
  /** [Out]*/
  kal_uint8 DRCLockPcg;         /* 0->UnLock, 1->Lock */
  /** [Out]*/
  kal_uint8 DRCLockPcgFinal;    /* Final value after persistence test, 0->UnLock, 1->Lock */
  /** [Out]*/
  kal_uint8 DRCLockCounter;       /* for persistence test */
  /** [Out]*/
  kal_uint8 HLARQBitPcg;        /* 1->ACK, 0->NAK */
  /** [Out]*/
  kal_int32 DRCLockMetric;      /* DRCLock metric, check sign for decision */
  /** [Out]*/  
  kal_int32  HLARQMetric;       /* [20:0], at subframe rate */
  /** [Out]*/  
  kal_int32  PARQMetric;        /* [20:0], at subframe rate */
  /** [Out]*/
  kal_uint32 CIMetric;          /* [21:0], C/I metric at subframe rate */
} CphMacBitsPCGT;

typedef struct
{
    /** [Out]*/
    kal_uint8  RABValid;           /* 0/1->NotValid/Valid, Valid occurs every slot T mod RABLengthn = RABOffsetn-1 */
    /** [Out]*/
    kal_uint8  DRCLockValid;       /* 0->NotVal, 1->Valid, Valid occurs every */
                               /* slot (T-FrameOffset) mod DRCLockPeriod x DRCLockLength */
                               /* = (DRCLockPeriod -1) x DRCLockLength */
                               /* For Rev A. DRCLockPeriod = 4 */
    /** [Out]*/                           
    kal_uint8  HLARQBit;           /* H/LARQ Bit combined over the PCGs */
                               /* 1->ACK, 0->NAK */ 
    /** [Out]*/                             
    kal_uint8  RPCValid;           /* 0->NotVal, 1->Valid, Valid occurs every  */  
    /** [Out]*/                             
    kal_uint8  RPCBit;             /* 0->up, 1->down*/                                
    /** [Out]*/                            
    kal_uint8  QRAB;               /* QRAB Hard value combined (logical OR) over all sectors */   
    /** [Out]*/                           
    kal_int32  FRAB;               /* FRAB for current subframe combined (max among) over all sectors */
    /** [Out]*/
    kal_int32  oldFRAB;            /* FRAB for previous subframe combined (max among) over all sectors */  
    /** [Out]*/
    CphMacBitsSectorT Sector[EVDO_MAX_NUM_PILOTS];
    /** [Out]*/
    CphMacBitsPCGT Pcg[EVDO_MAX_NUM_PCG];
}CphEvl1McdGetMacBitsOutputT;

typedef struct    
{
    /** [In]*/
    kal_bool   muEnable;
    /** [In]*/
    kal_uint8  dof;
    /** [In]*/
    kal_uint16 pmbCtrlInitTraffic;
    /** [In]*/
    kal_uint8  pmbMode;
    /** [In]*/
    kal_uint8  macIndex;
    /** [In]*/
    kal_uint16 pmbCtrl;
    /** [In]*/
    kal_uint16 pmbEnablePmabM;
}CphEvl1PdCtxT;


typedef struct 
{
    /** [In]*/
    kal_uint8   initBitmap;
    /** [In]*/
    kal_uint16  cfgBitmap;  /*indicate the configuration type*/
    /** [In]*/
    kal_int32   drcC2IMax;
    /** [In]*/
    kal_int32   drcC2IMin;
    /** [In]*/
    kal_int32   drcGlobalAdj;
    /** [In]*/
    kal_bool    globalByPass;
    /** [In]*/
    kal_int32   slmsInit[5];
    /** [In]*/
    kal_int32   drcThrByPass1;
    /** [In]*/
    kal_int32   drcThrByPass2;
    /** [In]*/
    kal_int32   drcSlmsMu;
    /** [In]*/
    kal_int32   drcIIrPole;
    /** [In]*/
    kal_int32   drcErrIIrPole;
    /** [In]*/
    kal_uint8   drcLength;
    /** [In]*/
    kal_bool    drcGating;
    /** [In]*/
    kal_int32   drcLvcrossLen;
    /** [In]*/
    kal_uint8   fixTxDrc;
    /** [In]*/
    kal_uint16  drcMode;
    /** [In]*/
    kal_int32   drcCtrl;
    /** [In]*/
    kal_uint16  pmbEnablePmabM;
    /** [In]*/
    kal_uint32  *pDrcOffset;
    /** [In]*/
    kal_int32   *pDrcC2IThr;
    /** [In]*/
    kal_uint32  *pDrcThrPut;
    /** [In]*/
    kal_uint32  *pDrcThrAwgn;
	/** [In]*/
	kal_bool	bDrcRangeFlag;
	/** [In]*/
	kal_uint32	maxDrcValue;
	/** [In]*/
	kal_uint32	minDrcValue;
}CphEvl1DrcCtxT;


typedef struct
{
    /** [Out]*/
    kal_uint8   timeStamp;
    /** [Out]*/
    kal_bool    reackFlag;
    /** [Out]*/
    kal_uint8   supMacindex;
    /** [Out]*/
    kal_uint8   preambleMacindex;
    /** [Out]*/
    kal_uint8   interlaceId;
} CphEvl1RxcPacketInfoReadT;

typedef struct
{
    /** [Out]*/
    kal_bool   interlaceStatus[RXC_INTERLACE_LENGTH];
} CphEvl1RxcInterlaceStatusReadT;


typedef struct
{
    /** [In]*/
    kal_bool   crcResultInterlace;
    /** [In]*/
    kal_uint8  interlaceId;
} CphEvl1RxcPacketCrcResultT;

typedef struct
{
    /** [In]*/
    kal_uint8 CntAcc;
    /** [In]*/
    kal_uint32 SNRAcc;
    /** [In]*/
    kal_int32  ReFineAcc;  
    /** [In]*/
    kal_int32  ImFineAcc;
    /** [In]*/
    kal_int32  ReCoarseAcc;
    /** [In]*/
    kal_int32  ImCoarseAcc;
} CphEvl1AfcAccMetricT;


typedef struct
{
    /** [In]*/
    kal_uint16 PreSnr1; /**Pre SNR 1 from CE, floating point 1/5/10 format*/
    /** [In]*/
    kal_uint16 PreSnr2; /**Pre SNR2 RXD from CE, floating point 1/5/10 format*/
}CphEvl1CePreSnrT;


typedef struct
{
    kal_bool       RESET_EN;
    kal_bool       EQ_MODE_L1_EN;
    kal_uint32     EQ_MODE;
    kal_bool       MMSE_FLAG_L1_EN;
    kal_uint32     MMSE_FLAG;
    kal_bool       ITER_NUM_L1_EN;
    kal_uint32     ITER_NUM;
    kal_bool       ALPHA_FILTER_MODE_L1_EN;
    kal_uint32     ALPHA_FILTER_MODE;
    kal_bool       DATA_FTM_L1_EN;
    kal_uint32     DATA_FRAC;
    kal_uint32     C2I_FRAC;
    kal_bool       PRE_COURSE_L1_EN;
    kal_uint32     PRE_COURSE;
    kal_bool       CORR_LEN_L1_EN;
    kal_uint32     CORR_LEN;
    kal_bool       ALPHA_SHIFT_L1_EN;
    kal_uint32     ALPHA_SHIFT;
    kal_bool       WIN_ADD_BD_L1_EN;
    kal_uint32     WIN_ADD_BD;
    kal_bool       PD_MATRIX_NOISE_L1_EN;
    kal_uint32     PD_MATRIX_NOISE;
}CphEvl1CuifCfgParamT;

void CphEvl1FlSrpRakeCmifReset(void);
void CphEvl1FlSrpRakeStart(CphEvl1RakeStartT *adsPtr);
void CphEvl1FlSrpRakeRestore(CphEvl1RakeStartT *adsPtr);
void CphEvl1FlSrpIdRegDump(kal_uint32 *ads_ptr);
void CphEvl1FlSrpCgRegDump(kal_uint32 *ads_ptr);
void CphEvl1FlSrpRakeCphichOn(kal_uint32 CpichOnTime);
void CphEvl1FlSrpRakeDeactive(kal_uint8 T5SlotIdx);
void CphEvl1FlSrpRakeEnterDormantDleep(void);
void CphEvl1FlSrpD2bifOff(void);
void CphEvl1FlSrpRakeStateCfg(CphEvl1StateT Evl1State);
void CphEvl1FlSrpRakeSubTypeCfg(kal_uint32 Evl1Subtype);
void CphEvl1FlSrpRakeT5Cfg(kal_uint8 T5SlotIdx);
void CphEvl1FlSrpRakeChCfg(CphEvl1StateT Evl1State, CphEvl1RakeChT *adsPtr);
void CphEvl1FlSrpRakeFngCfg(CphEvl1RakeFngCfgT *adsPtr);
void CphEvl1FlSrpTargetSectorCfg(kal_bool CellSwEnFlag, kal_uint8 TargetSectorId);
kal_bool CphEvl1FlSrpCsmEnCheck(void);
void CphEvl1FlSrpRakeTxFrameOffsetCfg(kal_uint16 TxFrameOffset);
kal_uint16 CphEvl1FlSrpFngTotalSNRRead(void);
kal_uint32 CphEvl1FlSrpFngSNRRead(kal_uint8 FngIdx);
kal_uint32 CphEvl1FlSrpFngRxDSNRRead(kal_uint8 FngIdx);
void CphEvl1FlSrpTrackerCfg(CphEvl1TrackerCfgT *adsPtr);
void CphEvl1FlSrpTrackerResultRead(CphEvl1TrackerResultT*adsPtr);
void CphEvl1FlSrpSpestCfg(CphEvl1SpestCfgT *adsPtr);
kal_uint32 CphEvl1FlSrpCurrSpeedRead(void);
void CphEvl1FlSrpRxdCfg(kal_bool RxDEn);
void CphEvl1FlSrpOCOnCfg(kal_bool OcEnFlag);
void CphEvl1FlSrpMcdStart(kal_uint32 MacSubType, CphEvl1BsrpMcdInfoT *adsPtr);
kal_uint8 CphEvl1FlSrpMcdHlArqRead( void );
void CphEvl1FlSrpMcdArqTypeCfg(kal_uint8 NextArqType);
void CphEvl1FlSrpMcdDbgCfg(Evl1McdDebugParamT *adsPtr);
void CphEvl1FlSrpMcdMacBitsRead(CphEvl1McdGetMacBitsInputT *adsPtrIn,  CphEvl1McdGetMacBitsOutputT *adsPtrOut);
void CphEvl1FlSrpUsipCfg(kal_bool UsipEnFlag);
void CphEvl1FlSrpUsipMacIndexCfg(kal_uint8 SupMacIndex);
void CphEvl1FlSrpPdEnable(kal_bool enable , void *adsPtr);
void CphEvl1FlSrpPdConfig(CphEvl1FlSrpPdCfgType cfgType, void *adsPtr);
void CphEvl1FlSrpDrcInit(CphEvl1FlSrpDrcInitType initType, void *adsPtr);
void CphEvl1FlSrpDrcConfig(CphEvl1FlSrpDrcCfgType cfgType, void *adsPtr);
void CphEvl1FlSrpDrcTableUpdate(void *adsPtr);
kal_int32 CphEvl1FlSrpDrcRegRead(APBADDR32 regAddr);
void CphEvl1FlSrpDrcRegWrite(APBADDR32 regAddr, kal_int32 regVal);
void CphEvl1FlSrpRxcInitialTimeConfig(kal_uint32 timeStamp);
void CphEvl1FlSrpRxcCrcResultConfig(CphEvl1RxcPacketCrcResultT *adsPtr);
void CphEvl1FlSrpRxcPacketInfoRead(CphEvl1RxcPacketInfoReadT *adsPtr);
void CphEvl1FlSrpRxcInterlaceStatusRead(CphEvl1RxcInterlaceStatusReadT *adsPtr);
void CphEvl1FlSrpAfcAccRead(CphEvl1AfcAccMetricT *adsPtr);
kal_bool CphEvl1FlSrpAfcBusyChk(void);
void CphEvl1FlSrpAfcRst(void);
void CphEvl1FlSrpAfcLock(void);
void CphEvl1FlSrpAfcUnLock(void);
void CphEvl1FlSrpAfcModeCfg(CphAfcModeT AfcMode);
void CphEvl1FlSrpPreSNRRead(CphEvl1CePreSnrT *CESnr);
kal_uint16 CphEvl1FlSrpPostSNRRead(kal_uint8 InterlaceId);
void CphEvl1FlSrpC2iMuCfg(kal_uint32 IirTime);
kal_uint16 CphEvl1FlSrpC2iSamplCntGet(kal_uint8 SecId);
void CphEvl1FlSrpC2iLogRlstGet(kal_uint8 SecId, kal_int16 *C2iLog0y, kal_int16 *C2iLog1y);
kal_uint8 CphEvl1FlSrpSupMacIndexRead(kal_uint8 InterlaceId);
kal_uint32 CphEvl1FlSrpFnSlotOffsetRead(void);
kal_uint8 CphEvl1FlSrpSubTypeRead(void);
kal_uint16 CphEvl1FlSrpDrcC2iShortRead(void);
kal_uint16 CphEvl1FlSrpDrcC2iLongRead(void);
kal_uint8 CphEvl1FlSrpDrcValueRead(void);
kal_uint8 CphEvl1FlSrpUserMacIndexRead(void);
extern void CphEvl1FlSrpGsrRead(CphEvl1FlSrpGsrT *adsPtr);
extern kal_uint32 CphEvl1FlSrpFngEnRead();
extern kal_uint32* CphEvl1FlSrpCalBigRAMAddr(void);
extern void CphEvl1FlSrpRxcConfigMinContSpan(kal_uint8 MinContSpan);
extern void CphEvl1FlSrpCuifCfg(CphEvl1CuifCfgParamT *adsPtr);
extern void CphEvl1FlSrpTimingAdjCfg(kal_int16 TimeAdjEchip);
#endif