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yu.dongc33b3072024-08-21 23:14:49 -07001/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * mddbg_pulbic.h
41 *
42 * Project:
43 * --------
44 * Maui_Software
45 *
46 * Description:
47 * ------------
48 * Modem debugging related implementation
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
58 * removed!
59 * removed!
60 * removed!
61 *
62 * removed!
63 * removed!
64 * removed!
65 * removed!
66 *
67 * removed!
68 * removed!
69 * removed!
70 * removed!
71 *
72 * removed!
73 * removed!
74 * removed!
75 *
76 * removed!
77 * removed!
78 * removed!
79 *
80 *------------------------------------------------------------------------------
81 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
82 *============================================================================
83 ****************************************************************************/
84#ifndef __MDDBG_PUBLIC_H__
85#define __MDDBG_PUBLIC_H__
86// remove to enable MDDBG for Gen97 FPGA debug temporarily, let user call
87// mddbg_set_bp_int_shaolin_temp
88// mddbg_set_wp_int_shaolin_temp
89#if (defined(__MTK_SECURE_PLATFORM__) || defined(__PRODUCTION_RELEASE__) || !defined(__MTK_TARGET__))
90 #define DISABLE_MDDBG_FUNCTION
91#endif
92
93
94typedef enum MDDBG_HDL_TYPE_e {
95 MDDBG_HT_MEMDUMP,
96 MDDBG_HT_LOG,
97 MDDBG_HT_MAX,
98} MDDBG_HDL_TYPE;
99
100typedef enum MDDBG_WP_ACCESS_TYPE_e {
101 MDDBG_WAT_WRITE = 1,
102 MDDBG_WAT_READ,
103 MDDBG_WAT_RW,
104} MDDBG_WP_ACCESS_TYPE;
105
106typedef enum MDDBG_WP_MONITOR_BYTE_e {
107 MDDBG_WMB_1BYTE = 1,
108 MDDBG_WMB_2BYTES,
109 MDDBG_WMB_3BYTES,
110 MDDBG_WMB_4BYTES,
111 MDDBG_WMB_MAX,
112} MDDBG_WP_MONITOR_BYTE;
113
114typedef enum MDDBG_RESULT_e {
115 MDDBG_SUCCESS,
116 MDDBG_INVALID_PARAM,
117 MDDBG_BP_TOO_MANY,
118 MDDBG_BP_ALREADY_ENABLED,
119 MDDBG_BP_ALREADY_DISABLED,
120 MDDBG_WP_TOO_MANY,
121 MDDBG_WP_MON_OUT_OF_RANGE,
122 MDDBG_VPE_INDEX_OUT_OF_RANGE,
123 MDDBG_BP_INDEX_OUT_OF_RANGE,
124 MDDBG_WP_INDEX_OUT_OF_RANGE,
125 MDDBG_SHOULD_NOT_CALL_IN_SYSTEMINIT,
126} MDDBG_RESULT;
127
128typedef enum MDDBG_BP_NUM_e{
129 MDDBG_BP_0,
130 MDDBG_BP_1,
131#if defined (__MIPS_I7200__)
132 MDDBG_BP_2,
133 MDDBG_BP_3,
134#endif
135}MDDBG_BP_NUM;
136
137typedef enum MDDBG_WP_NUM_e{
138 MDDBG_WP_0,
139#if defined (__MIPS_I7200__)
140 MDDBG_WP_1,
141 MDDBG_WP_2,
142#endif
143}MDDBG_WP_NUM;
144
145
146typedef struct mddbg_bp_info {
147 kal_uint32 address;
148 kal_bool enable;
149} mddbg_bp_info_st;
150
151typedef struct mddbg_wp_info {
152 kal_uint32 address;
153 kal_uint32 mask;
154 MDDBG_WP_ACCESS_TYPE access_type;
155 kal_bool enable;
156} mddbg_wp_info_st;
157
158typedef struct mddbg_reg_t{
159 kal_uint32 ctrl_addr;
160 kal_uint32 watchHi;
161 kal_uint32 queryNum;
162}mddbg_reg_t;
163
164
165
166
167#define CONFIG_TAG_BP0 0 // should not be used here, because used as stack protection. Check: KAL_WATCHPOINT_3_SET
168#define CONFIG_TAG_BP1 1
169#define CONFIG_TAG_WP0 2
170#define CONFIG_TAG_WP1 3
171
172#define CONFIG_ADDRESS(addr) (addr << 3)
173#define CONFIG_EXCEPTION_TYPE_BIT 0X7
174#define CONFIG_WRITE 0x1
175#define CONFIG_READ 0x2
176#define CONFIG_INSTRUCTION 0x4
177#define CONFIG_MASK_BIT 0X1FF
178#define CONFIG_MASK(mask) (mask << 3)
179#define CONFIG_NO_MASK 0
180#define CONFIG_NIL_ADDR 0xdead0000
181
182#define CONFIG_VPE0 1
183#define CONFIG_VPE1 1 << 1
184#define CONFIG_VPE2 1 << 2
185#define CONFIG_VPE3 1 << 3
186
187#if defined(__MIPS_IA__)
188 #define CONFIG_MAX_VPE 4
189 #define CONFIG_VPE_ALL CONFIG_VPE0 | CONFIG_VPE1 | CONFIG_VPE2 | CONFIG_VPE3
190
191#elif defined(__MIPS_I7200__)
192
193 #define CONFIG_VPE4 1 << 4
194 #define CONFIG_VPE5 1 << 5
195 #define CONFIG_VPE6 1 << 6
196 #define CONFIG_VPE7 1 << 7
197 #define CONFIG_VPE8 1 << 8
198 #define CONFIG_VPE9 1 << 9
199 #define CONFIG_VPE10 1 << 10
200 #define CONFIG_VPE11 1 << 11
201
202 #define CONFIG_MAX_VPE 12
203 /* 12 bit is 0xfff, too painful to OR all above */
204 #define CONFIG_VPE_ALL 0xfff
205
206#endif
207
208
209MDDBG_RESULT mddbg_init_public(void);
210MDDBG_RESULT mddbg_set_breakpoint(kal_uint32 vpeIndexes, kal_uint32 selectBP, kal_uint32 bp_addr, kal_uint32 addr_mask);
211MDDBG_RESULT mddbg_set_watchpoint(kal_uint32 vpeIndexes, kal_uint32 selectWP, kal_uint32 wp_addr, kal_uint32 addr_mask, kal_uint32 type);
212MDDBG_RESULT mddbg_remove_watchpoint(kal_uint32 vpeIndexes, kal_uint32 selectWP);
213MDDBG_RESULT mddbg_remove_breakpoint(kal_uint32 vpeIndexes, kal_uint32 selectBP);
214MDDBG_RESULT mddbg_applyAll(void/*MDDBG_HDL_TYPE*/);
215MDDBG_RESULT mddbg_resetAll(void);
216MDDBG_RESULT mddbg_query(void);
217mddbg_reg_t mddbg_get_queryBPResult(kal_uint32 vpeInd, kal_uint32 selectBP);
218mddbg_reg_t mddbg_get_queryWPResult(kal_uint32 vpeInd, kal_uint32 selectWP);
219kal_uint32 mddbg_get_offender(kal_uint32 vpe,kal_uint32 watchpoint);
220#if defined (__MIPS_I7200__)
221MDDBG_RESULT mddbg_set_bp_int_shaolin_temp (kal_uint32 tcIndex, kal_uint32 selectBP, kal_uint32 bp_addr, kal_uint32 addr_mask);
222MDDBG_RESULT mddbg_set_wp_int_shaolin_temp (kal_uint32 tcIndex, kal_uint32 selectWP, kal_uint32 wp_addr, kal_uint32 addr_mask, kal_uint32 type);
223#endif
224
225#endif // __MDDBG_PUBLIC_H__