| yu.dong | c33b307 | 2024-08-21 23:14:49 -0700 | [diff] [blame^] | 1 | #ifndef __SVC_EX_USIP_CACHE_DUMP_H__ |
| 2 | #define __SVC_EX_USIP_CACHE_DUMP_H__ |
| 3 | |
| 4 | #include "kal_general_types.h" |
| 5 | #include "reg_base.h" |
| 6 | #include "dsp_cache_public.h" |
| 7 | |
| 8 | /******************************************************************************* |
| 9 | * USIP APB Definition |
| 10 | *******************************************************************************/ |
| 11 | |
| 12 | #if defined(__MD97__) |
| 13 | #define USIP0_APB_BASE BASE_MADDR_USIP0_0_USIP0 |
| 14 | #define USIP1_APB_BASE BASE_MADDR_USIP1_0_USIP1 |
| 15 | #define USIP_APB_DBG_EN_OFFSET 0x0 |
| 16 | #define USIP_APB_MODE_SEL_OFFSET 0x4 |
| 17 | #define USIP_APB_DBG_INST_OFFSET 0x10 |
| 18 | #define USIP_APB_DBG_EXECUTE_OFFSET 0x14 |
| 19 | #define USIP_APB_DBG_WRITE_ADDR_OFFSET 0x18 |
| 20 | #define USIP_APB_DBG_WRITE_OFFSET 0x1c |
| 21 | #define USIP_APB_DBG_STATUS_OFFSET 0x20 |
| 22 | |
| 23 | #define USIP_APB_DBG_ATTACH_INST 0x900 |
| 24 | #define USIP_APB_DBG_REQ_INST 0x811 |
| 25 | #define USIP_APB_DBG_STATUS_INST 0x803 |
| 26 | #define USIP_APB_DBG_ADDR_INST 0x801 |
| 27 | #define USIP_APB_DBG_PM_LOAD_INST 0x840 |
| 28 | #define USIP_APB_DBG_INSTR_INST 0x802 |
| 29 | #define USIP_APB_DBG_RESUME_INST 0x812 |
| 30 | |
| 31 | #define USIP_CACHE_ALIGN 0x20 |
| 32 | #elif defined(__MD97P__) |
| 33 | #define USIP0_APB_BASE BASE_MADDR_USIP0_USIP0 |
| 34 | #define USIP1_APB_BASE BASE_MADDR_USIP1_USIP1 |
| 35 | #define USIP_APB_DBG_EN_OFFSET 0x0 |
| 36 | #define USIP_APB_MODE_SEL_OFFSET 0x4 |
| 37 | #define USIP_APB_DBG_INST_OFFSET 0x10 |
| 38 | #define USIP_APB_DBG_EXECUTE_OFFSET 0x14 |
| 39 | #define USIP_APB_DBG_WRITE_ADDR_OFFSET 0x18 |
| 40 | #define USIP_APB_DBG_WRITE_OFFSET 0x1c |
| 41 | #define USIP_APB_DBG_STATUS_OFFSET 0x20 |
| 42 | |
| 43 | #define USIP_APB_DBG_ATTACH_INST 0x900 |
| 44 | #define USIP_APB_DBG_REQ_INST 0x811 |
| 45 | #define USIP_APB_DBG_STATUS_INST 0x803 |
| 46 | #define USIP_APB_DBG_ADDR_INST 0x801 |
| 47 | #define USIP_APB_DBG_PM_LOAD_INST 0x840 |
| 48 | #define USIP_APB_DBG_INSTR_INST 0x802 |
| 49 | #define USIP_APB_DBG_RESUME_INST 0x812 |
| 50 | |
| 51 | #define USIP_CACHE_ALIGN 0x20 |
| 52 | #else |
| 53 | #error "undefined platform" |
| 54 | #endif |
| 55 | |
| 56 | /******************************************************************************* |
| 57 | * Enum |
| 58 | *******************************************************************************/ |
| 59 | typedef enum { |
| 60 | EX_IABT_NONE = 0xA0000000, |
| 61 | EX_READ_USIP_IABT_PC_DONE = 0xA0000001, |
| 62 | EX_READ_USIP_IABT_PATTERN_DONE = 0xA0000010, |
| 63 | EX_ENABLE_USIP_DBG_MODE_GET_ICACHE_CONTENT_START = 0xA0000020, |
| 64 | EX_ENABLE_USIP_DBG_MODE_START = 0xA0000030, |
| 65 | EX_ENABLE_USIP_DBG_MODE_DONE = 0xA0000040, |
| 66 | EX_USIP_ICAHCE_READ_START = 0xA0000050, |
| 67 | EX_USIP_ICAHCE_READ_DONE = 0xA0000060, |
| 68 | EX_USIP_RESUME_DONE = 0xA0000070 |
| 69 | } EX_USIP_ICACHE_RELATED_Step_Logging_t; |
| 70 | |
| 71 | /******************************************************************************* |
| 72 | * Macro |
| 73 | *******************************************************************************/ |
| 74 | #define EX_USIP_ICACHE_LOGGING_SYNC_TIMEOUT 2000000 |
| 75 | #define EX_USIP_ICACHE_LOGGING_STEP_SET(sts) ex_usip_icache_logging_step = (sts) |
| 76 | |
| 77 | |
| 78 | #if defined(__MD97__) && defined(__MTK_TARGET__) |
| 79 | |
| 80 | #define MCORE_CLKCTRL_ADDR 0xA40A0040 |
| 81 | #define VCORE_CLKCTRL_ADDR 0xA50A0040 |
| 82 | |
| 83 | #define MCORE_DCACHE_0_CLK_ON 0x10 |
| 84 | #define MCORE_DCACHE_1_CLK_ON 0x20 |
| 85 | #define MCORE_DCACHE_2_CLK_ON 0x40 |
| 86 | #define MCORE_DCACHE_3_CLK_ON 0x80 |
| 87 | |
| 88 | #define VCORE_DCACHE_0_CLK_ON 0x1 |
| 89 | #define VCORE_DCACHE_1_CLK_ON 0x2 |
| 90 | #define VCORE_DCACHE_2_CLK_ON 0x4 |
| 91 | #define VCORE_DCACHE_3_CLK_ON 0x8 |
| 92 | |
| 93 | extern void nr_bb_reg_init(void); |
| 94 | |
| 95 | #endif //defined(__MD97__) && defined(__MTK_TARGET__) |
| 96 | |
| 97 | #endif |