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192.168.1.100 / T800_MD_V1.6 / c33b3079c38f91561c2f84f1ebed20ad8c60532a / . / mcu / service / sst / include / spv_api.h
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yu.dongc33b3072024-08-21 23:14:49 -0700[diff] [blame^]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*******************************************************************************
37 * Filename:
38 * -----------
39 * spv_api.h
40 *
41 * Project:
42 * -----------
43 * UMOLY
44 *
45 * Description:
46 * ------------
47 * SPV Related API Code
48 *
49 * Author:
50 * -------
51 * -------
52 *
53 * ==========================================================================
54 * $Log$
55 *
56 * 07 16 2020 yunciou.lin
57 * [MOLY00546717] [MT6833] [Palmer] feature check-in: SPV option & disable emimpu for palmer bringup.
58 * [Palmer] feature check-in:
59 * SPV option &
60 * disable emimpu for palmer bringup.
61 *
62 * 02 07 2020 chia-fu.lee
63 * [MOLY00475722] [VMOLY][MT6853] Mouton call for check in
64 *
65 * [SSS] Trace feature support on sampling mode
66 *
67 * 01 21 2020 justin.chen
68 * [MOLY00475722] [VMOLY][MT6853] Mouton call for check in
69 * . Update SPV related file.
70 *
71 * 12 26 2019 justin.chen
72 * [MOLY00462986] [MT6885] elm driver development
73 * .Update MT6873 force latency API.
74 *
75 * 12 26 2019 gway.lo
76 * [MOLY00462986] [MT6885] elm driver development
77 * 1. word count threshold change api
78 * 2. toggle elm on/off api
79 *
80 * 12 24 2019 gway.lo
81 * [MOLY00462986] [MT6885] elm driver development
82 *
83 * enable Margaux ELM 2nd assert
84 *
85 * 12 06 2019 chia-fu.lee
86 * [MOLY00460633] [MT6885][Petrus][MP1][SQC][CTC][FT][NSA][5G FT][China][Shanghai][Extension FT][MDST][CAT]md1:(MCU_core0,vpe1,tc2(VPE1)) [ASSERT] file:mcu/l1/ul1/ul1d_public/ul1_bb_error_check.c line:108
87 *
88 * Rollback debugging patch for UL1 HRT fail issue
89 *
90 * 11 12 2019 chia-fu.lee
91 * [MOLY00458740] [MT6885][Petrus][MP1][SQC][CTC][FT][NSA][5G FT][China][Suzhou][Extension FT][MDST][CAT]file:mcu/l1/ul1/ul1d_public/ul1_bb_error_check.c line:108
92 *
93 * EWSP0000059818
94 * SSS debugging patch
95 *
96 * 11 07 2019 gway.lo
97 * [MOLY00457526] [MT6873] driver porting
98 * disable elm assert mode and porting emi force latency api on MT6873
99 *
100 * 09 19 2019 gway.lo
101 * [MOLY00403390] [MT6297] ELM driver development
102 * petrus force emi latency
103 *
104 * 09 19 2019 chia-fu.lee
105 * [MOLY00434384] [Apollo] Debugging patch for UL1D_RF_ImmRxCentralConfig abnormal execution time
106 *
107 * Rollback debug patch for IRQ0xF5 issue
108 *
109 * 08 26 2019 chia-fu.lee
110 * [MOLY00434384] [Apollo] Debugging patch for UL1D_RF_ImmRxCentralConfig abnormal execution time
111 *
112 * Fixed Mercury(MD97P) build error.
113 *
114 * 08 26 2019 chia-fu.lee
115 * [MOLY00434384] [Apollo] Debugging patch for UL1D_RF_ImmRxCentralConfig abnormal execution time
116 * SSS Profiling
117 *
118 * 05 27 2019 gway.lo
119 * [MOLY00408920] [MT6297] SPV long time profile update
120 * long time profile feature update
121 *
122 * 04 12 2019 gway.lo
123 * [MOLY00398406] [MT6297] SS SPV AMIF profile feature
124 * AMIF profiling feature
125 *
126 * 01 14 2019 chia-fu.lee
127 * [MOLY00378963] [SystemService][MT6297] SWLA and CM2 counter / SSS PMU Profiling Development
128 *
129 * SSS PMU Profiling API
130 *
131 * 12 18 2018 gway.lo
132 * [MOLY00367306] [MT6297][SPV] basic profiling code check-in
133 * fix build error
134 *
135 * 12 18 2018 gway.lo
136 * [MOLY00367306] [MT6297][SPV] basic profiling code check-in
137 * force emi latenct, long time profiling
138 *
139 * 07 16 2018 chia-fu.lee
140 * [MOLY00338914] [SPV][Gen95] EBM in BW runtime profiling
141 *
142 * .
143 *
144 * 05 21 2018 chia-fu.lee
145 * [MOLY00327212] [Gen95][L2C LOCK]Remove Static L2 Cache Lock input sections
146 *
147 * [UMOLYE] SPV service Remove Static L2 Cache Lock input sections
148 *
149 * 04 02 2018 chin-chieh.hung
150 * [MOLY00309439] Eiger SPV utilities support
151 * Update EBM driver for Gen95
152 *
153 * 03 19 2018 chia-fu.lee
154 * [MOLY00313462] [Gen95] SPV_SVC porting
155 * SPV_SVC modification support write latency information
156 *
157 * 03 14 2018 chia-fu.lee
158 * [MOLY00313462] [Gen95] SPV_SVC porting
159 *
160 * Modify ELM part
161 *
162 * 03 13 2018 chin-chieh.hung
163 * [MOLY00309439] Eiger SPV utilities support
164 * Disable EMI latency count by 26Mhz
165 *
166 * 03 08 2018 peng-chih.wang
167 * [MOLY00312351] [System Service] Add M4 force latency and AT cmd for Gen95 PS SPV
168 * Eiger PS SPV -- porting force M4 latency and AT cmd.
169 *
170 * 02 23 2018 chin-chieh.hung
171 * [MOLY00309439] Eiger SPV utilities support
172 * Add Gen95 SPV utilities - Force Latency / EBM counter
173 *
174 * 09 07 2017 yen-chun.liu
175 * [MOLY00274402] [Gen93] SPV profiling utility
176 * BW/latency profiling code v2.
177 *
178 * 09 07 2017 yen-chun.liu
179 * [MOLY00274402] [Gen93] SPV profiling utility
180 * BW/latency runtime profiling.
181 *
182 * 07 24 2017 wellken.chen
183 * [MOLY00265986] [SPVSVC] Add spv service 1st version related
184 *
185 * 06 02 2017 linson.du
186 * [MOLY00254730] [Gen93]: ELM driver update for EMI latency issue
187 * ELM driver update for SPV usage.
188 *
189 * 07 14 2015 wellken.chen
190 * [MOLY00128710] [Jade][SPV] Refine SPV API realted code
191 *
192 *
193 *
194 *
195 *
196 ****************************************************************************/
197
198
199#ifndef __SPV_API_H_
200#define __SPV_API_H_
201
202#include "reg_base.h"
203#include "kal_general_types.h"
204#include "elm.h"
205
206#if defined(__FORCE_EMI_LATENCY_ENABLE__)
207#if defined(MT6763)||defined(MT3967) //use AP EMI
208
209#define SPV_MADDR_MEMAPB (0xC0219000)
210
211#define EMI_CONE (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x20)
212#define EMI_DRCT (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x78)
213#define EMI_ARBD (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x118)
214#define EMI_ARBE (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x120)
215#define EMI_SLCT (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x158)
216#define EMI_CONM (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x60)
217#define EMI_TESTB (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0xE8)
218
219#if !defined(__SPV_EBM_DRIVER__)
220#define EMI_BMEN (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x400)
221#define EMI_BCNT (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x408)
222
223#define EMI_TSCT (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x418)
224#define EMI_WSCT (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x428)
225#define EMI_BACT (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x430)
226#define EMI_BSCT (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x438)
227#define EMI_MSEL (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x440)
228#define EMI_TSCT2 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x448)
229#define EMI_WSCT2 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x458)
230#define EMI_BMEN2 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x4E8)
231
232
233#define EMI_TTYPE1 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x500)
234#define EMI_TTYPE2 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x508)
235#define EMI_TTYPE3 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x510)
236#define EMI_TTYPE4 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x518)
237#define EMI_TTYPE5 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x520)
238#define EMI_TTYPE6 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x528)
239#define EMI_TTYPE7 (volatile kal_uint32 *)(SPV_MADDR_MEMAPB + 0x53C)
240#endif //!defined(__SPV_EBM_DRIVER__)
241
242#if defined(MT3967) //use AP EMI
243
244#define EMI_FORCE_LATENCY(r, w) \
245 do {\
246 *EMI_CONE |= 1;\
247 *EMI_DRCT = 0x23110000;\
248 *EMI_ARBD = 0x00003000 | (r<<16) | (w<<24);\
249 *EMI_SLCT = 0x1F011700;\
250 *EMI_CONM = 0xff000500;\
251 } while (0)
252
253#else
254
255//psmcu ultra
256#define SPV_PSMCU_QOS_CTL ((volatile kal_uint32 *)(BASE_MADDR_MDPERIMISC + 0xF0))
257
258#define EMI_FORCE_LATENCY(r, w) \
259 do {\
260 while (*SPV_PSMCU_QOS_CTL & 0x11) {*SPV_PSMCU_QOS_CTL &= ~(0x11);}\
261 *EMI_DRCT = 0x23110000;\
262 *EMI_ARBD = 0x00003000 | (r<<16) | (w<<24);\
263 *EMI_SLCT = 0x1F011700;\
264 *EMI_CONM = 0xff000500;\
265 } while (0)
266
267#define EMI_FORCE_M4_LATENCY(r, w) \
268 do {\
269 while (*SPV_PSMCU_QOS_CTL & 0x11) {*SPV_PSMCU_QOS_CTL &= ~(0x11);}\
270 *EMI_DRCT = 0x23110000;\
271 *EMI_ARBE = 0x00003000 | (r<<16) | (w<<24);\
272 *EMI_SLCT = 0x1F011700;\
273 *EMI_CONM = 0xff000500;\
274 } while (0)
275#endif
276
277#define EMI_FORCE_DISABLE_DRAMC_WRITE_EARLY_RESPONSE() \
278 do {\
279 *EMI_TESTB |= (1<<11);\
280 } while(0)
281
282#elif defined(MT6297)
283
284#define SPV_MADDR_MEMAPB (0xC0219000)
285
286#define EMI_CONE (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x20 )
287#define EMI_DRCT (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x78 )
288#define EMI_CONM (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x60 )
289#define EMI_TESTB (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xE8 )
290#define EMI_ARBD (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x118)
291#define EMI_ARBE_2ND (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x124)
292#define EMI_SLCT (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x158)
293#define EMI_SHF0 (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x710)
294#define EMI_BWLMTA (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x890)
295#define EMI_BWLMTF_2ND (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x8E4)
296#define EMI_BWLMTF_5TH (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0x934)
297#define EMI_QOS_MDR_BE0A (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xD04)
298#define EMI_QOS_MDR_BE0B (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xD08)
299#define EMI_QOS_MDR_BE1A (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xD0C)
300#define EMI_QOS_MDR_BE1B (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xD10)
301#define EMI_QOS_MDR_SHF0 (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xD14)
302#define EMI_QOS_MDR_SHF1 (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xD18)
303#define EMI_QOS_MDW_SHF0 (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xD2C)
304#define EMI_QOS_MDW_SHF1 (volatile kal_uint32*)(SPV_MADDR_MEMAPB + 0xD30)
305
306#define EMI_FORCE_LATENCY(r, w) \
307 do {\
308 *EMI_CONE |= 1;\
309 *EMI_DRCT = 0x23110000;\
310 *EMI_SHF0 &= 0xFFFFFFF0; \
311 *EMI_ARBD = 0x00003000 | (r<<16) | (w<<24);\
312 *EMI_ARBE_2ND = (*EMI_ARBE_2ND & 0x0000FFFF) | (r<<16) | (w<<24);\
313 *EMI_SLCT = 0x1F011700;\
314 *EMI_CONM = 0xff000500;\
315 \
316 *EMI_BWLMTA |= (0x01UL<< 3); \
317 *EMI_BWLMTA &= ~(0x01UL<<11); \
318 *EMI_BWLMTA &= ~(0x01UL<<27); \
319 *EMI_BWLMTF_2ND &= 0xFFFF0000UL; \
320 *EMI_BWLMTF_5TH &= 0xFFFF0000UL; \
321 *EMI_QOS_MDR_SHF0 = (*EMI_QOS_MDR_SHF0 & (0xFFF00000UL)) | (r&0xFF)<<8 | (r&0xFF); \
322 *EMI_QOS_MDR_SHF1 = (*EMI_QOS_MDR_SHF1 & (0xFFF00000UL)) | (r&0xFF)<<8 | (r&0xFF); \
323 *EMI_QOS_MDW_SHF0 = (*EMI_QOS_MDW_SHF0 & (0xFFF00000UL)) | (w&0xFF)<<8 | (w&0xFF); \
324 *EMI_QOS_MDW_SHF1 = (*EMI_QOS_MDW_SHF1 & (0xFFF00000UL)) | (w&0xFF)<<8 | (w&0xFF); \
325 *EMI_QOS_MDR_BE0A = 0x00000000; \
326 *EMI_QOS_MDR_BE0B = 0x00000000; \
327 *EMI_QOS_MDR_BE1A = 0x00000000; \
328 *EMI_QOS_MDR_BE1B = 0x00000000; \
329 } while (0)
330
331
332#define EMI_FORCE_DISABLE_DRAMC_WRITE_EARLY_RESPONSE() \
333 do {\
334 *EMI_TESTB |= (1<<11);\
335 } while(0)
336
337#define FORCE_MD_ULTRA(p) \
338 do {\
339 if(p==0){\
340 DRV_ClrReg32(BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG+0x1C,(0xF<<16)); \
341 DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x8, 0x0);\
342 DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0xC, 0x0);\
343 DRV_WriteReg32(BASE_MADDR_MCOREPERI_INFRA_DSPSL2C+0x658, 0x0);\
344 }else{\
345 DRV_SetReg32(BASE_MADDR_MDCORESYS_MDMCU_BUS_INTF_CFG+0x1C,(0xF<<16)); \
346 DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x8, 0xFFFFFFFF);\
347 DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0xC, 0xEF);\
348 DRV_WriteReg32(BASE_MADDR_MCOREPERI_INFRA_DSPSL2C+0x658, 0x2AAAA);\
349 }\
350 } while(0)
351#elif defined(MT6885) || defined(MT6880)
352
353#define EMI_N_ARBE_2ND (volatile kal_uint32*)(0xC0219124)
354#define EMI_N_ARBD (volatile kal_uint32*)(0xC0219118)
355#define EMI_N_QOS_MDR_SHF0 (volatile kal_uint32*)(0xC0219D14)
356#define EMI_N_QOS_MDR_SHF1 (volatile kal_uint32*)(0xC0219D18)
357
358#define EMI_S_ARBE_2ND (volatile kal_uint32*)(0xC021D124)
359#define EMI_S_ARBD (volatile kal_uint32*)(0xC021D118)
360#define EMI_S_QOS_MDR_SHF0 (volatile kal_uint32*)(0xC021DD14)
361#define EMI_S_QOS_MDR_SHF1 (volatile kal_uint32*)(0xC021DD18)
362
363#define EMI_CH0_TESTB (volatile kal_uint32*)(0xC0235048)
364#define EMI_CH1_TESTB (volatile kal_uint32*)(0xC0245048)
365#define EMI_CH2_TESTB (volatile kal_uint32*)(0xC0255048)
366#define EMI_CH3_TESTB (volatile kal_uint32*)(0xC0265048)
367
368
369/***********************/
370
371#define EMI_TESTC (volatile kal_uint32*)(0xc02190f0)
372#define EMI_TESTC_S (volatile kal_uint32*)(0xc021d0f0)
373
374#define EMI_CONH_2ND (volatile kal_uint32*)(0xc021903c)
375#define EMI_CONH_2ND_S (volatile kal_uint32*)(0xc021d03c)
376
377#define EMI_BWLMTE_4TH (volatile kal_uint32*)(0xc0219920)
378#define EMI_BWLMTE_4TH_S (volatile kal_uint32*)(0xc021d920)
379
380#define EMI_BWLMTF_4TH (volatile kal_uint32*)(0xc0219924)
381#define EMI_BWLMTF_4TH_S (volatile kal_uint32*)(0xc021d924)
382
383#define EMI_BWLMTE_5TH (volatile kal_uint32*)(0xc0219930)
384#define EMI_BWLMTE_5TH_S (volatile kal_uint32*)(0xc021d930)
385#define EMI_BWLMTF_5TH (volatile kal_uint32*)(0xc0219934)
386#define EMI_BWLMTF_5TH_S (volatile kal_uint32*)(0xc021d934)
387#define EMI_BWLMTG_5TH (volatile kal_uint32*)(0xc0219938)
388#define EMI_BWLMTG_5TH_S (volatile kal_uint32*)(0xc021d938)
389
390#define EMI_BWLMTE (volatile kal_uint32*)(0xc02198A0)
391#define EMI_BWLMTE_S (volatile kal_uint32*)(0xc021d8A0)
392#define EMI_BWLMTF (volatile kal_uint32*)(0xc02198A4)
393#define EMI_BWLMTF_S (volatile kal_uint32*)(0xc021d8A4)
394
395#define EMI_BWLMTE_2ND (volatile kal_uint32*)(0xc02198E0)
396#define EMI_BWLMTE_2ND_S (volatile kal_uint32*)(0xc021d8E0)
397#define EMI_BWLMTF_2ND (volatile kal_uint32*)(0xc02198E4)
398#define EMI_BWLMTF_2ND_S (volatile kal_uint32*)(0xc021d8E4)
399#define EMI_BWLMTG_2ND (volatile kal_uint32*)(0xc02198E8)
400#define EMI_BWLMTG_2ND_S (volatile kal_uint32*)(0xc021d8E8)
401
402#define EMI_MDCT (volatile kal_uint32*)(0xc0219078)
403#define EMI_MDCT_S (volatile kal_uint32*)(0xc021d078)
404
405#define EMI_THRO_PRD2 (volatile kal_uint32*)(0xC021985C)
406#define EMI_THRO_PRD2_S (volatile kal_uint32*)(0xC021D85C)
407
408#define EMI_QOS_MDR_BE0A (volatile kal_uint32*)(0xC0219D04)
409#define EMI_QOS_MDR_BE0A_S (volatile kal_uint32*)(0xC021DD04)
410#define EMI_QOS_MDR_BE0B (volatile kal_uint32*)(0xC0219D08)
411#define EMI_QOS_MDR_BE0B_S (volatile kal_uint32*)(0xC021DD08)
412#define EMI_QOS_MDR_BE1A (volatile kal_uint32*)(0xC0219D0C)
413#define EMI_QOS_MDR_BE1A_S (volatile kal_uint32*)(0xC021DD0C)
414#define EMI_QOS_MDR_BE1B (volatile kal_uint32*)(0xC0219D10)
415#define EMI_QOS_MDR_BE1B_S (volatile kal_uint32*)(0xC021DD10)
416
417#define EMI_QOS_MDW_BE0A (volatile kal_uint32*)(0xC0219D1C)
418#define EMI_QOS_MDW_BE0A_S (volatile kal_uint32*)(0xC021DD1C)
419#define EMI_QOS_MDW_BE0B (volatile kal_uint32*)(0xC0219D20)
420#define EMI_QOS_MDW_BE0B_S (volatile kal_uint32*)(0xC021DD20)
421#define EMI_QOS_MDW_BE1A (volatile kal_uint32*)(0xC0219D24)
422#define EMI_QOS_MDW_BE1A_S (volatile kal_uint32*)(0xC021DD24)
423#define EMI_QOS_MDW_BE1B (volatile kal_uint32*)(0xC0219D28)
424#define EMI_QOS_MDW_BE1B_S (volatile kal_uint32*)(0xC021DD28)
425
426#define EMI_QOS_MDHWR_BE0A (volatile kal_uint32*)(0xC0219D98)
427#define EMI_QOS_MDHWR_BE0A_S (volatile kal_uint32*)(0xC021DD98)
428#define EMI_QOS_MDHWR_BE0B (volatile kal_uint32*)(0xC0219D9C)
429#define EMI_QOS_MDHWR_BE0B_S (volatile kal_uint32*)(0xC021DD9C)
430#define EMI_QOS_MDHWR_BE1A (volatile kal_uint32*)(0xC0219DA0)
431#define EMI_QOS_MDHWR_BE1A_S (volatile kal_uint32*)(0xC021DDA0)
432#define EMI_QOS_MDHWR_BE1B (volatile kal_uint32*)(0xC0219DA4)
433#define EMI_QOS_MDHWR_BE1B_S (volatile kal_uint32*)(0xC021DDA4)
434
435#define EMI_QOS_MDHWW_BE0A (volatile kal_uint32*)(0xC0219DAC)
436#define EMI_QOS_MDHWW_BE0A_S (volatile kal_uint32*)(0xC021DDAC)
437#define EMI_QOS_MDHWW_BE0B (volatile kal_uint32*)(0xC0219DB0)
438#define EMI_QOS_MDHWW_BE0B_S (volatile kal_uint32*)(0xC021DDB0)
439#define EMI_QOS_MDHWW_BE1A (volatile kal_uint32*)(0xC0219DB4)
440#define EMI_QOS_MDHWW_BE1A_S (volatile kal_uint32*)(0xC021DDB4)
441#define EMI_QOS_MDHWW_BE1B (volatile kal_uint32*)(0xC0219DB8)
442#define EMI_QOS_MDHWW_BE1B_S (volatile kal_uint32*)(0xC021DDB8)
443
444#define EMI_CONE (volatile kal_uint32*)(0xc0219020)
445#define EMI_CONE_S (volatile kal_uint32*)(0xc021d020)
446
447#define CH0_EMI_CONC (volatile kal_uint32*)(0xC0235010)
448#define CH1_EMI_CONC (volatile kal_uint32*)(0xC0245010)
449#define CH2_EMI_CONC (volatile kal_uint32*)(0xC0255010)
450#define CH3_EMI_CONC (volatile kal_uint32*)(0xC0265010)
451
452#define EMI_QOS_CTRL1 (volatile kal_uint32*)(0xc0219DF4)
453#define EMI_QOS_CTRL1_S (volatile kal_uint32*)(0xc021dDF4)
454
455#define EMI_QOS_MDW_SHF0 (volatile kal_uint32*)(0xc0219D2C)
456#define EMI_QOS_MDW_SHF0_S (volatile kal_uint32*)(0xc021dD2C)
457#define EMI_QOS_MDW_SHF1 (volatile kal_uint32*)(0xc0219D30)
458#define EMI_QOS_MDW_SHF1_S (volatile kal_uint32*)(0xc021dD30)
459
460/***********************/
461#define EMI_FORCE_LATENCY(r, w) \
462 do {\
463 *EMI_TESTC |= 1<<19;\
464 *EMI_TESTC_S |= 1<<19;\
465 *EMI_CONH_2ND |= 1<<9;\
466 *EMI_CONH_2ND_S |= 1<<9;\
467 *EMI_BWLMTE_4TH = 0xFFFFFFFF;\
468 *EMI_BWLMTE_4TH_S = 0xFFFFFFFF;\
469 *EMI_BWLMTF_4TH |= 0xFFFF;\
470 *EMI_BWLMTF_4TH_S |= 0xFFFF;\
471 *EMI_BWLMTE_5TH = 0xFFFFFFFF;\
472 *EMI_BWLMTE_5TH_S = 0xFFFFFFFF;\
473 *EMI_BWLMTF_5TH = 0xFFFFFFFF;\
474 *EMI_BWLMTF_5TH_S = 0xFFFFFFFF;\
475 *EMI_BWLMTG_5TH = 0xFFFFFFFF;\
476 *EMI_BWLMTG_5TH_S = 0xFFFFFFFF;\
477 *EMI_BWLMTE = 0xFF00FFFF;\
478 *EMI_BWLMTE_S = 0xFF00FFFF;\
479 *EMI_BWLMTF |= 0xFFFF;\
480 *EMI_BWLMTF_S |= 0xFFFF;\
481 *EMI_BWLMTE_2ND = 0xFFFFFFFF;\
482 *EMI_BWLMTE_2ND_S = 0xFFFFFFFF;\
483 *EMI_BWLMTF_2ND = 0xFFFF0000;\
484 *EMI_BWLMTF_2ND_S = 0xFFFF0000;\
485 *EMI_BWLMTG_2ND = 0xFFFFFFFF;\
486 *EMI_BWLMTG_2ND_S = 0xFFFFFFFF;\
487 *EMI_N_ARBD |= 1<<13;\
488 *EMI_S_ARBD |= 1<<13;\
489 *EMI_N_ARBD &= ~(1<<14);\
490 *EMI_S_ARBD &= ~(1<<14);\
491 *EMI_MDCT &= ~((1<<1)|(1<<3));\
492 *EMI_MDCT_S &= ~((1<<1)|(1<<3));\
493 *EMI_THRO_PRD2 |= (7<<24) | (7<<28);\
494 *EMI_THRO_PRD2_S |= (7<<24) | (7<<28);\
495 \
496 *EMI_QOS_MDR_BE0A = 0;\
497 *EMI_QOS_MDR_BE0B = 0;\
498 *EMI_QOS_MDR_BE1A = 0;\
499 *EMI_QOS_MDR_BE1B = 0;\
500 *EMI_QOS_MDW_BE0A = 0;\
501 *EMI_QOS_MDW_BE0B = 0;\
502 *EMI_QOS_MDW_BE1A = 0;\
503 *EMI_QOS_MDW_BE1B = 0;\
504 *EMI_QOS_MDR_BE0A_S = 0;\
505 *EMI_QOS_MDR_BE0B_S = 0;\
506 *EMI_QOS_MDR_BE1A_S = 0;\
507 *EMI_QOS_MDR_BE1B_S = 0;\
508 *EMI_QOS_MDW_BE0A_S = 0;\
509 *EMI_QOS_MDW_BE0B_S = 0;\
510 *EMI_QOS_MDW_BE1A_S = 0;\
511 *EMI_QOS_MDW_BE1B_S = 0;\
512 \
513 *EMI_QOS_MDHWR_BE0A = 0;\
514 *EMI_QOS_MDHWR_BE0B = 0;\
515 *EMI_QOS_MDHWR_BE1A = 0;\
516 *EMI_QOS_MDHWR_BE1B = 0;\
517 *EMI_QOS_MDHWW_BE0A = 0;\
518 *EMI_QOS_MDHWW_BE0B = 0;\
519 *EMI_QOS_MDHWW_BE1A = 0;\
520 *EMI_QOS_MDHWW_BE1B = 0;\
521 *EMI_QOS_MDHWR_BE0A_S = 0;\
522 *EMI_QOS_MDHWR_BE0B_S = 0;\
523 *EMI_QOS_MDHWR_BE1A_S = 0;\
524 *EMI_QOS_MDHWR_BE1B_S = 0;\
525 *EMI_QOS_MDHWW_BE0A_S = 0;\
526 *EMI_QOS_MDHWW_BE0B_S = 0;\
527 *EMI_QOS_MDHWW_BE1A_S = 0;\
528 *EMI_QOS_MDHWW_BE1B_S = 0;\
529 \
530 *EMI_N_ARBD = (*EMI_N_ARBD&0x00FFFFFF) | (w<<24);\
531 *EMI_N_ARBE_2ND = (*EMI_N_ARBE_2ND&0x00FFFFFF) | (w<<24);\
532 *EMI_S_ARBD = (*EMI_S_ARBD&0x00FFFFFF) | (w<<24);\
533 *EMI_S_ARBE_2ND = (*EMI_S_ARBE_2ND&0x00FFFFFF) | (w<<24);\
534 \
535 *EMI_CONE |= 1 ;\
536 *EMI_CONE_S |= 1 ;\
537 \
538 *CH0_EMI_CONC |= (1<<5) ;\
539 *CH1_EMI_CONC |= (1<<5) ;\
540 *CH2_EMI_CONC |= (1<<5) ;\
541 *CH3_EMI_CONC |= (1<<5) ;\
542 \
543 *EMI_QOS_CTRL1 &= ~((0x1<<11)|(0x1<<27));\
544 *EMI_QOS_CTRL1_S &= ~((0x1<<11)|(0x1<<27));\
545 \
546 *EMI_QOS_MDW_SHF0 = (*EMI_QOS_MDW_SHF0&0xffffff00) | w;\
547 *EMI_QOS_MDW_SHF0_S = (*EMI_QOS_MDW_SHF0_S&0xffffff00) | w;\
548 *EMI_QOS_MDW_SHF1 = (*EMI_QOS_MDW_SHF1&0xffffff00) | w;\
549 *EMI_QOS_MDW_SHF1_S = (*EMI_QOS_MDW_SHF1_S&0xffffff00) | w;\
550 \
551 *EMI_N_ARBE_2ND = (*EMI_N_ARBE_2ND & 0xFF00FFFF) | (r<<16) ;\
552 *EMI_N_ARBD = (*EMI_N_ARBD & 0xFF00FFFF) | (r<<16) ;\
553 *EMI_N_QOS_MDR_SHF0 = (*EMI_N_QOS_MDR_SHF0 & 0xFFFF0000) | (r<<8) | (r);\
554 *EMI_N_QOS_MDR_SHF1 = (*EMI_N_QOS_MDR_SHF1 & 0xFFFF0000) | (r<<8) | (r);\
555 \
556 *EMI_S_ARBE_2ND = (*EMI_S_ARBE_2ND & 0xFF00FFFF) | (r<<16) ;\
557 *EMI_S_ARBD = (*EMI_S_ARBD & 0xFF00FFFF) | (r<<16) ;\
558 *EMI_S_QOS_MDR_SHF0 = (*EMI_S_QOS_MDR_SHF0 & 0xFFFF0000) | (r<<8) | (r);\
559 *EMI_S_QOS_MDR_SHF1 = (*EMI_S_QOS_MDR_SHF1 & 0xFFFF0000) | (r<<8) | (r);\
560 \
561 *EMI_CH0_TESTB |= ((1<<6)|(1<<13)) ; \
562 *EMI_CH1_TESTB |= ((1<<6)|(1<<13)) ; \
563 *EMI_CH2_TESTB |= ((1<<6)|(1<<13)) ; \
564 *EMI_CH3_TESTB |= ((1<<6)|(1<<13)) ; \
565 } while (0)
566
567#define EMI_AGING_26M() \
568 do {\
569 *EMI_CONE &= ~(1<<0) ;\
570 *EMI_CONE_S &= ~(1<<0) ;\
571 *CH0_EMI_CONC &= ~(1<<5) ;\
572 *CH1_EMI_CONC &= ~(1<<5) ;\
573 *CH2_EMI_CONC &= ~(1<<5) ;\
574 *CH3_EMI_CONC &= ~(1<<5) ;\
575 } while (0)
576
577#define EMI_FORCE_DISABLE_DRAMC_WRITE_EARLY_RESPONSE() \
578 do {\
579 *EMI_CH0_TESTB |= (1<<11) ; \
580 *EMI_CH1_TESTB |= (1<<11) ; \
581 *EMI_CH2_TESTB |= (1<<11) ; \
582 *EMI_CH3_TESTB |= (1<<11) ; \
583 } while(0)
584
585#define FORCE_MD_ULTRA(p) \
586 do {\
587 if(p==0){\
588 DRV_ClrReg32(0xa0060064,(0xf << 8)); \
589 DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x8, 0x0);\
590 DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0xC, 0x0);\
591 DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x1C, 0x0);\
592 DRV_WriteReg32(0xa4c00000+0x8658, 0x0);\
593 }else{\
594 DRV_SetReg32(0xa0060064,(0xf << 8)); \
595 DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x8, 0xFFFFFFFF);\
596 DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0xC, 0x7EF);\
597 DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x1C, 0x7E00000);\
598 DRV_WriteReg32(0xa4c00000+0x8658, 0x2AAAA);\
599 }\
600 } while(0)
601
602#elif defined(MT6873) || defined(MT6853) || defined(MT6833)
603
604#define EMI_ARBE_2ND (volatile kal_uint32*)(0xC0219124)
605#define EMI_ARBD (volatile kal_uint32*)(0xC0219118)
606#define EMI_QOS_MDR_SHF0 (volatile kal_uint32*)(0xC0219D14)
607#define EMI_QOS_MDR_SHF1 (volatile kal_uint32*)(0xC0219D18)
608
609#define EMI_CH0_TESTB (volatile kal_uint32*)(0xC0235048)
610#define EMI_CH1_TESTB (volatile kal_uint32*)(0xC0245048)
611
612
613/***********************/
614
615#define EMI_TESTC (volatile kal_uint32*)(0xc02190f0)
616#define EMI_CONH_2ND (volatile kal_uint32*)(0xc021903c)
617#define EMI_BWLMTE_4TH (volatile kal_uint32*)(0xc0219920)
618#define EMI_BWLMTF_4TH (volatile kal_uint32*)(0xc0219924)
619
620#define EMI_BWLMTE_5TH (volatile kal_uint32*)(0xc0219930)
621#define EMI_BWLMTF_5TH (volatile kal_uint32*)(0xc0219934)
622#define EMI_BWLMTG_5TH (volatile kal_uint32*)(0xc0219938)
623
624#define EMI_BWLMTE (volatile kal_uint32*)(0xc02198A0)
625#define EMI_BWLMTF (volatile kal_uint32*)(0xc02198A4)
626
627#define EMI_BWLMTE_2ND (volatile kal_uint32*)(0xc02198E0)
628#define EMI_BWLMTF_2ND (volatile kal_uint32*)(0xc02198E4)
629#define EMI_BWLMTG_2ND (volatile kal_uint32*)(0xc02198E8)
630
631#define EMI_MDCT (volatile kal_uint32*)(0xc0219078)
632
633#define EMI_THRO_PRD2 (volatile kal_uint32*)(0xC021985C)
634
635#define EMI_QOS_MDR_BE0A (volatile kal_uint32*)(0xC0219D04)
636#define EMI_QOS_MDR_BE0B (volatile kal_uint32*)(0xC0219D08)
637#define EMI_QOS_MDR_BE1A (volatile kal_uint32*)(0xC0219D0C)
638#define EMI_QOS_MDR_BE1B (volatile kal_uint32*)(0xC0219D10)
639
640#define EMI_QOS_MDW_BE0A (volatile kal_uint32*)(0xC0219D1C)
641#define EMI_QOS_MDW_BE0B (volatile kal_uint32*)(0xC0219D20)
642#define EMI_QOS_MDW_BE1A (volatile kal_uint32*)(0xC0219D24)
643#define EMI_QOS_MDW_BE1B (volatile kal_uint32*)(0xC0219D28)
644
645#define EMI_QOS_MDHWR_BE0A (volatile kal_uint32*)(0xC0219D98)
646#define EMI_QOS_MDHWR_BE0B (volatile kal_uint32*)(0xC0219D9C)
647#define EMI_QOS_MDHWR_BE1A (volatile kal_uint32*)(0xC0219DA0)
648#define EMI_QOS_MDHWR_BE1B (volatile kal_uint32*)(0xC0219DA4)
649
650#define EMI_QOS_MDHWW_BE0A (volatile kal_uint32*)(0xC0219DAC)
651#define EMI_QOS_MDHWW_BE0B (volatile kal_uint32*)(0xC0219DB0)
652#define EMI_QOS_MDHWW_BE1A (volatile kal_uint32*)(0xC0219DB4)
653#define EMI_QOS_MDHWW_BE1B (volatile kal_uint32*)(0xC0219DB8)
654
655#define EMI_CONE (volatile kal_uint32*)(0xc0219020)
656
657#define CH0_EMI_CONC (volatile kal_uint32*)(0xC0235010)
658#define CH1_EMI_CONC (volatile kal_uint32*)(0xC0245010)
659
660#define EMI_QOS_CTRL1 (volatile kal_uint32*)(0xc0219DF4)
661
662#define EMI_QOS_MDW_SHF0 (volatile kal_uint32*)(0xc0219D2C)
663#define EMI_QOS_MDW_SHF1 (volatile kal_uint32*)(0xc0219D30)
664
665/***********************/
666#define EMI_FORCE_LATENCY(r, w) \
667 do {\
668 *EMI_TESTC |= 1<<19;\
669 *EMI_CONH_2ND |= 1<<9;\
670 *EMI_BWLMTE_4TH = 0xFFFFFFFF;\
671 *EMI_BWLMTF_4TH |= 0xFFFF;\
672 *EMI_BWLMTE_5TH = 0xFFFFFFFF;\
673 *EMI_BWLMTF_5TH = 0xFFFFFFFF;\
674 *EMI_BWLMTG_5TH = 0xFFFFFFFF;\
675 *EMI_BWLMTE = 0xFF00FFFF;\
676 *EMI_BWLMTF |= 0xFFFF;\
677 *EMI_BWLMTE_2ND = 0xFFFFFFFF;\
678 *EMI_BWLMTF_2ND = 0xFFFF0000;\
679 *EMI_BWLMTG_2ND = 0xFFFFFFFF;\
680 *EMI_ARBD |= 1<<13;\
681 *EMI_ARBD &= ~(1<<14);\
682 *EMI_MDCT &= ~((1<<1)|(1<<3));\
683 *EMI_THRO_PRD2 |= (7<<24) | (7<<28);\
684 \
685 *EMI_QOS_MDR_BE0A = 0;\
686 *EMI_QOS_MDR_BE0B = 0;\
687 *EMI_QOS_MDR_BE1A = 0;\
688 *EMI_QOS_MDR_BE1B = 0;\
689 *EMI_QOS_MDW_BE0A = 0;\
690 *EMI_QOS_MDW_BE0B = 0;\
691 *EMI_QOS_MDW_BE1A = 0;\
692 *EMI_QOS_MDW_BE1B = 0;\
693 \
694 *EMI_QOS_MDHWR_BE0A = 0;\
695 *EMI_QOS_MDHWR_BE0B = 0;\
696 *EMI_QOS_MDHWR_BE1A = 0;\
697 *EMI_QOS_MDHWR_BE1B = 0;\
698 *EMI_QOS_MDHWW_BE0A = 0;\
699 *EMI_QOS_MDHWW_BE0B = 0;\
700 *EMI_QOS_MDHWW_BE1A = 0;\
701 *EMI_QOS_MDHWW_BE1B = 0;\
702 \
703 *EMI_ARBD = (*EMI_ARBD&0x00FFFFFF) | (w<<24);\
704 *EMI_ARBE_2ND = (*EMI_ARBE_2ND&0x00FFFFFF) | (w<<24);\
705 \
706 *EMI_CONE |= 1 ;\
707 \
708 *CH0_EMI_CONC |= (1<<5) ;\
709 *CH1_EMI_CONC |= (1<<5) ;\
710 \
711 *EMI_QOS_CTRL1 &= ~((0x1<<11)|(0x1<<27));\
712 \
713 *EMI_QOS_MDW_SHF0 = (*EMI_QOS_MDW_SHF0&0xffffff00) | w;\
714 *EMI_QOS_MDW_SHF1 = (*EMI_QOS_MDW_SHF1&0xffffff00) | w;\
715 \
716 *EMI_ARBE_2ND = (*EMI_ARBE_2ND & 0xFF00FFFF) | (r<<16) ;\
717 *EMI_ARBD = (*EMI_ARBD & 0xFF00FFFF) | (r<<16) ;\
718 *EMI_QOS_MDR_SHF0 = (*EMI_QOS_MDR_SHF0 & 0xFFFF0000) | (r<<8) | (r);\
719 *EMI_QOS_MDR_SHF1 = (*EMI_QOS_MDR_SHF1 & 0xFFFF0000) | (r<<8) | (r);\
720 \
721 *EMI_CH0_TESTB |= ((1<<6)|(1<<13)) ; \
722 *EMI_CH1_TESTB |= ((1<<6)|(1<<13)) ; \
723 } while (0)
724
725#define EMI_AGING_26M() \
726 do {\
727 *EMI_CONE &= ~(1<<0) ;\
728 *CH0_EMI_CONC &= ~(1<<5) ;\
729 *CH1_EMI_CONC &= ~(1<<5) ;\
730 } while (0)
731
732
733#define EMI_FORCE_DISABLE_DRAMC_WRITE_EARLY_RESPONSE() \
734 do {\
735 *EMI_CH0_TESTB |= (1<<11) ; \
736 *EMI_CH1_TESTB |= (1<<11) ; \
737 } while(0)
738
739#define FORCE_MD_ULTRA(p) \
740 do {\
741 if(p==0){\
742 DRV_ClrReg32(0xa0060064,(0xf << 8)); \
743 DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x8, 0x0);\
744 DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0xC, 0x0);\
745 DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x1C, 0x0);\
746 DRV_WriteReg32(0xa4c00000+0x8658, 0x0);\
747 }else{\
748 DRV_SetReg32(0xa0060064,(0xf << 8)); \
749 DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x8, 0xFFFFFFFF);\
750 DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0xC, 0x7EF);\
751 DRV_WriteReg32(BASE_MADDR_USIP_BUS_CONFIG___MPU_CONFIG+0x1C, 0x7E00000);\
752 DRV_WriteReg32(0xa4c00000+0x8658, 0x2AAAA);\
753 }\
754 } while(0)
755
756#else
757 #error "No support force emi latency on this project"
758#endif
759
760#endif //__FORCE_EMI_LATENCY_ENABLE__
761
762
763//for spv_service.c
764typedef struct _ELM_BW_LOG_T
765{
766 kal_uint32 m3_r_word_count;
767 kal_uint32 m3_w_word_count;
768 kal_uint32 m4_r_word_count;
769 kal_uint32 m4_w_word_count;
770} ELM_BW_LOG_T;
771
772typedef struct __SPVSVC_MON {
773 kal_uint32 apb_Reliable;
774 kal_uint32 apb_CurIsWorst;
775 kal_uint32 apb_Duration;
776 kal_uint32 apb_Avg_RLat;
777 kal_uint32 apb_Avg_WLat;
778 kal_uint32 apb_Worst_AvgRLat;
779 kal_uint32 apb_Worst_AvgWLat;
780 kal_uint32 apb_Total_RCnt;
781 kal_uint32 apb_Total_WCnt;
782 kal_uint32 apb_Dummy0;
783
784 kal_uint32 cm2_Reliable;
785 kal_uint32 cm2_CurIsWorst;
786 kal_uint32 cm2_Duration;
787 kal_uint32 cm2_Avg_UC_RW;
788 kal_uint32 cm2_Avg_L2Cache_RW;
789 kal_uint32 cm2_Worst_AvgUC_RW;
790 kal_uint32 cm2_Worst_AvgL2Cache_RW;
791 kal_uint32 cm2_Total_UC_RW;
792 kal_uint32 cm2_Total_L2Cache_RW;
793 kal_uint32 cm2_Dummy0;
794
795 //might use union?
796 kal_uint32 elm_Reliable;
797 kal_uint32 elm_CurIsWorst;
798 kal_uint32 elm_Duration;
799 kal_uint32 elm_Avg_RLat;
800 kal_uint32 elm_Avg_WLat;
801 kal_uint32 elm_Worst_AvgRLat;
802 kal_uint32 elm_Worst_AvgWLat;
803 kal_uint32 elm_Total_RCnt;
804 kal_uint32 elm_Total_WCnt;
805 kal_uint32 elm_Dummy0;
806
807} SPVSVC_MON;
808
809kal_bool SPVSVC_Monitor_Get(SPVSVC_MON *pCnts);
810extern kal_bool SPVSVC_Monitor_LogClear(void);
811
812#if defined(__BW_RUNTIME_PF__)
813
814#if defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)
815#define __MD_ELM_TLW__
816#endif
817#define WRAP_MAX 0xFFFFFFFF
818#define DIFF_WRAP_TYPE(start, end) (((end) >= (start))? (((end) - (start))): ((WRAP_MAX - (start) + (end) + 1)))
819
820#if defined(__MD_ELM_TLW__)
821
822typedef struct _ELM_PROFILING_LOG_T
823{
824 kal_uint32 m3_r_transaction;
825 kal_uint32 m3_r_word_count;
826 kal_uint32 m3_r_latency;
827 kal_uint32 m3_w_transaction;
828 kal_uint32 m3_w_word_count;
829 kal_uint32 m3_w_latency;
830 kal_uint32 m4_r_transaction;
831 kal_uint32 m4_r_word_count;
832 kal_uint32 m4_r_latency;
833 kal_uint32 m4_w_transaction;
834 kal_uint32 m4_w_word_count;
835 kal_uint32 m4_w_latency;
836#if defined(MT6297)
837 kal_uint32 m4b_r_transaction;
838 kal_uint32 m4b_r_word_count;
839 kal_uint32 m4b_r_latency;
840 kal_uint32 m4b_w_transaction;
841 kal_uint32 m4b_w_word_count;
842 kal_uint32 m4b_w_latency;
843#endif
844} ELM_PROFILING_LOG_T;
845
846#define ELM_GET_M3_BW_LOG(c, l) do { \
847 ELM_GET_WC_CNT(ELM_RD, (c), &((l).m3_r_word_count));\
848 ELM_GET_WC_CNT(ELM_WR, (c), &((l).m3_w_word_count));\
849 } while (0)
850
851#define ELM_GET_M4_BW_LOG(c, l) do { \
852 ELM_INFRA_GET_WC_CNT(ELM_RD, (c), &((l).m4_r_word_count));\
853 ELM_INFRA_GET_WC_CNT(ELM_WR, (c), &((l).m4_w_word_count));\
854 } while (0)
855
856#define ELM_GET_M3_LATENCY_LOG(c, l) do { \
857 ELM_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).m3_r_transaction));\
858 ELM_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).m3_r_latency));\
859 ELM_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).m3_w_transaction));\
860 ELM_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).m3_w_latency));\
861 } while (0)
862
863#define ELM_GET_M4_LATENCY_LOG(c, l) do { \
864 ELM_INFRA_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).m4_r_transaction));\
865 ELM_INFRA_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).m4_r_latency));\
866 ELM_INFRA_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).m4_w_transaction));\
867 ELM_INFRA_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).m4_w_latency));\
868 } while (0)
869
870#if defined(MT6297)
871#define ELM_GET_M4B_LATENCY_LOG(c, l) do { \
872 ELM_INFRA_B_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).m4b_r_transaction));\
873 ELM_INFRA_B_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).m4b_r_latency));\
874 ELM_INFRA_B_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).m4b_w_transaction));\
875 ELM_INFRA_B_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).m4b_w_latency));\
876 } while (0)
877#define ELM_GET_M4B_BW_LOG(c, l) do { \
878 ELM_INFRA_B_GET_WC_CNT(ELM_RD, (c), &((l).m4b_r_word_count));\
879 ELM_INFRA_B_GET_WC_CNT(ELM_WR, (c), &((l).m4b_w_word_count));\
880 } while (0)
881#endif
882
883#else
884
885typedef struct _ELM_PROFILING_LOG_T
886{
887 kal_uint32 m3_r_transaction;
888 kal_uint32 m3_r_word_count;
889 kal_uint32 m3_r_latency;
890 kal_uint32 m3_w_word_count;
891 kal_uint32 m4_r_transaction;
892 kal_uint32 m4_r_word_count;
893 kal_uint32 m4_r_latency;
894 kal_uint32 m4_w_word_count;
895} ELM_PROFILING_LOG_T;
896
897#define ELM_GET_M3_BW_LOG(c, l) do { \
898 ELM_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).m3_r_word_count));\
899 ELM_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).m3_w_word_count));\
900 } while (0)
901
902#define ELM_GET_M4_BW_LOG(c, l) do { \
903 ELM_INFRA_GET_CNT(ELM_WR, ELM_TYPE_TRANS, (c), &((l).m4_r_word_count));\
904 ELM_INFRA_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, (c), &((l).m4_w_word_count));\
905 } while (0)
906
907#define ELM_GET_M3_LATENCY_LOG(c, l) do { \
908 ELM_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).m3_r_transaction));\
909 ELM_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).m3_r_latency));\
910 } while (0)
911
912#define ELM_GET_M4_LATENCY_LOG(c, l) do { \
913 ELM_INFRA_GET_CNT(ELM_RD, ELM_TYPE_TRANS, (c), &((l).m4_r_transaction));\
914 ELM_INFRA_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, (c), &((l).m4_r_latency));\
915 } while (0)
916
917#endif /* __MD_ELM_TLW__ */
918
919
920kal_bool SPVSVC_BW_PF(kal_uint32 core_id);
921void SPVSVC_BW_Max_Print(void);
922void SPVSVC_BW_Max_Clear(void);
923void SPVSVC_BW_Threshold_Print(void);
924
925extern volatile kal_uint32 RECORD_AP_DVFSRC;
926extern volatile kal_uint32 BW_index;
927extern kal_uint32 BW_Cor_Duration[] ;
928extern kal_uint32 BW_Cor_Duration_Low[] ;
929extern kal_uint32 BW_Cor_Duration_High[] ;
930
931extern volatile kal_uint32 BW_Cor_Duration_core[] ;
932
933extern volatile kal_uint32 BW_Cor_Enable;
934
935extern volatile kal_uint32 BW_M3_Worst_core[];
936extern volatile kal_uint32 BW_M3_Worst_Dur_core[];
937extern volatile kal_uint32 BW_M4_Worst_core[] ;
938extern volatile kal_uint32 BW_M4_Worst_Dur_core[];
939extern volatile kal_uint32 BW_M3M4_Worst_core[];
940extern volatile kal_uint32 BW_M3M4_Worst_Dur_core[];
941
942
943extern volatile kal_uint32 BW_Dur_Low_core[] ;
944extern volatile kal_uint32 BW_Dur_High_core[];
945
946extern volatile kal_uint32 BW_Cor_Raw_Data_Print_Enable;
947
948extern volatile kal_uint32 BW_Transaction_Low_core[];
949
950extern volatile kal_uint32 BW_M3_Assertion_core[];
951extern volatile kal_uint32 BW_M4_Assertion_core[];
952extern volatile kal_uint32 BW_M3M4_Assertion_core[];
953extern volatile kal_uint32 Latency_M3_Read_Assertion_core[];
954extern volatile kal_uint32 Latency_M4_Read_Assertion_core[];
955#if defined(__MD_ELM_TLW__)
956extern volatile kal_uint32 Latency_M3_Write_Assertion_core[];
957extern volatile kal_uint32 Latency_M4_Write_Assertion_core[];
958#endif
959
960extern void SPV_IdleTask0( task_entry_struct * task_entry_ptr );
961extern void SPV_IdleTask1( task_entry_struct * task_entry_ptr );
962extern void SPV_IdleTask2( task_entry_struct * task_entry_ptr );
963extern void SPV_IdleTask3( task_entry_struct * task_entry_ptr );
964
965#endif /* defined(__BW_RUNTIME_PF__) */
966
967#if 0 // official load profiling
968/* under construction !*/
969/* under construction !*/
970/* under construction !*/
971#endif
972
973void SSS_PF_INIT(void);
974void SSS_CORE_PMU_PF_WriteRecord(kal_uint32 flag);
975void SSS_CORE_PMU_PF_START(void);
976void SSS_CORE_PMU_PF_END(void);
977#if defined(__SPV_SSS_PF__)
978#if defined(__SPV_SSS_CORE_PMU_PF__)
979 #if defined(__MIPS16__)
980 #if defined(__GNUC__)
981 #define SSS_MIPS32_ISA __attribute__((nomips16))
982 #endif
983 #endif
984
985#ifndef SSS_MIPS32_ISA
986#define SSS_MIPS32_ISA
987#endif
988
989#define SSS_MIPS32_INLINE INLINE SSS_MIPS32_ISA
990#define STATIC_INLINE \
991 __attribute__((always_inline)) SSS_MIPS32_ISA static
992
993#if defined(__MD95__)
994#define MAX_CORE_PMU_NUM_PER_VPE 8 // 2 pmu counters per TC, 4 TCs per-core => 2*4 = 8
995#elif defined(__MD97__) || defined(__MD97P__)
996#define MAX_CORE_PMU_NUM_PER_VPE 12 // 4 pmu counters per VPE, 3 VPEs per-core => 4*3 = 12
997#endif
998
999typedef struct {
1000 kal_int32 core_pmu_enable_return_state;
1001 kal_int32 core_pmu_disable_return_state;
1002 kal_int32 core_pmu_dump_return_state;
1003 kal_uint32 frc_start;
1004 kal_uint32 frc_end;
1005 kal_uint32 cpu_cycle_start;
1006 kal_uint32 core_pmu[MAX_CORE_PMU_NUM_PER_VPE];
1007 kal_uint32 cpu_cycle_end;
1008} SSS_CORE_PMU_PF_RECORD;
1009
1010#endif /* __SPV_SSS_CORE_PMU_PF__ */
1011#endif /* __SPV_SSS_PF__ */
1012
1013#endif //__SPV_API_H_
1014